2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
35 #define SCC_PATA_NAME "scc IDE"
37 #define TDVHSEL_MASTER 0x00000001
38 #define TDVHSEL_SLAVE 0x00000004
40 #define MODE_JCUSFEN 0x00000080
42 #define CCKCTRL_ATARESET 0x00040000
43 #define CCKCTRL_BUFCNT 0x00020000
44 #define CCKCTRL_CRST 0x00010000
45 #define CCKCTRL_OCLKEN 0x00000100
46 #define CCKCTRL_ATACLKOEN 0x00000002
47 #define CCKCTRL_LCLKEN 0x00000001
49 #define QCHCD_IOS_SS 0x00000001
51 #define QCHSD_STPDIAG 0x00020000
53 #define INTMASK_MSK 0xD1000012
54 #define INTSTS_SERROR 0x80000000
55 #define INTSTS_PRERR 0x40000000
56 #define INTSTS_RERR 0x10000000
57 #define INTSTS_ICERR 0x01000000
58 #define INTSTS_BMSINT 0x00000010
59 #define INTSTS_BMHE 0x00000008
60 #define INTSTS_IOIRQS 0x00000004
61 #define INTSTS_INTRQ 0x00000002
62 #define INTSTS_ACTEINT 0x00000001
64 #define ECMODE_VALUE 0x01
66 static struct scc_ports {
67 unsigned long ctl, dma;
68 ide_hwif_t *hwif; /* for removing port from system */
69 } scc_ports[MAX_HWIFS];
71 /* PIO transfer mode table */
73 static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
79 static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
85 static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
91 /* DMA transfer mode table */
93 static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
99 static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
105 static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
111 static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
116 /* JCACTSELS/JCACTSELM */
117 static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
123 static u8 scc_ide_inb(unsigned long port)
125 u32 data = in_be32((void*)port);
129 static u8 scc_read_sff_dma_status(ide_hwif_t *hwif)
131 return (u8)in_be32((void *)hwif->dma_status);
134 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
136 u16 *ptr = (u16 *)addr;
138 *ptr++ = le16_to_cpu(in_be32((void*)port));
142 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
144 u16 *ptr = (u16 *)addr;
146 *ptr++ = le16_to_cpu(in_be32((void*)port));
147 *ptr++ = le16_to_cpu(in_be32((void*)port));
151 static void scc_ide_outb(u8 addr, unsigned long port)
153 out_be32((void*)port, addr);
156 static void scc_ide_outbsync(ide_hwif_t *hwif, u8 addr, unsigned long port)
158 out_be32((void*)port, addr);
160 in_be32((void*)(hwif->dma_base + 0x01c));
165 scc_ide_outsw(unsigned long port, void *addr, u32 count)
167 u16 *ptr = (u16 *)addr;
169 out_be32((void*)port, cpu_to_le16(*ptr++));
174 scc_ide_outsl(unsigned long port, void *addr, u32 count)
176 u16 *ptr = (u16 *)addr;
178 out_be32((void*)port, cpu_to_le16(*ptr++));
179 out_be32((void*)port, cpu_to_le16(*ptr++));
184 * scc_set_pio_mode - set host controller for PIO mode
186 * @pio: PIO mode number
188 * Load the timing settings for this device mode into the
192 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
194 ide_hwif_t *hwif = HWIF(drive);
195 struct scc_ports *ports = ide_get_hwifdata(hwif);
196 unsigned long ctl_base = ports->ctl;
197 unsigned long cckctrl_port = ctl_base + 0xff0;
198 unsigned long piosht_port = ctl_base + 0x000;
199 unsigned long pioct_port = ctl_base + 0x004;
203 reg = in_be32((void __iomem *)cckctrl_port);
204 if (reg & CCKCTRL_ATACLKOEN) {
205 offset = 1; /* 133MHz */
207 offset = 0; /* 100MHz */
209 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
210 out_be32((void __iomem *)piosht_port, reg);
211 reg = JCHCTtbl[offset][pio];
212 out_be32((void __iomem *)pioct_port, reg);
216 * scc_set_dma_mode - set host controller for DMA mode
220 * Load the timing settings for this device mode into the
224 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
226 ide_hwif_t *hwif = HWIF(drive);
227 struct scc_ports *ports = ide_get_hwifdata(hwif);
228 unsigned long ctl_base = ports->ctl;
229 unsigned long cckctrl_port = ctl_base + 0xff0;
230 unsigned long mdmact_port = ctl_base + 0x008;
231 unsigned long mcrcst_port = ctl_base + 0x00c;
232 unsigned long sdmact_port = ctl_base + 0x010;
233 unsigned long scrcst_port = ctl_base + 0x014;
234 unsigned long udenvt_port = ctl_base + 0x018;
235 unsigned long tdvhsel_port = ctl_base + 0x020;
236 int is_slave = (&hwif->drives[1] == drive);
239 unsigned long jcactsel;
241 reg = in_be32((void __iomem *)cckctrl_port);
242 if (reg & CCKCTRL_ATACLKOEN) {
243 offset = 1; /* 133MHz */
245 offset = 0; /* 100MHz */
248 idx = speed - XFER_UDMA_0;
250 jcactsel = JCACTSELtbl[offset][idx];
252 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
253 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
254 jcactsel = jcactsel << 2;
255 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
257 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
258 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
259 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
261 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
262 out_be32((void __iomem *)udenvt_port, reg);
265 static void scc_dma_host_set(ide_drive_t *drive, int on)
267 ide_hwif_t *hwif = drive->hwif;
268 u8 unit = (drive->select.b.unit & 0x01);
269 u8 dma_stat = scc_ide_inb(hwif->dma_status);
272 dma_stat |= (1 << (5 + unit));
274 dma_stat &= ~(1 << (5 + unit));
276 scc_ide_outb(dma_stat, hwif->dma_status);
280 * scc_ide_dma_setup - begin a DMA phase
281 * @drive: target device
283 * Build an IDE DMA PRD (IDE speak for scatter gather table)
284 * and then set up the DMA transfer registers.
286 * Returns 0 on success. If a PIO fallback is required then 1
290 static int scc_dma_setup(ide_drive_t *drive)
292 ide_hwif_t *hwif = drive->hwif;
293 struct request *rq = HWGROUP(drive)->rq;
294 unsigned int reading;
302 /* fall back to pio! */
303 if (!ide_build_dmatable(drive, rq)) {
304 ide_map_sg(drive, rq);
309 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
312 out_be32((void __iomem *)hwif->dma_command, reading);
314 /* read dma_status for INTR & ERROR flags */
315 dma_stat = in_be32((void __iomem *)hwif->dma_status);
317 /* clear INTR & ERROR flags */
318 out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
319 drive->waiting_for_dma = 1;
323 static void scc_dma_start(ide_drive_t *drive)
325 ide_hwif_t *hwif = drive->hwif;
326 u8 dma_cmd = scc_ide_inb(hwif->dma_command);
329 scc_ide_outb(dma_cmd | 1, hwif->dma_command);
334 static int __scc_dma_end(ide_drive_t *drive)
336 ide_hwif_t *hwif = drive->hwif;
337 u8 dma_stat, dma_cmd;
339 drive->waiting_for_dma = 0;
340 /* get DMA command mode */
341 dma_cmd = scc_ide_inb(hwif->dma_command);
343 scc_ide_outb(dma_cmd & ~1, hwif->dma_command);
345 dma_stat = scc_ide_inb(hwif->dma_status);
346 /* clear the INTR & ERROR bits */
347 scc_ide_outb(dma_stat | 6, hwif->dma_status);
348 /* purge DMA mappings */
349 ide_destroy_dmatable(drive);
350 /* verify good DMA status */
353 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
357 * scc_dma_end - Stop DMA
360 * Check and clear INT Status register.
361 * Then call __scc_dma_end().
364 static int scc_dma_end(ide_drive_t *drive)
366 ide_hwif_t *hwif = HWIF(drive);
367 unsigned long intsts_port = hwif->dma_base + 0x014;
369 int dma_stat, data_loss = 0;
370 static int retry = 0;
372 /* errata A308 workaround: Step5 (check data loss) */
373 /* We don't check non ide_disk because it is limited to UDMA4 */
374 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
376 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
377 reg = in_be32((void __iomem *)intsts_port);
378 if (!(reg & INTSTS_ACTEINT)) {
379 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
383 struct request *rq = HWGROUP(drive)->rq;
385 /* ERROR_RESET and drive->crc_count are needed
386 * to reduce DMA transfer mode in retry process.
389 rq->errors |= ERROR_RESET;
390 for (unit = 0; unit < MAX_DRIVES; unit++) {
391 ide_drive_t *drive = &hwif->drives[unit];
399 reg = in_be32((void __iomem *)intsts_port);
401 if (reg & INTSTS_SERROR) {
402 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
403 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
405 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
409 if (reg & INTSTS_PRERR) {
411 unsigned long ctl_base = hwif->config_data;
413 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
414 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
416 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
418 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
420 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
424 if (reg & INTSTS_RERR) {
425 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
426 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
428 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
432 if (reg & INTSTS_ICERR) {
433 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
435 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
436 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
440 if (reg & INTSTS_BMSINT) {
441 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
442 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
448 if (reg & INTSTS_BMHE) {
449 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
453 if (reg & INTSTS_ACTEINT) {
454 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
458 if (reg & INTSTS_IOIRQS) {
459 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
465 dma_stat = __scc_dma_end(drive);
467 dma_stat |= 2; /* emulate DMA error (to retry command) */
471 /* returns 1 if dma irq issued, 0 otherwise */
472 static int scc_dma_test_irq(ide_drive_t *drive)
474 ide_hwif_t *hwif = HWIF(drive);
475 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
477 /* SCC errata A252,A308 workaround: Step4 */
478 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
480 (int_stat & INTSTS_INTRQ))
483 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
484 if (int_stat & INTSTS_IOIRQS)
487 if (!drive->waiting_for_dma)
488 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
489 drive->name, __func__);
493 static u8 scc_udma_filter(ide_drive_t *drive)
495 ide_hwif_t *hwif = drive->hwif;
496 u8 mask = hwif->ultra_mask;
498 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
499 if ((drive->media != ide_disk) && (mask & 0xE0)) {
500 printk(KERN_INFO "%s: limit %s to UDMA4\n",
501 SCC_PATA_NAME, drive->name);
509 * setup_mmio_scc - map CTRL/BMID region
510 * @dev: PCI device we are configuring
515 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
517 unsigned long ctl_base = pci_resource_start(dev, 0);
518 unsigned long dma_base = pci_resource_start(dev, 1);
519 unsigned long ctl_size = pci_resource_len(dev, 0);
520 unsigned long dma_size = pci_resource_len(dev, 1);
521 void __iomem *ctl_addr;
522 void __iomem *dma_addr;
525 for (i = 0; i < MAX_HWIFS; i++) {
526 if (scc_ports[i].ctl == 0)
532 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
534 printk(KERN_ERR "%s: can't reserve resources\n", name);
538 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
541 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
545 scc_ports[i].ctl = (unsigned long)ctl_addr;
546 scc_ports[i].dma = (unsigned long)dma_addr;
547 pci_set_drvdata(dev, (void *) &scc_ports[i]);
557 static int scc_ide_setup_pci_device(struct pci_dev *dev,
558 const struct ide_port_info *d)
560 struct scc_ports *ports = pci_get_drvdata(dev);
561 ide_hwif_t *hwif = NULL;
562 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
563 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
566 hwif = ide_find_port_slot(d);
570 memset(&hw, 0, sizeof(hw));
571 for (i = 0; i <= 8; i++)
572 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
575 hw.chipset = ide_pci;
577 idx[0] = hwif->index;
579 ide_device_add(idx, d, hws);
585 * init_setup_scc - set up an SCC PATA Controller
589 * Perform the initial set up for this device.
592 static int __devinit init_setup_scc(struct pci_dev *dev,
593 const struct ide_port_info *d)
595 unsigned long ctl_base;
596 unsigned long dma_base;
597 unsigned long cckctrl_port;
598 unsigned long intmask_port;
599 unsigned long mode_port;
600 unsigned long ecmode_port;
601 unsigned long dma_status_port;
603 struct scc_ports *ports;
606 rc = pci_enable_device(dev);
610 rc = setup_mmio_scc(dev, d->name);
614 ports = pci_get_drvdata(dev);
615 ctl_base = ports->ctl;
616 dma_base = ports->dma;
617 cckctrl_port = ctl_base + 0xff0;
618 intmask_port = dma_base + 0x010;
619 mode_port = ctl_base + 0x024;
620 ecmode_port = ctl_base + 0xf00;
621 dma_status_port = dma_base + 0x004;
623 /* controller initialization */
625 out_be32((void*)cckctrl_port, reg);
626 reg |= CCKCTRL_ATACLKOEN;
627 out_be32((void*)cckctrl_port, reg);
628 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
629 out_be32((void*)cckctrl_port, reg);
631 out_be32((void*)cckctrl_port, reg);
634 reg = in_be32((void*)cckctrl_port);
635 if (reg & CCKCTRL_CRST)
640 reg |= CCKCTRL_ATARESET;
641 out_be32((void*)cckctrl_port, reg);
643 out_be32((void*)ecmode_port, ECMODE_VALUE);
644 out_be32((void*)mode_port, MODE_JCUSFEN);
645 out_be32((void*)intmask_port, INTMASK_MSK);
647 rc = scc_ide_setup_pci_device(dev, d);
653 static void scc_tf_load(ide_drive_t *drive, ide_task_t *task)
655 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
656 struct ide_taskfile *tf = &task->tf;
657 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
659 if (task->tf_flags & IDE_TFLAG_FLAGGED)
662 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
663 out_be32((void *)io_ports->data_addr,
664 (tf->hob_data << 8) | tf->data);
666 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
667 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
668 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
669 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
670 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
671 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
672 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
673 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
674 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
675 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
677 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
678 scc_ide_outb(tf->feature, io_ports->feature_addr);
679 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
680 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
681 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
682 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
683 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
684 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
685 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
686 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
688 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
689 scc_ide_outb((tf->device & HIHI) | drive->select.all,
690 io_ports->device_addr);
693 static void scc_tf_read(ide_drive_t *drive, ide_task_t *task)
695 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
696 struct ide_taskfile *tf = &task->tf;
698 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
699 u16 data = (u16)in_be32((void *)io_ports->data_addr);
701 tf->data = data & 0xff;
702 tf->hob_data = (data >> 8) & 0xff;
705 /* be sure we're looking at the low order bits */
706 scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
708 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
709 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
710 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
711 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
712 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
713 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
714 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
715 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
716 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
717 tf->device = scc_ide_inb(io_ports->device_addr);
719 if (task->tf_flags & IDE_TFLAG_LBA48) {
720 scc_ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
722 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
723 tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
724 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
725 tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
726 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
727 tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr);
728 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
729 tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr);
730 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
731 tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr);
735 static void scc_input_data(ide_drive_t *drive, struct request *rq,
736 void *buf, unsigned int len)
738 unsigned long data_addr = drive->hwif->io_ports.data_addr;
742 if (drive->io_32bit) {
743 scc_ide_insl(data_addr, buf, len / 4);
746 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
748 scc_ide_insw(data_addr, buf, len / 2);
751 static void scc_output_data(ide_drive_t *drive, struct request *rq,
752 void *buf, unsigned int len)
754 unsigned long data_addr = drive->hwif->io_ports.data_addr;
758 if (drive->io_32bit) {
759 scc_ide_outsl(data_addr, buf, len / 4);
762 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
764 scc_ide_outsw(data_addr, buf, len / 2);
768 * init_mmio_iops_scc - set up the iops for MMIO
769 * @hwif: interface to set up
773 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
775 struct pci_dev *dev = to_pci_dev(hwif->dev);
776 struct scc_ports *ports = pci_get_drvdata(dev);
777 unsigned long dma_base = ports->dma;
779 ide_set_hwifdata(hwif, ports);
781 hwif->read_sff_dma_status = scc_read_sff_dma_status;
783 hwif->tf_load = scc_tf_load;
784 hwif->tf_read = scc_tf_read;
786 hwif->input_data = scc_input_data;
787 hwif->output_data = scc_output_data;
789 hwif->INB = scc_ide_inb;
790 hwif->OUTB = scc_ide_outb;
791 hwif->OUTBSYNC = scc_ide_outbsync;
793 hwif->dma_base = dma_base;
794 hwif->config_data = ports->ctl;
798 * init_iops_scc - set up iops
799 * @hwif: interface to set up
801 * Do the basic setup for the SCC hardware interface
802 * and then do the MMIO setup.
805 static void __devinit init_iops_scc(ide_hwif_t *hwif)
807 struct pci_dev *dev = to_pci_dev(hwif->dev);
809 hwif->hwif_data = NULL;
810 if (pci_get_drvdata(dev) == NULL)
812 init_mmio_iops_scc(hwif);
815 static u8 __devinit scc_cable_detect(ide_hwif_t *hwif)
817 return ATA_CBL_PATA80;
821 * init_hwif_scc - set up hwif
822 * @hwif: interface to set up
824 * We do the basic set up of the interface structure. The SCC
825 * requires several custom handlers so we override the default
826 * ide DMA handlers appropriately.
829 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
831 struct scc_ports *ports = ide_get_hwifdata(hwif);
835 hwif->dma_command = hwif->dma_base;
836 hwif->dma_status = hwif->dma_base + 0x04;
839 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
841 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
842 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
844 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
847 static const struct ide_port_ops scc_port_ops = {
848 .set_pio_mode = scc_set_pio_mode,
849 .set_dma_mode = scc_set_dma_mode,
850 .udma_filter = scc_udma_filter,
851 .cable_detect = scc_cable_detect,
854 static const struct ide_dma_ops scc_dma_ops = {
855 .dma_host_set = scc_dma_host_set,
856 .dma_setup = scc_dma_setup,
857 .dma_exec_cmd = ide_dma_exec_cmd,
858 .dma_start = scc_dma_start,
859 .dma_end = scc_dma_end,
860 .dma_test_irq = scc_dma_test_irq,
861 .dma_lost_irq = ide_dma_lost_irq,
862 .dma_timeout = ide_dma_timeout,
865 #define DECLARE_SCC_DEV(name_str) \
868 .init_iops = init_iops_scc, \
869 .init_hwif = init_hwif_scc, \
870 .port_ops = &scc_port_ops, \
871 .dma_ops = &scc_dma_ops, \
872 .host_flags = IDE_HFLAG_SINGLE, \
873 .pio_mask = ATA_PIO4, \
876 static const struct ide_port_info scc_chipsets[] __devinitdata = {
877 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
881 * scc_init_one - pci layer discovery entry
883 * @id: ident table entry
885 * Called by the PCI code when it finds an SCC PATA controller.
886 * We then use the IDE PCI generic helper to do most of the work.
889 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
891 return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
895 * scc_remove - pci layer remove entry
898 * Called by the PCI code when it removes an SCC PATA controller.
901 static void __devexit scc_remove(struct pci_dev *dev)
903 struct scc_ports *ports = pci_get_drvdata(dev);
904 ide_hwif_t *hwif = ports->hwif;
906 if (hwif->dmatable_cpu) {
907 pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES,
908 hwif->dmatable_cpu, hwif->dmatable_dma);
909 hwif->dmatable_cpu = NULL;
912 ide_unregister(hwif);
914 iounmap((void*)ports->dma);
915 iounmap((void*)ports->ctl);
916 pci_release_selected_regions(dev, (1 << 2) - 1);
917 memset(ports, 0, sizeof(*ports));
920 static const struct pci_device_id scc_pci_tbl[] = {
921 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
924 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
926 static struct pci_driver driver = {
928 .id_table = scc_pci_tbl,
929 .probe = scc_init_one,
930 .remove = scc_remove,
933 static int scc_ide_init(void)
935 return ide_pci_register_driver(&driver);
938 module_init(scc_ide_init);
940 static void scc_ide_exit(void)
942 ide_pci_unregister_driver(&driver);
944 module_exit(scc_ide_exit);
948 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
949 MODULE_LICENSE("GPL");