2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
3 * Copyright (C) 2008 MontaVista Software, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License
7 * as published by the Free Software Foundation.
9 * This program is distributed in the hope that it would be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 * You should have received a copy of the GNU General Public
14 * License along with this program; if not, write the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 * For further information regarding this notice, see:
19 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/ioport.h>
29 #include <linux/blkdev.h>
30 #include <linux/scatterlist.h>
31 #include <linux/ioc4.h>
34 #include <linux/ide.h>
36 #define DRV_NAME "SGIIOC4"
38 /* IOC4 Specific Definitions */
39 #define IOC4_CMD_OFFSET 0x100
40 #define IOC4_CTRL_OFFSET 0x120
41 #define IOC4_DMA_OFFSET 0x140
42 #define IOC4_INTR_OFFSET 0x0
44 #define IOC4_TIMING 0x00
45 #define IOC4_DMA_PTR_L 0x01
46 #define IOC4_DMA_PTR_H 0x02
47 #define IOC4_DMA_ADDR_L 0x03
48 #define IOC4_DMA_ADDR_H 0x04
49 #define IOC4_BC_DEV 0x05
50 #define IOC4_BC_MEM 0x06
51 #define IOC4_DMA_CTRL 0x07
52 #define IOC4_DMA_END_ADDR 0x08
54 /* Bits in the IOC4 Control/Status Register */
55 #define IOC4_S_DMA_START 0x01
56 #define IOC4_S_DMA_STOP 0x02
57 #define IOC4_S_DMA_DIR 0x04
58 #define IOC4_S_DMA_ACTIVE 0x08
59 #define IOC4_S_DMA_ERROR 0x10
60 #define IOC4_ATA_MEMERR 0x02
62 /* Read/Write Directions */
63 #define IOC4_DMA_WRITE 0x04
64 #define IOC4_DMA_READ 0x00
66 /* Interrupt Register Offsets */
67 #define IOC4_INTR_REG 0x03
68 #define IOC4_INTR_SET 0x05
69 #define IOC4_INTR_CLEAR 0x07
71 #define IOC4_IDE_CACHELINE_SIZE 128
72 #define IOC4_CMD_CTL_BLK_SIZE 0x20
73 #define IOC4_SUPPORTED_FIRMWARE_REV 46
87 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
88 /* IOC4 has only 1 IDE channel */
89 #define IOC4_PRD_BYTES 16
90 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
94 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
95 unsigned long ctrl_port, unsigned long irq_port)
97 unsigned long reg = data_port;
100 /* Registers are word (32 bit) aligned */
101 for (i = 0; i <= 7; i++)
102 hw->io_ports_array[i] = reg + i * 4;
105 hw->io_ports.ctl_addr = ctrl_port;
108 hw->io_ports.irq_addr = irq_port;
112 sgiioc4_maskproc(ide_drive_t * drive, int mask)
114 writeb(ATA_DEVCTL_OBS | (mask ? 2 : 0),
115 (void __iomem *)drive->hwif->io_ports.ctl_addr);
119 sgiioc4_checkirq(ide_hwif_t * hwif)
121 unsigned long intr_addr =
122 hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
124 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
130 static u8 sgiioc4_read_status(ide_hwif_t *);
133 sgiioc4_clearirq(ide_drive_t * drive)
136 ide_hwif_t *hwif = HWIF(drive);
137 struct ide_io_ports *io_ports = &hwif->io_ports;
138 unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
140 /* Code to check for PCI error conditions */
141 intr_reg = readl((void __iomem *)other_ir);
142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
144 * Using sgiioc4_read_status to read the Status register has a
145 * side effect of clearing the interrupt. The first read should
146 * clear it if it is set. The second read should return
147 * a "clear" status if it got cleared. If not, then spin
148 * for a bit trying to clear it.
150 u8 stat = sgiioc4_read_status(hwif);
153 stat = sgiioc4_read_status(hwif);
154 while ((stat & ATA_BUSY) && (count++ < 100)) {
156 stat = sgiioc4_read_status(hwif);
159 if (intr_reg & 0x02) {
160 struct pci_dev *dev = to_pci_dev(hwif->dev);
161 /* Error when transferring DMA data on PCI bus */
162 u32 pci_err_addr_low, pci_err_addr_high,
166 readl((void __iomem *)io_ports->irq_addr);
168 readl((void __iomem *)(io_ports->irq_addr + 4));
169 pci_read_config_dword(dev, PCI_COMMAND,
172 "%s(%s) : PCI Bus Error when doing DMA:"
173 " status-cmd reg is 0x%x\n",
174 __func__, drive->name, pci_stat_cmd_reg);
176 "%s(%s) : PCI Error Address is 0x%x%x\n",
177 __func__, drive->name,
178 pci_err_addr_high, pci_err_addr_low);
179 /* Clear the PCI Error indicator */
180 pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
183 /* Clear the Interrupt, Error bits on the IOC4 */
184 writel(0x03, (void __iomem *)other_ir);
186 intr_reg = readl((void __iomem *)other_ir);
192 static void sgiioc4_dma_start(ide_drive_t *drive)
194 ide_hwif_t *hwif = HWIF(drive);
195 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
196 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
197 unsigned int temp_reg = reg | IOC4_S_DMA_START;
199 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
203 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
205 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
210 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
211 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
213 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
218 /* Stops the IOC4 DMA Engine */
219 static int sgiioc4_dma_end(ide_drive_t *drive)
221 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
222 ide_hwif_t *hwif = HWIF(drive);
223 unsigned long dma_base = hwif->dma_base;
225 unsigned long *ending_dma = ide_get_hwifdata(hwif);
227 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
229 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
231 if (ioc4_dma & IOC4_S_DMA_STOP) {
233 "%s(%s): IOC4 DMA STOP bit is still 1 :"
234 "ioc4_dma_reg 0x%x\n",
235 __func__, drive->name, ioc4_dma);
240 * The IOC4 will DMA 1's to the ending dma area to indicate that
241 * previous data DMA is complete. This is necessary because of relaxed
242 * ordering between register reads and DMA writes on the Altix.
244 while ((cnt++ < 200) && (!valid)) {
245 for (num = 0; num < 16; num++) {
246 if (ending_dma[num]) {
254 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __func__,
259 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
260 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
262 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
263 if (bc_dev > bc_mem + 8) {
265 "%s(%s): WARNING!! byte_count_dev %d "
266 "!= byte_count_mem %d\n",
267 __func__, drive->name, bc_dev, bc_mem);
271 drive->waiting_for_dma = 0;
272 ide_destroy_dmatable(drive);
277 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
281 /* returns 1 if dma irq issued, 0 otherwise */
282 static int sgiioc4_dma_test_irq(ide_drive_t *drive)
284 return sgiioc4_checkirq(HWIF(drive));
287 static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
290 sgiioc4_clearirq(drive);
294 sgiioc4_resetproc(ide_drive_t * drive)
296 sgiioc4_dma_end(drive);
297 sgiioc4_clearirq(drive);
301 sgiioc4_dma_lost_irq(ide_drive_t * drive)
303 sgiioc4_resetproc(drive);
305 ide_dma_lost_irq(drive);
308 static u8 sgiioc4_read_status(ide_hwif_t *hwif)
310 unsigned long port = hwif->io_ports.status_addr;
311 u8 reg = (u8) readb((void __iomem *) port);
313 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
314 if (!(reg & ATA_BUSY)) { /* Not busy... check for interrupt */
315 unsigned long other_ir = port - 0x110;
316 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
318 /* Clear the Interrupt, Error bits on the IOC4 */
319 if (intr_reg & 0x03) {
320 writel(0x03, (void __iomem *) other_ir);
321 intr_reg = (u32) readl((void __iomem *) other_ir);
329 /* Creates a dma map for the scatter-gather list entries */
331 ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
333 struct pci_dev *dev = to_pci_dev(hwif->dev);
334 unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
335 void __iomem *virt_dma_base;
336 int num_ports = sizeof (ioc4_dma_regs_t);
342 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
344 if (request_mem_region(dma_base, num_ports, hwif->name) == NULL) {
345 printk(KERN_ERR "%s(%s) -- ERROR: addresses 0x%08lx to 0x%08lx "
346 "already in use\n", __func__, hwif->name,
347 dma_base, dma_base + num_ports - 1);
351 virt_dma_base = ioremap(dma_base, num_ports);
352 if (virt_dma_base == NULL) {
353 printk(KERN_ERR "%s(%s) -- ERROR: unable to map addresses "
354 "0x%lx to 0x%lx\n", __func__, hwif->name,
355 dma_base, dma_base + num_ports - 1);
356 goto dma_remap_failure;
358 hwif->dma_base = (unsigned long) virt_dma_base;
360 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
362 hwif->prd_max_nents = IOC4_PRD_ENTRIES;
363 hwif->prd_ent_size = IOC4_PRD_BYTES;
365 if (ide_allocate_dma_engine(hwif))
366 goto dma_pci_alloc_failure;
368 pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
369 (dma_addr_t *)&hwif->extra_base);
371 ide_set_hwifdata(hwif, pad);
375 ide_release_dma_engine(hwif);
377 printk(KERN_ERR "%s(%s) -- ERROR: Unable to allocate DMA maps\n",
378 __func__, hwif->name);
379 printk(KERN_INFO "%s: changing from DMA to PIO mode", hwif->name);
381 dma_pci_alloc_failure:
382 iounmap(virt_dma_base);
385 release_mem_region(dma_base, num_ports);
390 /* Initializes the IOC4 DMA Engine */
392 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
395 ide_hwif_t *hwif = HWIF(drive);
396 unsigned long dma_base = hwif->dma_base;
397 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
398 u32 dma_addr, ending_dma_addr;
400 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
402 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
404 "%s(%s):Warning!! DMA from previous transfer was still active\n",
405 __func__, drive->name);
406 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
407 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
409 if (ioc4_dma & IOC4_S_DMA_STOP)
411 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
412 __func__, drive->name);
415 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
416 if (ioc4_dma & IOC4_S_DMA_ERROR) {
418 "%s(%s) : Warning!! - DMA Error during Previous"
419 " transfer | status 0x%x\n",
420 __func__, drive->name, ioc4_dma);
421 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
422 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
424 if (ioc4_dma & IOC4_S_DMA_STOP)
426 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
427 __func__, drive->name);
430 /* Address of the Scatter Gather List */
431 dma_addr = cpu_to_le32(hwif->dmatable_dma);
432 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
434 /* Address of the Ending DMA */
435 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
436 ending_dma_addr = cpu_to_le32(hwif->extra_base);
437 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
439 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
440 drive->waiting_for_dma = 1;
443 /* IOC4 Scatter Gather list Format */
444 /* 128 Bit entries to support 64 bit addresses in the future */
445 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
446 /* --------------------------------------------------------------------- */
447 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
448 /* --------------------------------------------------------------------- */
449 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
450 /* --------------------------------------------------------------------- */
451 /* Creates the scatter gather list, DMA Table */
453 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
455 ide_hwif_t *hwif = HWIF(drive);
456 unsigned int *table = hwif->dmatable_cpu;
457 unsigned int count = 0, i = 1;
458 struct scatterlist *sg;
460 hwif->sg_nents = i = ide_build_sglist(drive, rq);
463 return 0; /* sglist of length Zero */
466 while (i && sg_dma_len(sg)) {
469 cur_addr = sg_dma_address(sg);
470 cur_len = sg_dma_len(sg);
473 if (count++ >= IOC4_PRD_ENTRIES) {
475 "%s: DMA table too small\n",
477 goto use_pio_instead;
480 0x10000 - (cur_addr & 0xffff);
482 if (bcount > cur_len)
485 /* put the addr, length in
486 * the IOC4 dma-table format */
489 *table = cpu_to_be32(cur_addr);
494 *table = cpu_to_be32(bcount);
508 *table |= cpu_to_be32(0x80000000);
513 ide_destroy_dmatable(drive);
515 return 0; /* revert to PIO for this request */
518 static int sgiioc4_dma_setup(ide_drive_t *drive)
520 struct request *rq = HWGROUP(drive)->rq;
521 unsigned int count = 0;
525 ddir = PCI_DMA_TODEVICE;
527 ddir = PCI_DMA_FROMDEVICE;
529 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
530 /* try PIO instead of DMA */
531 ide_map_sg(drive, rq);
536 /* Writes TO the IOC4 FROM Main Memory */
537 ddir = IOC4_DMA_READ;
539 /* Writes FROM the IOC4 TO Main Memory */
540 ddir = IOC4_DMA_WRITE;
542 sgiioc4_configure_for_dma(ddir, drive);
547 static const struct ide_tp_ops sgiioc4_tp_ops = {
548 .exec_command = ide_exec_command,
549 .read_status = sgiioc4_read_status,
550 .read_altstatus = ide_read_altstatus,
551 .read_sff_dma_status = ide_read_sff_dma_status,
553 .set_irq = ide_set_irq,
555 .tf_load = ide_tf_load,
556 .tf_read = ide_tf_read,
558 .input_data = ide_input_data,
559 .output_data = ide_output_data,
562 static const struct ide_port_ops sgiioc4_port_ops = {
563 .set_dma_mode = sgiioc4_set_dma_mode,
564 /* reset DMA engine, clear IRQs */
565 .resetproc = sgiioc4_resetproc,
566 /* mask on/off NIEN register */
567 .maskproc = sgiioc4_maskproc,
570 static const struct ide_dma_ops sgiioc4_dma_ops = {
571 .dma_host_set = sgiioc4_dma_host_set,
572 .dma_setup = sgiioc4_dma_setup,
573 .dma_start = sgiioc4_dma_start,
574 .dma_end = sgiioc4_dma_end,
575 .dma_test_irq = sgiioc4_dma_test_irq,
576 .dma_lost_irq = sgiioc4_dma_lost_irq,
577 .dma_timeout = ide_dma_timeout,
580 static const struct ide_port_info sgiioc4_port_info __devinitdata = {
583 .init_dma = ide_dma_sgiioc4,
584 .tp_ops = &sgiioc4_tp_ops,
585 .port_ops = &sgiioc4_port_ops,
586 .dma_ops = &sgiioc4_dma_ops,
587 .host_flags = IDE_HFLAG_MMIO,
588 .mwdma_mask = ATA_MWDMA2_ONLY,
592 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
594 unsigned long cmd_base, irqport;
595 unsigned long bar0, cmd_phys_base, ctl;
596 void __iomem *virt_base;
597 struct ide_host *host;
598 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
599 struct ide_port_info d = sgiioc4_port_info;
602 /* Get the CmdBlk and CtrlBlk Base Registers */
603 bar0 = pci_resource_start(dev, 0);
604 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
605 if (virt_base == NULL) {
606 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
610 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
611 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
612 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
614 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
615 if (request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
617 printk(KERN_ERR "%s %s -- ERROR: addresses 0x%08lx to 0x%08lx "
618 "already in use\n", DRV_NAME, pci_name(dev),
619 cmd_phys_base, cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
623 /* Initialize the IO registers */
624 memset(&hw, 0, sizeof(hw));
625 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
627 hw.chipset = ide_pci;
630 /* Initializing chipset IRQ Registers */
631 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
633 host = ide_host_alloc(&d, hws);
639 rc = ide_host_register(host, &d, hws);
647 release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE);
652 static unsigned int __devinit
653 pci_init_sgiioc4(struct pci_dev *dev)
657 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
658 DRV_NAME, pci_name(dev), dev->revision);
660 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
661 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
662 "firmware is obsolete - please upgrade to "
663 "revision46 or higher\n",
664 DRV_NAME, pci_name(dev));
668 ret = sgiioc4_ide_setup_pci_device(dev);
674 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
676 /* PCI-RT does not bring out IDE connection.
677 * Do not attach to this particular IOC4.
679 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
682 return pci_init_sgiioc4(idd->idd_pdev);
685 static struct ioc4_submodule ioc4_ide_submodule = {
686 .is_name = "IOC4_ide",
687 .is_owner = THIS_MODULE,
688 .is_probe = ioc4_ide_attach_one,
689 /* .is_remove = ioc4_ide_remove_one, */
692 static int __init ioc4_ide_init(void)
694 return ioc4_register_submodule(&ioc4_ide_submodule);
697 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
699 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
700 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
701 MODULE_LICENSE("GPL");