2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
41 * InfiniPath I2C driver for a serial eeprom. This is not a generic
42 * I2C interface. For a start, the device we're using (Atmel AT24C11)
43 * doesn't work like a regular I2C device. It looks like one
44 * electrically, but not logically. Normal I2C devices have a single
45 * 7-bit or 10-bit I2C address that they respond to. Valid 7-bit
46 * addresses range from 0x03 to 0x77. Addresses 0x00 to 0x02 and 0x78
47 * to 0x7F are special reserved addresses (e.g. 0x00 is the "general
48 * call" address.) The Atmel device, on the other hand, responds to ALL
49 * 7-bit addresses. It's designed to be the only device on a given I2C
50 * bus. A 7-bit address corresponds to the memory address within the
51 * Atmel device itself.
53 * Also, the timing requirements mean more than simple software
54 * bitbanging, with readbacks from chip to ensure timing (simple udelay
57 * This all means that accessing the device is specialized enough
58 * that using the standard kernel I2C bitbanging interface would be
59 * impossible. For example, the core I2C eeprom driver expects to find
60 * a device at one or more of a limited set of addresses only. It doesn't
61 * allow writing to an eeprom. It also doesn't provide any means of
62 * accessing eeprom contents from within the kernel, only via sysfs.
78 static int eeprom_init;
81 * The gpioval manipulation really should be protected by spinlocks
82 * or be converted to use atomic operations.
86 * i2c_gpio_set - set a GPIO line
87 * @dd: the infinipath device
88 * @line: the line to set
89 * @new_line_state: the state to set
91 * Returns 0 if the line was set to the new state successfully, non-zero
94 static int i2c_gpio_set(struct ipath_devdata *dd,
96 enum i2c_state new_line_state)
98 u64 out_mask, dir_mask, *gpioval;
99 unsigned long flags = 0;
101 gpioval = &dd->ipath_gpio_out;
103 if (line == i2c_line_scl) {
104 dir_mask = dd->ipath_gpio_scl;
105 out_mask = (1UL << dd->ipath_gpio_scl_num);
107 dir_mask = dd->ipath_gpio_sda;
108 out_mask = (1UL << dd->ipath_gpio_sda_num);
111 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
112 if (new_line_state == i2c_line_high) {
113 /* tri-state the output rather than force high */
114 dd->ipath_extctrl &= ~dir_mask;
116 /* config line to be an output */
117 dd->ipath_extctrl |= dir_mask;
119 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, dd->ipath_extctrl);
121 /* set output as well (no real verify) */
122 if (new_line_state == i2c_line_high)
123 *gpioval |= out_mask;
125 *gpioval &= ~out_mask;
127 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_out, *gpioval);
128 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
134 * i2c_gpio_get - get a GPIO line state
135 * @dd: the infinipath device
136 * @line: the line to get
137 * @curr_statep: where to put the line state
139 * Returns 0 if the line was set to the new state successfully, non-zero
140 * on error. curr_state is not set on error.
142 static int i2c_gpio_get(struct ipath_devdata *dd,
144 enum i2c_state *curr_statep)
148 unsigned long flags = 0;
151 if (curr_statep == NULL) {
156 /* config line to be an input */
157 if (line == i2c_line_scl)
158 mask = dd->ipath_gpio_scl;
160 mask = dd->ipath_gpio_sda;
162 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
163 dd->ipath_extctrl &= ~mask;
164 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, dd->ipath_extctrl);
166 * Below is very unlikely to reflect true input state if Output
167 * Enable actually changed.
169 read_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
170 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
173 *curr_statep = i2c_line_high;
175 *curr_statep = i2c_line_low;
184 * i2c_wait_for_writes - wait for a write
185 * @dd: the infinipath device
187 * We use this instead of udelay directly, so we can make sure
188 * that previous register writes have been flushed all the way
189 * to the chip. Since we are delaying anyway, the cost doesn't
190 * hurt, and makes the bit twiddling more regular
192 static void i2c_wait_for_writes(struct ipath_devdata *dd)
194 (void)ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
198 static void scl_out(struct ipath_devdata *dd, u8 bit)
201 i2c_gpio_set(dd, i2c_line_scl, bit ? i2c_line_high : i2c_line_low);
203 i2c_wait_for_writes(dd);
206 static void sda_out(struct ipath_devdata *dd, u8 bit)
208 i2c_gpio_set(dd, i2c_line_sda, bit ? i2c_line_high : i2c_line_low);
210 i2c_wait_for_writes(dd);
213 static u8 sda_in(struct ipath_devdata *dd, int wait)
217 if (i2c_gpio_get(dd, i2c_line_sda, &bit))
218 ipath_dbg("get bit failed!\n");
221 i2c_wait_for_writes(dd);
223 return bit == i2c_line_high ? 1U : 0;
227 * i2c_ackrcv - see if ack following write is true
228 * @dd: the infinipath device
230 static int i2c_ackrcv(struct ipath_devdata *dd)
234 /* AT ENTRY SCL = LOW */
235 /* change direction, ignore data */
236 ack_received = sda_in(dd, 1);
237 scl_out(dd, i2c_line_high);
238 ack_received = sda_in(dd, 1) == 0;
239 scl_out(dd, i2c_line_low);
244 * wr_byte - write a byte, one bit at a time
245 * @dd: the infinipath device
246 * @data: the byte to write
248 * Returns 0 if we got the following ack, otherwise 1
250 static int wr_byte(struct ipath_devdata *dd, u8 data)
255 for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
256 bit = (data >> bit_cntr) & 1;
258 scl_out(dd, i2c_line_high);
259 scl_out(dd, i2c_line_low);
261 return (!i2c_ackrcv(dd)) ? 1 : 0;
264 static void send_ack(struct ipath_devdata *dd)
266 sda_out(dd, i2c_line_low);
267 scl_out(dd, i2c_line_high);
268 scl_out(dd, i2c_line_low);
269 sda_out(dd, i2c_line_high);
273 * i2c_startcmd - transmit the start condition, followed by address/cmd
274 * @dd: the infinipath device
275 * @offset_dir: direction byte
277 * (both clock/data high, clock high, data low while clock is high)
279 static int i2c_startcmd(struct ipath_devdata *dd, u8 offset_dir)
283 /* issue start sequence */
284 sda_out(dd, i2c_line_high);
285 scl_out(dd, i2c_line_high);
286 sda_out(dd, i2c_line_low);
287 scl_out(dd, i2c_line_low);
289 /* issue length and direction byte */
290 res = wr_byte(dd, offset_dir);
293 ipath_cdbg(VERBOSE, "No ack to complete start\n");
299 * stop_cmd - transmit the stop condition
300 * @dd: the infinipath device
302 * (both clock/data low, clock high, data high while clock is high)
304 static void stop_cmd(struct ipath_devdata *dd)
306 scl_out(dd, i2c_line_low);
307 sda_out(dd, i2c_line_low);
308 scl_out(dd, i2c_line_high);
309 sda_out(dd, i2c_line_high);
314 * eeprom_reset - reset I2C communication
315 * @dd: the infinipath device
318 static int eeprom_reset(struct ipath_devdata *dd)
320 int clock_cycles_left = 9;
321 u64 *gpioval = &dd->ipath_gpio_out;
325 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
326 /* Make sure shadows are consistent */
327 dd->ipath_extctrl = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extctrl);
328 *gpioval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_out);
329 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
331 ipath_cdbg(VERBOSE, "Resetting i2c eeprom; initial gpioout reg "
332 "is %llx\n", (unsigned long long) *gpioval);
336 * This is to get the i2c into a known state, by first going low,
337 * then tristate sda (and then tristate scl as first thing
340 scl_out(dd, i2c_line_low);
341 sda_out(dd, i2c_line_high);
343 while (clock_cycles_left--) {
344 scl_out(dd, i2c_line_high);
347 sda_out(dd, i2c_line_low);
348 scl_out(dd, i2c_line_low);
353 scl_out(dd, i2c_line_low);
363 * ipath_eeprom_read - receives bytes from the eeprom via I2C
364 * @dd: the infinipath device
365 * @eeprom_offset: address to read from
366 * @buffer: where to store result
367 * @len: number of bytes to receive
370 int ipath_eeprom_read(struct ipath_devdata *dd, u8 eeprom_offset,
371 void *buffer, int len)
373 /* compiler complains unless initialized */
381 eeprom_offset = (eeprom_offset << 1) | READ_CMD;
383 if (i2c_startcmd(dd, eeprom_offset)) {
384 ipath_dbg("Failed startcmd\n");
391 * eeprom keeps clocking data out as long as we ack, automatically
392 * incrementing the address.
397 for (bit_cntr = 8; bit_cntr; bit_cntr--) {
399 scl_out(dd, i2c_line_high);
401 single_byte |= bit << (bit_cntr - 1);
402 scl_out(dd, i2c_line_low);
405 /* send ack if not the last byte */
409 *((u8 *) buffer) = single_byte;
422 * ipath_eeprom_write - writes data to the eeprom via I2C
423 * @dd: the infinipath device
424 * @eeprom_offset: where to place data
425 * @buffer: data to write
426 * @len: number of bytes to write
428 int ipath_eeprom_write(struct ipath_devdata *dd, u8 eeprom_offset,
429 const void *buffer, int len)
433 const u8 *bp = buffer;
434 int max_wait_time, i;
441 if (i2c_startcmd(dd, (eeprom_offset << 1) | WRITE_CMD)) {
442 ipath_dbg("Failed to start cmd offset %u\n",
447 sub_len = min(len, 4);
448 eeprom_offset += sub_len;
451 for (i = 0; i < sub_len; i++) {
452 if (wr_byte(dd, *bp++)) {
453 ipath_dbg("no ack after byte %u/%u (%u "
454 "total remain)\n", i, sub_len,
463 * wait for write complete by waiting for a successful
464 * read (the chip replies with a zero after the write
465 * cmd completes, and before it writes to the eeprom.
466 * The startcmd for the read will fail the ack until
467 * the writes have completed. We do this inline to avoid
468 * the debug prints that are in the real read routine
469 * if the startcmd fails.
472 while (i2c_startcmd(dd, READ_CMD)) {
474 if (!--max_wait_time) {
475 ipath_dbg("Did not get successful read to "
480 /* now read the zero byte */
481 for (i = single_byte = 0; i < 8; i++) {
483 scl_out(dd, i2c_line_high);
485 scl_out(dd, i2c_line_low);
503 static u8 flash_csum(struct ipath_flash *ifp, int adjust)
508 for (len = 0; len < ifp->if_length; len++)
510 csum -= ifp->if_csum;
519 * ipath_get_guid - get the GUID from the i2c device
520 * @dd: the infinipath device
522 * We have the capability to use the ipath_nguid field, and get
523 * the guid from the first chip's flash, to use for all of them.
525 void ipath_get_eeprom_info(struct ipath_devdata *dd)
528 struct ipath_flash *ifp;
532 int t = dd->ipath_unit;
533 struct ipath_devdata *dd0 = ipath_lookup(0);
535 if (t && dd0->ipath_nguid > 1 && t <= dd0->ipath_nguid) {
537 dd->ipath_guid = dd0->ipath_guid;
538 bguid = (u8 *) & dd->ipath_guid;
542 if (oguid > bguid[7]) {
543 if (bguid[6] == 0xff) {
544 if (bguid[5] == 0xff) {
547 "Can't set %s GUID from "
548 "base, wraps to OUI!\n",
549 ipath_get_unit_name(t));
559 ipath_dbg("nguid %u, so adding %u to device 0 guid, "
562 (unsigned long long) be64_to_cpu(dd->ipath_guid));
566 len = offsetof(struct ipath_flash, if_future);
569 ipath_dev_err(dd, "Couldn't allocate memory to read %u "
570 "bytes from eeprom for GUID\n", len);
574 if (ipath_eeprom_read(dd, 0, buf, len)) {
575 ipath_dev_err(dd, "Failed reading GUID from eeprom\n");
578 ifp = (struct ipath_flash *)buf;
580 csum = flash_csum(ifp, 0);
581 if (csum != ifp->if_csum) {
582 dev_info(&dd->pcidev->dev, "Bad I2C flash checksum: "
583 "0x%x, not 0x%x\n", csum, ifp->if_csum);
586 if (*(__be64 *) ifp->if_guid == 0ULL ||
587 *(__be64 *) ifp->if_guid == __constant_cpu_to_be64(-1LL)) {
588 ipath_dev_err(dd, "Invalid GUID %llx from flash; "
590 *(unsigned long long *) ifp->if_guid);
591 /* don't allow GUID if all 0 or all 1's */
595 /* complain, but allow it */
596 if (*(u64 *) ifp->if_guid == 0x100007511000000ULL)
597 dev_info(&dd->pcidev->dev, "Warning, GUID %llx is "
598 "default, probably not correct!\n",
599 *(unsigned long long *) ifp->if_guid);
601 bguid = ifp->if_guid;
602 if (!bguid[0] && !bguid[1] && !bguid[2]) {
603 /* original incorrect GUID format in flash; fix in
604 * core copy, by shifting up 2 octets; don't need to
605 * change top octet, since both it and shifted are
609 bguid[3] = bguid[4] = 0;
610 guid = *(__be64 *) ifp->if_guid;
611 ipath_cdbg(VERBOSE, "Old GUID format in flash, top 3 zero, "
612 "shifting 2 octets\n");
614 guid = *(__be64 *) ifp->if_guid;
615 dd->ipath_guid = guid;
616 dd->ipath_nguid = ifp->if_numguid;
618 * Things are slightly complicated by the desire to transparently
619 * support both the Pathscale 10-digit serial number and the QLogic
620 * 13-character version.
622 if ((ifp->if_fversion > 1) && ifp->if_sprefix[0]
623 && ((u8 *)ifp->if_sprefix)[0] != 0xFF) {
624 /* This board has a Serial-prefix, which is stored
625 * elsewhere for backward-compatibility.
627 char *snp = dd->ipath_serial;
629 memcpy(snp, ifp->if_sprefix, sizeof ifp->if_sprefix);
630 snp[sizeof ifp->if_sprefix] = '\0';
633 len = (sizeof dd->ipath_serial) - len;
634 if (len > sizeof ifp->if_serial) {
635 len = sizeof ifp->if_serial;
637 memcpy(snp, ifp->if_serial, len);
639 memcpy(dd->ipath_serial, ifp->if_serial,
640 sizeof ifp->if_serial);
641 if (!strstr(ifp->if_comment, "Tested successfully"))
642 ipath_dev_err(dd, "Board SN %s did not pass functional "
643 "test: %s\n", dd->ipath_serial,
646 ipath_cdbg(VERBOSE, "Initted GUID to %llx from eeprom\n",
647 (unsigned long long) be64_to_cpu(dd->ipath_guid));