drivers/infiniband/hw/ipath/ipath_iba6120.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 /*
  34  * This file contains all of the code that is specific to the
  35  * InfiniPath PCIe chip.
  36  */
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
  47
  48 /*
  49  * This file contains all the chip-specific register information and
  50  * access functions for the QLogic InfiniPath PCI-Express chip.
  51  *
  52  * This lists the InfiniPath registers, in the actual chip layout.
  53  * This structure should never be directly accessed.
  54  */
  55 struct _infinipath_do_not_use_kernel_regs {
  56         unsigned long long Revision;
  57         unsigned long long Control;
  58         unsigned long long PageAlign;
  59         unsigned long long PortCnt;
  60         unsigned long long DebugPortSelect;
  61         unsigned long long Reserved0;
  62         unsigned long long SendRegBase;
  63         unsigned long long UserRegBase;
  64         unsigned long long CounterRegBase;
  65         unsigned long long Scratch;
  66         unsigned long long Reserved1;
  67         unsigned long long Reserved2;
  68         unsigned long long IntBlocked;
  69         unsigned long long IntMask;
  70         unsigned long long IntStatus;
  71         unsigned long long IntClear;
  72         unsigned long long ErrorMask;
  73         unsigned long long ErrorStatus;
  74         unsigned long long ErrorClear;
  75         unsigned long long HwErrMask;
  76         unsigned long long HwErrStatus;
  77         unsigned long long HwErrClear;
  78         unsigned long long HwDiagCtrl;
  79         unsigned long long MDIO;
  80         unsigned long long IBCStatus;
  81         unsigned long long IBCCtrl;
  82         unsigned long long ExtStatus;
  83         unsigned long long ExtCtrl;
  84         unsigned long long GPIOOut;
  85         unsigned long long GPIOMask;
  86         unsigned long long GPIOStatus;
  87         unsigned long long GPIOClear;
  88         unsigned long long RcvCtrl;
  89         unsigned long long RcvBTHQP;
  90         unsigned long long RcvHdrSize;
  91         unsigned long long RcvHdrCnt;
  92         unsigned long long RcvHdrEntSize;
  93         unsigned long long RcvTIDBase;
  94         unsigned long long RcvTIDCnt;
  95         unsigned long long RcvEgrBase;
  96         unsigned long long RcvEgrCnt;
  97         unsigned long long RcvBufBase;
  98         unsigned long long RcvBufSize;
  99         unsigned long long RxIntMemBase;
 100         unsigned long long RxIntMemSize;
 101         unsigned long long RcvPartitionKey;
 102         unsigned long long Reserved3;
 103         unsigned long long RcvPktLEDCnt;
 104         unsigned long long Reserved4[8];
 105         unsigned long long SendCtrl;
 106         unsigned long long SendPIOBufBase;
 107         unsigned long long SendPIOSize;
 108         unsigned long long SendPIOBufCnt;
 109         unsigned long long SendPIOAvailAddr;
 110         unsigned long long TxIntMemBase;
 111         unsigned long long TxIntMemSize;
 112         unsigned long long Reserved5;
 113         unsigned long long PCIeRBufTestReg0;
 114         unsigned long long PCIeRBufTestReg1;
 115         unsigned long long Reserved51[6];
 116         unsigned long long SendBufferError;
 117         unsigned long long SendBufferErrorCONT1;
 118         unsigned long long Reserved6SBE[6];
 119         unsigned long long RcvHdrAddr0;
 120         unsigned long long RcvHdrAddr1;
 121         unsigned long long RcvHdrAddr2;
 122         unsigned long long RcvHdrAddr3;
 123         unsigned long long RcvHdrAddr4;
 124         unsigned long long Reserved7RHA[11];
 125         unsigned long long RcvHdrTailAddr0;
 126         unsigned long long RcvHdrTailAddr1;
 127         unsigned long long RcvHdrTailAddr2;
 128         unsigned long long RcvHdrTailAddr3;
 129         unsigned long long RcvHdrTailAddr4;
 130         unsigned long long Reserved8RHTA[11];
 131         unsigned long long Reserved9SW[8];
 132         unsigned long long SerdesConfig0;
 133         unsigned long long SerdesConfig1;
 134         unsigned long long SerdesStatus;
 135         unsigned long long XGXSConfig;
 136         unsigned long long IBPLLCfg;
 137         unsigned long long Reserved10SW2[3];
 138         unsigned long long PCIEQ0SerdesConfig0;
 139         unsigned long long PCIEQ0SerdesConfig1;
 140         unsigned long long PCIEQ0SerdesStatus;
 141         unsigned long long Reserved11;
 142         unsigned long long PCIEQ1SerdesConfig0;
 143         unsigned long long PCIEQ1SerdesConfig1;
 144         unsigned long long PCIEQ1SerdesStatus;
 145         unsigned long long Reserved12;
 146 };
 147
 148 struct _infinipath_do_not_use_counters {
 149         __u64 LBIntCnt;
 150         __u64 LBFlowStallCnt;
 151         __u64 Reserved1;
 152         __u64 TxUnsupVLErrCnt;
 153         __u64 TxDataPktCnt;
 154         __u64 TxFlowPktCnt;
 155         __u64 TxDwordCnt;
 156         __u64 TxLenErrCnt;
 157         __u64 TxMaxMinLenErrCnt;
 158         __u64 TxUnderrunCnt;
 159         __u64 TxFlowStallCnt;
 160         __u64 TxDroppedPktCnt;
 161         __u64 RxDroppedPktCnt;
 162         __u64 RxDataPktCnt;
 163         __u64 RxFlowPktCnt;
 164         __u64 RxDwordCnt;
 165         __u64 RxLenErrCnt;
 166         __u64 RxMaxMinLenErrCnt;
 167         __u64 RxICRCErrCnt;
 168         __u64 RxVCRCErrCnt;
 169         __u64 RxFlowCtrlErrCnt;
 170         __u64 RxBadFormatCnt;
 171         __u64 RxLinkProblemCnt;
 172         __u64 RxEBPCnt;
 173         __u64 RxLPCRCErrCnt;
 174         __u64 RxBufOvflCnt;
 175         __u64 RxTIDFullErrCnt;
 176         __u64 RxTIDValidErrCnt;
 177         __u64 RxPKeyMismatchCnt;
 178         __u64 RxP0HdrEgrOvflCnt;
 179         __u64 RxP1HdrEgrOvflCnt;
 180         __u64 RxP2HdrEgrOvflCnt;
 181         __u64 RxP3HdrEgrOvflCnt;
 182         __u64 RxP4HdrEgrOvflCnt;
 183         __u64 RxP5HdrEgrOvflCnt;
 184         __u64 RxP6HdrEgrOvflCnt;
 185         __u64 RxP7HdrEgrOvflCnt;
 186         __u64 RxP8HdrEgrOvflCnt;
 187         __u64 Reserved6;
 188         __u64 Reserved7;
 189         __u64 IBStatusChangeCnt;
 190         __u64 IBLinkErrRecoveryCnt;
 191         __u64 IBLinkDownedCnt;
 192         __u64 IBSymbolErrCnt;
 193 };
 194
 195 #define IPATH_KREG_OFFSET(field) (offsetof( \
 196         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 197 #define IPATH_CREG_OFFSET(field) (offsetof( \
 198         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
 199
 200 static const struct ipath_kregs ipath_pe_kregs = {
 201         .kr_control = IPATH_KREG_OFFSET(Control),
 202         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 203         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 204         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 205         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 206         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 207         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 208         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 209         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 210         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 211         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 212         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 213         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 214         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 215         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 216         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 217         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 218         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 219         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 220         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 221         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 222         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 223         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 224         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 225         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 226         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 227         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 228         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 229         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 230         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 231         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 232         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 233         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 234         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 235         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 236         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 237         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 238         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 239         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 240         .kr_revision = IPATH_KREG_OFFSET(Revision),
 241         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 242         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 243         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 244         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 245         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 246         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 247         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 248         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 249         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 250         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 251         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 252         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 253         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 254         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 255         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 256         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
 257
 258         /*
 259          * These should not be used directly via ipath_write_kreg64(),
 260          * use them with ipath_write_kreg64_port(),
 261          */
 262         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 263         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
 264
 265         /* The rcvpktled register controls one of the debug port signals, so
 266          * a packet activity LED can be connected to it. */
 267         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
 268         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
 269         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
 270         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
 271         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
 272         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
 273         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
 274         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
 275         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
 276 };
 277
 278 static const struct ipath_cregs ipath_pe_cregs = {
 279         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 280         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 281         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 282         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 283         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 284         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 285         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 286         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 287         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 288         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 289         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 290         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 291         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 292         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 293         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 294         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 295         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 296         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 297         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 298         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 299         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 300         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 301         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 302         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 303         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 304         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 305         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 306         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 307         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 308         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 309         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 310         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 311         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 312 };
 313
 314 /* kr_intstatus, kr_intclear, kr_intmask bits */
 315 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
 316 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
 317
 318 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 319 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 320 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
 321 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 322 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 323 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 324 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 325 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 326 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 327 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 328 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 329 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 330 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 331
 332 /* kr_extstatus bits */
 333 #define INFINIPATH_EXTS_FREQSEL 0x2
 334 #define INFINIPATH_EXTS_SERDESSEL 0x4
 335 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 336 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
 337
 338 #define _IPATH_GPIO_SDA_NUM 1
 339 #define _IPATH_GPIO_SCL_NUM 0
 340
 341 #define IPATH_GPIO_SDA (1ULL << \
 342         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 343 #define IPATH_GPIO_SCL (1ULL << \
 344         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 345
 346 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
 347 #define INFINIPATH_R_TAILUPD_SHIFT 31
 348
 349 /* 6120 specific hardware errors... */
 350 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
 351         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
 352         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
 353         /*
 354          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 355          * parity or memory parity error failures, because most likely we
 356          * won't be able to talk to the core of the chip.  Nonetheless, we
 357          * might see them, if they are in parts of the PCIe core that aren't
 358          * essential.
 359          */
 360         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
 361         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
 362         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
 363         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
 364         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
 365         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 366         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 367 };
 368
 369 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 370                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 371                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 372
 373 static int ipath_pe_txe_recover(struct ipath_devdata *);
 374 static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
 375                                u32, unsigned long);
 376
 377 /**
 378  * ipath_pe_handle_hwerrors - display hardware errors.
 379  * @dd: the infinipath device
 380  * @msg: the output buffer
 381  * @msgl: the size of the output buffer
 382  *
 383  * Use same msg buffer as regular errors to avoid excessive stack
 384  * use.  Most hardware errors are catastrophic, but for right now,
 385  * we'll print them and continue.  We reuse the same message buffer as
 386  * ipath_handle_errors() to avoid excessive stack usage.
 387  */
 388 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 389                                      size_t msgl)
 390 {
 391         ipath_err_t hwerrs;
 392         u32 bits, ctrl;
 393         int isfatal = 0;
 394         char bitsmsg[64];
 395         int log_idx;
 396
 397         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 398         if (!hwerrs) {
 399                 /*
 400                  * better than printing cofusing messages
 401                  * This seems to be related to clearing the crc error, or
 402                  * the pll error during init.
 403                  */
 404                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 405                 return;
 406         } else if (hwerrs == ~0ULL) {
 407                 ipath_dev_err(dd, "Read of hardware error status failed "
 408                               "(all bits set); ignoring\n");
 409                 return;
 410         }
 411         ipath_stats.sps_hwerrs++;
 412
 413         /* Always clear the error status register, except MEMBISTFAIL,
 414          * regardless of whether we continue or stop using the chip.
 415          * We want that set so we know it failed, even across driver reload.
 416          * We'll still ignore it in the hwerrmask.  We do this partly for
 417          * diagnostics, but also for support */
 418         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 419                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 420
 421         hwerrs &= dd->ipath_hwerrmask;
 422
 423         /* We log some errors to EEPROM, check if we have any of those. */
 424         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 425                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 426                         ipath_inc_eeprom_err(dd, log_idx, 1);
 427
 428         /*
 429          * make sure we get this much out, unless told to be quiet,
 430          * or it's occurred within the last 5 seconds
 431          */
 432         if ((hwerrs & ~(dd->ipath_lasthwerror |
 433                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 434                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 435                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 436             (ipath_debug & __IPATH_VERBDBG))
 437                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 438                          "(cleared)\n", (unsigned long long) hwerrs);
 439         dd->ipath_lasthwerror |= hwerrs;
 440
 441         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 442                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 443                               "%llx set\n", (unsigned long long)
 444                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 445
 446         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 447         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 448                 /*
 449                  * parity errors in send memory are recoverable,
 450                  * just cancel the send (if indicated in * sendbuffererror),
 451                  * count the occurrence, unfreeze (if no other handled
 452                  * hardware error bits are set), and continue. They can
 453                  * occur if a processor speculative read is done to the PIO
 454                  * buffer while we are sending a packet, for example.
 455                  */
 456                 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
 457                         hwerrs &= ~TXE_PIO_PARITY;
 458                 if (hwerrs) {
 459                         /*
 460                          * if any set that we aren't ignoring only make the
 461                          * complaint once, in case it's stuck or recurring,
 462                          * and we get here multiple times
 463                          * Force link down, so switch knows, and
 464                          * LEDs are turned off
 465                          */
 466                         if (dd->ipath_flags & IPATH_INITTED) {
 467                                 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 468                                 ipath_setup_pe_setextled(dd,
 469                                         INFINIPATH_IBCS_L_STATE_DOWN,
 470                                         INFINIPATH_IBCS_LT_STATE_DISABLED);
 471                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 472                                               "mode), no longer usable, SN %.16s\n",
 473                                                   dd->ipath_serial);
 474                                 isfatal = 1;
 475                         }
 476                         /*
 477                          * Mark as having had an error for driver, and also
 478                          * for /sys and status word mapped to user programs.
 479                          * This marks unit as not usable, until reset
 480                          */
 481                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 482                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 483                         dd->ipath_flags &= ~IPATH_INITTED;
 484                 } else {
 485                         static u32 freeze_cnt;
 486
 487                         freeze_cnt++;
 488                         ipath_dbg("Clearing freezemode on ignored or recovered "
 489                                   "hardware error (%u)\n", freeze_cnt);
 490                         ipath_clear_freeze(dd);
 491                 }
 492         }
 493
 494         *msg = '\0';
 495
 496         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 497                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 498                         msgl);
 499                 /* ignore from now on, so disable until driver reloaded */
 500                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 501                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 502                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 503                                  dd->ipath_hwerrmask);
 504         }
 505
 506         ipath_format_hwerrors(hwerrs,
 507                               ipath_6120_hwerror_msgs,
 508                               sizeof(ipath_6120_hwerror_msgs)/
 509                               sizeof(ipath_6120_hwerror_msgs[0]),
 510                               msg, msgl);
 511
 512         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
 513                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
 514                 bits = (u32) ((hwerrs >>
 515                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
 516                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
 517                 snprintf(bitsmsg, sizeof bitsmsg,
 518                          "[PCIe Mem Parity Errs %x] ", bits);
 519                 strlcat(msg, bitsmsg, msgl);
 520         }
 521
 522 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 523                          INFINIPATH_HWE_COREPLL_RFSLIP )
 524
 525         if (hwerrs & _IPATH_PLL_FAIL) {
 526                 snprintf(bitsmsg, sizeof bitsmsg,
 527                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 528                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
 529                 strlcat(msg, bitsmsg, msgl);
 530                 /* ignore from now on, so disable until driver reloaded */
 531                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 532                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 533                                  dd->ipath_hwerrmask);
 534         }
 535
 536         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 537                 /*
 538                  * If it occurs, it is left masked since the eternal
 539                  * interface is unused
 540                  */
 541                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 542                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 543                                  dd->ipath_hwerrmask);
 544         }
 545
 546         if (*msg)
 547                 ipath_dev_err(dd, "%s hardware error\n", msg);
 548         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
 549                 /*
 550                  * for /sys status file ; if no trailing } is copied, we'll
 551                  * know it was truncated.
 552                  */
 553                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
 554                          "{%s}", msg);
 555         }
 556 }
 557
 558 /**
 559  * ipath_pe_boardname - fill in the board name
 560  * @dd: the infinipath device
 561  * @name: the output buffer
 562  * @namelen: the size of the output buffer
 563  *
 564  * info is based on the board revision register
 565  */
 566 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
 567                               size_t namelen)
 568 {
 569         char *n = NULL;
 570         u8 boardrev = dd->ipath_boardrev;
 571         int ret;
 572
 573         switch (boardrev) {
 574         case 0:
 575                 n = "InfiniPath_Emulation";
 576                 break;
 577         case 1:
 578                 n = "InfiniPath_QLE7140-Bringup";
 579                 break;
 580         case 2:
 581                 n = "InfiniPath_QLE7140";
 582                 break;
 583         case 3:
 584                 n = "InfiniPath_QMI7140";
 585                 break;
 586         case 4:
 587                 n = "InfiniPath_QEM7140";
 588                 break;
 589         case 5:
 590                 n = "InfiniPath_QMH7140";
 591                 break;
 592         case 6:
 593                 n = "InfiniPath_QLE7142";
 594                 break;
 595         default:
 596                 ipath_dev_err(dd,
 597                               "Don't yet know about board with ID %u\n",
 598                               boardrev);
 599                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
 600                          boardrev);
 601                 break;
 602         }
 603         if (n)
 604                 snprintf(name, namelen, "%s", n);
 605
 606         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
 607                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
 608                               dd->ipath_majrev, dd->ipath_minrev);
 609                 ret = 1;
 610         } else {
 611                 ret = 0;
 612                 if (dd->ipath_minrev >= 2)
 613                         dd->ipath_f_put_tid = ipath_pe_put_tid_2;
 614         }
 615
 616         return ret;
 617 }
 618
 619 /**
 620  * ipath_pe_init_hwerrors - enable hardware errors
 621  * @dd: the infinipath device
 622  *
 623  * now that we have finished initializing everything that might reasonably
 624  * cause a hardware error, and cleared those errors bits as they occur,
 625  * we can enable hardware errors in the mask (potentially enabling
 626  * freeze mode), and enable hardware errors as errors (along with
 627  * everything else) in errormask
 628  */
 629 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
 630 {
 631         ipath_err_t val;
 632         u64 extsval;
 633
 634         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 635
 636         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
 637                 ipath_dev_err(dd, "MemBIST did not complete!\n");
 638         if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
 639                 ipath_dbg("MemBIST corrected\n");
 640
 641         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
 642
 643         if (!dd->ipath_boardrev)        // no PLL for Emulator
 644                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 645
 646         if (dd->ipath_minrev < 2) {
 647                 /* workaround bug 9460 in internal interface bus parity
 648                  * checking. Fixed (HW bug 9490) in Rev2.
 649                  */
 650                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
 651         }
 652         dd->ipath_hwerrmask = val;
 653 }
 654
 655 /**
 656  * ipath_pe_bringup_serdes - bring up the serdes
 657  * @dd: the infinipath device
 658  */
 659 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
 660 {
 661         u64 val, config1, prev_val;
 662         int ret = 0;
 663
 664         ipath_dbg("Trying to bringup serdes\n");
 665
 666         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
 667             INFINIPATH_HWE_SERDESPLLFAILED) {
 668                 ipath_dbg("At start, serdes PLL failed bit set "
 669                           "in hwerrstatus, clearing and continuing\n");
 670                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 671                                  INFINIPATH_HWE_SERDESPLLFAILED);
 672         }
 673
 674         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 675         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
 676
 677         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
 678                    "xgxsconfig %llx\n", (unsigned long long) val,
 679                    (unsigned long long) config1, (unsigned long long)
 680                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 681
 682         /*
 683          * Force reset on, also set rxdetect enable.  Must do before reading
 684          * serdesstatus at least for simulation, or some of the bits in
 685          * serdes status will come back as undefined and cause simulation
 686          * failures
 687          */
 688         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
 689                 | INFINIPATH_SERDC0_L1PWR_DN;
 690         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 691         /* be sure chip saw it */
 692         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 693         udelay(5);              /* need pll reset set at least for a bit */
 694         /*
 695          * after PLL is reset, set the per-lane Resets and TxIdle and
 696          * clear the PLL reset and rxdetect (to get falling edge).
 697          * Leave L1PWR bits set (permanently)
 698          */
 699         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
 700                  | INFINIPATH_SERDC0_L1PWR_DN);
 701         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
 702         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
 703                    "and txidle (%llx)\n", (unsigned long long) val);
 704         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 705         /* be sure chip saw it */
 706         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 707         /* need PLL reset clear for at least 11 usec before lane
 708          * resets cleared; give it a few more to be sure */
 709         udelay(15);
 710         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
 711
 712         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
 713                    "(writing %llx)\n", (unsigned long long) val);
 714         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 715         /* be sure chip saw it */
 716         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 717
 718         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
 719         prev_val = val;
 720         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
 721              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
 722                 val &=
 723                         ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
 724                           INFINIPATH_XGXS_MDIOADDR_SHIFT);
 725                 /* MDIO address 3 */
 726                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
 727         }
 728         if (val & INFINIPATH_XGXS_RESET) {
 729                 val &= ~INFINIPATH_XGXS_RESET;
 730         }
 731         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
 732              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
 733                 /* need to compensate for Tx inversion in partner */
 734                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
 735                          INFINIPATH_XGXS_RX_POL_SHIFT);
 736                 val |= dd->ipath_rx_pol_inv <<
 737                         INFINIPATH_XGXS_RX_POL_SHIFT;
 738         }
 739         if (val != prev_val)
 740                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
 741
 742         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 743
 744         /* clear current and de-emphasis bits */
 745         config1 &= ~0x0ffffffff00ULL;
 746         /* set current to 20ma */
 747         config1 |= 0x00000000000ULL;
 748         /* set de-emphasis to -5.68dB */
 749         config1 |= 0x0cccc000000ULL;
 750         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
 751
 752         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
 753                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
 754                    (unsigned long long) val, (unsigned long long) config1,
 755                    (unsigned long long)
 756                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
 757                    (unsigned long long)
 758                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 759
 760         if (!ipath_waitfor_mdio_cmdready(dd)) {
 761                 ipath_write_kreg(
 762                         dd, dd->ipath_kregs->kr_mdio,
 763                         ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
 764                                        IPATH_MDIO_CTRL_XGXS_REG_8, 0));
 765                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
 766                                            IPATH_MDIO_DATAVALID, &val))
 767                         ipath_dbg("Never got MDIO data for XGXS "
 768                                   "status read\n");
 769                 else
 770                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
 771                                    "'bank' 31 %x\n", (u32) val);
 772         } else
 773                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
 774
 775         return ret;
 776 }
 777
 778 /**
 779  * ipath_pe_quiet_serdes - set serdes to txidle
 780  * @dd: the infinipath device
 781  * Called when driver is being unloaded
 782  */
 783 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
 784 {
 785         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 786
 787         val |= INFINIPATH_SERDC0_TXIDLE;
 788         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
 789                   (unsigned long long) val);
 790         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 791 }
 792
 793 static int ipath_pe_intconfig(struct ipath_devdata *dd)
 794 {
 795         u32 chiprev;
 796
 797         /*
 798          * If the chip supports added error indication via GPIO pins,
 799          * enable interrupts on those bits so the interrupt routine
 800          * can count the events. Also set flag so interrupt routine
 801          * can know they are expected.
 802          */
 803         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
 804         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
 805                 /* Rev2+ reports extra errors via internal GPIO pins */
 806                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
 807                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
 808                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
 809                                  dd->ipath_gpio_mask);
 810         }
 811         return 0;
 812 }
 813
 814 /**
 815  * ipath_setup_pe_setextled - set the state of the two external LEDs
 816  * @dd: the infinipath device
 817  * @lst: the L state
 818  * @ltst: the LT state
 819
 820  * These LEDs indicate the physical and logical state of IB link.
 821  * For this chip (at least with recommended board pinouts), LED1
 822  * is Yellow (logical state) and LED2 is Green (physical state),
 823  *
 824  * Note:  We try to match the Mellanox HCA LED behavior as best
 825  * we can.  Green indicates physical link state is OK (something is
 826  * plugged in, and we can train).
 827  * Amber indicates the link is logically up (ACTIVE).
 828  * Mellanox further blinks the amber LED to indicate data packet
 829  * activity, but we have no hardware support for that, so it would
 830  * require waking up every 10-20 msecs and checking the counters
 831  * on the chip, and then turning the LED off if appropriate.  That's
 832  * visible overhead, so not something we will do.
 833  *
 834  */
 835 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
 836                                      u64 ltst)
 837 {
 838         u64 extctl;
 839         unsigned long flags = 0;
 840
 841         /* the diags use the LED to indicate diag info, so we leave
 842          * the external LED alone when the diags are running */
 843         if (ipath_diag_inuse)
 844                 return;
 845
 846         /* Allow override of LED display for, e.g. Locating system in rack */
 847         if (dd->ipath_led_override) {
 848                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
 849                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
 850                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
 851                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
 852                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
 853                         : INFINIPATH_IBCS_L_STATE_DOWN;
 854         }
 855
 856         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
 857         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
 858                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
 859
 860         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
 861                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
 862         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
 863                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
 864         dd->ipath_extctrl = extctl;
 865         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
 866         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
 867 }
 868
 869 /**
 870  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
 871  * @dd: the infinipath device
 872  *
 873  * This is called during driver unload.
 874  * We do the pci_disable_msi here, not in generic code, because it
 875  * isn't used for the HT chips. If we do end up needing pci_enable_msi
 876  * at some point in the future for HT, we'll move the call back
 877  * into the main init_one code.
 878  */
 879 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
 880 {
 881         dd->ipath_msi_lo = 0;   /* just in case unload fails */
 882         pci_disable_msi(dd->pcidev);
 883 }
 884
 885 /**
 886  * ipath_setup_pe_config - setup PCIe config related stuff
 887  * @dd: the infinipath device
 888  * @pdev: the PCI device
 889  *
 890  * The pci_enable_msi() call will fail on systems with MSI quirks
 891  * such as those with AMD8131, even if the device of interest is not
 892  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
 893  * late in 2.6.16).
 894  * All that can be done is to edit the kernel source to remove the quirk
 895  * check until that is fixed.
 896  * We do not need to call enable_msi() for our HyperTransport chip,
 897  * even though it uses MSI, and we want to avoid the quirk warning, so
 898  * So we call enable_msi only for PCIe.  If we do end up needing
 899  * pci_enable_msi at some point in the future for HT, we'll move the
 900  * call back into the main init_one code.
 901  * We save the msi lo and hi values, so we can restore them after
 902  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 903  * correctly).
 904  */
 905 static int ipath_setup_pe_config(struct ipath_devdata *dd,
 906                                  struct pci_dev *pdev)
 907 {
 908         int pos, ret;
 909
 910         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
 911         ret = pci_enable_msi(dd->pcidev);
 912         if (ret)
 913                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
 914                               "interrupts may not work\n", ret);
 915         /* continue even if it fails, we may still be OK... */
 916         dd->ipath_irq = pdev->irq;
 917
 918         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 919                 u16 control;
 920                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 921                                       &dd->ipath_msi_lo);
 922                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 923                                       &dd->ipath_msi_hi);
 924                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 925                                      &control);
 926                 /* now save the data (vector) info */
 927                 pci_read_config_word(dd->pcidev,
 928                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
 929                                             ? 12 : 8),
 930                                      &dd->ipath_msi_data);
 931                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
 932                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
 933                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 934                            control);
 935                 /* we save the cachelinesize also, although it doesn't
 936                  * really matter */
 937                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 938                                      &dd->ipath_pci_cacheline);
 939         } else
 940                 ipath_dev_err(dd, "Can't find MSI capability, "
 941                               "can't save MSI settings for reset\n");
 942         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
 943                 u16 linkstat;
 944                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
 945                                      &linkstat);
 946                 linkstat >>= 4;
 947                 linkstat &= 0x1f;
 948                 if (linkstat != 8)
 949                         ipath_dev_err(dd, "PCIe width %u, "
 950                                       "performance reduced\n", linkstat);
 951         }
 952         else
 953                 ipath_dev_err(dd, "Can't find PCI Express "
 954                               "capability!\n");
 955         return 0;
 956 }
 957
 958 static void ipath_init_pe_variables(struct ipath_devdata *dd)
 959 {
 960         /*
 961          * bits for selecting i2c direction and values,
 962          * used for I2C serial flash
 963          */
 964         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
 965         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
 966         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
 967         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
 968
 969         /* Fill in shifts for RcvCtrl. */
 970         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
 971         dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
 972         dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
 973         dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
 974
 975         /* variables for sanity checking interrupt and errors */
 976         dd->ipath_hwe_bitsextant =
 977                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 978                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
 979                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
 980                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
 981                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
 982                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
 983                 INFINIPATH_HWE_PCIE1PLLFAILED |
 984                 INFINIPATH_HWE_PCIE0PLLFAILED |
 985                 INFINIPATH_HWE_PCIEPOISONEDTLP |
 986                 INFINIPATH_HWE_PCIECPLTIMEOUT |
 987                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
 988                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
 989                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
 990                 INFINIPATH_HWE_MEMBISTFAILED |
 991                 INFINIPATH_HWE_COREPLL_FBSLIP |
 992                 INFINIPATH_HWE_COREPLL_RFSLIP |
 993                 INFINIPATH_HWE_SERDESPLLFAILED |
 994                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
 995                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
 996         dd->ipath_i_bitsextant =
 997                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
 998                 (INFINIPATH_I_RCVAVAIL_MASK <<
 999                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1000                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1001                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1002         dd->ipath_e_bitsextant =
1003                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1004                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1005                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1006                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1007                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1008                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1009                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1010                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1011                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1012                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1013                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1014                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1015                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1016                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1017                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1018                 INFINIPATH_E_HARDWARE;
1019
1020         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1021         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1022
1023         /*
1024          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1025          * 2 is Some Misc, 3 is reserved for future.
1026          */
1027         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1028                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1029                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1030
1031         /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1032         if (ipath_unordered_wc())
1033                 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1034
1035         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1036                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1037                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1038
1039         dd->ipath_eep_st_masks[2].errs_to_log =
1040                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1041
1042
1043 }
1044
1045 /* setup the MSI stuff again after a reset.  I'd like to just call
1046  * pci_enable_msi() and request_irq() again, but when I do that,
1047  * the MSI enable bit doesn't get set in the command word, and
1048  * we switch to to a different interrupt vector, which is confusing,
1049  * so I instead just do it all inline.  Perhaps somehow can tie this
1050  * into the PCIe hotplug support at some point
1051  * Note, because I'm doing it all here, I don't call pci_disable_msi()
1052  * or free_irq() at the start of ipath_setup_pe_reset().
1053  */
1054 static int ipath_reinit_msi(struct ipath_devdata *dd)
1055 {
1056         int pos;
1057         u16 control;
1058         int ret;
1059
1060         if (!dd->ipath_msi_lo) {
1061                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1062                          "initial setup failed?\n");
1063                 ret = 0;
1064                 goto bail;
1065         }
1066
1067         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1068                 ipath_dev_err(dd, "Can't find MSI capability, "
1069                               "can't restore MSI settings\n");
1070                 ret = 0;
1071                 goto bail;
1072         }
1073         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1074                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1075         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1076                                dd->ipath_msi_lo);
1077         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1078                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1079         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1080                                dd->ipath_msi_hi);
1081         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1082         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1083                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1084                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1085                            control, control | PCI_MSI_FLAGS_ENABLE);
1086                 control |= PCI_MSI_FLAGS_ENABLE;
1087                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1088                                       control);
1089         }
1090         /* now rewrite the data (vector) info */
1091         pci_write_config_word(dd->pcidev, pos +
1092                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1093                               dd->ipath_msi_data);
1094         /* we restore the cachelinesize also, although it doesn't really
1095          * matter */
1096         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1097                               dd->ipath_pci_cacheline);
1098         /* and now set the pci master bit again */
1099         pci_set_master(dd->pcidev);
1100         ret = 1;
1101
1102 bail:
1103         return ret;
1104 }
1105
1106 /* This routine sleeps, so it can only be called from user context, not
1107  * from interrupt context.  If we need interrupt context, we can split
1108  * it into two routines.
1109 */
1110 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1111 {
1112         u64 val;
1113         int i;
1114         int ret;
1115
1116         /* Use ERROR so it shows up in logs, etc. */
1117         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1118         /* keep chip from being accessed in a few places */
1119         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1120         val = dd->ipath_control | INFINIPATH_C_RESET;
1121         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1122         mb();
1123
1124         for (i = 1; i <= 5; i++) {
1125                 int r;
1126                 /* allow MBIST, etc. to complete; longer on each retry.
1127                  * We sometimes get machine checks from bus timeout if no
1128                  * response, so for now, make it *really* long.
1129                  */
1130                 msleep(1000 + (1 + i) * 2000);
1131                 if ((r =
1132                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1133                                             dd->ipath_pcibar0)))
1134                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1135                                       r);
1136                 if ((r =
1137                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1138                                             dd->ipath_pcibar1)))
1139                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1140                                       r);
1141                 /* now re-enable memory access */
1142                 if ((r = pci_enable_device(dd->pcidev)))
1143                         ipath_dev_err(dd, "pci_enable_device failed after "
1144                                       "reset: %d\n", r);
1145                 /* whether it worked or not, mark as present, again */
1146                 dd->ipath_flags |= IPATH_PRESENT;
1147                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1148                 if (val == dd->ipath_revision) {
1149                         ipath_cdbg(VERBOSE, "Got matching revision "
1150                                    "register %llx on try %d\n",
1151                                    (unsigned long long) val, i);
1152                         ret = ipath_reinit_msi(dd);
1153                         goto bail;
1154                 }
1155                 /* Probably getting -1 back */
1156                 ipath_dbg("Didn't get expected revision register, "
1157                           "got %llx, try %d\n", (unsigned long long) val,
1158                           i + 1);
1159         }
1160         ret = 0; /* failed */
1161
1162 bail:
1163         return ret;
1164 }
1165
1166 /**
1167  * ipath_pe_put_tid - write a TID in chip
1168  * @dd: the infinipath device
1169  * @tidptr: pointer to the expected TID (in chip) to udpate
1170  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1171  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1172  *
1173  * This exists as a separate routine to allow for special locking etc.
1174  * It's used for both the full cleanup on exit, as well as the normal
1175  * setup and teardown.
1176  */
1177 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1178                              u32 type, unsigned long pa)
1179 {
1180         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1181         unsigned long flags = 0; /* keep gcc quiet */
1182
1183         if (pa != dd->ipath_tidinvalid) {
1184                 if (pa & ((1U << 11) - 1)) {
1185                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1186                                  "not 4KB aligned!\n", pa);
1187                         return;
1188                 }
1189                 pa >>= 11;
1190                 /* paranoia check */
1191                 if (pa & (7<<29))
1192                         ipath_dev_err(dd,
1193                                       "BUG: Physical page address 0x%lx "
1194                                       "has bits set in 31-29\n", pa);
1195
1196                 if (type == RCVHQ_RCV_TYPE_EAGER)
1197                         pa |= dd->ipath_tidtemplate;
1198                 else /* for now, always full 4KB page */
1199                         pa |= 2 << 29;
1200         }
1201
1202         /*
1203          * Workaround chip bug 9437 by writing the scratch register
1204          * before and after the TID, and with an io write barrier.
1205          * We use a spinlock around the writes, so they can't intermix
1206          * with other TID (eager or expected) writes (the chip bug
1207          * is triggered by back to back TID writes). Unfortunately, this
1208          * call can be done from interrupt level for the port 0 eager TIDs,
1209          * so we have to use irqsave locks.
1210          */
1211         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1212         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1213         if (dd->ipath_kregbase)
1214                 writel(pa, tidp32);
1215         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1216         mmiowb();
1217         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1218 }
1219 /**
1220  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1221  * @dd: the infinipath device
1222  * @tidptr: pointer to the expected TID (in chip) to udpate
1223  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1224  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1225  *
1226  * This exists as a separate routine to allow for selection of the
1227  * appropriate "flavor". The static calls in cleanup just use the
1228  * revision-agnostic form, as they are not performance critical.
1229  */
1230 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1231                              u32 type, unsigned long pa)
1232 {
1233         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1234
1235         if (pa != dd->ipath_tidinvalid) {
1236                 if (pa & ((1U << 11) - 1)) {
1237                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1238                                  "not 2KB aligned!\n", pa);
1239                         return;
1240                 }
1241                 pa >>= 11;
1242                 /* paranoia check */
1243                 if (pa & (7<<29))
1244                         ipath_dev_err(dd,
1245                                       "BUG: Physical page address 0x%lx "
1246                                       "has bits set in 31-29\n", pa);
1247
1248                 if (type == RCVHQ_RCV_TYPE_EAGER)
1249                         pa |= dd->ipath_tidtemplate;
1250                 else /* for now, always full 4KB page */
1251                         pa |= 2 << 29;
1252         }
1253         if (dd->ipath_kregbase)
1254                 writel(pa, tidp32);
1255         mmiowb();
1256 }
1257
1258
1259 /**
1260  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1261  * @dd: the infinipath device
1262  * @port: the port
1263  *
1264  * clear all TID entries for a port, expected and eager.
1265  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1266  * not 64, but they are still on 64 bit boundaries, so tidbase
1267  * is declared as u64 * for the pointer math, even though we write 32 bits
1268  */
1269 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1270 {
1271         u64 __iomem *tidbase;
1272         unsigned long tidinv;
1273         int i;
1274
1275         if (!dd->ipath_kregbase)
1276                 return;
1277
1278         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1279
1280         tidinv = dd->ipath_tidinvalid;
1281         tidbase = (u64 __iomem *)
1282                 ((char __iomem *)(dd->ipath_kregbase) +
1283                  dd->ipath_rcvtidbase +
1284                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1285
1286         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1287                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1288                                  tidinv);
1289
1290         tidbase = (u64 __iomem *)
1291                 ((char __iomem *)(dd->ipath_kregbase) +
1292                  dd->ipath_rcvegrbase +
1293                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1294
1295         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1296                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1297                                  tidinv);
1298 }
1299
1300 /**
1301  * ipath_pe_tidtemplate - setup constants for TID updates
1302  * @dd: the infinipath device
1303  *
1304  * We setup stuff that we use a lot, to avoid calculating each time
1305  */
1306 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1307 {
1308         u32 egrsize = dd->ipath_rcvegrbufsize;
1309
1310         /* For now, we always allocate 4KB buffers (at init) so we can
1311          * receive max size packets.  We may want a module parameter to
1312          * specify 2KB or 4KB and/or make be per port instead of per device
1313          * for those who want to reduce memory footprint.  Note that the
1314          * ipath_rcvhdrentsize size must be large enough to hold the largest
1315          * IB header (currently 96 bytes) that we expect to handle (plus of
1316          * course the 2 dwords of RHF).
1317          */
1318         if (egrsize == 2048)
1319                 dd->ipath_tidtemplate = 1U << 29;
1320         else if (egrsize == 4096)
1321                 dd->ipath_tidtemplate = 2U << 29;
1322         else {
1323                 egrsize = 4096;
1324                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1325                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1326                          egrsize);
1327                 dd->ipath_tidtemplate = 2U << 29;
1328         }
1329         dd->ipath_tidinvalid = 0;
1330 }
1331
1332 static int ipath_pe_early_init(struct ipath_devdata *dd)
1333 {
1334         dd->ipath_flags |= IPATH_4BYTE_TID;
1335         if (ipath_unordered_wc())
1336                 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1337
1338         /*
1339          * For openfabrics, we need to be able to handle an IB header of
1340          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1341          * made them the same size as the PIO buffers.  This chip does not
1342          * handle arbitrary size buffers, so we need the header large enough
1343          * to handle largest IB header, but still have room for a 2KB MTU
1344          * standard IB packet.
1345          */
1346         dd->ipath_rcvhdrentsize = 24;
1347         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1348
1349         /*
1350          * To truly support a 4KB MTU (for usermode), we need to
1351          * bump this to a larger value.  For now, we use them for
1352          * the kernel only.
1353          */
1354         dd->ipath_rcvegrbufsize = 2048;
1355         /*
1356          * the min() check here is currently a nop, but it may not always
1357          * be, depending on just how we do ipath_rcvegrbufsize
1358          */
1359         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1360                                  dd->ipath_rcvegrbufsize +
1361                                  (dd->ipath_rcvhdrentsize << 2));
1362         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1363
1364         /*
1365          * We can request a receive interrupt for 1 or
1366          * more packets from current offset.  For now, we set this
1367          * up for a single packet.
1368          */
1369         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1370
1371         ipath_get_eeprom_info(dd);
1372
1373         return 0;
1374 }
1375
1376 int __attribute__((weak)) ipath_unordered_wc(void)
1377 {
1378         return 0;
1379 }
1380
1381 /**
1382  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1383  * @pd: the infinipath port
1384  * @kbase: ipath_base_info pointer
1385  *
1386  * We set the PCIE flag because the lower bandwidth on PCIe vs
1387  * HyperTransport can affect some user packet algorithms.
1388  */
1389 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1390 {
1391         struct ipath_base_info *kinfo = kbase;
1392         struct ipath_devdata *dd;
1393
1394         if (ipath_unordered_wc()) {
1395                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1396                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1397         }
1398         else
1399                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1400
1401         if (pd == NULL)
1402                 goto done;
1403
1404         dd = pd->port_dd;
1405
1406 done:
1407         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1408                 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1409         return 0;
1410 }
1411
1412 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1413 {
1414         free_irq(dd->ipath_irq, dd);
1415         dd->ipath_irq = 0;
1416 }
1417
1418 static void ipath_pe_read_counters(struct ipath_devdata *dd,
1419                                    struct infinipath_counters *cntrs)
1420 {
1421         cntrs->LBIntCnt =
1422                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1423         cntrs->LBFlowStallCnt =
1424                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1425         cntrs->TxSDmaDescCnt = 0;
1426         cntrs->TxUnsupVLErrCnt =
1427                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1428         cntrs->TxDataPktCnt =
1429                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1430         cntrs->TxFlowPktCnt =
1431                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1432         cntrs->TxDwordCnt =
1433                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1434         cntrs->TxLenErrCnt =
1435                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1436         cntrs->TxMaxMinLenErrCnt =
1437                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1438         cntrs->TxUnderrunCnt =
1439                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1440         cntrs->TxFlowStallCnt =
1441                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1442         cntrs->TxDroppedPktCnt =
1443                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1444         cntrs->RxDroppedPktCnt =
1445                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1446         cntrs->RxDataPktCnt =
1447                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1448         cntrs->RxFlowPktCnt =
1449                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1450         cntrs->RxDwordCnt =
1451                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1452         cntrs->RxLenErrCnt =
1453                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1454         cntrs->RxMaxMinLenErrCnt =
1455                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1456         cntrs->RxICRCErrCnt =
1457                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1458         cntrs->RxVCRCErrCnt =
1459                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1460         cntrs->RxFlowCtrlErrCnt =
1461                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1462         cntrs->RxBadFormatCnt =
1463                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1464         cntrs->RxLinkProblemCnt =
1465                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1466         cntrs->RxEBPCnt =
1467                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1468         cntrs->RxLPCRCErrCnt =
1469                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1470         cntrs->RxBufOvflCnt =
1471                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1472         cntrs->RxTIDFullErrCnt =
1473                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1474         cntrs->RxTIDValidErrCnt =
1475                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1476         cntrs->RxPKeyMismatchCnt =
1477                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1478         cntrs->RxP0HdrEgrOvflCnt =
1479                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1480         cntrs->RxP1HdrEgrOvflCnt =
1481                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1482         cntrs->RxP2HdrEgrOvflCnt =
1483                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1484         cntrs->RxP3HdrEgrOvflCnt =
1485                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1486         cntrs->RxP4HdrEgrOvflCnt =
1487                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1488         cntrs->RxP5HdrEgrOvflCnt = 0;
1489         cntrs->RxP6HdrEgrOvflCnt = 0;
1490         cntrs->RxP7HdrEgrOvflCnt = 0;
1491         cntrs->RxP8HdrEgrOvflCnt = 0;
1492         cntrs->RxP9HdrEgrOvflCnt = 0;
1493         cntrs->RxP10HdrEgrOvflCnt = 0;
1494         cntrs->RxP11HdrEgrOvflCnt = 0;
1495         cntrs->RxP12HdrEgrOvflCnt = 0;
1496         cntrs->RxP13HdrEgrOvflCnt = 0;
1497         cntrs->RxP14HdrEgrOvflCnt = 0;
1498         cntrs->RxP15HdrEgrOvflCnt = 0;
1499         cntrs->RxP16HdrEgrOvflCnt = 0;
1500         cntrs->IBStatusChangeCnt =
1501                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1502         cntrs->IBLinkErrRecoveryCnt =
1503                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1504         cntrs->IBLinkDownedCnt =
1505                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1506         cntrs->IBSymbolErrCnt =
1507                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1508         cntrs->RxVL15DroppedPktCnt = 0;
1509         cntrs->RxOtherLocalPhyErrCnt = 0;
1510         cntrs->PcieRetryBufDiagQwordCnt = 0;
1511         cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1512         cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1513         cntrs->RxVlErrCnt = 0;
1514         cntrs->RxDlidFltrCnt = 0;
1515 }
1516
1517 /*
1518  * On platforms using this chip, and not having ordered WC stores, we
1519  * can get TXE parity errors due to speculative reads to the PIO buffers,
1520  * and this, due to a chip bug can result in (many) false parity error
1521  * reports.  So it's a debug print on those, and an info print on systems
1522  * where the speculative reads don't occur.
1523  * Because we can get lots of false errors, we have no upper limit
1524  * on recovery attempts on those platforms.
1525  */
1526 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1527 {
1528         if (ipath_unordered_wc())
1529                 ipath_dbg("Recovering from TXE PIO parity error\n");
1530         else {
1531                 int cnt = ++ipath_stats.sps_txeparity;
1532                 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1533                         if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1534                                 ipath_dev_err(dd,
1535                                         "Too many attempts to recover from "
1536                                         "TXE parity, giving up\n");
1537                         return 0;
1538                 }
1539                 dev_info(&dd->pcidev->dev,
1540                         "Recovering from TXE PIO parity error\n");
1541         }
1542         return 1;
1543 }
1544
1545 /**
1546  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1547  * @dd: the infinipath device
1548  *
1549  * This is global, and is called directly at init to set up the
1550  * chip-specific function pointers for later use.
1551  */
1552 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1553 {
1554         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1555         dd->ipath_f_bus = ipath_setup_pe_config;
1556         dd->ipath_f_reset = ipath_setup_pe_reset;
1557         dd->ipath_f_get_boardname = ipath_pe_boardname;
1558         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1559         dd->ipath_f_early_init = ipath_pe_early_init;
1560         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1561         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1562         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1563         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1564         /*
1565          * this may get changed after we read the chip revision,
1566          * but we start with the safe version for all revs
1567          */
1568         dd->ipath_f_put_tid = ipath_pe_put_tid;
1569         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1570         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1571         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1572         dd->ipath_f_free_irq = ipath_pe_free_irq;
1573
1574         /* initialize chip-specific variables */
1575         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1576         dd->ipath_f_read_counters = ipath_pe_read_counters;
1577
1578         /*
1579          * setup the register offsets, since they are different for each
1580          * chip
1581          */
1582         dd->ipath_kregs = &ipath_pe_kregs;
1583         dd->ipath_cregs = &ipath_pe_cregs;
1584
1585         ipath_init_pe_variables(dd);
1586 }
1587