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IB/ipath: Provide I/O bus speeds for diagnostic purposes
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1 /*
2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33 /*
34  * This file contains all of the code that is specific to the
35  * InfiniPath PCIe chip.
36  */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <rdma/ib_verbs.h>
42
43 #include "ipath_kernel.h"
44 #include "ipath_registers.h"
45
46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
47
48 /*
49  * This file contains all the chip-specific register information and
50  * access functions for the QLogic InfiniPath PCI-Express chip.
51  *
52  * This lists the InfiniPath registers, in the actual chip layout.
53  * This structure should never be directly accessed.
54  */
55 struct _infinipath_do_not_use_kernel_regs {
56         unsigned long long Revision;
57         unsigned long long Control;
58         unsigned long long PageAlign;
59         unsigned long long PortCnt;
60         unsigned long long DebugPortSelect;
61         unsigned long long Reserved0;
62         unsigned long long SendRegBase;
63         unsigned long long UserRegBase;
64         unsigned long long CounterRegBase;
65         unsigned long long Scratch;
66         unsigned long long Reserved1;
67         unsigned long long Reserved2;
68         unsigned long long IntBlocked;
69         unsigned long long IntMask;
70         unsigned long long IntStatus;
71         unsigned long long IntClear;
72         unsigned long long ErrorMask;
73         unsigned long long ErrorStatus;
74         unsigned long long ErrorClear;
75         unsigned long long HwErrMask;
76         unsigned long long HwErrStatus;
77         unsigned long long HwErrClear;
78         unsigned long long HwDiagCtrl;
79         unsigned long long MDIO;
80         unsigned long long IBCStatus;
81         unsigned long long IBCCtrl;
82         unsigned long long ExtStatus;
83         unsigned long long ExtCtrl;
84         unsigned long long GPIOOut;
85         unsigned long long GPIOMask;
86         unsigned long long GPIOStatus;
87         unsigned long long GPIOClear;
88         unsigned long long RcvCtrl;
89         unsigned long long RcvBTHQP;
90         unsigned long long RcvHdrSize;
91         unsigned long long RcvHdrCnt;
92         unsigned long long RcvHdrEntSize;
93         unsigned long long RcvTIDBase;
94         unsigned long long RcvTIDCnt;
95         unsigned long long RcvEgrBase;
96         unsigned long long RcvEgrCnt;
97         unsigned long long RcvBufBase;
98         unsigned long long RcvBufSize;
99         unsigned long long RxIntMemBase;
100         unsigned long long RxIntMemSize;
101         unsigned long long RcvPartitionKey;
102         unsigned long long Reserved3;
103         unsigned long long RcvPktLEDCnt;
104         unsigned long long Reserved4[8];
105         unsigned long long SendCtrl;
106         unsigned long long SendPIOBufBase;
107         unsigned long long SendPIOSize;
108         unsigned long long SendPIOBufCnt;
109         unsigned long long SendPIOAvailAddr;
110         unsigned long long TxIntMemBase;
111         unsigned long long TxIntMemSize;
112         unsigned long long Reserved5;
113         unsigned long long PCIeRBufTestReg0;
114         unsigned long long PCIeRBufTestReg1;
115         unsigned long long Reserved51[6];
116         unsigned long long SendBufferError;
117         unsigned long long SendBufferErrorCONT1;
118         unsigned long long Reserved6SBE[6];
119         unsigned long long RcvHdrAddr0;
120         unsigned long long RcvHdrAddr1;
121         unsigned long long RcvHdrAddr2;
122         unsigned long long RcvHdrAddr3;
123         unsigned long long RcvHdrAddr4;
124         unsigned long long Reserved7RHA[11];
125         unsigned long long RcvHdrTailAddr0;
126         unsigned long long RcvHdrTailAddr1;
127         unsigned long long RcvHdrTailAddr2;
128         unsigned long long RcvHdrTailAddr3;
129         unsigned long long RcvHdrTailAddr4;
130         unsigned long long Reserved8RHTA[11];
131         unsigned long long Reserved9SW[8];
132         unsigned long long SerdesConfig0;
133         unsigned long long SerdesConfig1;
134         unsigned long long SerdesStatus;
135         unsigned long long XGXSConfig;
136         unsigned long long IBPLLCfg;
137         unsigned long long Reserved10SW2[3];
138         unsigned long long PCIEQ0SerdesConfig0;
139         unsigned long long PCIEQ0SerdesConfig1;
140         unsigned long long PCIEQ0SerdesStatus;
141         unsigned long long Reserved11;
142         unsigned long long PCIEQ1SerdesConfig0;
143         unsigned long long PCIEQ1SerdesConfig1;
144         unsigned long long PCIEQ1SerdesStatus;
145         unsigned long long Reserved12;
146 };
147
148 struct _infinipath_do_not_use_counters {
149         __u64 LBIntCnt;
150         __u64 LBFlowStallCnt;
151         __u64 Reserved1;
152         __u64 TxUnsupVLErrCnt;
153         __u64 TxDataPktCnt;
154         __u64 TxFlowPktCnt;
155         __u64 TxDwordCnt;
156         __u64 TxLenErrCnt;
157         __u64 TxMaxMinLenErrCnt;
158         __u64 TxUnderrunCnt;
159         __u64 TxFlowStallCnt;
160         __u64 TxDroppedPktCnt;
161         __u64 RxDroppedPktCnt;
162         __u64 RxDataPktCnt;
163         __u64 RxFlowPktCnt;
164         __u64 RxDwordCnt;
165         __u64 RxLenErrCnt;
166         __u64 RxMaxMinLenErrCnt;
167         __u64 RxICRCErrCnt;
168         __u64 RxVCRCErrCnt;
169         __u64 RxFlowCtrlErrCnt;
170         __u64 RxBadFormatCnt;
171         __u64 RxLinkProblemCnt;
172         __u64 RxEBPCnt;
173         __u64 RxLPCRCErrCnt;
174         __u64 RxBufOvflCnt;
175         __u64 RxTIDFullErrCnt;
176         __u64 RxTIDValidErrCnt;
177         __u64 RxPKeyMismatchCnt;
178         __u64 RxP0HdrEgrOvflCnt;
179         __u64 RxP1HdrEgrOvflCnt;
180         __u64 RxP2HdrEgrOvflCnt;
181         __u64 RxP3HdrEgrOvflCnt;
182         __u64 RxP4HdrEgrOvflCnt;
183         __u64 RxP5HdrEgrOvflCnt;
184         __u64 RxP6HdrEgrOvflCnt;
185         __u64 RxP7HdrEgrOvflCnt;
186         __u64 RxP8HdrEgrOvflCnt;
187         __u64 Reserved6;
188         __u64 Reserved7;
189         __u64 IBStatusChangeCnt;
190         __u64 IBLinkErrRecoveryCnt;
191         __u64 IBLinkDownedCnt;
192         __u64 IBSymbolErrCnt;
193 };
194
195 #define IPATH_KREG_OFFSET(field) (offsetof( \
196         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
197 #define IPATH_CREG_OFFSET(field) (offsetof( \
198         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
199
200 static const struct ipath_kregs ipath_pe_kregs = {
201         .kr_control = IPATH_KREG_OFFSET(Control),
202         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
203         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
204         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
205         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
206         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
207         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
208         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
209         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
210         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
211         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
212         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
213         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
214         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
215         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
216         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
217         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
218         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
219         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
220         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
221         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
222         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
223         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
224         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
225         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
226         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
227         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
228         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
229         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
230         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
231         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
232         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
233         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
234         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
235         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
236         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
237         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
238         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
239         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
240         .kr_revision = IPATH_KREG_OFFSET(Revision),
241         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
242         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
243         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
244         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
245         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
246         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
247         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
248         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
249         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
250         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
251         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
252         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
253         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
254         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
255         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
256         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
257
258         /*
259          * These should not be used directly via ipath_write_kreg64(),
260          * use them with ipath_write_kreg64_port(),
261          */
262         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
263         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
264
265         /* The rcvpktled register controls one of the debug port signals, so
266          * a packet activity LED can be connected to it. */
267         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
268         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
269         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
270         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
271         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
272         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
273         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
274         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
275         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
276 };
277
278 static const struct ipath_cregs ipath_pe_cregs = {
279         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
280         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
281         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
282         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
283         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
284         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
285         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
286         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
287         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
288         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
289         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
290         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
291         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
292         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
293         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
294         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
295         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
296         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
297         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
298         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
299         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
300         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
301         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
302         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
303         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
304         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
305         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
306         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
307         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
308         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
309         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
310         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
311         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
312 };
313
314 /* kr_control bits */
315 #define INFINIPATH_C_RESET 1U
316
317 /* kr_intstatus, kr_intclear, kr_intmask bits */
318 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
319 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
320
321 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
322 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
323 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
324 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
325 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
326 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
327 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
328 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
329 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
330 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
331 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
332 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
333 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
334
335 #define IBA6120_IBCS_LINKTRAININGSTATE_MASK 0xf
336 #define IBA6120_IBCS_LINKSTATE_SHIFT 4
337
338 /* kr_extstatus bits */
339 #define INFINIPATH_EXTS_FREQSEL 0x2
340 #define INFINIPATH_EXTS_SERDESSEL 0x4
341 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
342 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
343
344 /* kr_xgxsconfig bits */
345 #define INFINIPATH_XGXS_RESET          0x5ULL
346
347 #define _IPATH_GPIO_SDA_NUM 1
348 #define _IPATH_GPIO_SCL_NUM 0
349
350 #define IPATH_GPIO_SDA (1ULL << \
351         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
352 #define IPATH_GPIO_SCL (1ULL << \
353         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
354
355 #define INFINIPATH_RT_BUFSIZE_MASK 0xe0000000ULL
356 #define INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid) \
357         ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
358 #define INFINIPATH_RT_BUFSIZE(tid) (1 << INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid))
359 #define INFINIPATH_RT_IS_VALID(tid) \
360         (((tid) & INFINIPATH_RT_BUFSIZE_MASK) && \
361          ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) != INFINIPATH_RT_BUFSIZE_MASK)))
362 #define INFINIPATH_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
363 #define INFINIPATH_RT_ADDR_SHIFT 10
364
365 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
366 #define INFINIPATH_R_TAILUPD_SHIFT 31
367
368 /* 6120 specific hardware errors... */
369 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
370         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
371         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
372         /*
373          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
374          * parity or memory parity error failures, because most likely we
375          * won't be able to talk to the core of the chip.  Nonetheless, we
376          * might see them, if they are in parts of the PCIe core that aren't
377          * essential.
378          */
379         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
380         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
381         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
382         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
383         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
384         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
385         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
386 };
387
388 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
389                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
390                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
391 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
392                           << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
393
394 static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
395                                u32, unsigned long);
396
397 /*
398  * On platforms using this chip, and not having ordered WC stores, we
399  * can get TXE parity errors due to speculative reads to the PIO buffers,
400  * and this, due to a chip bug can result in (many) false parity error
401  * reports.  So it's a debug print on those, and an info print on systems
402  * where the speculative reads don't occur.
403  */
404 static void ipath_pe_txe_recover(struct ipath_devdata *dd)
405 {
406         if (ipath_unordered_wc())
407                 ipath_dbg("Recovering from TXE PIO parity error\n");
408         else {
409                 ++ipath_stats.sps_txeparity;
410                 dev_info(&dd->pcidev->dev,
411                         "Recovering from TXE PIO parity error\n");
412         }
413 }
414
415
416 /**
417  * ipath_pe_handle_hwerrors - display hardware errors.
418  * @dd: the infinipath device
419  * @msg: the output buffer
420  * @msgl: the size of the output buffer
421  *
422  * Use same msg buffer as regular errors to avoid excessive stack
423  * use.  Most hardware errors are catastrophic, but for right now,
424  * we'll print them and continue.  We reuse the same message buffer as
425  * ipath_handle_errors() to avoid excessive stack usage.
426  */
427 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
428                                      size_t msgl)
429 {
430         ipath_err_t hwerrs;
431         u32 bits, ctrl;
432         int isfatal = 0;
433         char bitsmsg[64];
434         int log_idx;
435
436         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
437         if (!hwerrs) {
438                 /*
439                  * better than printing cofusing messages
440                  * This seems to be related to clearing the crc error, or
441                  * the pll error during init.
442                  */
443                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
444                 return;
445         } else if (hwerrs == ~0ULL) {
446                 ipath_dev_err(dd, "Read of hardware error status failed "
447                               "(all bits set); ignoring\n");
448                 return;
449         }
450         ipath_stats.sps_hwerrs++;
451
452         /* Always clear the error status register, except MEMBISTFAIL,
453          * regardless of whether we continue or stop using the chip.
454          * We want that set so we know it failed, even across driver reload.
455          * We'll still ignore it in the hwerrmask.  We do this partly for
456          * diagnostics, but also for support */
457         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
458                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
459
460         hwerrs &= dd->ipath_hwerrmask;
461
462         /* We log some errors to EEPROM, check if we have any of those. */
463         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
464                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
465                         ipath_inc_eeprom_err(dd, log_idx, 1);
466
467         /*
468          * make sure we get this much out, unless told to be quiet,
469          * or it's occurred within the last 5 seconds
470          */
471         if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
472                         RXE_EAGER_PARITY)) ||
473             (ipath_debug & __IPATH_VERBDBG))
474                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
475                          "(cleared)\n", (unsigned long long) hwerrs);
476         dd->ipath_lasthwerror |= hwerrs;
477
478         if (hwerrs & ~dd->ipath_hwe_bitsextant)
479                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
480                               "%llx set\n", (unsigned long long)
481                               (hwerrs & ~dd->ipath_hwe_bitsextant));
482
483         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
484         if (ctrl & INFINIPATH_C_FREEZEMODE) {
485                 /*
486                  * parity errors in send memory are recoverable,
487                  * just cancel the send (if indicated in * sendbuffererror),
488                  * count the occurrence, unfreeze (if no other handled
489                  * hardware error bits are set), and continue. They can
490                  * occur if a processor speculative read is done to the PIO
491                  * buffer while we are sending a packet, for example.
492                  */
493                 if (hwerrs & TXE_PIO_PARITY) {
494                         ipath_pe_txe_recover(dd);
495                         hwerrs &= ~TXE_PIO_PARITY;
496                 }
497                 if (!hwerrs) {
498                         static u32 freeze_cnt;
499
500                         freeze_cnt++;
501                         ipath_dbg("Clearing freezemode on ignored or recovered "
502                                   "hardware error (%u)\n", freeze_cnt);
503                         ipath_clear_freeze(dd);
504                 }
505         }
506
507         *msg = '\0';
508
509         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
510                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
511                         msgl);
512                 /* ignore from now on, so disable until driver reloaded */
513                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
514                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
515                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
516                                  dd->ipath_hwerrmask);
517         }
518
519         ipath_format_hwerrors(hwerrs,
520                               ipath_6120_hwerror_msgs,
521                               sizeof(ipath_6120_hwerror_msgs)/
522                               sizeof(ipath_6120_hwerror_msgs[0]),
523                               msg, msgl);
524
525         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
526                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
527                 bits = (u32) ((hwerrs >>
528                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
529                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
530                 snprintf(bitsmsg, sizeof bitsmsg,
531                          "[PCIe Mem Parity Errs %x] ", bits);
532                 strlcat(msg, bitsmsg, msgl);
533         }
534
535 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
536                          INFINIPATH_HWE_COREPLL_RFSLIP )
537
538         if (hwerrs & _IPATH_PLL_FAIL) {
539                 snprintf(bitsmsg, sizeof bitsmsg,
540                          "[PLL failed (%llx), InfiniPath hardware unusable]",
541                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
542                 strlcat(msg, bitsmsg, msgl);
543                 /* ignore from now on, so disable until driver reloaded */
544                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
545                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
546                                  dd->ipath_hwerrmask);
547         }
548
549         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
550                 /*
551                  * If it occurs, it is left masked since the external
552                  * interface is unused
553                  */
554                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
555                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
556                                  dd->ipath_hwerrmask);
557         }
558
559         if (*msg)
560                 ipath_dev_err(dd, "%s hardware error\n", msg);
561         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
562                 /*
563                  * for /sys status file ; if no trailing } is copied, we'll
564                  * know it was truncated.
565                  */
566                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
567                          "{%s}", msg);
568         }
569 }
570
571 /**
572  * ipath_pe_boardname - fill in the board name
573  * @dd: the infinipath device
574  * @name: the output buffer
575  * @namelen: the size of the output buffer
576  *
577  * info is based on the board revision register
578  */
579 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
580                               size_t namelen)
581 {
582         char *n = NULL;
583         u8 boardrev = dd->ipath_boardrev;
584         int ret;
585
586         switch (boardrev) {
587         case 0:
588                 n = "InfiniPath_Emulation";
589                 break;
590         case 1:
591                 n = "InfiniPath_QLE7140-Bringup";
592                 break;
593         case 2:
594                 n = "InfiniPath_QLE7140";
595                 break;
596         case 3:
597                 n = "InfiniPath_QMI7140";
598                 break;
599         case 4:
600                 n = "InfiniPath_QEM7140";
601                 break;
602         case 5:
603                 n = "InfiniPath_QMH7140";
604                 break;
605         case 6:
606                 n = "InfiniPath_QLE7142";
607                 break;
608         default:
609                 ipath_dev_err(dd,
610                               "Don't yet know about board with ID %u\n",
611                               boardrev);
612                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
613                          boardrev);
614                 break;
615         }
616         if (n)
617                 snprintf(name, namelen, "%s", n);
618
619         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
620                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
621                               dd->ipath_majrev, dd->ipath_minrev);
622                 ret = 1;
623         } else {
624                 ret = 0;
625                 if (dd->ipath_minrev >= 2)
626                         dd->ipath_f_put_tid = ipath_pe_put_tid_2;
627         }
628
629         /*
630          * set here, not in ipath_init_*_funcs because we have to do
631          * it after we can read chip registers.
632          */
633         dd->ipath_ureg_align =
634                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
635
636         return ret;
637 }
638
639 /**
640  * ipath_pe_init_hwerrors - enable hardware errors
641  * @dd: the infinipath device
642  *
643  * now that we have finished initializing everything that might reasonably
644  * cause a hardware error, and cleared those errors bits as they occur,
645  * we can enable hardware errors in the mask (potentially enabling
646  * freeze mode), and enable hardware errors as errors (along with
647  * everything else) in errormask
648  */
649 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
650 {
651         ipath_err_t val;
652         u64 extsval;
653
654         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
655
656         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
657                 ipath_dev_err(dd, "MemBIST did not complete!\n");
658         if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
659                 ipath_dbg("MemBIST corrected\n");
660
661         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
662
663         if (!dd->ipath_boardrev)        // no PLL for Emulator
664                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
665
666         if (dd->ipath_minrev < 2) {
667                 /* workaround bug 9460 in internal interface bus parity
668                  * checking. Fixed (HW bug 9490) in Rev2.
669                  */
670                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
671         }
672         dd->ipath_hwerrmask = val;
673 }
674
675 /**
676  * ipath_pe_bringup_serdes - bring up the serdes
677  * @dd: the infinipath device
678  */
679 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
680 {
681         u64 val, config1, prev_val;
682         int ret = 0;
683
684         ipath_dbg("Trying to bringup serdes\n");
685
686         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
687             INFINIPATH_HWE_SERDESPLLFAILED) {
688                 ipath_dbg("At start, serdes PLL failed bit set "
689                           "in hwerrstatus, clearing and continuing\n");
690                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
691                                  INFINIPATH_HWE_SERDESPLLFAILED);
692         }
693
694         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
695         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
696
697         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
698                    "xgxsconfig %llx\n", (unsigned long long) val,
699                    (unsigned long long) config1, (unsigned long long)
700                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
701
702         /*
703          * Force reset on, also set rxdetect enable.  Must do before reading
704          * serdesstatus at least for simulation, or some of the bits in
705          * serdes status will come back as undefined and cause simulation
706          * failures
707          */
708         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
709                 | INFINIPATH_SERDC0_L1PWR_DN;
710         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
711         /* be sure chip saw it */
712         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
713         udelay(5);              /* need pll reset set at least for a bit */
714         /*
715          * after PLL is reset, set the per-lane Resets and TxIdle and
716          * clear the PLL reset and rxdetect (to get falling edge).
717          * Leave L1PWR bits set (permanently)
718          */
719         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
720                  | INFINIPATH_SERDC0_L1PWR_DN);
721         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
722         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
723                    "and txidle (%llx)\n", (unsigned long long) val);
724         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
725         /* be sure chip saw it */
726         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
727         /* need PLL reset clear for at least 11 usec before lane
728          * resets cleared; give it a few more to be sure */
729         udelay(15);
730         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
731
732         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
733                    "(writing %llx)\n", (unsigned long long) val);
734         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
735         /* be sure chip saw it */
736         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
737
738         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
739         prev_val = val;
740         if (val & INFINIPATH_XGXS_RESET)
741                 val &= ~INFINIPATH_XGXS_RESET;
742         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
743              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
744                 /* need to compensate for Tx inversion in partner */
745                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
746                          INFINIPATH_XGXS_RX_POL_SHIFT);
747                 val |= dd->ipath_rx_pol_inv <<
748                         INFINIPATH_XGXS_RX_POL_SHIFT;
749         }
750         if (val != prev_val)
751                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
752
753         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
754
755         /* clear current and de-emphasis bits */
756         config1 &= ~0x0ffffffff00ULL;
757         /* set current to 20ma */
758         config1 |= 0x00000000000ULL;
759         /* set de-emphasis to -5.68dB */
760         config1 |= 0x0cccc000000ULL;
761         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
762
763         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
764                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
765                    (unsigned long long) val, (unsigned long long) config1,
766                    (unsigned long long)
767                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
768                    (unsigned long long)
769                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
770
771         return ret;
772 }
773
774 /**
775  * ipath_pe_quiet_serdes - set serdes to txidle
776  * @dd: the infinipath device
777  * Called when driver is being unloaded
778  */
779 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
780 {
781         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
782
783         val |= INFINIPATH_SERDC0_TXIDLE;
784         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
785                   (unsigned long long) val);
786         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
787 }
788
789 static int ipath_pe_intconfig(struct ipath_devdata *dd)
790 {
791         u32 chiprev;
792
793         /*
794          * If the chip supports added error indication via GPIO pins,
795          * enable interrupts on those bits so the interrupt routine
796          * can count the events. Also set flag so interrupt routine
797          * can know they are expected.
798          */
799         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
800         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
801                 /* Rev2+ reports extra errors via internal GPIO pins */
802                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
803                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
804                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
805                                  dd->ipath_gpio_mask);
806         }
807         return 0;
808 }
809
810 /**
811  * ipath_setup_pe_setextled - set the state of the two external LEDs
812  * @dd: the infinipath device
813  * @lst: the L state
814  * @ltst: the LT state
815
816  * These LEDs indicate the physical and logical state of IB link.
817  * For this chip (at least with recommended board pinouts), LED1
818  * is Yellow (logical state) and LED2 is Green (physical state),
819  *
820  * Note:  We try to match the Mellanox HCA LED behavior as best
821  * we can.  Green indicates physical link state is OK (something is
822  * plugged in, and we can train).
823  * Amber indicates the link is logically up (ACTIVE).
824  * Mellanox further blinks the amber LED to indicate data packet
825  * activity, but we have no hardware support for that, so it would
826  * require waking up every 10-20 msecs and checking the counters
827  * on the chip, and then turning the LED off if appropriate.  That's
828  * visible overhead, so not something we will do.
829  *
830  */
831 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
832                                      u64 ltst)
833 {
834         u64 extctl;
835         unsigned long flags = 0;
836
837         /* the diags use the LED to indicate diag info, so we leave
838          * the external LED alone when the diags are running */
839         if (ipath_diag_inuse)
840                 return;
841
842         /* Allow override of LED display for, e.g. Locating system in rack */
843         if (dd->ipath_led_override) {
844                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
845                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
846                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
847                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
848                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
849                         : INFINIPATH_IBCS_L_STATE_DOWN;
850         }
851
852         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
853         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
854                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
855
856         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
857                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
858         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
859                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
860         dd->ipath_extctrl = extctl;
861         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
862         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
863 }
864
865 /**
866  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
867  * @dd: the infinipath device
868  *
869  * This is called during driver unload.
870  * We do the pci_disable_msi here, not in generic code, because it
871  * isn't used for the HT chips. If we do end up needing pci_enable_msi
872  * at some point in the future for HT, we'll move the call back
873  * into the main init_one code.
874  */
875 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
876 {
877         dd->ipath_msi_lo = 0;   /* just in case unload fails */
878         pci_disable_msi(dd->pcidev);
879 }
880
881 static void ipath_6120_pcie_params(struct ipath_devdata *dd)
882 {
883         u16 linkstat, speed;
884         int pos;
885
886         pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
887         if (!pos) {
888                 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
889                 goto bail;
890         }
891
892         pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
893                              &linkstat);
894         /*
895          * speed is bits 0-4, linkwidth is bits 4-8
896          * no defines for them in headers
897          */
898         speed = linkstat & 0xf;
899         linkstat >>= 4;
900         linkstat &= 0x1f;
901         dd->ipath_lbus_width = linkstat;
902
903         switch (speed) {
904         case 1:
905                 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
906                 break;
907         case 2:
908                 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
909                 break;
910         default: /* not defined, assume gen1 */
911                 dd->ipath_lbus_speed = 2500;
912                 break;
913         }
914
915         if (linkstat < 8)
916                 ipath_dev_err(dd,
917                         "PCIe width %u (x8 HCA), performance reduced\n",
918                         linkstat);
919         else
920                 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x8 HCA)\n",
921                         dd->ipath_lbus_speed, linkstat);
922
923         if (speed != 1)
924                 ipath_dev_err(dd,
925                         "PCIe linkspeed %u is incorrect; "
926                         "should be 1 (2500)!\n", speed);
927 bail:
928         /* fill in string, even on errors */
929         snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
930                 "PCIe,%uMHz,x%u\n",
931                 dd->ipath_lbus_speed,
932                 dd->ipath_lbus_width);
933
934         return;
935 }
936
937 /**
938  * ipath_setup_pe_config - setup PCIe config related stuff
939  * @dd: the infinipath device
940  * @pdev: the PCI device
941  *
942  * The pci_enable_msi() call will fail on systems with MSI quirks
943  * such as those with AMD8131, even if the device of interest is not
944  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
945  * late in 2.6.16).
946  * All that can be done is to edit the kernel source to remove the quirk
947  * check until that is fixed.
948  * We do not need to call enable_msi() for our HyperTransport chip,
949  * even though it uses MSI, and we want to avoid the quirk warning, so
950  * So we call enable_msi only for PCIe.  If we do end up needing
951  * pci_enable_msi at some point in the future for HT, we'll move the
952  * call back into the main init_one code.
953  * We save the msi lo and hi values, so we can restore them after
954  * chip reset (the kernel PCI infrastructure doesn't yet handle that
955  * correctly).
956  */
957 static int ipath_setup_pe_config(struct ipath_devdata *dd,
958                                  struct pci_dev *pdev)
959 {
960         int pos, ret;
961
962         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
963         ret = pci_enable_msi(dd->pcidev);
964         if (ret)
965                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
966                               "interrupts may not work\n", ret);
967         /* continue even if it fails, we may still be OK... */
968         dd->ipath_irq = pdev->irq;
969
970         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
971                 u16 control;
972                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
973                                       &dd->ipath_msi_lo);
974                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
975                                       &dd->ipath_msi_hi);
976                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
977                                      &control);
978                 /* now save the data (vector) info */
979                 pci_read_config_word(dd->pcidev,
980                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
981                                             ? 12 : 8),
982                                      &dd->ipath_msi_data);
983                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
984                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
985                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
986                            control);
987                 /* we save the cachelinesize also, although it doesn't
988                  * really matter */
989                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
990                                      &dd->ipath_pci_cacheline);
991         } else
992                 ipath_dev_err(dd, "Can't find MSI capability, "
993                               "can't save MSI settings for reset\n");
994
995         ipath_6120_pcie_params(dd);
996
997         dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
998         dd->ipath_link_speed_supported = IPATH_IB_SDR;
999         dd->ipath_link_width_enabled = IB_WIDTH_4X;
1000         dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1001         /* these can't change for this chip, so set once */
1002         dd->ipath_link_width_active = dd->ipath_link_width_enabled;
1003         dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
1004         return 0;
1005 }
1006
1007 static void ipath_init_pe_variables(struct ipath_devdata *dd)
1008 {
1009         /*
1010          * setup the register offsets, since they are different for each
1011          * chip
1012          */
1013         dd->ipath_kregs = &ipath_pe_kregs;
1014         dd->ipath_cregs = &ipath_pe_cregs;
1015
1016         /*
1017          * bits for selecting i2c direction and values,
1018          * used for I2C serial flash
1019          */
1020         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1021         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1022         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1023         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1024
1025         /*
1026          * Fill in data for field-values that change in newer chips.
1027          * We dynamically specify only the mask for LINKTRAININGSTATE
1028          * and only the shift for LINKSTATE, as they are the only ones
1029          * that change.  Also precalculate the 3 link states of interest
1030          * and the combined mask.
1031          */
1032         dd->ibcs_ls_shift = IBA6120_IBCS_LINKSTATE_SHIFT;
1033         dd->ibcs_lts_mask = IBA6120_IBCS_LINKTRAININGSTATE_MASK;
1034         dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1035                 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1036         dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1037                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1038                 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1039         dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1040                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1041                 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1042         dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1043                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1044                 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1045
1046         /*
1047          * Fill in data for ibcc field-values that change in newer chips.
1048          * We dynamically specify only the mask for LINKINITCMD
1049          * and only the shift for LINKCMD and MAXPKTLEN, as they are
1050          * the only ones that change.
1051          */
1052         dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
1053         dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1054         dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1055
1056         /* Fill in shifts for RcvCtrl. */
1057         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1058         dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1059         dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1060         dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
1061
1062         /* variables for sanity checking interrupt and errors */
1063         dd->ipath_hwe_bitsextant =
1064                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1065                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1066                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1067                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1068                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1069                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1070                 INFINIPATH_HWE_PCIE1PLLFAILED |
1071                 INFINIPATH_HWE_PCIE0PLLFAILED |
1072                 INFINIPATH_HWE_PCIEPOISONEDTLP |
1073                 INFINIPATH_HWE_PCIECPLTIMEOUT |
1074                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1075                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1076                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1077                 INFINIPATH_HWE_MEMBISTFAILED |
1078                 INFINIPATH_HWE_COREPLL_FBSLIP |
1079                 INFINIPATH_HWE_COREPLL_RFSLIP |
1080                 INFINIPATH_HWE_SERDESPLLFAILED |
1081                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1082                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1083         dd->ipath_i_bitsextant =
1084                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1085                 (INFINIPATH_I_RCVAVAIL_MASK <<
1086                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1087                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1088                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1089         dd->ipath_e_bitsextant =
1090                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1091                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1092                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1093                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1094                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1095                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1096                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1097                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1098                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1099                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1100                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1101                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1102                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1103                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1104                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1105                 INFINIPATH_E_HARDWARE;
1106
1107         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1108         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1109         dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1110         dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1111
1112         /*
1113          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1114          * 2 is Some Misc, 3 is reserved for future.
1115          */
1116         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1117                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1118                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1119
1120         /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1121         if (ipath_unordered_wc())
1122                 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1123
1124         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1125                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1126                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1127
1128         dd->ipath_eep_st_masks[2].errs_to_log =
1129                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1130
1131
1132         dd->delay_mult = 2; /* SDR, 4X, can't change */
1133 }
1134
1135 /* setup the MSI stuff again after a reset.  I'd like to just call
1136  * pci_enable_msi() and request_irq() again, but when I do that,
1137  * the MSI enable bit doesn't get set in the command word, and
1138  * we switch to to a different interrupt vector, which is confusing,
1139  * so I instead just do it all inline.  Perhaps somehow can tie this
1140  * into the PCIe hotplug support at some point
1141  * Note, because I'm doing it all here, I don't call pci_disable_msi()
1142  * or free_irq() at the start of ipath_setup_pe_reset().
1143  */
1144 static int ipath_reinit_msi(struct ipath_devdata *dd)
1145 {
1146         int pos;
1147         u16 control;
1148         int ret;
1149
1150         if (!dd->ipath_msi_lo) {
1151                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1152                          "initial setup failed?\n");
1153                 ret = 0;
1154                 goto bail;
1155         }
1156
1157         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1158                 ipath_dev_err(dd, "Can't find MSI capability, "
1159                               "can't restore MSI settings\n");
1160                 ret = 0;
1161                 goto bail;
1162         }
1163         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1164                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1165         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1166                                dd->ipath_msi_lo);
1167         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1168                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1169         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1170                                dd->ipath_msi_hi);
1171         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1172         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1173                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1174                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1175                            control, control | PCI_MSI_FLAGS_ENABLE);
1176                 control |= PCI_MSI_FLAGS_ENABLE;
1177                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1178                                       control);
1179         }
1180         /* now rewrite the data (vector) info */
1181         pci_write_config_word(dd->pcidev, pos +
1182                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1183                               dd->ipath_msi_data);
1184         /* we restore the cachelinesize also, although it doesn't really
1185          * matter */
1186         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1187                               dd->ipath_pci_cacheline);
1188         /* and now set the pci master bit again */
1189         pci_set_master(dd->pcidev);
1190         ret = 1;
1191
1192 bail:
1193         return ret;
1194 }
1195
1196 /* This routine sleeps, so it can only be called from user context, not
1197  * from interrupt context.  If we need interrupt context, we can split
1198  * it into two routines.
1199 */
1200 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1201 {
1202         u64 val;
1203         int i;
1204         int ret;
1205
1206         /* Use ERROR so it shows up in logs, etc. */
1207         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1208         /* keep chip from being accessed in a few places */
1209         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1210         val = dd->ipath_control | INFINIPATH_C_RESET;
1211         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1212         mb();
1213
1214         for (i = 1; i <= 5; i++) {
1215                 int r;
1216                 /* allow MBIST, etc. to complete; longer on each retry.
1217                  * We sometimes get machine checks from bus timeout if no
1218                  * response, so for now, make it *really* long.
1219                  */
1220                 msleep(1000 + (1 + i) * 2000);
1221                 if ((r =
1222                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1223                                             dd->ipath_pcibar0)))
1224                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1225                                       r);
1226                 if ((r =
1227                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1228                                             dd->ipath_pcibar1)))
1229                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1230                                       r);
1231                 /* now re-enable memory access */
1232                 if ((r = pci_enable_device(dd->pcidev)))
1233                         ipath_dev_err(dd, "pci_enable_device failed after "
1234                                       "reset: %d\n", r);
1235                 /* whether it worked or not, mark as present, again */
1236                 dd->ipath_flags |= IPATH_PRESENT;
1237                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1238                 if (val == dd->ipath_revision) {
1239                         ipath_cdbg(VERBOSE, "Got matching revision "
1240                                    "register %llx on try %d\n",
1241                                    (unsigned long long) val, i);
1242                         ret = ipath_reinit_msi(dd);
1243                         goto bail;
1244                 }
1245                 /* Probably getting -1 back */
1246                 ipath_dbg("Didn't get expected revision register, "
1247                           "got %llx, try %d\n", (unsigned long long) val,
1248                           i + 1);
1249         }
1250         ret = 0; /* failed */
1251
1252 bail:
1253         if (ret)
1254                 ipath_6120_pcie_params(dd);
1255         return ret;
1256 }
1257
1258 /**
1259  * ipath_pe_put_tid - write a TID in chip
1260  * @dd: the infinipath device
1261  * @tidptr: pointer to the expected TID (in chip) to udpate
1262  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1263  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1264  *
1265  * This exists as a separate routine to allow for special locking etc.
1266  * It's used for both the full cleanup on exit, as well as the normal
1267  * setup and teardown.
1268  */
1269 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1270                              u32 type, unsigned long pa)
1271 {
1272         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1273         unsigned long flags = 0; /* keep gcc quiet */
1274
1275         if (pa != dd->ipath_tidinvalid) {
1276                 if (pa & ((1U << 11) - 1)) {
1277                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1278                                  "not 4KB aligned!\n", pa);
1279                         return;
1280                 }
1281                 pa >>= 11;
1282                 /* paranoia check */
1283                 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1284                         ipath_dev_err(dd,
1285                                       "BUG: Physical page address 0x%lx "
1286                                       "has bits set in 31-29\n", pa);
1287
1288                 if (type == RCVHQ_RCV_TYPE_EAGER)
1289                         pa |= dd->ipath_tidtemplate;
1290                 else /* for now, always full 4KB page */
1291                         pa |= 2 << 29;
1292         }
1293
1294         /*
1295          * Workaround chip bug 9437 by writing the scratch register
1296          * before and after the TID, and with an io write barrier.
1297          * We use a spinlock around the writes, so they can't intermix
1298          * with other TID (eager or expected) writes (the chip bug
1299          * is triggered by back to back TID writes). Unfortunately, this
1300          * call can be done from interrupt level for the port 0 eager TIDs,
1301          * so we have to use irqsave locks.
1302          */
1303         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1304         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1305         if (dd->ipath_kregbase)
1306                 writel(pa, tidp32);
1307         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1308         mmiowb();
1309         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1310 }
1311 /**
1312  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1313  * @dd: the infinipath device
1314  * @tidptr: pointer to the expected TID (in chip) to udpate
1315  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1316  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1317  *
1318  * This exists as a separate routine to allow for selection of the
1319  * appropriate "flavor". The static calls in cleanup just use the
1320  * revision-agnostic form, as they are not performance critical.
1321  */
1322 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1323                              u32 type, unsigned long pa)
1324 {
1325         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1326
1327         if (pa != dd->ipath_tidinvalid) {
1328                 if (pa & ((1U << 11) - 1)) {
1329                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1330                                  "not 2KB aligned!\n", pa);
1331                         return;
1332                 }
1333                 pa >>= 11;
1334                 /* paranoia check */
1335                 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1336                         ipath_dev_err(dd,
1337                                       "BUG: Physical page address 0x%lx "
1338                                       "has bits set in 31-29\n", pa);
1339
1340                 if (type == RCVHQ_RCV_TYPE_EAGER)
1341                         pa |= dd->ipath_tidtemplate;
1342                 else /* for now, always full 4KB page */
1343                         pa |= 2 << 29;
1344         }
1345         if (dd->ipath_kregbase)
1346                 writel(pa, tidp32);
1347         mmiowb();
1348 }
1349
1350
1351 /**
1352  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1353  * @dd: the infinipath device
1354  * @port: the port
1355  *
1356  * clear all TID entries for a port, expected and eager.
1357  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1358  * not 64, but they are still on 64 bit boundaries, so tidbase
1359  * is declared as u64 * for the pointer math, even though we write 32 bits
1360  */
1361 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1362 {
1363         u64 __iomem *tidbase;
1364         unsigned long tidinv;
1365         int i;
1366
1367         if (!dd->ipath_kregbase)
1368                 return;
1369
1370         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1371
1372         tidinv = dd->ipath_tidinvalid;
1373         tidbase = (u64 __iomem *)
1374                 ((char __iomem *)(dd->ipath_kregbase) +
1375                  dd->ipath_rcvtidbase +
1376                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1377
1378         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1379                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1380                                  tidinv);
1381
1382         tidbase = (u64 __iomem *)
1383                 ((char __iomem *)(dd->ipath_kregbase) +
1384                  dd->ipath_rcvegrbase +
1385                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1386
1387         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1388                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1389                                  tidinv);
1390 }
1391
1392 /**
1393  * ipath_pe_tidtemplate - setup constants for TID updates
1394  * @dd: the infinipath device
1395  *
1396  * We setup stuff that we use a lot, to avoid calculating each time
1397  */
1398 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1399 {
1400         u32 egrsize = dd->ipath_rcvegrbufsize;
1401
1402         /* For now, we always allocate 4KB buffers (at init) so we can
1403          * receive max size packets.  We may want a module parameter to
1404          * specify 2KB or 4KB and/or make be per port instead of per device
1405          * for those who want to reduce memory footprint.  Note that the
1406          * ipath_rcvhdrentsize size must be large enough to hold the largest
1407          * IB header (currently 96 bytes) that we expect to handle (plus of
1408          * course the 2 dwords of RHF).
1409          */
1410         if (egrsize == 2048)
1411                 dd->ipath_tidtemplate = 1U << 29;
1412         else if (egrsize == 4096)
1413                 dd->ipath_tidtemplate = 2U << 29;
1414         else {
1415                 egrsize = 4096;
1416                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1417                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1418                          egrsize);
1419                 dd->ipath_tidtemplate = 2U << 29;
1420         }
1421         dd->ipath_tidinvalid = 0;
1422 }
1423
1424 static int ipath_pe_early_init(struct ipath_devdata *dd)
1425 {
1426         dd->ipath_flags |= IPATH_4BYTE_TID;
1427         if (ipath_unordered_wc())
1428                 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1429
1430         /*
1431          * For openfabrics, we need to be able to handle an IB header of
1432          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1433          * made them the same size as the PIO buffers.  This chip does not
1434          * handle arbitrary size buffers, so we need the header large enough
1435          * to handle largest IB header, but still have room for a 2KB MTU
1436          * standard IB packet.
1437          */
1438         dd->ipath_rcvhdrentsize = 24;
1439         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1440         dd->ipath_rhf_offset = 0;
1441         dd->ipath_egrtidbase = (u64 __iomem *)
1442                 ((char __iomem *) dd->ipath_kregbase + dd->ipath_rcvegrbase);
1443
1444         /*
1445          * To truly support a 4KB MTU (for usermode), we need to
1446          * bump this to a larger value.  For now, we use them for
1447          * the kernel only.
1448          */
1449         dd->ipath_rcvegrbufsize = 2048;
1450         /*
1451          * the min() check here is currently a nop, but it may not always
1452          * be, depending on just how we do ipath_rcvegrbufsize
1453          */
1454         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1455                                  dd->ipath_rcvegrbufsize +
1456                                  (dd->ipath_rcvhdrentsize << 2));
1457         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1458
1459         /*
1460          * We can request a receive interrupt for 1 or
1461          * more packets from current offset.  For now, we set this
1462          * up for a single packet.
1463          */
1464         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1465
1466         ipath_get_eeprom_info(dd);
1467
1468         return 0;
1469 }
1470
1471 int __attribute__((weak)) ipath_unordered_wc(void)
1472 {
1473         return 0;
1474 }
1475
1476 /**
1477  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1478  * @pd: the infinipath port
1479  * @kbase: ipath_base_info pointer
1480  *
1481  * We set the PCIE flag because the lower bandwidth on PCIe vs
1482  * HyperTransport can affect some user packet algorithms.
1483  */
1484 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1485 {
1486         struct ipath_base_info *kinfo = kbase;
1487         struct ipath_devdata *dd;
1488
1489         if (ipath_unordered_wc()) {
1490                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1491                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1492         }
1493         else
1494                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1495
1496         if (pd == NULL)
1497                 goto done;
1498
1499         dd = pd->port_dd;
1500
1501 done:
1502         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1503                 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1504         return 0;
1505 }
1506
1507 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1508 {
1509         free_irq(dd->ipath_irq, dd);
1510         dd->ipath_irq = 0;
1511 }
1512
1513
1514 static struct ipath_message_header *
1515 ipath_pe_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1516 {
1517         return (struct ipath_message_header *)
1518                 &rhf_addr[sizeof(u64) / sizeof(u32)];
1519 }
1520
1521 static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports)
1522 {
1523         dd->ipath_portcnt =
1524                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1525         dd->ipath_p0_rcvegrcnt =
1526                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1527 }
1528
1529 static void ipath_pe_read_counters(struct ipath_devdata *dd,
1530                                    struct infinipath_counters *cntrs)
1531 {
1532         cntrs->LBIntCnt =
1533                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1534         cntrs->LBFlowStallCnt =
1535                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1536         cntrs->TxSDmaDescCnt = 0;
1537         cntrs->TxUnsupVLErrCnt =
1538                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1539         cntrs->TxDataPktCnt =
1540                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1541         cntrs->TxFlowPktCnt =
1542                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1543         cntrs->TxDwordCnt =
1544                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1545         cntrs->TxLenErrCnt =
1546                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1547         cntrs->TxMaxMinLenErrCnt =
1548                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1549         cntrs->TxUnderrunCnt =
1550                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1551         cntrs->TxFlowStallCnt =
1552                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1553         cntrs->TxDroppedPktCnt =
1554                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1555         cntrs->RxDroppedPktCnt =
1556                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1557         cntrs->RxDataPktCnt =
1558                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1559         cntrs->RxFlowPktCnt =
1560                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1561         cntrs->RxDwordCnt =
1562                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1563         cntrs->RxLenErrCnt =
1564                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1565         cntrs->RxMaxMinLenErrCnt =
1566                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1567         cntrs->RxICRCErrCnt =
1568                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1569         cntrs->RxVCRCErrCnt =
1570                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1571         cntrs->RxFlowCtrlErrCnt =
1572                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1573         cntrs->RxBadFormatCnt =
1574                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1575         cntrs->RxLinkProblemCnt =
1576                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1577         cntrs->RxEBPCnt =
1578                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1579         cntrs->RxLPCRCErrCnt =
1580                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1581         cntrs->RxBufOvflCnt =
1582                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1583         cntrs->RxTIDFullErrCnt =
1584                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1585         cntrs->RxTIDValidErrCnt =
1586                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1587         cntrs->RxPKeyMismatchCnt =
1588                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1589         cntrs->RxP0HdrEgrOvflCnt =
1590                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1591         cntrs->RxP1HdrEgrOvflCnt =
1592                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1593         cntrs->RxP2HdrEgrOvflCnt =
1594                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1595         cntrs->RxP3HdrEgrOvflCnt =
1596                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1597         cntrs->RxP4HdrEgrOvflCnt =
1598                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1599         cntrs->RxP5HdrEgrOvflCnt = 0;
1600         cntrs->RxP6HdrEgrOvflCnt = 0;
1601         cntrs->RxP7HdrEgrOvflCnt = 0;
1602         cntrs->RxP8HdrEgrOvflCnt = 0;
1603         cntrs->RxP9HdrEgrOvflCnt = 0;
1604         cntrs->RxP10HdrEgrOvflCnt = 0;
1605         cntrs->RxP11HdrEgrOvflCnt = 0;
1606         cntrs->RxP12HdrEgrOvflCnt = 0;
1607         cntrs->RxP13HdrEgrOvflCnt = 0;
1608         cntrs->RxP14HdrEgrOvflCnt = 0;
1609         cntrs->RxP15HdrEgrOvflCnt = 0;
1610         cntrs->RxP16HdrEgrOvflCnt = 0;
1611         cntrs->IBStatusChangeCnt =
1612                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1613         cntrs->IBLinkErrRecoveryCnt =
1614                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1615         cntrs->IBLinkDownedCnt =
1616                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1617         cntrs->IBSymbolErrCnt =
1618                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1619         cntrs->RxVL15DroppedPktCnt = 0;
1620         cntrs->RxOtherLocalPhyErrCnt = 0;
1621         cntrs->PcieRetryBufDiagQwordCnt = 0;
1622         cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1623         cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1624         cntrs->RxVlErrCnt = 0;
1625         cntrs->RxDlidFltrCnt = 0;
1626 }
1627
1628
1629 /* no interrupt fallback for these chips */
1630 static int ipath_pe_nointr_fallback(struct ipath_devdata *dd)
1631 {
1632         return 0;
1633 }
1634
1635
1636 /*
1637  * reset the XGXS (between serdes and IBC).  Slightly less intrusive
1638  * than resetting the IBC or external link state, and useful in some
1639  * cases to cause some retraining.  To do this right, we reset IBC
1640  * as well.
1641  */
1642 static void ipath_pe_xgxs_reset(struct ipath_devdata *dd)
1643 {
1644         u64 val, prev_val;
1645
1646         prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1647         val = prev_val | INFINIPATH_XGXS_RESET;
1648         prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1649         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1650                          dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1651         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1652         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1653         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1654         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1655                          dd->ipath_control);
1656 }
1657
1658
1659 static int ipath_pe_get_ib_cfg(struct ipath_devdata *dd, int which)
1660 {
1661         int ret;
1662
1663         switch (which) {
1664         case IPATH_IB_CFG_LWID:
1665                 ret = dd->ipath_link_width_active;
1666                 break;
1667         case IPATH_IB_CFG_SPD:
1668                 ret = dd->ipath_link_speed_active;
1669                 break;
1670         case IPATH_IB_CFG_LWID_ENB:
1671                 ret = dd->ipath_link_width_enabled;
1672                 break;
1673         case IPATH_IB_CFG_SPD_ENB:
1674                 ret = dd->ipath_link_speed_enabled;
1675                 break;
1676         default:
1677                 ret =  -ENOTSUPP;
1678                 break;
1679         }
1680         return ret;
1681 }
1682
1683
1684 /* we assume range checking is already done, if needed */
1685 static int ipath_pe_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1686 {
1687         int ret = 0;
1688
1689         if (which == IPATH_IB_CFG_LWID_ENB)
1690                 dd->ipath_link_width_enabled = val;
1691         else if (which == IPATH_IB_CFG_SPD_ENB)
1692                 dd->ipath_link_speed_enabled = val;
1693         else
1694                 ret = -ENOTSUPP;
1695         return ret;
1696 }
1697
1698 static void ipath_pe_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1699 {
1700 }
1701
1702
1703 static int ipath_pe_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1704 {
1705         ipath_setup_pe_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1706                 ipath_ib_linktrstate(dd, ibcs));
1707         return 0;
1708 }
1709
1710
1711 /**
1712  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1713  * @dd: the infinipath device
1714  *
1715  * This is global, and is called directly at init to set up the
1716  * chip-specific function pointers for later use.
1717  */
1718 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1719 {
1720         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1721         dd->ipath_f_bus = ipath_setup_pe_config;
1722         dd->ipath_f_reset = ipath_setup_pe_reset;
1723         dd->ipath_f_get_boardname = ipath_pe_boardname;
1724         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1725         dd->ipath_f_early_init = ipath_pe_early_init;
1726         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1727         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1728         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1729         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1730         /*
1731          * _f_put_tid may get changed after we read the chip revision,
1732          * but we start with the safe version for all revs
1733          */
1734         dd->ipath_f_put_tid = ipath_pe_put_tid;
1735         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1736         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1737         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1738         dd->ipath_f_free_irq = ipath_pe_free_irq;
1739         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1740         dd->ipath_f_intr_fallback = ipath_pe_nointr_fallback;
1741         dd->ipath_f_xgxs_reset = ipath_pe_xgxs_reset;
1742         dd->ipath_f_get_msgheader = ipath_pe_get_msgheader;
1743         dd->ipath_f_config_ports = ipath_pe_config_ports;
1744         dd->ipath_f_read_counters = ipath_pe_read_counters;
1745         dd->ipath_f_get_ib_cfg = ipath_pe_get_ib_cfg;
1746         dd->ipath_f_set_ib_cfg = ipath_pe_set_ib_cfg;
1747         dd->ipath_f_config_jint = ipath_pe_config_jint;
1748         dd->ipath_f_ib_updown = ipath_pe_ib_updown;
1749
1750
1751         /* initialize chip-specific variables */
1752         ipath_init_pe_variables(dd);
1753 }
1754