drivers/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  *
   9  * Authors:
  10  *   Dor Laor <dor.laor@qumranet.com>
  11  *   Gregory Haskins <ghaskins@novell.com>
  12  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  13  *
  14  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  */
  19
  20 #include "kvm.h"
  21 #include <linux/kvm.h>
  22 #include <linux/mm.h>
  23 #include <linux/highmem.h>
  24 #include <linux/smp.h>
  25 #include <linux/hrtimer.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <asm/processor.h>
  29 #include <asm/msr.h>
  30 #include <asm/page.h>
  31 #include <asm/current.h>
  32 #include <asm/apicdef.h>
  33 #include <asm/atomic.h>
  34 #include <asm/div64.h>
  35 #include "irq.h"
  36
  37 #define PRId64 "d"
  38 #define PRIx64 "llx"
  39 #define PRIu64 "u"
  40 #define PRIo64 "o"
  41
  42 #define APIC_BUS_CYCLE_NS 1
  43
  44 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  45 #define apic_debug(fmt, arg...)
  46
  47 #define APIC_LVT_NUM                    6
  48 /* 14 is the version for Xeon and Pentium 8.4.8*/
  49 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  50 #define LAPIC_MMIO_LENGTH               (1 << 12)
  51 /* followed define is not in apicdef.h */
  52 #define APIC_SHORT_MASK                 0xc0000
  53 #define APIC_DEST_NOSHORT               0x0
  54 #define APIC_DEST_MASK                  0x800
  55 #define MAX_APIC_VECTOR                 256
  56
  57 #define VEC_POS(v) ((v) & (32 - 1))
  58 #define REG_POS(v) (((v) >> 5) << 4)
  59 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  60 {
  61         return *((u32 *) (apic->regs + reg_off));
  62 }
  63
  64 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  65 {
  66         *((u32 *) (apic->regs + reg_off)) = val;
  67 }
  68
  69 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  70 {
  71         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  72 }
  73
  74 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  75 {
  76         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  77 }
  78
  79 static inline void apic_set_vector(int vec, void *bitmap)
  80 {
  81         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  82 }
  83
  84 static inline void apic_clear_vector(int vec, void *bitmap)
  85 {
  86         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  87 }
  88
  89 static inline int apic_hw_enabled(struct kvm_lapic *apic)
  90 {
  91         return (apic)->vcpu->apic_base & MSR_IA32_APICBASE_ENABLE;
  92 }
  93
  94 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
  95 {
  96         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
  97 }
  98
  99 static inline int apic_enabled(struct kvm_lapic *apic)
 100 {
 101         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 102 }
 103
 104 #define LVT_MASK        \
 105         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 106
 107 #define LINT_MASK       \
 108         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 109          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 110
 111 static inline int kvm_apic_id(struct kvm_lapic *apic)
 112 {
 113         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 114 }
 115
 116 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 117 {
 118         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 119 }
 120
 121 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 122 {
 123         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 124 }
 125
 126 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 127 {
 128         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 129 }
 130
 131 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 132         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 133         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 134         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 135         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 136         LVT_MASK                /* LVTERR */
 137 };
 138
 139 static int find_highest_vector(void *bitmap)
 140 {
 141         u32 *word = bitmap;
 142         int word_offset = MAX_APIC_VECTOR >> 5;
 143
 144         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 145                 continue;
 146
 147         if (likely(!word_offset && !word[0]))
 148                 return -1;
 149         else
 150                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 151 }
 152
 153 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 154 {
 155         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 156 }
 157
 158 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 159 {
 160         apic_clear_vector(vec, apic->regs + APIC_IRR);
 161 }
 162
 163 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 164 {
 165         int result;
 166
 167         result = find_highest_vector(apic->regs + APIC_IRR);
 168         ASSERT(result == -1 || result >= 16);
 169
 170         return result;
 171 }
 172
 173 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 174 {
 175         struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
 176         int highest_irr;
 177
 178         if (!apic)
 179                 return 0;
 180         highest_irr = apic_find_highest_irr(apic);
 181
 182         return highest_irr;
 183 }
 184 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 185
 186 int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig)
 187 {
 188         if (!apic_test_and_set_irr(vec, apic)) {
 189                 /* a new pending irq is set in IRR */
 190                 if (trig)
 191                         apic_set_vector(vec, apic->regs + APIC_TMR);
 192                 else
 193                         apic_clear_vector(vec, apic->regs + APIC_TMR);
 194                 kvm_vcpu_kick(apic->vcpu);
 195                 return 1;
 196         }
 197         return 0;
 198 }
 199
 200 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 201 {
 202         int result;
 203
 204         result = find_highest_vector(apic->regs + APIC_ISR);
 205         ASSERT(result == -1 || result >= 16);
 206
 207         return result;
 208 }
 209
 210 static void apic_update_ppr(struct kvm_lapic *apic)
 211 {
 212         u32 tpr, isrv, ppr;
 213         int isr;
 214
 215         tpr = apic_get_reg(apic, APIC_TASKPRI);
 216         isr = apic_find_highest_isr(apic);
 217         isrv = (isr != -1) ? isr : 0;
 218
 219         if ((tpr & 0xf0) >= (isrv & 0xf0))
 220                 ppr = tpr & 0xff;
 221         else
 222                 ppr = isrv & 0xf0;
 223
 224         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 225                    apic, ppr, isr, isrv);
 226
 227         apic_set_reg(apic, APIC_PROCPRI, ppr);
 228 }
 229
 230 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 231 {
 232         apic_set_reg(apic, APIC_TASKPRI, tpr);
 233         apic_update_ppr(apic);
 234 }
 235
 236 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 237 {
 238         return kvm_apic_id(apic) == dest;
 239 }
 240
 241 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 242 {
 243         int result = 0;
 244         u8 logical_id;
 245
 246         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 247
 248         switch (apic_get_reg(apic, APIC_DFR)) {
 249         case APIC_DFR_FLAT:
 250                 if (logical_id & mda)
 251                         result = 1;
 252                 break;
 253         case APIC_DFR_CLUSTER:
 254                 if (((logical_id >> 4) == (mda >> 0x4))
 255                     && (logical_id & mda & 0xf))
 256                         result = 1;
 257                 break;
 258         default:
 259                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 260                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 261                 break;
 262         }
 263
 264         return result;
 265 }
 266
 267 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 268                            int short_hand, int dest, int dest_mode)
 269 {
 270         int result = 0;
 271         struct kvm_lapic *target = vcpu->apic;
 272
 273         apic_debug("target %p, source %p, dest 0x%x, "
 274                    "dest_mode 0x%x, short_hand 0x%x",
 275                    target, source, dest, dest_mode, short_hand);
 276
 277         ASSERT(!target);
 278         switch (short_hand) {
 279         case APIC_DEST_NOSHORT:
 280                 if (dest_mode == 0) {
 281                         /* Physical mode. */
 282                         if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
 283                                 result = 1;
 284                 } else
 285                         /* Logical mode. */
 286                         result = kvm_apic_match_logical_addr(target, dest);
 287                 break;
 288         case APIC_DEST_SELF:
 289                 if (target == source)
 290                         result = 1;
 291                 break;
 292         case APIC_DEST_ALLINC:
 293                 result = 1;
 294                 break;
 295         case APIC_DEST_ALLBUT:
 296                 if (target != source)
 297                         result = 1;
 298                 break;
 299         default:
 300                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 301                        short_hand);
 302                 break;
 303         }
 304
 305         return result;
 306 }
 307
 308 /*
 309  * Add a pending IRQ into lapic.
 310  * Return 1 if successfully added and 0 if discarded.
 311  */
 312 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 313                              int vector, int level, int trig_mode)
 314 {
 315         int orig_irr, result = 0;
 316         struct kvm_vcpu *vcpu = apic->vcpu;
 317
 318         switch (delivery_mode) {
 319         case APIC_DM_FIXED:
 320         case APIC_DM_LOWEST:
 321                 /* FIXME add logic for vcpu on reset */
 322                 if (unlikely(!apic_enabled(apic)))
 323                         break;
 324
 325                 orig_irr = apic_test_and_set_irr(vector, apic);
 326                 if (orig_irr && trig_mode) {
 327                         apic_debug("level trig mode repeatedly for vector %d",
 328                                    vector);
 329                         break;
 330                 }
 331
 332                 if (trig_mode) {
 333                         apic_debug("level trig mode for vector %d", vector);
 334                         apic_set_vector(vector, apic->regs + APIC_TMR);
 335                 } else
 336                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 337
 338                 if (vcpu->mp_state == VCPU_MP_STATE_RUNNABLE)
 339                         kvm_vcpu_kick(vcpu);
 340                 else if (vcpu->mp_state == VCPU_MP_STATE_HALTED) {
 341                         vcpu->mp_state = VCPU_MP_STATE_RUNNABLE;
 342                         if (waitqueue_active(&vcpu->wq))
 343                                 wake_up_interruptible(&vcpu->wq);
 344                 }
 345
 346                 result = (orig_irr == 0);
 347                 break;
 348
 349         case APIC_DM_REMRD:
 350                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 351                 break;
 352
 353         case APIC_DM_SMI:
 354                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 355                 break;
 356         case APIC_DM_NMI:
 357                 printk(KERN_DEBUG "Ignoring guest NMI\n");
 358                 break;
 359
 360         case APIC_DM_INIT:
 361                 if (level) {
 362                         if (vcpu->mp_state == VCPU_MP_STATE_RUNNABLE)
 363                                 printk(KERN_DEBUG
 364                                        "INIT on a runnable vcpu %d\n",
 365                                        vcpu->vcpu_id);
 366                         vcpu->mp_state = VCPU_MP_STATE_INIT_RECEIVED;
 367                         kvm_vcpu_kick(vcpu);
 368                 } else {
 369                         printk(KERN_DEBUG
 370                                "Ignoring de-assert INIT to vcpu %d\n",
 371                                vcpu->vcpu_id);
 372                 }
 373
 374                 break;
 375
 376         case APIC_DM_STARTUP:
 377                 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n",
 378                        vcpu->vcpu_id, vector);
 379                 if (vcpu->mp_state == VCPU_MP_STATE_INIT_RECEIVED) {
 380                         vcpu->sipi_vector = vector;
 381                         vcpu->mp_state = VCPU_MP_STATE_SIPI_RECEIVED;
 382                         if (waitqueue_active(&vcpu->wq))
 383                                 wake_up_interruptible(&vcpu->wq);
 384                 }
 385                 break;
 386
 387         default:
 388                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 389                        delivery_mode);
 390                 break;
 391         }
 392         return result;
 393 }
 394
 395 struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
 396                                        unsigned long bitmap)
 397 {
 398         int vcpu_id;
 399         int last;
 400         int next;
 401         struct kvm_lapic *apic;
 402
 403         last = kvm->round_robin_prev_vcpu;
 404         next = last;
 405
 406         do {
 407                 if (++next == KVM_MAX_VCPUS)
 408                         next = 0;
 409                 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
 410                         continue;
 411                 apic = kvm->vcpus[next]->apic;
 412                 if (apic && apic_enabled(apic))
 413                         break;
 414                 apic = NULL;
 415         } while (next != last);
 416         kvm->round_robin_prev_vcpu = next;
 417
 418         if (!apic) {
 419                 vcpu_id = ffs(bitmap) - 1;
 420                 if (vcpu_id < 0) {
 421                         vcpu_id = 0;
 422                         printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
 423                 }
 424                 apic = kvm->vcpus[vcpu_id]->apic;
 425         }
 426
 427         return apic;
 428 }
 429
 430 static void apic_set_eoi(struct kvm_lapic *apic)
 431 {
 432         int vector = apic_find_highest_isr(apic);
 433
 434         /*
 435          * Not every write EOI will has corresponding ISR,
 436          * one example is when Kernel check timer on setup_IO_APIC
 437          */
 438         if (vector == -1)
 439                 return;
 440
 441         apic_clear_vector(vector, apic->regs + APIC_ISR);
 442         apic_update_ppr(apic);
 443
 444         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 445                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector);
 446 }
 447
 448 static void apic_send_ipi(struct kvm_lapic *apic)
 449 {
 450         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 451         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 452
 453         unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
 454         unsigned int short_hand = icr_low & APIC_SHORT_MASK;
 455         unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
 456         unsigned int level = icr_low & APIC_INT_ASSERT;
 457         unsigned int dest_mode = icr_low & APIC_DEST_MASK;
 458         unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
 459         unsigned int vector = icr_low & APIC_VECTOR_MASK;
 460
 461         struct kvm_lapic *target;
 462         struct kvm_vcpu *vcpu;
 463         unsigned long lpr_map = 0;
 464         int i;
 465
 466         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 467                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 468                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 469                    icr_high, icr_low, short_hand, dest,
 470                    trig_mode, level, dest_mode, delivery_mode, vector);
 471
 472         for (i = 0; i < KVM_MAX_VCPUS; i++) {
 473                 vcpu = apic->vcpu->kvm->vcpus[i];
 474                 if (!vcpu)
 475                         continue;
 476
 477                 if (vcpu->apic &&
 478                     apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
 479                         if (delivery_mode == APIC_DM_LOWEST)
 480                                 set_bit(vcpu->vcpu_id, &lpr_map);
 481                         else
 482                                 __apic_accept_irq(vcpu->apic, delivery_mode,
 483                                                   vector, level, trig_mode);
 484                 }
 485         }
 486
 487         if (delivery_mode == APIC_DM_LOWEST) {
 488                 target = kvm_apic_round_robin(vcpu->kvm, vector, lpr_map);
 489                 if (target != NULL)
 490                         __apic_accept_irq(target, delivery_mode,
 491                                           vector, level, trig_mode);
 492         }
 493 }
 494
 495 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 496 {
 497         u32 counter_passed;
 498         ktime_t passed, now = apic->timer.dev.base->get_time();
 499         u32 tmcct = apic_get_reg(apic, APIC_TMICT);
 500
 501         ASSERT(apic != NULL);
 502
 503         if (unlikely(ktime_to_ns(now) <=
 504                 ktime_to_ns(apic->timer.last_update))) {
 505                 /* Wrap around */
 506                 passed = ktime_add(( {
 507                                     (ktime_t) {
 508                                     .tv64 = KTIME_MAX -
 509                                     (apic->timer.last_update).tv64}; }
 510                                    ), now);
 511                 apic_debug("time elapsed\n");
 512         } else
 513                 passed = ktime_sub(now, apic->timer.last_update);
 514
 515         counter_passed = div64_64(ktime_to_ns(passed),
 516                                   (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
 517         tmcct -= counter_passed;
 518
 519         if (tmcct <= 0) {
 520                 if (unlikely(!apic_lvtt_period(apic)))
 521                         tmcct = 0;
 522                 else
 523                         do {
 524                                 tmcct += apic_get_reg(apic, APIC_TMICT);
 525                         } while (tmcct <= 0);
 526         }
 527
 528         return tmcct;
 529 }
 530
 531 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 532 {
 533         u32 val = 0;
 534
 535         if (offset >= LAPIC_MMIO_LENGTH)
 536                 return 0;
 537
 538         switch (offset) {
 539         case APIC_ARBPRI:
 540                 printk(KERN_WARNING "Access APIC ARBPRI register "
 541                        "which is for P6\n");
 542                 break;
 543
 544         case APIC_TMCCT:        /* Timer CCR */
 545                 val = apic_get_tmcct(apic);
 546                 break;
 547
 548         default:
 549                 apic_update_ppr(apic);
 550                 val = apic_get_reg(apic, offset);
 551                 break;
 552         }
 553
 554         return val;
 555 }
 556
 557 static void apic_mmio_read(struct kvm_io_device *this,
 558                            gpa_t address, int len, void *data)
 559 {
 560         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 561         unsigned int offset = address - apic->base_address;
 562         unsigned char alignment = offset & 0xf;
 563         u32 result;
 564
 565         if ((alignment + len) > 4) {
 566                 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
 567                        (unsigned long)address, len);
 568                 return;
 569         }
 570         result = __apic_read(apic, offset & ~0xf);
 571
 572         switch (len) {
 573         case 1:
 574         case 2:
 575         case 4:
 576                 memcpy(data, (char *)&result + alignment, len);
 577                 break;
 578         default:
 579                 printk(KERN_ERR "Local APIC read with len = %x, "
 580                        "should be 1,2, or 4 instead\n", len);
 581                 break;
 582         }
 583 }
 584
 585 static void update_divide_count(struct kvm_lapic *apic)
 586 {
 587         u32 tmp1, tmp2, tdcr;
 588
 589         tdcr = apic_get_reg(apic, APIC_TDCR);
 590         tmp1 = tdcr & 0xf;
 591         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 592         apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
 593
 594         apic_debug("timer divide count is 0x%x\n",
 595                                    apic->timer.divide_count);
 596 }
 597
 598 static void start_apic_timer(struct kvm_lapic *apic)
 599 {
 600         ktime_t now = apic->timer.dev.base->get_time();
 601
 602         apic->timer.last_update = now;
 603
 604         apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
 605                     APIC_BUS_CYCLE_NS * apic->timer.divide_count;
 606         atomic_set(&apic->timer.pending, 0);
 607         hrtimer_start(&apic->timer.dev,
 608                       ktime_add_ns(now, apic->timer.period),
 609                       HRTIMER_MODE_ABS);
 610
 611         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 612                            PRIx64 ", "
 613                            "timer initial count 0x%x, period %lldns, "
 614                            "expire @ 0x%016" PRIx64 ".\n", __FUNCTION__,
 615                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 616                            apic_get_reg(apic, APIC_TMICT),
 617                            apic->timer.period,
 618                            ktime_to_ns(ktime_add_ns(now,
 619                                         apic->timer.period)));
 620 }
 621
 622 static void apic_mmio_write(struct kvm_io_device *this,
 623                             gpa_t address, int len, const void *data)
 624 {
 625         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 626         unsigned int offset = address - apic->base_address;
 627         unsigned char alignment = offset & 0xf;
 628         u32 val;
 629
 630         /*
 631          * APIC register must be aligned on 128-bits boundary.
 632          * 32/64/128 bits registers must be accessed thru 32 bits.
 633          * Refer SDM 8.4.1
 634          */
 635         if (len != 4 || alignment) {
 636                 if (printk_ratelimit())
 637                         printk(KERN_ERR "apic write: bad size=%d %lx\n",
 638                                len, (long)address);
 639                 return;
 640         }
 641
 642         val = *(u32 *) data;
 643
 644         /* too common printing */
 645         if (offset != APIC_EOI)
 646                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 647                            "0x%x\n", __FUNCTION__, offset, len, val);
 648
 649         offset &= 0xff0;
 650
 651         switch (offset) {
 652         case APIC_ID:           /* Local APIC ID */
 653                 apic_set_reg(apic, APIC_ID, val);
 654                 break;
 655
 656         case APIC_TASKPRI:
 657                 apic_set_tpr(apic, val & 0xff);
 658                 break;
 659
 660         case APIC_EOI:
 661                 apic_set_eoi(apic);
 662                 break;
 663
 664         case APIC_LDR:
 665                 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 666                 break;
 667
 668         case APIC_DFR:
 669                 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 670                 break;
 671
 672         case APIC_SPIV:
 673                 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
 674                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 675                         int i;
 676                         u32 lvt_val;
 677
 678                         for (i = 0; i < APIC_LVT_NUM; i++) {
 679                                 lvt_val = apic_get_reg(apic,
 680                                                        APIC_LVTT + 0x10 * i);
 681                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 682                                              lvt_val | APIC_LVT_MASKED);
 683                         }
 684                         atomic_set(&apic->timer.pending, 0);
 685
 686                 }
 687                 break;
 688
 689         case APIC_ICR:
 690                 /* No delay here, so we always clear the pending bit */
 691                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 692                 apic_send_ipi(apic);
 693                 break;
 694
 695         case APIC_ICR2:
 696                 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
 697                 break;
 698
 699         case APIC_LVTT:
 700         case APIC_LVTTHMR:
 701         case APIC_LVTPC:
 702         case APIC_LVT0:
 703         case APIC_LVT1:
 704         case APIC_LVTERR:
 705                 /* TODO: Check vector */
 706                 if (!apic_sw_enabled(apic))
 707                         val |= APIC_LVT_MASKED;
 708
 709                 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
 710                 apic_set_reg(apic, offset, val);
 711
 712                 break;
 713
 714         case APIC_TMICT:
 715                 hrtimer_cancel(&apic->timer.dev);
 716                 apic_set_reg(apic, APIC_TMICT, val);
 717                 start_apic_timer(apic);
 718                 return;
 719
 720         case APIC_TDCR:
 721                 if (val & 4)
 722                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 723                 apic_set_reg(apic, APIC_TDCR, val);
 724                 update_divide_count(apic);
 725                 break;
 726
 727         default:
 728                 apic_debug("Local APIC Write to read-only register %x\n",
 729                            offset);
 730                 break;
 731         }
 732
 733 }
 734
 735 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr)
 736 {
 737         struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
 738         int ret = 0;
 739
 740
 741         if (apic_hw_enabled(apic) &&
 742             (addr >= apic->base_address) &&
 743             (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
 744                 ret = 1;
 745
 746         return ret;
 747 }
 748
 749 void kvm_free_apic(struct kvm_lapic *apic)
 750 {
 751         if (!apic)
 752                 return;
 753
 754         hrtimer_cancel(&apic->timer.dev);
 755
 756         if (apic->regs_page) {
 757                 __free_page(apic->regs_page);
 758                 apic->regs_page = 0;
 759         }
 760
 761         kfree(apic);
 762 }
 763
 764 /*
 765  *----------------------------------------------------------------------
 766  * LAPIC interface
 767  *----------------------------------------------------------------------
 768  */
 769
 770 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 771 {
 772         struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
 773
 774         if (!apic)
 775                 return;
 776         apic_set_tpr(apic, ((cr8 & 0x0f) << 4));
 777 }
 778
 779 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 780 {
 781         struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
 782         u64 tpr;
 783
 784         if (!apic)
 785                 return 0;
 786         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 787
 788         return (tpr & 0xf0) >> 4;
 789 }
 790 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 791
 792 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 793 {
 794         struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
 795
 796         if (!apic) {
 797                 value |= MSR_IA32_APICBASE_BSP;
 798                 vcpu->apic_base = value;
 799                 return;
 800         }
 801         if (apic->vcpu->vcpu_id)
 802                 value &= ~MSR_IA32_APICBASE_BSP;
 803
 804         vcpu->apic_base = value;
 805         apic->base_address = apic->vcpu->apic_base &
 806                              MSR_IA32_APICBASE_BASE;
 807
 808         /* with FSB delivery interrupt, we can restart APIC functionality */
 809         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 810                    "0x%lx.\n", apic->apic_base, apic->base_address);
 811
 812 }
 813
 814 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
 815 {
 816         return vcpu->apic_base;
 817 }
 818 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
 819
 820 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 821 {
 822         struct kvm_lapic *apic;
 823         int i;
 824
 825         apic_debug("%s\n", __FUNCTION__);
 826
 827         ASSERT(vcpu);
 828         apic = vcpu->apic;
 829         ASSERT(apic != NULL);
 830
 831         /* Stop the timer in case it's a reset to an active apic */
 832         hrtimer_cancel(&apic->timer.dev);
 833
 834         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 835         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
 836
 837         for (i = 0; i < APIC_LVT_NUM; i++)
 838                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 839         apic_set_reg(apic, APIC_LVT0,
 840                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 841
 842         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 843         apic_set_reg(apic, APIC_SPIV, 0xff);
 844         apic_set_reg(apic, APIC_TASKPRI, 0);
 845         apic_set_reg(apic, APIC_LDR, 0);
 846         apic_set_reg(apic, APIC_ESR, 0);
 847         apic_set_reg(apic, APIC_ICR, 0);
 848         apic_set_reg(apic, APIC_ICR2, 0);
 849         apic_set_reg(apic, APIC_TDCR, 0);
 850         apic_set_reg(apic, APIC_TMICT, 0);
 851         for (i = 0; i < 8; i++) {
 852                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 853                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 854                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 855         }
 856         update_divide_count(apic);
 857         atomic_set(&apic->timer.pending, 0);
 858         if (vcpu->vcpu_id == 0)
 859                 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
 860         apic_update_ppr(apic);
 861
 862         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 863                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __FUNCTION__,
 864                    vcpu, kvm_apic_id(apic),
 865                    vcpu->apic_base, apic->base_address);
 866 }
 867 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 868
 869 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 870 {
 871         struct kvm_lapic *apic = (struct kvm_lapic *)vcpu->apic;
 872         int ret = 0;
 873
 874         if (!apic)
 875                 return 0;
 876         ret = apic_enabled(apic);
 877
 878         return ret;
 879 }
 880 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 881
 882 /*
 883  *----------------------------------------------------------------------
 884  * timer interface
 885  *----------------------------------------------------------------------
 886  */
 887
 888 /* TODO: make sure __apic_timer_fn runs in current pCPU */
 889 static int __apic_timer_fn(struct kvm_lapic *apic)
 890 {
 891         int result = 0;
 892         wait_queue_head_t *q = &apic->vcpu->wq;
 893
 894         atomic_inc(&apic->timer.pending);
 895         if (waitqueue_active(q))
 896         {
 897                 apic->vcpu->mp_state = VCPU_MP_STATE_RUNNABLE;
 898                 wake_up_interruptible(q);
 899         }
 900         if (apic_lvtt_period(apic)) {
 901                 result = 1;
 902                 apic->timer.dev.expires = ktime_add_ns(
 903                                         apic->timer.dev.expires,
 904                                         apic->timer.period);
 905         }
 906         return result;
 907 }
 908
 909 static int __inject_apic_timer_irq(struct kvm_lapic *apic)
 910 {
 911         int vector;
 912
 913         vector = apic_lvt_vector(apic, APIC_LVTT);
 914         return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
 915 }
 916
 917 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
 918 {
 919         struct kvm_lapic *apic;
 920         int restart_timer = 0;
 921
 922         apic = container_of(data, struct kvm_lapic, timer.dev);
 923
 924         restart_timer = __apic_timer_fn(apic);
 925
 926         if (restart_timer)
 927                 return HRTIMER_RESTART;
 928         else
 929                 return HRTIMER_NORESTART;
 930 }
 931
 932 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 933 {
 934         struct kvm_lapic *apic;
 935
 936         ASSERT(vcpu != NULL);
 937         apic_debug("apic_init %d\n", vcpu->vcpu_id);
 938
 939         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
 940         if (!apic)
 941                 goto nomem;
 942
 943         vcpu->apic = apic;
 944
 945         apic->regs_page = alloc_page(GFP_KERNEL);
 946         if (apic->regs_page == NULL) {
 947                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
 948                        vcpu->vcpu_id);
 949                 goto nomem;
 950         }
 951         apic->regs = page_address(apic->regs_page);
 952         memset(apic->regs, 0, PAGE_SIZE);
 953         apic->vcpu = vcpu;
 954
 955         hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
 956         apic->timer.dev.function = apic_timer_fn;
 957         apic->base_address = APIC_DEFAULT_PHYS_BASE;
 958         vcpu->apic_base = APIC_DEFAULT_PHYS_BASE;
 959
 960         kvm_lapic_reset(vcpu);
 961         apic->dev.read = apic_mmio_read;
 962         apic->dev.write = apic_mmio_write;
 963         apic->dev.in_range = apic_mmio_range;
 964         apic->dev.private = apic;
 965
 966         return 0;
 967 nomem:
 968         kvm_free_apic(apic);
 969         return -ENOMEM;
 970 }
 971 EXPORT_SYMBOL_GPL(kvm_create_lapic);
 972
 973 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
 974 {
 975         struct kvm_lapic *apic = vcpu->apic;
 976         int highest_irr;
 977
 978         if (!apic || !apic_enabled(apic))
 979                 return -1;
 980
 981         apic_update_ppr(apic);
 982         highest_irr = apic_find_highest_irr(apic);
 983         if ((highest_irr == -1) ||
 984             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
 985                 return -1;
 986         return highest_irr;
 987 }
 988
 989 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
 990 {
 991         u32 lvt0 = apic_get_reg(vcpu->apic, APIC_LVT0);
 992         int r = 0;
 993
 994         if (vcpu->vcpu_id == 0) {
 995                 if (!apic_hw_enabled(vcpu->apic))
 996                         r = 1;
 997                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
 998                     GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
 999                         r = 1;
1000         }
1001         return r;
1002 }
1003
1004 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1005 {
1006         struct kvm_lapic *apic = vcpu->apic;
1007
1008         if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1009                 atomic_read(&apic->timer.pending) > 0) {
1010                 if (__inject_apic_timer_irq(apic))
1011                         atomic_dec(&apic->timer.pending);
1012         }
1013 }
1014
1015 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1016 {
1017         struct kvm_lapic *apic = vcpu->apic;
1018
1019         if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1020                 apic->timer.last_update = ktime_add_ns(
1021                                 apic->timer.last_update,
1022                                 apic->timer.period);
1023 }
1024
1025 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1026 {
1027         int vector = kvm_apic_has_interrupt(vcpu);
1028         struct kvm_lapic *apic = vcpu->apic;
1029
1030         if (vector == -1)
1031                 return -1;
1032
1033         apic_set_vector(vector, apic->regs + APIC_ISR);
1034         apic_update_ppr(apic);
1035         apic_clear_irr(vector, apic);
1036         return vector;
1037 }
1038
1039 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1040 {
1041         struct kvm_lapic *apic = vcpu->apic;
1042
1043         apic->base_address = vcpu->apic_base &
1044                              MSR_IA32_APICBASE_BASE;
1045         apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1046         apic_update_ppr(apic);
1047         hrtimer_cancel(&apic->timer.dev);
1048         update_divide_count(apic);
1049         start_apic_timer(apic);
1050 }
1051
1052 void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1053 {
1054         struct kvm_lapic *apic = vcpu->apic;
1055         struct hrtimer *timer;
1056
1057         if (!apic)
1058                 return;
1059
1060         timer = &apic->timer.dev;
1061         if (hrtimer_cancel(timer))
1062                 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
1063 }
1064 EXPORT_SYMBOL_GPL(kvm_migrate_apic_timer);