drivers/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "kvm.h"
  19 #include "x86.h"
  20 #include "x86_emulate.h"
  21 #include "irq.h"
  22 #include "vmx.h"
  23 #include "segment_descriptor.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 struct vmcs {
  42         u32 revision_id;
  43         u32 abort;
  44         char data[0];
  45 };
  46
  47 struct vcpu_vmx {
  48         struct kvm_vcpu       vcpu;
  49         int                   launched;
  50         u8                    fail;
  51         u32                   idt_vectoring_info;
  52         struct kvm_msr_entry *guest_msrs;
  53         struct kvm_msr_entry *host_msrs;
  54         int                   nmsrs;
  55         int                   save_nmsrs;
  56         int                   msr_offset_efer;
  57 #ifdef CONFIG_X86_64
  58         int                   msr_offset_kernel_gs_base;
  59 #endif
  60         struct vmcs          *vmcs;
  61         struct {
  62                 int           loaded;
  63                 u16           fs_sel, gs_sel, ldt_sel;
  64                 int           gs_ldt_reload_needed;
  65                 int           fs_reload_needed;
  66                 int           guest_efer_loaded;
  67         } host_state;
  68         struct {
  69                 struct {
  70                         bool pending;
  71                         u8 vector;
  72                         unsigned rip;
  73                 } irq;
  74         } rmode;
  75 };
  76
  77 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  78 {
  79         return container_of(vcpu, struct vcpu_vmx, vcpu);
  80 }
  81
  82 static int init_rmode_tss(struct kvm *kvm);
  83
  84 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  85 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  86
  87 static struct page *vmx_io_bitmap_a;
  88 static struct page *vmx_io_bitmap_b;
  89
  90 static struct vmcs_config {
  91         int size;
  92         int order;
  93         u32 revision_id;
  94         u32 pin_based_exec_ctrl;
  95         u32 cpu_based_exec_ctrl;
  96         u32 cpu_based_2nd_exec_ctrl;
  97         u32 vmexit_ctrl;
  98         u32 vmentry_ctrl;
  99 } vmcs_config;
 100
 101 #define VMX_SEGMENT_FIELD(seg)                                  \
 102         [VCPU_SREG_##seg] = {                                   \
 103                 .selector = GUEST_##seg##_SELECTOR,             \
 104                 .base = GUEST_##seg##_BASE,                     \
 105                 .limit = GUEST_##seg##_LIMIT,                   \
 106                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 107         }
 108
 109 static struct kvm_vmx_segment_field {
 110         unsigned selector;
 111         unsigned base;
 112         unsigned limit;
 113         unsigned ar_bytes;
 114 } kvm_vmx_segment_fields[] = {
 115         VMX_SEGMENT_FIELD(CS),
 116         VMX_SEGMENT_FIELD(DS),
 117         VMX_SEGMENT_FIELD(ES),
 118         VMX_SEGMENT_FIELD(FS),
 119         VMX_SEGMENT_FIELD(GS),
 120         VMX_SEGMENT_FIELD(SS),
 121         VMX_SEGMENT_FIELD(TR),
 122         VMX_SEGMENT_FIELD(LDTR),
 123 };
 124
 125 /*
 126  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 127  * away by decrementing the array size.
 128  */
 129 static const u32 vmx_msr_index[] = {
 130 #ifdef CONFIG_X86_64
 131         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 132 #endif
 133         MSR_EFER, MSR_K6_STAR,
 134 };
 135 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 136
 137 static void load_msrs(struct kvm_msr_entry *e, int n)
 138 {
 139         int i;
 140
 141         for (i = 0; i < n; ++i)
 142                 wrmsrl(e[i].index, e[i].data);
 143 }
 144
 145 static void save_msrs(struct kvm_msr_entry *e, int n)
 146 {
 147         int i;
 148
 149         for (i = 0; i < n; ++i)
 150                 rdmsrl(e[i].index, e[i].data);
 151 }
 152
 153 static inline int is_page_fault(u32 intr_info)
 154 {
 155         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 156                              INTR_INFO_VALID_MASK)) ==
 157                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 158 }
 159
 160 static inline int is_no_device(u32 intr_info)
 161 {
 162         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 163                              INTR_INFO_VALID_MASK)) ==
 164                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 165 }
 166
 167 static inline int is_invalid_opcode(u32 intr_info)
 168 {
 169         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 170                              INTR_INFO_VALID_MASK)) ==
 171                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 172 }
 173
 174 static inline int is_external_interrupt(u32 intr_info)
 175 {
 176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 177                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 178 }
 179
 180 static inline int cpu_has_vmx_tpr_shadow(void)
 181 {
 182         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 183 }
 184
 185 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 186 {
 187         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 188 }
 189
 190 static inline int cpu_has_secondary_exec_ctrls(void)
 191 {
 192         return (vmcs_config.cpu_based_exec_ctrl &
 193                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 194 }
 195
 196 static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
 197 {
 198         return ((cpu_has_secondary_exec_ctrls()) && (irqchip_in_kernel(kvm)));
 199 }
 200
 201 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
 202 {
 203         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 204                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 205 }
 206
 207 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 208 {
 209         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 210                 (irqchip_in_kernel(kvm)));
 211 }
 212
 213 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 214 {
 215         int i;
 216
 217         for (i = 0; i < vmx->nmsrs; ++i)
 218                 if (vmx->guest_msrs[i].index == msr)
 219                         return i;
 220         return -1;
 221 }
 222
 223 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 224 {
 225         int i;
 226
 227         i = __find_msr_index(vmx, msr);
 228         if (i >= 0)
 229                 return &vmx->guest_msrs[i];
 230         return NULL;
 231 }
 232
 233 static void vmcs_clear(struct vmcs *vmcs)
 234 {
 235         u64 phys_addr = __pa(vmcs);
 236         u8 error;
 237
 238         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
 239                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 240                       : "cc", "memory");
 241         if (error)
 242                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 243                        vmcs, phys_addr);
 244 }
 245
 246 static void __vcpu_clear(void *arg)
 247 {
 248         struct vcpu_vmx *vmx = arg;
 249         int cpu = raw_smp_processor_id();
 250
 251         if (vmx->vcpu.cpu == cpu)
 252                 vmcs_clear(vmx->vmcs);
 253         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 254                 per_cpu(current_vmcs, cpu) = NULL;
 255         rdtscll(vmx->vcpu.host_tsc);
 256 }
 257
 258 static void vcpu_clear(struct vcpu_vmx *vmx)
 259 {
 260         if (vmx->vcpu.cpu == -1)
 261                 return;
 262         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
 263         vmx->launched = 0;
 264 }
 265
 266 static unsigned long vmcs_readl(unsigned long field)
 267 {
 268         unsigned long value;
 269
 270         asm volatile (ASM_VMX_VMREAD_RDX_RAX
 271                       : "=a"(value) : "d"(field) : "cc");
 272         return value;
 273 }
 274
 275 static u16 vmcs_read16(unsigned long field)
 276 {
 277         return vmcs_readl(field);
 278 }
 279
 280 static u32 vmcs_read32(unsigned long field)
 281 {
 282         return vmcs_readl(field);
 283 }
 284
 285 static u64 vmcs_read64(unsigned long field)
 286 {
 287 #ifdef CONFIG_X86_64
 288         return vmcs_readl(field);
 289 #else
 290         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 291 #endif
 292 }
 293
 294 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 295 {
 296         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 297                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 298         dump_stack();
 299 }
 300
 301 static void vmcs_writel(unsigned long field, unsigned long value)
 302 {
 303         u8 error;
 304
 305         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
 306                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 307         if (unlikely(error))
 308                 vmwrite_error(field, value);
 309 }
 310
 311 static void vmcs_write16(unsigned long field, u16 value)
 312 {
 313         vmcs_writel(field, value);
 314 }
 315
 316 static void vmcs_write32(unsigned long field, u32 value)
 317 {
 318         vmcs_writel(field, value);
 319 }
 320
 321 static void vmcs_write64(unsigned long field, u64 value)
 322 {
 323 #ifdef CONFIG_X86_64
 324         vmcs_writel(field, value);
 325 #else
 326         vmcs_writel(field, value);
 327         asm volatile ("");
 328         vmcs_writel(field+1, value >> 32);
 329 #endif
 330 }
 331
 332 static void vmcs_clear_bits(unsigned long field, u32 mask)
 333 {
 334         vmcs_writel(field, vmcs_readl(field) & ~mask);
 335 }
 336
 337 static void vmcs_set_bits(unsigned long field, u32 mask)
 338 {
 339         vmcs_writel(field, vmcs_readl(field) | mask);
 340 }
 341
 342 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 343 {
 344         u32 eb;
 345
 346         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 347         if (!vcpu->fpu_active)
 348                 eb |= 1u << NM_VECTOR;
 349         if (vcpu->guest_debug.enabled)
 350                 eb |= 1u << 1;
 351         if (vcpu->rmode.active)
 352                 eb = ~0;
 353         vmcs_write32(EXCEPTION_BITMAP, eb);
 354 }
 355
 356 static void reload_tss(void)
 357 {
 358 #ifndef CONFIG_X86_64
 359
 360         /*
 361          * VT restores TR but not its size.  Useless.
 362          */
 363         struct descriptor_table gdt;
 364         struct segment_descriptor *descs;
 365
 366         get_gdt(&gdt);
 367         descs = (void *)gdt.base;
 368         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 369         load_TR_desc();
 370 #endif
 371 }
 372
 373 static void load_transition_efer(struct vcpu_vmx *vmx)
 374 {
 375         int efer_offset = vmx->msr_offset_efer;
 376         u64 host_efer = vmx->host_msrs[efer_offset].data;
 377         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 378         u64 ignore_bits;
 379
 380         if (efer_offset < 0)
 381                 return;
 382         /*
 383          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 384          * outside long mode
 385          */
 386         ignore_bits = EFER_NX | EFER_SCE;
 387 #ifdef CONFIG_X86_64
 388         ignore_bits |= EFER_LMA | EFER_LME;
 389         /* SCE is meaningful only in long mode on Intel */
 390         if (guest_efer & EFER_LMA)
 391                 ignore_bits &= ~(u64)EFER_SCE;
 392 #endif
 393         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 394                 return;
 395
 396         vmx->host_state.guest_efer_loaded = 1;
 397         guest_efer &= ~ignore_bits;
 398         guest_efer |= host_efer & ignore_bits;
 399         wrmsrl(MSR_EFER, guest_efer);
 400         vmx->vcpu.stat.efer_reload++;
 401 }
 402
 403 static void reload_host_efer(struct vcpu_vmx *vmx)
 404 {
 405         if (vmx->host_state.guest_efer_loaded) {
 406                 vmx->host_state.guest_efer_loaded = 0;
 407                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 408         }
 409 }
 410
 411 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 412 {
 413         struct vcpu_vmx *vmx = to_vmx(vcpu);
 414
 415         if (vmx->host_state.loaded)
 416                 return;
 417
 418         vmx->host_state.loaded = 1;
 419         /*
 420          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 421          * allow segment selectors with cpl > 0 or ti == 1.
 422          */
 423         vmx->host_state.ldt_sel = read_ldt();
 424         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 425         vmx->host_state.fs_sel = read_fs();
 426         if (!(vmx->host_state.fs_sel & 7)) {
 427                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 428                 vmx->host_state.fs_reload_needed = 0;
 429         } else {
 430                 vmcs_write16(HOST_FS_SELECTOR, 0);
 431                 vmx->host_state.fs_reload_needed = 1;
 432         }
 433         vmx->host_state.gs_sel = read_gs();
 434         if (!(vmx->host_state.gs_sel & 7))
 435                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 436         else {
 437                 vmcs_write16(HOST_GS_SELECTOR, 0);
 438                 vmx->host_state.gs_ldt_reload_needed = 1;
 439         }
 440
 441 #ifdef CONFIG_X86_64
 442         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 443         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 444 #else
 445         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 446         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 447 #endif
 448
 449 #ifdef CONFIG_X86_64
 450         if (is_long_mode(&vmx->vcpu))
 451                 save_msrs(vmx->host_msrs +
 452                           vmx->msr_offset_kernel_gs_base, 1);
 453
 454 #endif
 455         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 456         load_transition_efer(vmx);
 457 }
 458
 459 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 460 {
 461         unsigned long flags;
 462
 463         if (!vmx->host_state.loaded)
 464                 return;
 465
 466         vmx->host_state.loaded = 0;
 467         if (vmx->host_state.fs_reload_needed)
 468                 load_fs(vmx->host_state.fs_sel);
 469         if (vmx->host_state.gs_ldt_reload_needed) {
 470                 load_ldt(vmx->host_state.ldt_sel);
 471                 /*
 472                  * If we have to reload gs, we must take care to
 473                  * preserve our gs base.
 474                  */
 475                 local_irq_save(flags);
 476                 load_gs(vmx->host_state.gs_sel);
 477 #ifdef CONFIG_X86_64
 478                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 479 #endif
 480                 local_irq_restore(flags);
 481         }
 482         reload_tss();
 483         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 484         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 485         reload_host_efer(vmx);
 486 }
 487
 488 /*
 489  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 490  * vcpu mutex is already taken.
 491  */
 492 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 493 {
 494         struct vcpu_vmx *vmx = to_vmx(vcpu);
 495         u64 phys_addr = __pa(vmx->vmcs);
 496         u64 tsc_this, delta;
 497
 498         if (vcpu->cpu != cpu) {
 499                 vcpu_clear(vmx);
 500                 kvm_migrate_apic_timer(vcpu);
 501         }
 502
 503         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 504                 u8 error;
 505
 506                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 507                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
 508                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 509                               : "cc");
 510                 if (error)
 511                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 512                                vmx->vmcs, phys_addr);
 513         }
 514
 515         if (vcpu->cpu != cpu) {
 516                 struct descriptor_table dt;
 517                 unsigned long sysenter_esp;
 518
 519                 vcpu->cpu = cpu;
 520                 /*
 521                  * Linux uses per-cpu TSS and GDT, so set these when switching
 522                  * processors.
 523                  */
 524                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 525                 get_gdt(&dt);
 526                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 527
 528                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 529                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 530
 531                 /*
 532                  * Make sure the time stamp counter is monotonous.
 533                  */
 534                 rdtscll(tsc_this);
 535                 delta = vcpu->host_tsc - tsc_this;
 536                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
 537         }
 538 }
 539
 540 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 541 {
 542         vmx_load_host_state(to_vmx(vcpu));
 543         kvm_put_guest_fpu(vcpu);
 544 }
 545
 546 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 547 {
 548         if (vcpu->fpu_active)
 549                 return;
 550         vcpu->fpu_active = 1;
 551         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 552         if (vcpu->cr0 & X86_CR0_TS)
 553                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 554         update_exception_bitmap(vcpu);
 555 }
 556
 557 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 558 {
 559         if (!vcpu->fpu_active)
 560                 return;
 561         vcpu->fpu_active = 0;
 562         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 563         update_exception_bitmap(vcpu);
 564 }
 565
 566 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 567 {
 568         vcpu_clear(to_vmx(vcpu));
 569 }
 570
 571 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 572 {
 573         return vmcs_readl(GUEST_RFLAGS);
 574 }
 575
 576 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 577 {
 578         if (vcpu->rmode.active)
 579                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 580         vmcs_writel(GUEST_RFLAGS, rflags);
 581 }
 582
 583 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 584 {
 585         unsigned long rip;
 586         u32 interruptibility;
 587
 588         rip = vmcs_readl(GUEST_RIP);
 589         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 590         vmcs_writel(GUEST_RIP, rip);
 591
 592         /*
 593          * We emulated an instruction, so temporary interrupt blocking
 594          * should be removed, if set.
 595          */
 596         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 597         if (interruptibility & 3)
 598                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 599                              interruptibility & ~3);
 600         vcpu->interrupt_window_open = 1;
 601 }
 602
 603 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
 604 {
 605         printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
 606                vmcs_readl(GUEST_RIP));
 607         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 608         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 609                      GP_VECTOR |
 610                      INTR_TYPE_EXCEPTION |
 611                      INTR_INFO_DELIEVER_CODE_MASK |
 612                      INTR_INFO_VALID_MASK);
 613 }
 614
 615 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
 616 {
 617         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 618                      UD_VECTOR |
 619                      INTR_TYPE_EXCEPTION |
 620                      INTR_INFO_VALID_MASK);
 621 }
 622
 623 /*
 624  * Swap MSR entry in host/guest MSR entry array.
 625  */
 626 #ifdef CONFIG_X86_64
 627 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 628 {
 629         struct kvm_msr_entry tmp;
 630
 631         tmp = vmx->guest_msrs[to];
 632         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 633         vmx->guest_msrs[from] = tmp;
 634         tmp = vmx->host_msrs[to];
 635         vmx->host_msrs[to] = vmx->host_msrs[from];
 636         vmx->host_msrs[from] = tmp;
 637 }
 638 #endif
 639
 640 /*
 641  * Set up the vmcs to automatically save and restore system
 642  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 643  * mode, as fiddling with msrs is very expensive.
 644  */
 645 static void setup_msrs(struct vcpu_vmx *vmx)
 646 {
 647         int save_nmsrs;
 648
 649         save_nmsrs = 0;
 650 #ifdef CONFIG_X86_64
 651         if (is_long_mode(&vmx->vcpu)) {
 652                 int index;
 653
 654                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 655                 if (index >= 0)
 656                         move_msr_up(vmx, index, save_nmsrs++);
 657                 index = __find_msr_index(vmx, MSR_LSTAR);
 658                 if (index >= 0)
 659                         move_msr_up(vmx, index, save_nmsrs++);
 660                 index = __find_msr_index(vmx, MSR_CSTAR);
 661                 if (index >= 0)
 662                         move_msr_up(vmx, index, save_nmsrs++);
 663                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 664                 if (index >= 0)
 665                         move_msr_up(vmx, index, save_nmsrs++);
 666                 /*
 667                  * MSR_K6_STAR is only needed on long mode guests, and only
 668                  * if efer.sce is enabled.
 669                  */
 670                 index = __find_msr_index(vmx, MSR_K6_STAR);
 671                 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
 672                         move_msr_up(vmx, index, save_nmsrs++);
 673         }
 674 #endif
 675         vmx->save_nmsrs = save_nmsrs;
 676
 677 #ifdef CONFIG_X86_64
 678         vmx->msr_offset_kernel_gs_base =
 679                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 680 #endif
 681         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 682 }
 683
 684 /*
 685  * reads and returns guest's timestamp counter "register"
 686  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 687  */
 688 static u64 guest_read_tsc(void)
 689 {
 690         u64 host_tsc, tsc_offset;
 691
 692         rdtscll(host_tsc);
 693         tsc_offset = vmcs_read64(TSC_OFFSET);
 694         return host_tsc + tsc_offset;
 695 }
 696
 697 /*
 698  * writes 'guest_tsc' into guest's timestamp counter "register"
 699  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 700  */
 701 static void guest_write_tsc(u64 guest_tsc)
 702 {
 703         u64 host_tsc;
 704
 705         rdtscll(host_tsc);
 706         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 707 }
 708
 709 /*
 710  * Reads an msr value (of 'msr_index') into 'pdata'.
 711  * Returns 0 on success, non-0 otherwise.
 712  * Assumes vcpu_load() was already called.
 713  */
 714 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 715 {
 716         u64 data;
 717         struct kvm_msr_entry *msr;
 718
 719         if (!pdata) {
 720                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 721                 return -EINVAL;
 722         }
 723
 724         switch (msr_index) {
 725 #ifdef CONFIG_X86_64
 726         case MSR_FS_BASE:
 727                 data = vmcs_readl(GUEST_FS_BASE);
 728                 break;
 729         case MSR_GS_BASE:
 730                 data = vmcs_readl(GUEST_GS_BASE);
 731                 break;
 732         case MSR_EFER:
 733                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 734 #endif
 735         case MSR_IA32_TIME_STAMP_COUNTER:
 736                 data = guest_read_tsc();
 737                 break;
 738         case MSR_IA32_SYSENTER_CS:
 739                 data = vmcs_read32(GUEST_SYSENTER_CS);
 740                 break;
 741         case MSR_IA32_SYSENTER_EIP:
 742                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 743                 break;
 744         case MSR_IA32_SYSENTER_ESP:
 745                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 746                 break;
 747         default:
 748                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 749                 if (msr) {
 750                         data = msr->data;
 751                         break;
 752                 }
 753                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 754         }
 755
 756         *pdata = data;
 757         return 0;
 758 }
 759
 760 /*
 761  * Writes msr value into into the appropriate "register".
 762  * Returns 0 on success, non-0 otherwise.
 763  * Assumes vcpu_load() was already called.
 764  */
 765 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 766 {
 767         struct vcpu_vmx *vmx = to_vmx(vcpu);
 768         struct kvm_msr_entry *msr;
 769         int ret = 0;
 770
 771         switch (msr_index) {
 772 #ifdef CONFIG_X86_64
 773         case MSR_EFER:
 774                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 775                 if (vmx->host_state.loaded) {
 776                         reload_host_efer(vmx);
 777                         load_transition_efer(vmx);
 778                 }
 779                 break;
 780         case MSR_FS_BASE:
 781                 vmcs_writel(GUEST_FS_BASE, data);
 782                 break;
 783         case MSR_GS_BASE:
 784                 vmcs_writel(GUEST_GS_BASE, data);
 785                 break;
 786 #endif
 787         case MSR_IA32_SYSENTER_CS:
 788                 vmcs_write32(GUEST_SYSENTER_CS, data);
 789                 break;
 790         case MSR_IA32_SYSENTER_EIP:
 791                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 792                 break;
 793         case MSR_IA32_SYSENTER_ESP:
 794                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 795                 break;
 796         case MSR_IA32_TIME_STAMP_COUNTER:
 797                 guest_write_tsc(data);
 798                 break;
 799         default:
 800                 msr = find_msr_entry(vmx, msr_index);
 801                 if (msr) {
 802                         msr->data = data;
 803                         if (vmx->host_state.loaded)
 804                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 805                         break;
 806                 }
 807                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 808         }
 809
 810         return ret;
 811 }
 812
 813 /*
 814  * Sync the rsp and rip registers into the vcpu structure.  This allows
 815  * registers to be accessed by indexing vcpu->regs.
 816  */
 817 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 818 {
 819         vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 820         vcpu->rip = vmcs_readl(GUEST_RIP);
 821 }
 822
 823 /*
 824  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 825  * modification.
 826  */
 827 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 828 {
 829         vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
 830         vmcs_writel(GUEST_RIP, vcpu->rip);
 831 }
 832
 833 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 834 {
 835         unsigned long dr7 = 0x400;
 836         int old_singlestep;
 837
 838         old_singlestep = vcpu->guest_debug.singlestep;
 839
 840         vcpu->guest_debug.enabled = dbg->enabled;
 841         if (vcpu->guest_debug.enabled) {
 842                 int i;
 843
 844                 dr7 |= 0x200;  /* exact */
 845                 for (i = 0; i < 4; ++i) {
 846                         if (!dbg->breakpoints[i].enabled)
 847                                 continue;
 848                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 849                         dr7 |= 2 << (i*2);    /* global enable */
 850                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 851                 }
 852
 853                 vcpu->guest_debug.singlestep = dbg->singlestep;
 854         } else
 855                 vcpu->guest_debug.singlestep = 0;
 856
 857         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 858                 unsigned long flags;
 859
 860                 flags = vmcs_readl(GUEST_RFLAGS);
 861                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 862                 vmcs_writel(GUEST_RFLAGS, flags);
 863         }
 864
 865         update_exception_bitmap(vcpu);
 866         vmcs_writel(GUEST_DR7, dr7);
 867
 868         return 0;
 869 }
 870
 871 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 872 {
 873         struct vcpu_vmx *vmx = to_vmx(vcpu);
 874         u32 idtv_info_field;
 875
 876         idtv_info_field = vmx->idt_vectoring_info;
 877         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 878                 if (is_external_interrupt(idtv_info_field))
 879                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 880                 else
 881                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 882         }
 883         return -1;
 884 }
 885
 886 static __init int cpu_has_kvm_support(void)
 887 {
 888         unsigned long ecx = cpuid_ecx(1);
 889         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
 890 }
 891
 892 static __init int vmx_disabled_by_bios(void)
 893 {
 894         u64 msr;
 895
 896         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 897         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 898                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 899             == MSR_IA32_FEATURE_CONTROL_LOCKED;
 900         /* locked but not enabled */
 901 }
 902
 903 static void hardware_enable(void *garbage)
 904 {
 905         int cpu = raw_smp_processor_id();
 906         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 907         u64 old;
 908
 909         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
 910         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 911                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 912             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
 913                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 914                 /* enable and lock */
 915                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
 916                        MSR_IA32_FEATURE_CONTROL_LOCKED |
 917                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
 918         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
 919         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
 920                       : "memory", "cc");
 921 }
 922
 923 static void hardware_disable(void *garbage)
 924 {
 925         asm volatile (ASM_VMX_VMXOFF : : : "cc");
 926 }
 927
 928 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 929                                       u32 msr, u32 *result)
 930 {
 931         u32 vmx_msr_low, vmx_msr_high;
 932         u32 ctl = ctl_min | ctl_opt;
 933
 934         rdmsr(msr, vmx_msr_low, vmx_msr_high);
 935
 936         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
 937         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
 938
 939         /* Ensure minimum (required) set of control bits are supported. */
 940         if (ctl_min & ~ctl)
 941                 return -EIO;
 942
 943         *result = ctl;
 944         return 0;
 945 }
 946
 947 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 948 {
 949         u32 vmx_msr_low, vmx_msr_high;
 950         u32 min, opt;
 951         u32 _pin_based_exec_control = 0;
 952         u32 _cpu_based_exec_control = 0;
 953         u32 _cpu_based_2nd_exec_control = 0;
 954         u32 _vmexit_control = 0;
 955         u32 _vmentry_control = 0;
 956
 957         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
 958         opt = 0;
 959         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
 960                                 &_pin_based_exec_control) < 0)
 961                 return -EIO;
 962
 963         min = CPU_BASED_HLT_EXITING |
 964 #ifdef CONFIG_X86_64
 965               CPU_BASED_CR8_LOAD_EXITING |
 966               CPU_BASED_CR8_STORE_EXITING |
 967 #endif
 968               CPU_BASED_USE_IO_BITMAPS |
 969               CPU_BASED_MOV_DR_EXITING |
 970               CPU_BASED_USE_TSC_OFFSETING;
 971         opt = CPU_BASED_TPR_SHADOW |
 972               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 973         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 974                                 &_cpu_based_exec_control) < 0)
 975                 return -EIO;
 976 #ifdef CONFIG_X86_64
 977         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
 978                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 979                                            ~CPU_BASED_CR8_STORE_EXITING;
 980 #endif
 981         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
 982                 min = 0;
 983                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 984                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
 985                                         &_cpu_based_2nd_exec_control) < 0)
 986                         return -EIO;
 987         }
 988 #ifndef CONFIG_X86_64
 989         if (!(_cpu_based_2nd_exec_control &
 990                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
 991                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
 992 #endif
 993
 994         min = 0;
 995 #ifdef CONFIG_X86_64
 996         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 997 #endif
 998         opt = 0;
 999         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1000                                 &_vmexit_control) < 0)
1001                 return -EIO;
1002
1003         min = opt = 0;
1004         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1005                                 &_vmentry_control) < 0)
1006                 return -EIO;
1007
1008         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1009
1010         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1011         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1012                 return -EIO;
1013
1014 #ifdef CONFIG_X86_64
1015         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1016         if (vmx_msr_high & (1u<<16))
1017                 return -EIO;
1018 #endif
1019
1020         /* Require Write-Back (WB) memory type for VMCS accesses. */
1021         if (((vmx_msr_high >> 18) & 15) != 6)
1022                 return -EIO;
1023
1024         vmcs_conf->size = vmx_msr_high & 0x1fff;
1025         vmcs_conf->order = get_order(vmcs_config.size);
1026         vmcs_conf->revision_id = vmx_msr_low;
1027
1028         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1029         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1030         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1031         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1032         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1033
1034         return 0;
1035 }
1036
1037 static struct vmcs *alloc_vmcs_cpu(int cpu)
1038 {
1039         int node = cpu_to_node(cpu);
1040         struct page *pages;
1041         struct vmcs *vmcs;
1042
1043         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1044         if (!pages)
1045                 return NULL;
1046         vmcs = page_address(pages);
1047         memset(vmcs, 0, vmcs_config.size);
1048         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1049         return vmcs;
1050 }
1051
1052 static struct vmcs *alloc_vmcs(void)
1053 {
1054         return alloc_vmcs_cpu(raw_smp_processor_id());
1055 }
1056
1057 static void free_vmcs(struct vmcs *vmcs)
1058 {
1059         free_pages((unsigned long)vmcs, vmcs_config.order);
1060 }
1061
1062 static void free_kvm_area(void)
1063 {
1064         int cpu;
1065
1066         for_each_online_cpu(cpu)
1067                 free_vmcs(per_cpu(vmxarea, cpu));
1068 }
1069
1070 static __init int alloc_kvm_area(void)
1071 {
1072         int cpu;
1073
1074         for_each_online_cpu(cpu) {
1075                 struct vmcs *vmcs;
1076
1077                 vmcs = alloc_vmcs_cpu(cpu);
1078                 if (!vmcs) {
1079                         free_kvm_area();
1080                         return -ENOMEM;
1081                 }
1082
1083                 per_cpu(vmxarea, cpu) = vmcs;
1084         }
1085         return 0;
1086 }
1087
1088 static __init int hardware_setup(void)
1089 {
1090         if (setup_vmcs_config(&vmcs_config) < 0)
1091                 return -EIO;
1092         return alloc_kvm_area();
1093 }
1094
1095 static __exit void hardware_unsetup(void)
1096 {
1097         free_kvm_area();
1098 }
1099
1100 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1101 {
1102         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1103
1104         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1105                 vmcs_write16(sf->selector, save->selector);
1106                 vmcs_writel(sf->base, save->base);
1107                 vmcs_write32(sf->limit, save->limit);
1108                 vmcs_write32(sf->ar_bytes, save->ar);
1109         } else {
1110                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1111                         << AR_DPL_SHIFT;
1112                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1113         }
1114 }
1115
1116 static void enter_pmode(struct kvm_vcpu *vcpu)
1117 {
1118         unsigned long flags;
1119
1120         vcpu->rmode.active = 0;
1121
1122         vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1123         vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1124         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1125
1126         flags = vmcs_readl(GUEST_RFLAGS);
1127         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1128         flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1129         vmcs_writel(GUEST_RFLAGS, flags);
1130
1131         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1132                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1133
1134         update_exception_bitmap(vcpu);
1135
1136         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1137         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1138         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1139         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1140
1141         vmcs_write16(GUEST_SS_SELECTOR, 0);
1142         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1143
1144         vmcs_write16(GUEST_CS_SELECTOR,
1145                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1146         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1147 }
1148
1149 static gva_t rmode_tss_base(struct kvm *kvm)
1150 {
1151         if (!kvm->tss_addr) {
1152                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1153                                  kvm->memslots[0].npages - 3;
1154                 return base_gfn << PAGE_SHIFT;
1155         }
1156         return kvm->tss_addr;
1157 }
1158
1159 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1160 {
1161         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1162
1163         save->selector = vmcs_read16(sf->selector);
1164         save->base = vmcs_readl(sf->base);
1165         save->limit = vmcs_read32(sf->limit);
1166         save->ar = vmcs_read32(sf->ar_bytes);
1167         vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1168         vmcs_write32(sf->limit, 0xffff);
1169         vmcs_write32(sf->ar_bytes, 0xf3);
1170 }
1171
1172 static void enter_rmode(struct kvm_vcpu *vcpu)
1173 {
1174         unsigned long flags;
1175
1176         vcpu->rmode.active = 1;
1177
1178         vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1179         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1180
1181         vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1182         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1183
1184         vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1185         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1186
1187         flags = vmcs_readl(GUEST_RFLAGS);
1188         vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1189
1190         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1191
1192         vmcs_writel(GUEST_RFLAGS, flags);
1193         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1194         update_exception_bitmap(vcpu);
1195
1196         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1197         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1198         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1199
1200         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1201         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1202         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1203                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1204         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1205
1206         fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1207         fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1208         fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1209         fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1210
1211         kvm_mmu_reset_context(vcpu);
1212         init_rmode_tss(vcpu->kvm);
1213 }
1214
1215 #ifdef CONFIG_X86_64
1216
1217 static void enter_lmode(struct kvm_vcpu *vcpu)
1218 {
1219         u32 guest_tr_ar;
1220
1221         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1222         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1223                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1224                        __FUNCTION__);
1225                 vmcs_write32(GUEST_TR_AR_BYTES,
1226                              (guest_tr_ar & ~AR_TYPE_MASK)
1227                              | AR_TYPE_BUSY_64_TSS);
1228         }
1229
1230         vcpu->shadow_efer |= EFER_LMA;
1231
1232         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1233         vmcs_write32(VM_ENTRY_CONTROLS,
1234                      vmcs_read32(VM_ENTRY_CONTROLS)
1235                      | VM_ENTRY_IA32E_MODE);
1236 }
1237
1238 static void exit_lmode(struct kvm_vcpu *vcpu)
1239 {
1240         vcpu->shadow_efer &= ~EFER_LMA;
1241
1242         vmcs_write32(VM_ENTRY_CONTROLS,
1243                      vmcs_read32(VM_ENTRY_CONTROLS)
1244                      & ~VM_ENTRY_IA32E_MODE);
1245 }
1246
1247 #endif
1248
1249 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1250 {
1251         vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1252         vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1253 }
1254
1255 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1256 {
1257         vmx_fpu_deactivate(vcpu);
1258
1259         if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1260                 enter_pmode(vcpu);
1261
1262         if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1263                 enter_rmode(vcpu);
1264
1265 #ifdef CONFIG_X86_64
1266         if (vcpu->shadow_efer & EFER_LME) {
1267                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1268                         enter_lmode(vcpu);
1269                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1270                         exit_lmode(vcpu);
1271         }
1272 #endif
1273
1274         vmcs_writel(CR0_READ_SHADOW, cr0);
1275         vmcs_writel(GUEST_CR0,
1276                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1277         vcpu->cr0 = cr0;
1278
1279         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1280                 vmx_fpu_activate(vcpu);
1281 }
1282
1283 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1284 {
1285         vmcs_writel(GUEST_CR3, cr3);
1286         if (vcpu->cr0 & X86_CR0_PE)
1287                 vmx_fpu_deactivate(vcpu);
1288 }
1289
1290 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1291 {
1292         vmcs_writel(CR4_READ_SHADOW, cr4);
1293         vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1294                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1295         vcpu->cr4 = cr4;
1296 }
1297
1298 #ifdef CONFIG_X86_64
1299
1300 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1301 {
1302         struct vcpu_vmx *vmx = to_vmx(vcpu);
1303         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1304
1305         vcpu->shadow_efer = efer;
1306         if (efer & EFER_LMA) {
1307                 vmcs_write32(VM_ENTRY_CONTROLS,
1308                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1309                                      VM_ENTRY_IA32E_MODE);
1310                 msr->data = efer;
1311
1312         } else {
1313                 vmcs_write32(VM_ENTRY_CONTROLS,
1314                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1315                                      ~VM_ENTRY_IA32E_MODE);
1316
1317                 msr->data = efer & ~EFER_LME;
1318         }
1319         setup_msrs(vmx);
1320 }
1321
1322 #endif
1323
1324 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1325 {
1326         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1327
1328         return vmcs_readl(sf->base);
1329 }
1330
1331 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1332                             struct kvm_segment *var, int seg)
1333 {
1334         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1335         u32 ar;
1336
1337         var->base = vmcs_readl(sf->base);
1338         var->limit = vmcs_read32(sf->limit);
1339         var->selector = vmcs_read16(sf->selector);
1340         ar = vmcs_read32(sf->ar_bytes);
1341         if (ar & AR_UNUSABLE_MASK)
1342                 ar = 0;
1343         var->type = ar & 15;
1344         var->s = (ar >> 4) & 1;
1345         var->dpl = (ar >> 5) & 3;
1346         var->present = (ar >> 7) & 1;
1347         var->avl = (ar >> 12) & 1;
1348         var->l = (ar >> 13) & 1;
1349         var->db = (ar >> 14) & 1;
1350         var->g = (ar >> 15) & 1;
1351         var->unusable = (ar >> 16) & 1;
1352 }
1353
1354 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1355 {
1356         u32 ar;
1357
1358         if (var->unusable)
1359                 ar = 1 << 16;
1360         else {
1361                 ar = var->type & 15;
1362                 ar |= (var->s & 1) << 4;
1363                 ar |= (var->dpl & 3) << 5;
1364                 ar |= (var->present & 1) << 7;
1365                 ar |= (var->avl & 1) << 12;
1366                 ar |= (var->l & 1) << 13;
1367                 ar |= (var->db & 1) << 14;
1368                 ar |= (var->g & 1) << 15;
1369         }
1370         if (ar == 0) /* a 0 value means unusable */
1371                 ar = AR_UNUSABLE_MASK;
1372
1373         return ar;
1374 }
1375
1376 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1377                             struct kvm_segment *var, int seg)
1378 {
1379         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1380         u32 ar;
1381
1382         if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1383                 vcpu->rmode.tr.selector = var->selector;
1384                 vcpu->rmode.tr.base = var->base;
1385                 vcpu->rmode.tr.limit = var->limit;
1386                 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1387                 return;
1388         }
1389         vmcs_writel(sf->base, var->base);
1390         vmcs_write32(sf->limit, var->limit);
1391         vmcs_write16(sf->selector, var->selector);
1392         if (vcpu->rmode.active && var->s) {
1393                 /*
1394                  * Hack real-mode segments into vm86 compatibility.
1395                  */
1396                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1397                         vmcs_writel(sf->base, 0xf0000);
1398                 ar = 0xf3;
1399         } else
1400                 ar = vmx_segment_access_rights(var);
1401         vmcs_write32(sf->ar_bytes, ar);
1402 }
1403
1404 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1405 {
1406         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1407
1408         *db = (ar >> 14) & 1;
1409         *l = (ar >> 13) & 1;
1410 }
1411
1412 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1413 {
1414         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1415         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1416 }
1417
1418 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1419 {
1420         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1421         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1422 }
1423
1424 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1425 {
1426         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1427         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1428 }
1429
1430 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1431 {
1432         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1433         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1434 }
1435
1436 static int init_rmode_tss(struct kvm *kvm)
1437 {
1438         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1439         u16 data = 0;
1440         int r;
1441
1442         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1443         if (r < 0)
1444                 return 0;
1445         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1446         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1447         if (r < 0)
1448                 return 0;
1449         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1450         if (r < 0)
1451                 return 0;
1452         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1453         if (r < 0)
1454                 return 0;
1455         data = ~0;
1456         r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1457                         sizeof(u8));
1458         if (r < 0)
1459                 return 0;
1460         return 1;
1461 }
1462
1463 static void seg_setup(int seg)
1464 {
1465         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1466
1467         vmcs_write16(sf->selector, 0);
1468         vmcs_writel(sf->base, 0);
1469         vmcs_write32(sf->limit, 0xffff);
1470         vmcs_write32(sf->ar_bytes, 0x93);
1471 }
1472
1473 static int alloc_apic_access_page(struct kvm *kvm)
1474 {
1475         struct kvm_userspace_memory_region kvm_userspace_mem;
1476         int r = 0;
1477
1478         mutex_lock(&kvm->lock);
1479         if (kvm->apic_access_page)
1480                 goto out;
1481         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1482         kvm_userspace_mem.flags = 0;
1483         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1484         kvm_userspace_mem.memory_size = PAGE_SIZE;
1485         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1486         if (r)
1487                 goto out;
1488         kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1489 out:
1490         mutex_unlock(&kvm->lock);
1491         return r;
1492 }
1493
1494 /*
1495  * Sets up the vmcs for emulated real mode.
1496  */
1497 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1498 {
1499         u32 host_sysenter_cs;
1500         u32 junk;
1501         unsigned long a;
1502         struct descriptor_table dt;
1503         int i;
1504         unsigned long kvm_vmx_return;
1505         u32 exec_control;
1506
1507         /* I/O */
1508         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1509         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1510
1511         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1512
1513         /* Control */
1514         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1515                 vmcs_config.pin_based_exec_ctrl);
1516
1517         exec_control = vmcs_config.cpu_based_exec_ctrl;
1518         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1519                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1520 #ifdef CONFIG_X86_64
1521                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1522                                 CPU_BASED_CR8_LOAD_EXITING;
1523 #endif
1524         }
1525         if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1526                 exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1527         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1528
1529         if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1530                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
1531                              vmcs_config.cpu_based_2nd_exec_ctrl);
1532
1533         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1534         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1535         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1536
1537         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1538         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1539         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1540
1541         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1542         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1543         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1544         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1545         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1546         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1547 #ifdef CONFIG_X86_64
1548         rdmsrl(MSR_FS_BASE, a);
1549         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1550         rdmsrl(MSR_GS_BASE, a);
1551         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1552 #else
1553         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1554         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1555 #endif
1556
1557         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1558
1559         get_idt(&dt);
1560         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1561
1562         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1563         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1564         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1565         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1566         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1567
1568         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1569         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1570         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1571         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1572         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1573         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1574
1575         for (i = 0; i < NR_VMX_MSR; ++i) {
1576                 u32 index = vmx_msr_index[i];
1577                 u32 data_low, data_high;
1578                 u64 data;
1579                 int j = vmx->nmsrs;
1580
1581                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1582                         continue;
1583                 if (wrmsr_safe(index, data_low, data_high) < 0)
1584                         continue;
1585                 data = data_low | ((u64)data_high << 32);
1586                 vmx->host_msrs[j].index = index;
1587                 vmx->host_msrs[j].reserved = 0;
1588                 vmx->host_msrs[j].data = data;
1589                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1590                 ++vmx->nmsrs;
1591         }
1592
1593         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1594
1595         /* 22.2.1, 20.8.1 */
1596         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1597
1598         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1599         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1600
1601         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1602                 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1603                         return -ENOMEM;
1604
1605         return 0;
1606 }
1607
1608 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1609 {
1610         struct vcpu_vmx *vmx = to_vmx(vcpu);
1611         u64 msr;
1612         int ret;
1613
1614         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1615                 ret = -ENOMEM;
1616                 goto out;
1617         }
1618
1619         vmx->vcpu.rmode.active = 0;
1620
1621         vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1622         set_cr8(&vmx->vcpu, 0);
1623         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1624         if (vmx->vcpu.vcpu_id == 0)
1625                 msr |= MSR_IA32_APICBASE_BSP;
1626         kvm_set_apic_base(&vmx->vcpu, msr);
1627
1628         fx_init(&vmx->vcpu);
1629
1630         /*
1631          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1632          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1633          */
1634         if (vmx->vcpu.vcpu_id == 0) {
1635                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1636                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1637         } else {
1638                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1639                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1640         }
1641         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1642         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1643
1644         seg_setup(VCPU_SREG_DS);
1645         seg_setup(VCPU_SREG_ES);
1646         seg_setup(VCPU_SREG_FS);
1647         seg_setup(VCPU_SREG_GS);
1648         seg_setup(VCPU_SREG_SS);
1649
1650         vmcs_write16(GUEST_TR_SELECTOR, 0);
1651         vmcs_writel(GUEST_TR_BASE, 0);
1652         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1653         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1654
1655         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1656         vmcs_writel(GUEST_LDTR_BASE, 0);
1657         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1658         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1659
1660         vmcs_write32(GUEST_SYSENTER_CS, 0);
1661         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1662         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1663
1664         vmcs_writel(GUEST_RFLAGS, 0x02);
1665         if (vmx->vcpu.vcpu_id == 0)
1666                 vmcs_writel(GUEST_RIP, 0xfff0);
1667         else
1668                 vmcs_writel(GUEST_RIP, 0);
1669         vmcs_writel(GUEST_RSP, 0);
1670
1671         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1672         vmcs_writel(GUEST_DR7, 0x400);
1673
1674         vmcs_writel(GUEST_GDTR_BASE, 0);
1675         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1676
1677         vmcs_writel(GUEST_IDTR_BASE, 0);
1678         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1679
1680         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1681         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1682         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1683
1684         guest_write_tsc(0);
1685
1686         /* Special registers */
1687         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1688
1689         setup_msrs(vmx);
1690
1691         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1692
1693         if (cpu_has_vmx_tpr_shadow()) {
1694                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1695                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1696                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1697                                      page_to_phys(vmx->vcpu.apic->regs_page));
1698                 vmcs_write32(TPR_THRESHOLD, 0);
1699         }
1700
1701         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1702                 vmcs_write64(APIC_ACCESS_ADDR,
1703                              page_to_phys(vmx->vcpu.kvm->apic_access_page));
1704
1705         vmx->vcpu.cr0 = 0x60000010;
1706         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1707         vmx_set_cr4(&vmx->vcpu, 0);
1708 #ifdef CONFIG_X86_64
1709         vmx_set_efer(&vmx->vcpu, 0);
1710 #endif
1711         vmx_fpu_activate(&vmx->vcpu);
1712         update_exception_bitmap(&vmx->vcpu);
1713
1714         return 0;
1715
1716 out:
1717         return ret;
1718 }
1719
1720 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1721 {
1722         struct vcpu_vmx *vmx = to_vmx(vcpu);
1723
1724         if (vcpu->rmode.active) {
1725                 vmx->rmode.irq.pending = true;
1726                 vmx->rmode.irq.vector = irq;
1727                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1728                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1729                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1730                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1731                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1732                 return;
1733         }
1734         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1735                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1736 }
1737
1738 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1739 {
1740         int word_index = __ffs(vcpu->irq_summary);
1741         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1742         int irq = word_index * BITS_PER_LONG + bit_index;
1743
1744         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1745         if (!vcpu->irq_pending[word_index])
1746                 clear_bit(word_index, &vcpu->irq_summary);
1747         vmx_inject_irq(vcpu, irq);
1748 }
1749
1750
1751 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1752                                        struct kvm_run *kvm_run)
1753 {
1754         u32 cpu_based_vm_exec_control;
1755
1756         vcpu->interrupt_window_open =
1757                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1758                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1759
1760         if (vcpu->interrupt_window_open &&
1761             vcpu->irq_summary &&
1762             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1763                 /*
1764                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1765                  */
1766                 kvm_do_inject_irq(vcpu);
1767
1768         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1769         if (!vcpu->interrupt_window_open &&
1770             (vcpu->irq_summary || kvm_run->request_interrupt_window))
1771                 /*
1772                  * Interrupts blocked.  Wait for unblock.
1773                  */
1774                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1775         else
1776                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1777         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1778 }
1779
1780 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1781 {
1782         int ret;
1783         struct kvm_userspace_memory_region tss_mem = {
1784                 .slot = 8,
1785                 .guest_phys_addr = addr,
1786                 .memory_size = PAGE_SIZE * 3,
1787                 .flags = 0,
1788         };
1789
1790         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1791         if (ret)
1792                 return ret;
1793         kvm->tss_addr = addr;
1794         return 0;
1795 }
1796
1797 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1798 {
1799         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1800
1801         set_debugreg(dbg->bp[0], 0);
1802         set_debugreg(dbg->bp[1], 1);
1803         set_debugreg(dbg->bp[2], 2);
1804         set_debugreg(dbg->bp[3], 3);
1805
1806         if (dbg->singlestep) {
1807                 unsigned long flags;
1808
1809                 flags = vmcs_readl(GUEST_RFLAGS);
1810                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1811                 vmcs_writel(GUEST_RFLAGS, flags);
1812         }
1813 }
1814
1815 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1816                                   int vec, u32 err_code)
1817 {
1818         if (!vcpu->rmode.active)
1819                 return 0;
1820
1821         /*
1822          * Instruction with address size override prefix opcode 0x67
1823          * Cause the #SS fault with 0 error code in VM86 mode.
1824          */
1825         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1826                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1827                         return 1;
1828         return 0;
1829 }
1830
1831 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1832 {
1833         struct vcpu_vmx *vmx = to_vmx(vcpu);
1834         u32 intr_info, error_code;
1835         unsigned long cr2, rip;
1836         u32 vect_info;
1837         enum emulation_result er;
1838
1839         vect_info = vmx->idt_vectoring_info;
1840         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1841
1842         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1843                                                 !is_page_fault(intr_info))
1844                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1845                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1846
1847         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1848                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1849                 set_bit(irq, vcpu->irq_pending);
1850                 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1851         }
1852
1853         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1854                 return 1;  /* already handled by vmx_vcpu_run() */
1855
1856         if (is_no_device(intr_info)) {
1857                 vmx_fpu_activate(vcpu);
1858                 return 1;
1859         }
1860
1861         if (is_invalid_opcode(intr_info)) {
1862                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1863                 if (er != EMULATE_DONE)
1864                         vmx_inject_ud(vcpu);
1865
1866                 return 1;
1867         }
1868
1869         error_code = 0;
1870         rip = vmcs_readl(GUEST_RIP);
1871         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1872                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1873         if (is_page_fault(intr_info)) {
1874                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1875                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1876         }
1877
1878         if (vcpu->rmode.active &&
1879             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1880                                                                 error_code)) {
1881                 if (vcpu->halt_request) {
1882                         vcpu->halt_request = 0;
1883                         return kvm_emulate_halt(vcpu);
1884                 }
1885                 return 1;
1886         }
1887
1888         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1889             (INTR_TYPE_EXCEPTION | 1)) {
1890                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1891                 return 0;
1892         }
1893         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1894         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1895         kvm_run->ex.error_code = error_code;
1896         return 0;
1897 }
1898
1899 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1900                                      struct kvm_run *kvm_run)
1901 {
1902         ++vcpu->stat.irq_exits;
1903         return 1;
1904 }
1905
1906 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1907 {
1908         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1909         return 0;
1910 }
1911
1912 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1913 {
1914         unsigned long exit_qualification;
1915         int size, down, in, string, rep;
1916         unsigned port;
1917
1918         ++vcpu->stat.io_exits;
1919         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1920         string = (exit_qualification & 16) != 0;
1921
1922         if (string) {
1923                 if (emulate_instruction(vcpu,
1924                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1925                         return 0;
1926                 return 1;
1927         }
1928
1929         size = (exit_qualification & 7) + 1;
1930         in = (exit_qualification & 8) != 0;
1931         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1932         rep = (exit_qualification & 32) != 0;
1933         port = exit_qualification >> 16;
1934
1935         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1936 }
1937
1938 static void
1939 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1940 {
1941         /*
1942          * Patch in the VMCALL instruction:
1943          */
1944         hypercall[0] = 0x0f;
1945         hypercall[1] = 0x01;
1946         hypercall[2] = 0xc1;
1947 }
1948
1949 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1950 {
1951         unsigned long exit_qualification;
1952         int cr;
1953         int reg;
1954
1955         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1956         cr = exit_qualification & 15;
1957         reg = (exit_qualification >> 8) & 15;
1958         switch ((exit_qualification >> 4) & 3) {
1959         case 0: /* mov to cr */
1960                 switch (cr) {
1961                 case 0:
1962                         vcpu_load_rsp_rip(vcpu);
1963                         set_cr0(vcpu, vcpu->regs[reg]);
1964                         skip_emulated_instruction(vcpu);
1965                         return 1;
1966                 case 3:
1967                         vcpu_load_rsp_rip(vcpu);
1968                         set_cr3(vcpu, vcpu->regs[reg]);
1969                         skip_emulated_instruction(vcpu);
1970                         return 1;
1971                 case 4:
1972                         vcpu_load_rsp_rip(vcpu);
1973                         set_cr4(vcpu, vcpu->regs[reg]);
1974                         skip_emulated_instruction(vcpu);
1975                         return 1;
1976                 case 8:
1977                         vcpu_load_rsp_rip(vcpu);
1978                         set_cr8(vcpu, vcpu->regs[reg]);
1979                         skip_emulated_instruction(vcpu);
1980                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1981                         return 0;
1982                 };
1983                 break;
1984         case 2: /* clts */
1985                 vcpu_load_rsp_rip(vcpu);
1986                 vmx_fpu_deactivate(vcpu);
1987                 vcpu->cr0 &= ~X86_CR0_TS;
1988                 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1989                 vmx_fpu_activate(vcpu);
1990                 skip_emulated_instruction(vcpu);
1991                 return 1;
1992         case 1: /*mov from cr*/
1993                 switch (cr) {
1994                 case 3:
1995                         vcpu_load_rsp_rip(vcpu);
1996                         vcpu->regs[reg] = vcpu->cr3;
1997                         vcpu_put_rsp_rip(vcpu);
1998                         skip_emulated_instruction(vcpu);
1999                         return 1;
2000                 case 8:
2001                         vcpu_load_rsp_rip(vcpu);
2002                         vcpu->regs[reg] = get_cr8(vcpu);
2003                         vcpu_put_rsp_rip(vcpu);
2004                         skip_emulated_instruction(vcpu);
2005                         return 1;
2006                 }
2007                 break;
2008         case 3: /* lmsw */
2009                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2010
2011                 skip_emulated_instruction(vcpu);
2012                 return 1;
2013         default:
2014                 break;
2015         }
2016         kvm_run->exit_reason = 0;
2017         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2018                (int)(exit_qualification >> 4) & 3, cr);
2019         return 0;
2020 }
2021
2022 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2023 {
2024         unsigned long exit_qualification;
2025         unsigned long val;
2026         int dr, reg;
2027
2028         /*
2029          * FIXME: this code assumes the host is debugging the guest.
2030          *        need to deal with guest debugging itself too.
2031          */
2032         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2033         dr = exit_qualification & 7;
2034         reg = (exit_qualification >> 8) & 15;
2035         vcpu_load_rsp_rip(vcpu);
2036         if (exit_qualification & 16) {
2037                 /* mov from dr */
2038                 switch (dr) {
2039                 case 6:
2040                         val = 0xffff0ff0;
2041                         break;
2042                 case 7:
2043                         val = 0x400;
2044                         break;
2045                 default:
2046                         val = 0;
2047                 }
2048                 vcpu->regs[reg] = val;
2049         } else {
2050                 /* mov to dr */
2051         }
2052         vcpu_put_rsp_rip(vcpu);
2053         skip_emulated_instruction(vcpu);
2054         return 1;
2055 }
2056
2057 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2058 {
2059         kvm_emulate_cpuid(vcpu);
2060         return 1;
2061 }
2062
2063 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2064 {
2065         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2066         u64 data;
2067
2068         if (vmx_get_msr(vcpu, ecx, &data)) {
2069                 vmx_inject_gp(vcpu, 0);
2070                 return 1;
2071         }
2072
2073         /* FIXME: handling of bits 32:63 of rax, rdx */
2074         vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2075         vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2076         skip_emulated_instruction(vcpu);
2077         return 1;
2078 }
2079
2080 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2081 {
2082         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2083         u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2084                 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2085
2086         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2087                 vmx_inject_gp(vcpu, 0);
2088                 return 1;
2089         }
2090
2091         skip_emulated_instruction(vcpu);
2092         return 1;
2093 }
2094
2095 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2096                                       struct kvm_run *kvm_run)
2097 {
2098         return 1;
2099 }
2100
2101 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2102                                    struct kvm_run *kvm_run)
2103 {
2104         u32 cpu_based_vm_exec_control;
2105
2106         /* clear pending irq */
2107         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2108         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2109         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2110         /*
2111          * If the user space waits to inject interrupts, exit as soon as
2112          * possible
2113          */
2114         if (kvm_run->request_interrupt_window &&
2115             !vcpu->irq_summary) {
2116                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2117                 ++vcpu->stat.irq_window_exits;
2118                 return 0;
2119         }
2120         return 1;
2121 }
2122
2123 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2124 {
2125         skip_emulated_instruction(vcpu);
2126         return kvm_emulate_halt(vcpu);
2127 }
2128
2129 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2130 {
2131         skip_emulated_instruction(vcpu);
2132         kvm_emulate_hypercall(vcpu);
2133         return 1;
2134 }
2135
2136 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2137 {
2138         u64 exit_qualification;
2139         enum emulation_result er;
2140         unsigned long offset;
2141
2142         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2143         offset = exit_qualification & 0xffful;
2144
2145         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2146
2147         if (er !=  EMULATE_DONE) {
2148                 printk(KERN_ERR
2149                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2150                        offset);
2151                 return -ENOTSUPP;
2152         }
2153         return 1;
2154 }
2155
2156 /*
2157  * The exit handlers return 1 if the exit was handled fully and guest execution
2158  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2159  * to be done to userspace and return 0.
2160  */
2161 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2162                                       struct kvm_run *kvm_run) = {
2163         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2164         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2165         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2166         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2167         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2168         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2169         [EXIT_REASON_CPUID]                   = handle_cpuid,
2170         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2171         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2172         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2173         [EXIT_REASON_HLT]                     = handle_halt,
2174         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2175         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2176         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2177 };
2178
2179 static const int kvm_vmx_max_exit_handlers =
2180         ARRAY_SIZE(kvm_vmx_exit_handlers);
2181
2182 /*
2183  * The guest has exited.  See if we can fix it or if we need userspace
2184  * assistance.
2185  */
2186 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2187 {
2188         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2189         struct vcpu_vmx *vmx = to_vmx(vcpu);
2190         u32 vectoring_info = vmx->idt_vectoring_info;
2191
2192         if (unlikely(vmx->fail)) {
2193                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2194                 kvm_run->fail_entry.hardware_entry_failure_reason
2195                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2196                 return 0;
2197         }
2198
2199         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2200                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2201                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2202                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2203         if (exit_reason < kvm_vmx_max_exit_handlers
2204             && kvm_vmx_exit_handlers[exit_reason])
2205                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2206         else {
2207                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2208                 kvm_run->hw.hardware_exit_reason = exit_reason;
2209         }
2210         return 0;
2211 }
2212
2213 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2214 {
2215 }
2216
2217 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2218 {
2219         int max_irr, tpr;
2220
2221         if (!vm_need_tpr_shadow(vcpu->kvm))
2222                 return;
2223
2224         if (!kvm_lapic_enabled(vcpu) ||
2225             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2226                 vmcs_write32(TPR_THRESHOLD, 0);
2227                 return;
2228         }
2229
2230         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2231         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2232 }
2233
2234 static void enable_irq_window(struct kvm_vcpu *vcpu)
2235 {
2236         u32 cpu_based_vm_exec_control;
2237
2238         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2239         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2240         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2241 }
2242
2243 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2244 {
2245         struct vcpu_vmx *vmx = to_vmx(vcpu);
2246         u32 idtv_info_field, intr_info_field;
2247         int has_ext_irq, interrupt_window_open;
2248         int vector;
2249
2250         update_tpr_threshold(vcpu);
2251
2252         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2253         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2254         idtv_info_field = vmx->idt_vectoring_info;
2255         if (intr_info_field & INTR_INFO_VALID_MASK) {
2256                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2257                         /* TODO: fault when IDT_Vectoring */
2258                         printk(KERN_ERR "Fault when IDT_Vectoring\n");
2259                 }
2260                 if (has_ext_irq)
2261                         enable_irq_window(vcpu);
2262                 return;
2263         }
2264         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2265                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2266                     == INTR_TYPE_EXT_INTR
2267                     && vcpu->rmode.active) {
2268                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2269
2270                         vmx_inject_irq(vcpu, vect);
2271                         if (unlikely(has_ext_irq))
2272                                 enable_irq_window(vcpu);
2273                         return;
2274                 }
2275
2276                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2277                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2278                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2279
2280                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2281                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2282                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2283                 if (unlikely(has_ext_irq))
2284                         enable_irq_window(vcpu);
2285                 return;
2286         }
2287         if (!has_ext_irq)
2288                 return;
2289         interrupt_window_open =
2290                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2291                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2292         if (interrupt_window_open) {
2293                 vector = kvm_cpu_get_interrupt(vcpu);
2294                 vmx_inject_irq(vcpu, vector);
2295                 kvm_timer_intr_post(vcpu, vector);
2296         } else
2297                 enable_irq_window(vcpu);
2298 }
2299
2300 /*
2301  * Failure to inject an interrupt should give us the information
2302  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2303  * when fetching the interrupt redirection bitmap in the real-mode
2304  * tss, this doesn't happen.  So we do it ourselves.
2305  */
2306 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2307 {
2308         vmx->rmode.irq.pending = 0;
2309         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2310                 return;
2311         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2312         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2313                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2314                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2315                 return;
2316         }
2317         vmx->idt_vectoring_info =
2318                 VECTORING_INFO_VALID_MASK
2319                 | INTR_TYPE_EXT_INTR
2320                 | vmx->rmode.irq.vector;
2321 }
2322
2323 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2324 {
2325         struct vcpu_vmx *vmx = to_vmx(vcpu);
2326         u32 intr_info;
2327
2328         /*
2329          * Loading guest fpu may have cleared host cr0.ts
2330          */
2331         vmcs_writel(HOST_CR0, read_cr0());
2332
2333         asm(
2334                 /* Store host registers */
2335 #ifdef CONFIG_X86_64
2336                 "push %%rdx; push %%rbp;"
2337                 "push %%rcx \n\t"
2338 #else
2339                 "push %%edx; push %%ebp;"
2340                 "push %%ecx \n\t"
2341 #endif
2342                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2343                 /* Check if vmlaunch of vmresume is needed */
2344                 "cmp $0, %1 \n\t"
2345                 /* Load guest registers.  Don't clobber flags. */
2346 #ifdef CONFIG_X86_64
2347                 "mov %c[cr2](%3), %%rax \n\t"
2348                 "mov %%rax, %%cr2 \n\t"
2349                 "mov %c[rax](%3), %%rax \n\t"
2350                 "mov %c[rbx](%3), %%rbx \n\t"
2351                 "mov %c[rdx](%3), %%rdx \n\t"
2352                 "mov %c[rsi](%3), %%rsi \n\t"
2353                 "mov %c[rdi](%3), %%rdi \n\t"
2354                 "mov %c[rbp](%3), %%rbp \n\t"
2355                 "mov %c[r8](%3),  %%r8  \n\t"
2356                 "mov %c[r9](%3),  %%r9  \n\t"
2357                 "mov %c[r10](%3), %%r10 \n\t"
2358                 "mov %c[r11](%3), %%r11 \n\t"
2359                 "mov %c[r12](%3), %%r12 \n\t"
2360                 "mov %c[r13](%3), %%r13 \n\t"
2361                 "mov %c[r14](%3), %%r14 \n\t"
2362                 "mov %c[r15](%3), %%r15 \n\t"
2363                 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2364 #else
2365                 "mov %c[cr2](%3), %%eax \n\t"
2366                 "mov %%eax,   %%cr2 \n\t"
2367                 "mov %c[rax](%3), %%eax \n\t"
2368                 "mov %c[rbx](%3), %%ebx \n\t"
2369                 "mov %c[rdx](%3), %%edx \n\t"
2370                 "mov %c[rsi](%3), %%esi \n\t"
2371                 "mov %c[rdi](%3), %%edi \n\t"
2372                 "mov %c[rbp](%3), %%ebp \n\t"
2373                 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2374 #endif
2375                 /* Enter guest mode */
2376                 "jne .Llaunched \n\t"
2377                 ASM_VMX_VMLAUNCH "\n\t"
2378                 "jmp .Lkvm_vmx_return \n\t"
2379                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2380                 ".Lkvm_vmx_return: "
2381                 /* Save guest registers, load host registers, keep flags */
2382 #ifdef CONFIG_X86_64
2383                 "xchg %3,     (%%rsp) \n\t"
2384                 "mov %%rax, %c[rax](%3) \n\t"
2385                 "mov %%rbx, %c[rbx](%3) \n\t"
2386                 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2387                 "mov %%rdx, %c[rdx](%3) \n\t"
2388                 "mov %%rsi, %c[rsi](%3) \n\t"
2389                 "mov %%rdi, %c[rdi](%3) \n\t"
2390                 "mov %%rbp, %c[rbp](%3) \n\t"
2391                 "mov %%r8,  %c[r8](%3) \n\t"
2392                 "mov %%r9,  %c[r9](%3) \n\t"
2393                 "mov %%r10, %c[r10](%3) \n\t"
2394                 "mov %%r11, %c[r11](%3) \n\t"
2395                 "mov %%r12, %c[r12](%3) \n\t"
2396                 "mov %%r13, %c[r13](%3) \n\t"
2397                 "mov %%r14, %c[r14](%3) \n\t"
2398                 "mov %%r15, %c[r15](%3) \n\t"
2399                 "mov %%cr2, %%rax   \n\t"
2400                 "mov %%rax, %c[cr2](%3) \n\t"
2401
2402                 "pop  %%rcx; pop  %%rbp; pop  %%rdx \n\t"
2403 #else
2404                 "xchg %3, (%%esp) \n\t"
2405                 "mov %%eax, %c[rax](%3) \n\t"
2406                 "mov %%ebx, %c[rbx](%3) \n\t"
2407                 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2408                 "mov %%edx, %c[rdx](%3) \n\t"
2409                 "mov %%esi, %c[rsi](%3) \n\t"
2410                 "mov %%edi, %c[rdi](%3) \n\t"
2411                 "mov %%ebp, %c[rbp](%3) \n\t"
2412                 "mov %%cr2, %%eax  \n\t"
2413                 "mov %%eax, %c[cr2](%3) \n\t"
2414
2415                 "pop %%ecx; pop %%ebp; pop %%edx \n\t"
2416 #endif
2417                 "setbe %0 \n\t"
2418               : "=q" (vmx->fail)
2419               : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2420                 "c"(vcpu),
2421                 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2422                 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2423                 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2424                 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2425                 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2426                 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2427                 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2428 #ifdef CONFIG_X86_64
2429                 [r8]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8])),
2430                 [r9]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9])),
2431                 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2432                 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2433                 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2434                 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2435                 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2436                 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2437 #endif
2438                 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2439               : "cc", "memory"
2440 #ifdef CONFIG_X86_64
2441                 , "rbx", "rdi", "rsi"
2442                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2443 #else
2444                 , "ebx", "edi", "rsi"
2445 #endif
2446               );
2447
2448         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2449         if (vmx->rmode.irq.pending)
2450                 fixup_rmode_irq(vmx);
2451
2452         vcpu->interrupt_window_open =
2453                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2454
2455         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2456         vmx->launched = 1;
2457
2458         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2459
2460         /* We need to handle NMIs before interrupts are enabled */
2461         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2462                 asm("int $2");
2463 }
2464
2465 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2466                                   unsigned long addr,
2467                                   u32 err_code)
2468 {
2469         struct vcpu_vmx *vmx = to_vmx(vcpu);
2470         u32 vect_info = vmx->idt_vectoring_info;
2471
2472         ++vcpu->stat.pf_guest;
2473
2474         if (is_page_fault(vect_info)) {
2475                 printk(KERN_DEBUG "inject_page_fault: "
2476                        "double fault 0x%lx @ 0x%lx\n",
2477                        addr, vmcs_readl(GUEST_RIP));
2478                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2479                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2480                              DF_VECTOR |
2481                              INTR_TYPE_EXCEPTION |
2482                              INTR_INFO_DELIEVER_CODE_MASK |
2483                              INTR_INFO_VALID_MASK);
2484                 return;
2485         }
2486         vcpu->cr2 = addr;
2487         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2488         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2489                      PF_VECTOR |
2490                      INTR_TYPE_EXCEPTION |
2491                      INTR_INFO_DELIEVER_CODE_MASK |
2492                      INTR_INFO_VALID_MASK);
2493
2494 }
2495
2496 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2497 {
2498         struct vcpu_vmx *vmx = to_vmx(vcpu);
2499
2500         if (vmx->vmcs) {
2501                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2502                 free_vmcs(vmx->vmcs);
2503                 vmx->vmcs = NULL;
2504         }
2505 }
2506
2507 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2508 {
2509         struct vcpu_vmx *vmx = to_vmx(vcpu);
2510
2511         vmx_free_vmcs(vcpu);
2512         kfree(vmx->host_msrs);
2513         kfree(vmx->guest_msrs);
2514         kvm_vcpu_uninit(vcpu);
2515         kmem_cache_free(kvm_vcpu_cache, vmx);
2516 }
2517
2518 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2519 {
2520         int err;
2521         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2522         int cpu;
2523
2524         if (!vmx)
2525                 return ERR_PTR(-ENOMEM);
2526
2527         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2528         if (err)
2529                 goto free_vcpu;
2530
2531         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2532         if (!vmx->guest_msrs) {
2533                 err = -ENOMEM;
2534                 goto uninit_vcpu;
2535         }
2536
2537         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2538         if (!vmx->host_msrs)
2539                 goto free_guest_msrs;
2540
2541         vmx->vmcs = alloc_vmcs();
2542         if (!vmx->vmcs)
2543                 goto free_msrs;
2544
2545         vmcs_clear(vmx->vmcs);
2546
2547         cpu = get_cpu();
2548         vmx_vcpu_load(&vmx->vcpu, cpu);
2549         err = vmx_vcpu_setup(vmx);
2550         vmx_vcpu_put(&vmx->vcpu);
2551         put_cpu();
2552         if (err)
2553                 goto free_vmcs;
2554
2555         return &vmx->vcpu;
2556
2557 free_vmcs:
2558         free_vmcs(vmx->vmcs);
2559 free_msrs:
2560         kfree(vmx->host_msrs);
2561 free_guest_msrs:
2562         kfree(vmx->guest_msrs);
2563 uninit_vcpu:
2564         kvm_vcpu_uninit(&vmx->vcpu);
2565 free_vcpu:
2566         kmem_cache_free(kvm_vcpu_cache, vmx);
2567         return ERR_PTR(err);
2568 }
2569
2570 static void __init vmx_check_processor_compat(void *rtn)
2571 {
2572         struct vmcs_config vmcs_conf;
2573
2574         *(int *)rtn = 0;
2575         if (setup_vmcs_config(&vmcs_conf) < 0)
2576                 *(int *)rtn = -EIO;
2577         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2578                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2579                                 smp_processor_id());
2580                 *(int *)rtn = -EIO;
2581         }
2582 }
2583
2584 static struct kvm_x86_ops vmx_x86_ops = {
2585         .cpu_has_kvm_support = cpu_has_kvm_support,
2586         .disabled_by_bios = vmx_disabled_by_bios,
2587         .hardware_setup = hardware_setup,
2588         .hardware_unsetup = hardware_unsetup,
2589         .check_processor_compatibility = vmx_check_processor_compat,
2590         .hardware_enable = hardware_enable,
2591         .hardware_disable = hardware_disable,
2592
2593         .vcpu_create = vmx_create_vcpu,
2594         .vcpu_free = vmx_free_vcpu,
2595         .vcpu_reset = vmx_vcpu_reset,
2596
2597         .prepare_guest_switch = vmx_save_host_state,
2598         .vcpu_load = vmx_vcpu_load,
2599         .vcpu_put = vmx_vcpu_put,
2600         .vcpu_decache = vmx_vcpu_decache,
2601
2602         .set_guest_debug = set_guest_debug,
2603         .guest_debug_pre = kvm_guest_debug_pre,
2604         .get_msr = vmx_get_msr,
2605         .set_msr = vmx_set_msr,
2606         .get_segment_base = vmx_get_segment_base,
2607         .get_segment = vmx_get_segment,
2608         .set_segment = vmx_set_segment,
2609         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2610         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2611         .set_cr0 = vmx_set_cr0,
2612         .set_cr3 = vmx_set_cr3,
2613         .set_cr4 = vmx_set_cr4,
2614 #ifdef CONFIG_X86_64
2615         .set_efer = vmx_set_efer,
2616 #endif
2617         .get_idt = vmx_get_idt,
2618         .set_idt = vmx_set_idt,
2619         .get_gdt = vmx_get_gdt,
2620         .set_gdt = vmx_set_gdt,
2621         .cache_regs = vcpu_load_rsp_rip,
2622         .decache_regs = vcpu_put_rsp_rip,
2623         .get_rflags = vmx_get_rflags,
2624         .set_rflags = vmx_set_rflags,
2625
2626         .tlb_flush = vmx_flush_tlb,
2627         .inject_page_fault = vmx_inject_page_fault,
2628
2629         .inject_gp = vmx_inject_gp,
2630
2631         .run = vmx_vcpu_run,
2632         .handle_exit = kvm_handle_exit,
2633         .skip_emulated_instruction = skip_emulated_instruction,
2634         .patch_hypercall = vmx_patch_hypercall,
2635         .get_irq = vmx_get_irq,
2636         .set_irq = vmx_inject_irq,
2637         .inject_pending_irq = vmx_intr_assist,
2638         .inject_pending_vectors = do_interrupt_requests,
2639
2640         .set_tss_addr = vmx_set_tss_addr,
2641 };
2642
2643 static int __init vmx_init(void)
2644 {
2645         void *iova;
2646         int r;
2647
2648         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2649         if (!vmx_io_bitmap_a)
2650                 return -ENOMEM;
2651
2652         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2653         if (!vmx_io_bitmap_b) {
2654                 r = -ENOMEM;
2655                 goto out;
2656         }
2657
2658         /*
2659          * Allow direct access to the PC debug port (it is often used for I/O
2660          * delays, but the vmexits simply slow things down).
2661          */
2662         iova = kmap(vmx_io_bitmap_a);
2663         memset(iova, 0xff, PAGE_SIZE);
2664         clear_bit(0x80, iova);
2665         kunmap(vmx_io_bitmap_a);
2666
2667         iova = kmap(vmx_io_bitmap_b);
2668         memset(iova, 0xff, PAGE_SIZE);
2669         kunmap(vmx_io_bitmap_b);
2670
2671         r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2672         if (r)
2673                 goto out1;
2674
2675         if (bypass_guest_pf)
2676                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2677
2678         return 0;
2679
2680 out1:
2681         __free_page(vmx_io_bitmap_b);
2682 out:
2683         __free_page(vmx_io_bitmap_a);
2684         return r;
2685 }
2686
2687 static void __exit vmx_exit(void)
2688 {
2689         __free_page(vmx_io_bitmap_b);
2690         __free_page(vmx_io_bitmap_a);
2691
2692         kvm_exit_x86();
2693 }
2694
2695 module_init(vmx_init)
2696 module_exit(vmx_exit)