2 * Driver for Zarlink DVB-T MT352 demodulator
4 * Written by Holger Waechtler <holger@qanu.de>
5 * and Daniel Mack <daniel@qanu.de>
7 * AVerMedia AVerTV DVB-T 771 support by
8 * Wolfram Joost <dbox2@frokaschwei.de>
10 * Support for Samsung TDTC9251DH01C(M) tuner
11 * Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
12 * Amauri Celani <acelani@essegi.net>
14 * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
15 * Christopher Pascoe <c.pascoe@itee.uq.edu.au>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/init.h>
37 #include <linux/delay.h>
39 #include "dvb_frontend.h"
40 #include "mt352_priv.h"
44 struct i2c_adapter* i2c;
45 struct dvb_frontend frontend;
46 struct dvb_frontend_ops ops;
48 /* configuration settings */
49 const struct mt352_config* config;
53 #define dprintk(args...) \
55 if (debug) printk(KERN_DEBUG "mt352: " args); \
58 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
60 struct mt352_state* state = fe->demodulator_priv;
61 u8 buf[2] = { reg, val };
62 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0,
63 .buf = buf, .len = 2 };
64 int err = i2c_transfer(state->i2c, &msg, 1);
66 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
72 int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
75 for (i=0; i < ilen-1; i++)
76 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
82 static int mt352_read_register(struct mt352_state* state, u8 reg)
87 struct i2c_msg msg [] = { { .addr = state->config->demod_address,
89 .buf = b0, .len = 1 },
90 { .addr = state->config->demod_address,
92 .buf = b1, .len = 1 } };
94 ret = i2c_transfer(state->i2c, msg, 2);
97 printk("%s: readreg error (reg=%d, ret==%i)\n",
98 __FUNCTION__, reg, ret);
105 int mt352_read(struct dvb_frontend *fe, u8 reg)
107 return mt352_read_register(fe->demodulator_priv,reg);
110 static int mt352_sleep(struct dvb_frontend* fe)
112 static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
114 mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
118 static void mt352_calc_nominal_rate(struct mt352_state* state,
119 enum fe_bandwidth bandwidth,
122 u32 adc_clock = 20480; /* 20.340 MHz */
126 case BANDWIDTH_6_MHZ:
129 case BANDWIDTH_7_MHZ:
132 case BANDWIDTH_8_MHZ:
137 if (state->config->adc_clock)
138 adc_clock = state->config->adc_clock;
140 value = 64 * bw * (1<<16) / (7 * 8);
141 value = value * 1000 / adc_clock;
142 dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
143 __FUNCTION__, bw, adc_clock, value);
148 static void mt352_calc_input_freq(struct mt352_state* state,
151 int adc_clock = 20480; /* 20.480000 MHz */
152 int if2 = 36167; /* 36.166667 MHz */
155 if (state->config->adc_clock)
156 adc_clock = state->config->adc_clock;
157 if (state->config->if2)
158 if2 = state->config->if2;
160 ife = (2*adc_clock - if2);
161 value = -16374 * ife / adc_clock;
162 dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
163 __FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
168 static int mt352_set_parameters(struct dvb_frontend* fe,
169 struct dvb_frontend_parameters *param)
171 struct mt352_state* state = fe->demodulator_priv;
172 unsigned char buf[13];
173 static unsigned char tuner_go[] = { 0x5d, 0x01 };
174 static unsigned char fsm_go[] = { 0x5e, 0x01 };
175 unsigned int tps = 0;
176 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
178 switch (op->code_rate_HP) {
198 switch (op->code_rate_LP) {
215 if (op->hierarchy_information == HIERARCHY_AUTO ||
216 op->hierarchy_information == HIERARCHY_NONE)
222 switch (op->constellation) {
236 switch (op->transmission_mode) {
237 case TRANSMISSION_MODE_2K:
238 case TRANSMISSION_MODE_AUTO:
240 case TRANSMISSION_MODE_8K:
247 switch (op->guard_interval) {
248 case GUARD_INTERVAL_1_32:
249 case GUARD_INTERVAL_AUTO:
251 case GUARD_INTERVAL_1_16:
254 case GUARD_INTERVAL_1_8:
257 case GUARD_INTERVAL_1_4:
264 switch (op->hierarchy_information) {
282 buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
284 buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
287 buf[3] = 0x50; // old
288 // buf[3] = 0xf4; // pinnacle
290 mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
291 mt352_calc_input_freq(state, buf+6);
292 state->config->pll_set(fe, param, buf+8);
294 mt352_write(fe, buf, sizeof(buf));
295 if (state->config->no_tuner) {
297 mt352_write(fe, fsm_go, 2);
300 mt352_write(fe, tuner_go, 2);
305 static int mt352_get_parameters(struct dvb_frontend* fe,
306 struct dvb_frontend_parameters *param)
308 struct mt352_state* state = fe->demodulator_priv;
312 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
313 static const u8 tps_fec_to_api[8] =
325 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
328 /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
329 * the mt352 sometimes works with the wrong parameters
331 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
332 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
333 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
335 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
336 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
338 switch ( (tps >> 13) & 3)
341 op->constellation = QPSK;
344 op->constellation = QAM_16;
347 op->constellation = QAM_64;
350 op->constellation = QAM_AUTO;
354 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
356 switch ( (tps >> 2) & 3)
359 op->guard_interval = GUARD_INTERVAL_1_32;
362 op->guard_interval = GUARD_INTERVAL_1_16;
365 op->guard_interval = GUARD_INTERVAL_1_8;
368 op->guard_interval = GUARD_INTERVAL_1_4;
371 op->guard_interval = GUARD_INTERVAL_AUTO;
375 switch ( (tps >> 10) & 7)
378 op->hierarchy_information = HIERARCHY_NONE;
381 op->hierarchy_information = HIERARCHY_1;
384 op->hierarchy_information = HIERARCHY_2;
387 op->hierarchy_information = HIERARCHY_4;
390 op->hierarchy_information = HIERARCHY_AUTO;
394 param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
397 op->bandwidth = BANDWIDTH_8_MHZ;
398 else if (trl == 0x64)
399 op->bandwidth = BANDWIDTH_7_MHZ;
401 op->bandwidth = BANDWIDTH_6_MHZ;
404 if (mt352_read_register(state, STATUS_2) & 0x02)
405 param->inversion = INVERSION_OFF;
407 param->inversion = INVERSION_ON;
412 static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
414 struct mt352_state* state = fe->demodulator_priv;
419 * The MT352 design manual from Zarlink states (page 46-47):
421 * Notes about the TUNER_GO register:
423 * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
424 * byte is copied from the tuner to the STATUS_3 register and
425 * completion of the read operation is indicated by bit-5 of the
426 * INTERRUPT_3 register.
429 if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
431 if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
433 if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
438 *status |= FE_HAS_CARRIER;
440 *status |= FE_HAS_VITERBI;
442 *status |= FE_HAS_LOCK;
444 *status |= FE_HAS_SYNC;
446 *status |= FE_HAS_SIGNAL;
448 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
449 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
450 *status &= ~FE_HAS_LOCK;
455 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
457 struct mt352_state* state = fe->demodulator_priv;
459 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
460 (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
461 (mt352_read_register (state, RS_ERR_CNT_0));
466 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
468 struct mt352_state* state = fe->demodulator_priv;
470 u16 signal = ((mt352_read_register(state, AGC_GAIN_1) << 8) & 0x0f) |
471 (mt352_read_register(state, AGC_GAIN_0));
477 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
479 struct mt352_state* state = fe->demodulator_priv;
481 u8 _snr = mt352_read_register (state, SNR);
482 *snr = (_snr << 8) | _snr;
487 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
489 struct mt352_state* state = fe->demodulator_priv;
491 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
492 (mt352_read_register (state, RS_UBC_0));
497 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
499 fe_tune_settings->min_delay_ms = 800;
500 fe_tune_settings->step_size = 0;
501 fe_tune_settings->max_drift = 0;
506 static int mt352_init(struct dvb_frontend* fe)
508 struct mt352_state* state = fe->demodulator_priv;
510 static u8 mt352_reset_attach [] = { RESET, 0xC0 };
512 dprintk("%s: hello\n",__FUNCTION__);
514 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
515 (mt352_read_register(state, CONFIG) & 0x20) == 0) {
517 /* Do a "hard" reset */
518 mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
519 return state->config->demod_init(fe);
525 static void mt352_release(struct dvb_frontend* fe)
527 struct mt352_state* state = fe->demodulator_priv;
531 static struct dvb_frontend_ops mt352_ops;
533 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
534 struct i2c_adapter* i2c)
536 struct mt352_state* state = NULL;
538 /* allocate memory for the internal state */
539 state = kmalloc(sizeof(struct mt352_state), GFP_KERNEL);
540 if (state == NULL) goto error;
541 memset(state,0,sizeof(*state));
543 /* setup the state */
544 state->config = config;
546 memcpy(&state->ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
548 /* check if the demod is there */
549 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
551 /* create dvb_frontend */
552 state->frontend.ops = &state->ops;
553 state->frontend.demodulator_priv = state;
554 return &state->frontend;
561 static struct dvb_frontend_ops mt352_ops = {
564 .name = "Zarlink MT352 DVB-T",
566 .frequency_min = 174000000,
567 .frequency_max = 862000000,
568 .frequency_stepsize = 166667,
569 .frequency_tolerance = 0,
570 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
571 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
573 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
574 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
575 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
579 .release = mt352_release,
582 .sleep = mt352_sleep,
584 .set_frontend = mt352_set_parameters,
585 .get_frontend = mt352_get_parameters,
586 .get_tune_settings = mt352_get_tune_settings,
588 .read_status = mt352_read_status,
589 .read_ber = mt352_read_ber,
590 .read_signal_strength = mt352_read_signal_strength,
591 .read_snr = mt352_read_snr,
592 .read_ucblocks = mt352_read_ucblocks,
595 module_param(debug, int, 0644);
596 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
598 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
599 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
600 MODULE_LICENSE("GPL");
602 EXPORT_SYMBOL(mt352_attach);
603 EXPORT_SYMBOL(mt352_write);
604 EXPORT_SYMBOL(mt352_read);
608 * compile-command: "make DVB=1"