2 * drivers/media/video/ov9640.c
6 * Author: Andy Lowe (source@mvista.com)
7 * Contact: Trilok Soni <soni.trilok@gmail.com>
9 * Copyright (C) 2004 MontaVista Software, Inc.
10 * Copyright (C) 2004 Texas Instruments.
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
17 #include <linux/i2c.h>
18 #include <linux/delay.h>
19 #include <media/v4l2-int-device.h>
23 #define DRIVER_NAME "ov9640"
25 struct ov9640_sensor {
26 const struct ov9640_platform_data *pdata;
27 struct v4l2_int_device *v4l2_int_device;
28 struct i2c_client *i2c_client;
29 struct v4l2_pix_format pix;
30 struct v4l2_fract timeperframe;
31 int ver; /*ov9640 chip version*/
34 static struct ov9640_sensor ov9640;
35 static struct i2c_driver ov9640sensor_i2c_driver;
37 /* list of image formats supported by OV9640 sensor */
38 const static struct v4l2_fmtdesc ov9640_formats[] = {
40 /* Note: V4L2 defines RGB565 as:
43 * g2 g1 g0 r4 r3 r2 r1 r0 b4 b3 b2 b1 b0 g5 g4 g3
45 * We interpret RGB565 as:
48 * g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3
50 .description = "RGB565, le",
51 .pixelformat = V4L2_PIX_FMT_RGB565,
54 /* Note: V4L2 defines RGB565X as:
57 * b4 b3 b2 b1 b0 g5 g4 g3 g2 g1 g0 r4 r3 r2 r1 r0
59 * We interpret RGB565X as:
62 * r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
64 .description = "RGB565, be",
65 .pixelformat = V4L2_PIX_FMT_RGB565X,
68 .description = "YUYV (YUV 4:2:2), packed",
69 .pixelformat = V4L2_PIX_FMT_YUYV,
72 .description = "UYVY, packed",
73 .pixelformat = V4L2_PIX_FMT_UYVY,
76 /* Note: V4L2 defines RGB555 as:
79 * g2 g1 g0 r4 r3 r2 r1 r0 x b4 b3 b2 b1 b0 g4 g3
81 * We interpret RGB555 as:
84 * g2 g1 g0 b4 b3 b2 b1 b0 x r4 r3 r2 r1 r0 g4 g3
86 .description = "RGB555, le",
87 .pixelformat = V4L2_PIX_FMT_RGB555,
90 /* Note: V4L2 defines RGB555X as:
93 * x b4 b3 b2 b1 b0 g4 g3 g2 g1 g0 r4 r3 r2 r1 r0
95 * We interpret RGB555X as:
98 * x r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0
100 .description = "RGB555, be",
101 .pixelformat = V4L2_PIX_FMT_RGB555X,
105 #define NUM_CAPTURE_FORMATS ARRAY_SIZE(ov9640_formats)
108 * OV9640 register configuration for all combinations of pixel format and
111 /* YUV (YCbCr) QQCIF */
112 const static struct ov9640_reg qqcif_yuv[] = {
113 { 0x12, 0x08 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
114 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
115 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
116 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
117 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
118 { 0x58, 0x0F }, /* MTXS */
119 { OV9640_REG_TERM, OV9640_VAL_TERM }
121 /* YUV (YCbCr) QQVGA */
122 const static struct ov9640_reg qqvga_yuv[] = {
123 { 0x12, 0x10 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
124 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
125 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
126 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
127 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
128 { 0x58, 0x0F }, /* MTXS */
129 { OV9640_REG_TERM, OV9640_VAL_TERM }
131 /* YUV (YCbCr) QCIF */
132 const static struct ov9640_reg qcif_yuv[] = {
133 { 0x12, 0x08 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
134 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
135 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
136 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
137 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
138 { 0x58, 0x0F }, /* MTXS */
139 { OV9640_REG_TERM, OV9640_VAL_TERM }
141 /* YUV (YCbCr) QVGA */
142 const static struct ov9640_reg qvga_yuv[] = {
143 { 0x12, 0x10 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
144 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
145 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
146 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
147 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
148 { 0x58, 0x0F }, /* MTXS */
149 { OV9640_REG_TERM, OV9640_VAL_TERM }
151 /* YUV (YCbCr) CIF */
152 const static struct ov9640_reg cif_yuv[] = {
153 { 0x12, 0x20 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
154 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
155 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
156 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
157 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
158 { 0x58, 0x0F }, /* MTXS */
159 { OV9640_REG_TERM, OV9640_VAL_TERM }
161 /* YUV (YCbCr) VGA */
162 const static struct ov9640_reg vga_yuv[] = {
163 { 0x12, 0x40 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
164 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
165 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
166 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
167 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
168 { 0x58, 0x0F }, /* MTXS */
169 { OV9640_REG_TERM, OV9640_VAL_TERM }
171 /* YUV (YCbCr) SXGA */
172 const static struct ov9640_reg sxga_yuv[] = {
173 { 0x12, 0x00 }, { 0x3C, 0x46 }, { 0x40, 0xC0 }, /* COM7, COM12, COM15 */
174 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
175 { 0x4F, 0x50 }, { 0x50, 0x43 }, { 0x51, 0x0D }, /* MTX1, MTX2, MTX3 */
176 { 0x52, 0x19 }, { 0x53, 0x4C }, { 0x54, 0x65 }, /* MTX4, MTX5, MTX6 */
177 { 0x55, 0x40 }, { 0x56, 0x40 }, { 0x57, 0x40 }, /* MTX7, MTX8, MTX9 */
178 { 0x58, 0x0F }, /* MTXS */
179 { OV9640_REG_TERM, OV9640_VAL_TERM }
182 const static struct ov9640_reg qqcif_565[] = {
183 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
184 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
185 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
186 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
187 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
188 { 0x58, 0x65 }, /* MTXS */
189 { OV9640_REG_TERM, OV9640_VAL_TERM }
192 const static struct ov9640_reg qqvga_565[] = {
193 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
194 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
195 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
196 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
197 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
198 { 0x58, 0x65 }, /* MTXS */
199 { OV9640_REG_TERM, OV9640_VAL_TERM }
202 const static struct ov9640_reg qcif_565[] = {
203 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
204 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
205 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
206 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
207 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
208 { 0x58, 0x65 }, /* MTXS */
209 { OV9640_REG_TERM, OV9640_VAL_TERM }
212 const static struct ov9640_reg qvga_565[] = {
213 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
214 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
215 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
216 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
217 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
218 { 0x58, 0x65 }, /* MTXS */
219 { OV9640_REG_TERM, OV9640_VAL_TERM }
222 const static struct ov9640_reg cif_565[] = {
223 { 0x12, 0x24 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
224 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
225 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
226 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
227 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
228 { 0x58, 0x65 }, /* MTXS */
229 { OV9640_REG_TERM, OV9640_VAL_TERM }
232 const static struct ov9640_reg vga_565[] = {
233 { 0x12, 0x44 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
234 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
235 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
236 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
237 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
238 { 0x58, 0x65 }, /* MTXS */
239 { OV9640_REG_TERM, OV9640_VAL_TERM }
242 const static struct ov9640_reg sxga_565[] = {
243 { 0x12, 0x04 }, { 0x3C, 0x40 }, { 0x40, 0x10 }, /* COM7, COM12, COM15 */
244 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
245 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
246 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
247 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
248 { 0x58, 0x65 }, /* MTXS */
249 { OV9640_REG_TERM, OV9640_VAL_TERM }
252 const static struct ov9640_reg qqcif_555[] = {
253 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
254 { 0x04, 0x24 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
255 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
256 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
257 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
258 { 0x58, 0x65 }, /* MTXS */
259 { OV9640_REG_TERM, OV9640_VAL_TERM }
262 const static struct ov9640_reg qqvga_555[] = {
263 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
264 { 0x04, 0x24 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
265 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
266 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
267 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
268 { 0x58, 0x65 }, /* MTXS */
269 { OV9640_REG_TERM, OV9640_VAL_TERM }
272 const static struct ov9640_reg qcif_555[] = {
273 { 0x12, 0x0C }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
274 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
275 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
276 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
277 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
278 { 0x58, 0x65 }, /* MTXS */
279 { OV9640_REG_TERM, OV9640_VAL_TERM }
282 const static struct ov9640_reg qvga_555[] = {
283 { 0x12, 0x14 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
284 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
285 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
286 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
287 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
288 { 0x58, 0x65 }, /* MTXS */
289 { OV9640_REG_TERM, OV9640_VAL_TERM }
292 const static struct ov9640_reg cif_555[] = {
293 { 0x12, 0x24 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
294 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
295 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
296 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
297 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
298 { 0x58, 0x65 }, /* MTXS */
299 { OV9640_REG_TERM, OV9640_VAL_TERM }
302 const static struct ov9640_reg vga_555[] = {
303 { 0x12, 0x44 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
304 { 0x04, 0x00 }, { 0x0C, 0x04 }, { 0x0D, 0xC0 }, /* COM1, COM3, COM4 */
305 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
306 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
307 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
308 { 0x58, 0x65 }, /* MTXS */
309 { OV9640_REG_TERM, OV9640_VAL_TERM }
312 const static struct ov9640_reg sxga_555[] = {
313 { 0x12, 0x04 }, { 0x3C, 0x40 }, { 0x40, 0x30 }, /* COM7, COM12, COM15 */
314 { 0x04, 0x00 }, { 0x0C, 0x00 }, { 0x0D, 0x40 }, /* COM1, COM3, COM4 */
315 { 0x4F, 0x71 }, { 0x50, 0x3E }, { 0x51, 0x0C }, /* MTX1, MTX2, MTX3 */
316 { 0x52, 0x33 }, { 0x53, 0x72 }, { 0x54, 0x00 }, /* MTX4, MTX5, MTX6 */
317 { 0x55, 0x2B }, { 0x56, 0x66 }, { 0x57, 0xD2 }, /* MTX7, MTX8, MTX9 */
318 { 0x58, 0x65 }, /* MTXS */
319 { OV9640_REG_TERM, OV9640_VAL_TERM }
324 #define DEF_AUTOGAIN 1
325 #define DEF_EXPOSURE 154
327 #define DEF_FREEZE_AGCAEC 0
329 #define DEF_RED (255 - DEF_BLUE)
334 /* Our own specific controls */
335 #define V4L2_CID_FREEZE_AGCAEC V4L2_CID_PRIVATE_BASE
336 #define V4L2_CID_AUTOEXPOSURE V4L2_CID_PRIVATE_BASE + 1
337 #define V4L2_CID_LAST_PRIV V4L2_CID_AUTOEXPOSURE
340 static struct vcontrol {
341 struct v4l2_queryctrl qc;
346 } video_control[] = {
350 .type = V4L2_CTRL_TYPE_INTEGER,
355 .default_value = DEF_GAIN,
364 .id = V4L2_CID_AUTOGAIN,
365 .type = V4L2_CTRL_TYPE_BOOLEAN,
370 .default_value = DEF_AUTOGAIN,
379 .id = V4L2_CID_EXPOSURE,
380 .type = V4L2_CTRL_TYPE_INTEGER,
385 .default_value = DEF_EXPOSURE,
394 .id = V4L2_CID_AUTOEXPOSURE,
395 .type = V4L2_CTRL_TYPE_BOOLEAN,
396 .name = "Auto Exposure",
400 .default_value = DEF_AEC,
409 .id = V4L2_CID_FREEZE_AGCAEC,
410 .type = V4L2_CTRL_TYPE_BOOLEAN,
411 .name = "Freeze AGC/AEC",
415 .default_value = DEF_FREEZE_AGCAEC,
424 .id = V4L2_CID_RED_BALANCE,
425 .type = V4L2_CTRL_TYPE_INTEGER,
426 .name = "Red Balance",
430 .default_value = DEF_RED,
439 .id = V4L2_CID_BLUE_BALANCE,
440 .type = V4L2_CTRL_TYPE_INTEGER,
441 .name = "Blue Balance",
445 .default_value = DEF_BLUE,
454 .id = V4L2_CID_AUTO_WHITE_BALANCE,
455 .type = V4L2_CTRL_TYPE_BOOLEAN,
456 .name = "Auto White Balance",
460 .default_value = DEF_AWB,
469 .id = V4L2_CID_HFLIP,
470 .type = V4L2_CTRL_TYPE_BOOLEAN,
471 .name = "Mirror Image",
475 .default_value = DEF_HFLIP,
484 .id = V4L2_CID_VFLIP,
485 .type = V4L2_CTRL_TYPE_BOOLEAN,
486 .name = "Vertical Flip",
490 .default_value = DEF_VFLIP,
499 const static struct ov9640_reg *
500 ov9640_reg_init[NUM_PIXEL_FORMATS][NUM_IMAGE_SIZES] =
502 { qqcif_yuv, qqvga_yuv, qcif_yuv, qvga_yuv, cif_yuv, vga_yuv, sxga_yuv },
503 { qqcif_565, qqvga_565, qcif_565, qvga_565, cif_565, vga_565, sxga_565 },
504 { qqcif_555, qqvga_555, qcif_555, qvga_555, cif_555, vga_555, sxga_555 },
509 * Read a value from a register in an OV9640 sensor device.
510 * The value is returned in 'val'.
511 * Returns zero if successful, or non-zero otherwise.
514 ov9640_read_reg(struct i2c_client *client, u8 reg, u8 *val)
517 struct i2c_msg msg[1];
518 unsigned char data[1];
520 if (!client->adapter)
523 msg->addr = client->addr;
528 err = i2c_transfer(client->adapter, msg, 1);
530 msg->flags = I2C_M_RD;
531 err = i2c_transfer(client->adapter, msg, 1);
541 * Write a value to a register in an OV9640 sensor device.
542 * Returns zero if successful, or non-zero otherwise.
545 ov9640_write_reg(struct i2c_client *client, u8 reg, u8 val)
548 struct i2c_msg msg[1];
549 unsigned char data[2];
551 if (!client->adapter)
554 msg->addr = client->addr;
560 err = i2c_transfer(client->adapter, msg, 1);
567 ov9640_write_reg_mask(struct i2c_client *client, u8 reg, u8 *val, u8 mask)
575 /* need to do read - modify - write */
576 rc = ov9640_read_reg(client, reg, &oldval);
579 oldval &= (~mask); /* Clear the masked bits */
580 *val &= mask; /* Enforce mask on value */
581 newval = oldval | *val; /* Set the desired bits */
584 /* write the new value to the register */
585 rc = ov9640_write_reg(client, reg, newval);
589 rc = ov9640_read_reg(client, reg, &newval);
593 *val = newval & mask;
598 ov9640_read_reg_mask(struct i2c_client *client, u8 reg, u8 *val, u8 mask)
602 rc = ov9640_read_reg(client, reg, val);
611 * Initialize a list of OV9640 registers.
612 * The list of registers is terminated by the pair of values
613 * { OV9640_REG_TERM, OV9640_VAL_TERM }.
614 * Returns zero if successful, or non-zero otherwise.
617 ov9640_write_regs(struct i2c_client *client, const struct ov9640_reg reglist[])
620 const struct ov9640_reg *next = reglist;
622 while (!((next->reg == OV9640_REG_TERM)
623 && (next->val == OV9640_VAL_TERM))) {
624 err = ov9640_write_reg(client, next->reg, next->val);
633 /* Returns the index of the requested ID from the control structure array */
639 if (id < V4L2_CID_BASE)
642 for (i = (ARRAY_SIZE(video_control) - 1); i >= 0; i--)
643 if (video_control[i].qc.id == id)
651 * Calculate the internal clock divisor (value of the CLKRC register) of the
652 * OV9640 given the image size, the frequency (in Hz) of its XCLK input and a
653 * desired frame period (in seconds). The frame period 'fper' is expressed as
654 * a fraction. The frame period is an input/output parameter.
655 * Returns the value of the OV9640 CLKRC register that will yield the frame
656 * period returned in 'fper' at the specified xclk frequency. The
657 * returned period will be as close to the requested period as possible.
660 ov9640_clkrc(enum image_size isize, unsigned long xclk, struct v4l2_fract *fper)
662 unsigned long fpm, fpm_max; /* frames per minute */
663 unsigned long divisor;
664 const unsigned long divisor_max = 64;
666 * clks_per_frame should come from platform data
668 #ifdef CONFIG_ARCH_OMAP24XX
669 const static unsigned long clks_per_frame[] =
670 { 200000, 400000, 200000, 400000, 400000, 800000, 3200000 };
671 /* QQCIF QQVGA QCIF QVGA CIF VGA SXGA
672 * 199680,400000, 199680, 400000, 399360, 800000, 3200000
675 const static unsigned long clks_per_frame[] =
676 { 200000, 200000, 200000, 200000, 400000, 800000, 3200000 };
679 if (fper->numerator > 0)
680 fpm = (fper->denominator*60)/fper->numerator;
683 fpm_max = (xclk*60)/clks_per_frame[isize];
690 divisor = fpm_max/fpm;
691 if (divisor > divisor_max)
692 divisor = divisor_max;
693 fper->numerator = divisor*60;
694 fper->denominator = fpm_max;
696 /* try to reduce the fraction */
697 while (!(fper->denominator % 5) && !(fper->numerator % 5)) {
698 fper->numerator /= 5;
699 fper->denominator /= 5;
701 while (!(fper->denominator % 3) && !(fper->numerator % 3)) {
702 fper->numerator /= 3;
703 fper->denominator /= 3;
705 while (!(fper->denominator % 2) && !(fper->numerator % 2)) {
706 fper->numerator /= 2;
707 fper->denominator /= 2;
709 if (fper->numerator < fper->denominator) {
710 if (!(fper->denominator % fper->numerator)) {
711 fper->denominator /= fper->numerator;
715 if (!(fper->numerator % fper->denominator)) {
716 fper->numerator /= fper->denominator;
717 fper->denominator = 1;
721 /* we set bit 7 in CLKRC to enable the digital PLL */
722 return (0x80 | (divisor - 1));
726 * Find the best match for a requested image capture size. The best match
727 * is chosen as the nearest match that has the same number or fewer pixels
728 * as the requested size, or the smallest image size if the requested size
729 * has fewer pixels than the smallest image.
731 static enum image_size
732 ov9640_find_size(unsigned int width, unsigned int height)
734 enum image_size isize;
735 unsigned long pixels = width*height;
737 for (isize = QQCIF; isize < SXGA; isize++) {
738 if (ov9640_sizes[isize + 1].height *
739 ov9640_sizes[isize + 1].width > pixels)
746 * Given the image capture format in pix, the nominal frame period in
747 * timeperframe, calculate the required xclk frequency
750 ov9640sensor_calc_xclk(struct i2c_client *c)
752 struct ov9640_sensor *sensor = i2c_get_clientdata(c);
753 struct v4l2_fract *timeperframe = &sensor->timeperframe;
754 struct v4l2_pix_format *pix = &sensor->pix;
756 unsigned long tgt_xclk; /* target xclk */
757 unsigned long tgt_fpm; /* target frames per minute */
758 enum image_size isize;
761 * We use arbitrary rules to select the xclk frequency. If the
762 * capture size is VGA and the frame rate is greater than 900
763 * frames per minute, or if the capture size is SXGA and the
764 * frame rate is greater than 450 frames per minutes, then the
765 * xclk frequency will be set to 48MHz. Otherwise, the xclk
766 * frequency will be set to 24MHz. If the mclk frequency is such that
767 * the target xclk frequency is not achievable, then xclk will be set
768 * as close as to the target as possible.
770 tgt_fpm = (timeperframe->denominator*60)
771 / timeperframe->numerator;
772 tgt_xclk = OV9640_XCLK_NOM;
773 isize = ov9640_find_size(pix->width, pix->height);
777 tgt_xclk = OV9640_XCLK_MAX;
781 tgt_xclk = OV9640_XCLK_MAX;
790 * Configure the OV9640 for a specified image size, pixel format, and frame
791 * period. xclk is the frequency (in Hz) of the xclk input to the OV9640.
792 * fper is the frame period (in seconds) expressed as a fraction.
793 * Returns zero if successful, or non-zero otherwise.
794 * The actual frame period is returned in fper.
796 static int ov9640_configure(struct v4l2_int_device *s)
798 struct ov9640_sensor *sensor = s->priv;
799 struct v4l2_pix_format *pix = &sensor->pix;
800 struct v4l2_fract *fper = &sensor->timeperframe;
801 struct i2c_client *client = sensor->i2c_client;
802 enum image_size isize;
807 enum pixel_format pfmt = YUV;
809 switch (pix->pixelformat) {
810 case V4L2_PIX_FMT_RGB565:
811 case V4L2_PIX_FMT_RGB565X:
814 case V4L2_PIX_FMT_RGB555:
815 case V4L2_PIX_FMT_RGB555X:
818 case V4L2_PIX_FMT_YUYV:
819 case V4L2_PIX_FMT_UYVY:
824 xclk = ov9640sensor_calc_xclk(client);
826 isize = ov9640_find_size(pix->width, pix->height);
828 /* common register initialization */
829 err = ov9640_write_regs(client, sensor->pdata->default_regs);
833 /* configure image size and pixel format */
834 err = ov9640_write_regs(client, ov9640_reg_init[pfmt][isize]);
838 /* configure frame rate */
839 clkrc = ov9640_clkrc(isize, xclk, fper);
840 err = ov9640_write_reg(client, OV9640_CLKRC, clkrc);
848 * Detect if an OV9640 is present, and if so which revision.
849 * A device is considered to be detected if the manufacturer ID (MIDH and MIDL)
850 * and the product ID (PID) registers match the expected values.
851 * Any value of the version ID (VER) register is accepted.
852 * Here are the version numbers we know about:
853 * 0x48 --> OV9640 Revision 1 or OV9640 Revision 2
854 * 0x49 --> OV9640 Revision 3
855 * Returns a negative error number if no device is detected, or the
856 * non-negative value of the version ID register if a device is detected.
859 ov9640_detect(struct i2c_client *client)
861 u8 midh, midl, pid, ver;
866 if (ov9640_read_reg(client, OV9640_MIDH, &midh))
868 if (ov9640_read_reg(client, OV9640_MIDL, &midl))
870 if (ov9640_read_reg(client, OV9640_PID, &pid))
872 if (ov9640_read_reg(client, OV9640_VER, &ver))
875 if ((midh != OV9640_MIDH_MAGIC)
876 || (midl != OV9640_MIDL_MAGIC)
877 || (pid != OV9640_PID_MAGIC))
879 * We didn't read the values we expected, so
880 * this must not be an OV9640.
888 * following are sensor interface functions implemented by
889 * OV9640 sensor driver.
891 static int ioctl_queryctrl(struct v4l2_int_device *s,
892 struct v4l2_queryctrl *qc)
896 i = find_vctrl(qc->id);
898 qc->flags = V4L2_CTRL_FLAG_DISABLED;
904 *qc = video_control[i].qc;
908 static int ioctl_g_ctrl(struct v4l2_int_device *s,
909 struct v4l2_control *vc)
911 struct ov9640_sensor *sensor = s->priv;
912 struct i2c_client *client = sensor->i2c_client;
914 struct vcontrol *lvc;
916 i = find_vctrl(vc->id);
920 lvc = &video_control[i];
921 if (ov9640_read_reg_mask(client, lvc->reg, (u8 *)&val, lvc->mask))
924 val = val >> lvc->start_bit;
926 vc->value = lvc->current_value = val;
932 static int ioctl_s_ctrl(struct v4l2_int_device *s,
933 struct v4l2_control *vc)
935 struct ov9640_sensor *sensor = s->priv;
936 struct i2c_client *client = sensor->i2c_client;
937 struct vcontrol *lvc;
941 i = find_vctrl(vc->id);
945 lvc = &video_control[i];
946 val = val << lvc->start_bit;
947 if (ov9640_write_reg_mask(client, lvc->reg, (u8 *)&val, (u8)lvc->mask))
950 val = val >> lvc->start_bit;
952 lvc->current_value = val;
959 * Implement the VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
961 static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
962 struct v4l2_fmtdesc *fmt)
964 int index = fmt->index;
965 enum v4l2_buf_type type = fmt->type;
967 memset(fmt, 0, sizeof(*fmt));
972 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
973 if (index >= NUM_CAPTURE_FORMATS)
980 fmt->flags = ov9640_formats[index].flags;
981 strlcpy(fmt->description, ov9640_formats[index].description,
982 sizeof(fmt->description));
983 fmt->pixelformat = ov9640_formats[index].pixelformat;
989 * Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This
990 * ioctl is used to negotiate the image capture size and pixel format
991 * without actually making it take effect.
993 static int ioctl_try_fmt_cap(struct v4l2_int_device *s,
994 struct v4l2_format *f)
996 enum image_size isize;
998 struct v4l2_pix_format *pix = &f->fmt.pix;
1000 isize = ov9640_find_size(pix->width, pix->height);
1001 pix->width = ov9640_sizes[isize].width;
1002 pix->height = ov9640_sizes[isize].height;
1003 for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) {
1004 if (pix->pixelformat == ov9640_formats[ifmt].pixelformat)
1007 if (ifmt == NUM_CAPTURE_FORMATS)
1009 pix->pixelformat = ov9640_formats[ifmt].pixelformat;
1010 pix->field = V4L2_FIELD_NONE;
1011 pix->bytesperline = pix->width*2;
1012 pix->sizeimage = pix->bytesperline*pix->height;
1014 switch (pix->pixelformat) {
1015 case V4L2_PIX_FMT_YUYV:
1016 case V4L2_PIX_FMT_UYVY:
1018 pix->colorspace = V4L2_COLORSPACE_JPEG;
1020 case V4L2_PIX_FMT_RGB565:
1021 case V4L2_PIX_FMT_RGB565X:
1022 case V4L2_PIX_FMT_RGB555:
1023 case V4L2_PIX_FMT_RGB555X:
1024 pix->colorspace = V4L2_COLORSPACE_SRGB;
1030 static int ioctl_s_fmt_cap(struct v4l2_int_device *s,
1031 struct v4l2_format *f)
1033 struct ov9640_sensor *sensor = s->priv;
1034 struct v4l2_pix_format *pix = &f->fmt.pix;
1037 rval = ioctl_try_fmt_cap(s, f);
1041 rval = ov9640_configure(s);
1049 static int ioctl_g_fmt_cap(struct v4l2_int_device *s,
1050 struct v4l2_format *f)
1052 struct ov9640_sensor *sensor = s->priv;
1054 f->fmt.pix = sensor->pix;
1059 static int ioctl_g_parm(struct v4l2_int_device *s,
1060 struct v4l2_streamparm *a)
1062 struct ov9640_sensor *sensor = s->priv;
1063 struct v4l2_captureparm *cparm = &a->parm.capture;
1065 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1068 memset(a, 0, sizeof(*a));
1069 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1071 cparm->capability = V4L2_CAP_TIMEPERFRAME;
1072 cparm->timeperframe = sensor->timeperframe;
1077 static int ioctl_s_parm(struct v4l2_int_device *s,
1078 struct v4l2_streamparm *a)
1080 struct ov9640_sensor *sensor = s->priv;
1081 struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
1082 struct v4l2_fract timeperframe_old;
1085 timeperframe_old = sensor->timeperframe;
1086 sensor->timeperframe = *timeperframe;
1088 rval = ov9640_configure(s);
1091 sensor->timeperframe = timeperframe_old;
1093 *timeperframe = sensor->timeperframe;
1098 static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
1100 struct ov9640_sensor *sensor = s->priv;
1101 struct i2c_client *client = sensor->i2c_client;
1102 u32 xclk; /* target xclk */
1105 rval = sensor->pdata->ifparm(p);
1109 xclk = ov9640sensor_calc_xclk(client);
1111 p->u.bt656.clock_curr = xclk;
1116 static int ioctl_s_power(struct v4l2_int_device *s, int on)
1118 struct ov9640_sensor *sensor = s->priv;
1120 return sensor->pdata->power_set(on);
1123 static int ioctl_init(struct v4l2_int_device *s)
1125 return ov9640_configure(s);
1128 static int ioctl_dev_exit(struct v4l2_int_device *s)
1133 static int ioctl_dev_init(struct v4l2_int_device *s)
1135 struct ov9640_sensor *sensor = s->priv;
1136 struct i2c_client *c = sensor->i2c_client;
1139 err = ov9640_detect(c);
1141 dev_err(&c->dev, "Unable to detect " DRIVER_NAME " sensor\n");
1146 pr_info(DRIVER_NAME " chip version 0x%02x detected\n", sensor->ver);
1151 static struct v4l2_int_ioctl_desc ov9640_ioctl_desc[] = {
1152 { vidioc_int_dev_init_num,
1153 (v4l2_int_ioctl_func *)ioctl_dev_init },
1154 { vidioc_int_dev_exit_num,
1155 (v4l2_int_ioctl_func *)ioctl_dev_exit },
1156 { vidioc_int_s_power_num,
1157 (v4l2_int_ioctl_func *)ioctl_s_power },
1158 { vidioc_int_g_ifparm_num,
1159 (v4l2_int_ioctl_func *)ioctl_g_ifparm },
1160 { vidioc_int_init_num,
1161 (v4l2_int_ioctl_func *)ioctl_init },
1162 { vidioc_int_enum_fmt_cap_num,
1163 (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap },
1164 { vidioc_int_try_fmt_cap_num,
1165 (v4l2_int_ioctl_func *)ioctl_try_fmt_cap },
1166 { vidioc_int_g_fmt_cap_num,
1167 (v4l2_int_ioctl_func *)ioctl_g_fmt_cap },
1168 { vidioc_int_s_fmt_cap_num,
1169 (v4l2_int_ioctl_func *)ioctl_s_fmt_cap },
1170 { vidioc_int_g_parm_num,
1171 (v4l2_int_ioctl_func *)ioctl_g_parm },
1172 { vidioc_int_s_parm_num,
1173 (v4l2_int_ioctl_func *)ioctl_s_parm },
1174 { vidioc_int_queryctrl_num,
1175 (v4l2_int_ioctl_func *)ioctl_queryctrl },
1176 { vidioc_int_g_ctrl_num,
1177 (v4l2_int_ioctl_func *)ioctl_g_ctrl },
1178 { vidioc_int_s_ctrl_num,
1179 (v4l2_int_ioctl_func *)ioctl_s_ctrl },
1182 static struct v4l2_int_slave ov9640_slave = {
1183 .ioctls = ov9640_ioctl_desc,
1184 .num_ioctls = ARRAY_SIZE(ov9640_ioctl_desc),
1187 static struct v4l2_int_device ov9640_int_device = {
1188 .module = THIS_MODULE,
1189 .name = DRIVER_NAME,
1191 .type = v4l2_int_type_slave,
1193 .slave = &ov9640_slave,
1198 ov9640_probe(struct i2c_client *client)
1200 struct ov9640_sensor *sensor = &ov9640;
1203 if (i2c_get_clientdata(client))
1206 sensor->pdata = client->dev.platform_data;
1208 if (!sensor->pdata || !sensor->pdata->default_regs) {
1209 dev_err(&client->dev, "no platform data?\n");
1213 sensor->v4l2_int_device = &ov9640_int_device;
1214 sensor->i2c_client = client;
1216 i2c_set_clientdata(client, sensor);
1218 /* Make the default capture format QCIF RGB565 */
1219 sensor->pix.width = ov9640_sizes[QCIF].width;
1220 sensor->pix.height = ov9640_sizes[QCIF].height;
1221 sensor->pix.pixelformat = V4L2_PIX_FMT_RGB565;
1223 err = v4l2_int_device_register(sensor->v4l2_int_device);
1225 i2c_set_clientdata(client, NULL);
1231 ov9640_remove(struct i2c_client *client)
1233 struct ov9640_sensor *sensor = i2c_get_clientdata(client);
1235 if (!client->adapter)
1236 return -ENODEV; /* our client isn't attached */
1238 v4l2_int_device_unregister(sensor->v4l2_int_device);
1239 i2c_set_clientdata(client, NULL);
1244 static struct i2c_driver ov9640sensor_i2c_driver = {
1246 .name = DRIVER_NAME,
1248 .probe = ov9640_probe,
1249 .remove = __exit_p(ov9640_remove),
1252 static struct ov9640_sensor ov9640 = {
1259 static int ov9640sensor_init(void)
1263 err = i2c_add_driver(&ov9640sensor_i2c_driver);
1265 printk(KERN_ERR "Failed to register" DRIVER_NAME ".\n");
1270 module_init(ov9640sensor_init);
1272 static void __exit ov9640sensor_cleanup(void)
1274 i2c_del_driver(&ov9640sensor_i2c_driver);
1276 module_exit(ov9640sensor_cleanup);
1278 MODULE_LICENSE("GPL");
1279 MODULE_DESCRIPTION("OV9640 camera sensor driver");