2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <mach/camera.h>
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43 /* Camera Interface */
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
166 * YUV422P picture size should be a multiple of 16, so the heuristic aligns
167 * height, width on 4 byte boundaries to reach the 16 multiple for the size.
169 #define YUV422P_X_Y_ALIGN 4
170 #define YUV422P_SIZE_ALIGN YUV422P_X_Y_ALIGN * YUV422P_X_Y_ALIGN
175 enum pxa_camera_active_dma {
181 /* descriptor needed for the PXA DMA engine */
184 struct pxa_dma_desc *sg_cpu;
189 /* buffer for one video frame */
191 /* common v4l buffer stuff -- must be first */
192 struct videobuf_buffer vb;
194 const struct soc_camera_data_format *fmt;
196 /* our descriptor lists for Y, U and V channels */
197 struct pxa_cam_dma dmas[3];
201 enum pxa_camera_active_dma active_dma;
204 struct pxa_camera_dev {
206 /* PXA27x is only supposed to handle one camera on its Quick Capture
207 * interface. If anyone ever builds hardware to enable more than
208 * one camera, they will have to modify this driver too */
209 struct soc_camera_device *icd;
216 unsigned int dma_chans[3];
218 struct pxacamera_platform_data *pdata;
219 struct resource *res;
220 unsigned long platform_flags;
225 struct list_head capture;
229 struct pxa_buffer *active;
230 struct pxa_dma_desc *sg_tail[3];
235 static const char *pxa_cam_driver_description = "PXA_Camera";
237 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
240 * Videobuf operations
242 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
245 struct soc_camera_device *icd = vq->priv_data;
247 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
249 *size = roundup(icd->width * icd->height *
250 ((icd->current_fmt->depth + 7) >> 3), 8);
254 while (*size * *count > vid_limit * 1024 * 1024)
260 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
262 struct soc_camera_device *icd = vq->priv_data;
263 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
264 struct pxa_camera_dev *pcdev = ici->priv;
265 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
268 BUG_ON(in_interrupt());
270 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
271 &buf->vb, buf->vb.baddr, buf->vb.bsize);
273 /* This waits until this buffer is out of danger, i.e., until it is no
274 * longer in STATE_QUEUED or STATE_ACTIVE */
275 videobuf_waiton(&buf->vb, 0, 0);
276 videobuf_dma_unmap(vq, dma);
277 videobuf_dma_free(dma);
279 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
280 if (buf->dmas[i].sg_cpu)
281 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
283 buf->dmas[i].sg_dma);
284 buf->dmas[i].sg_cpu = NULL;
287 buf->vb.state = VIDEOBUF_NEEDS_INIT;
290 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
291 int sg_first_ofs, int size)
293 int i, offset, dma_len, xfer_len;
294 struct scatterlist *sg;
296 offset = sg_first_ofs;
297 for_each_sg(sglist, sg, sglen, i) {
298 dma_len = sg_dma_len(sg);
300 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
301 xfer_len = roundup(min(dma_len - offset, size), 8);
303 size = max(0, size - xfer_len);
314 * pxa_init_dma_channel - init dma descriptors
315 * @pcdev: pxa camera device
316 * @buf: pxa buffer to find pxa dma channel
317 * @dma: dma video buffer
318 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
319 * @cibr: camera Receive Buffer Register
320 * @size: bytes to transfer
321 * @sg_first: first element of sg_list
322 * @sg_first_ofs: offset in first element of sg_list
324 * Prepares the pxa dma descriptors to transfer one camera channel.
325 * Beware sg_first and sg_first_ofs are both input and output parameters.
327 * Returns 0 or -ENOMEM if no coherent memory is available
329 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
330 struct pxa_buffer *buf,
331 struct videobuf_dmabuf *dma, int channel,
333 struct scatterlist **sg_first, int *sg_first_ofs)
335 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
336 struct scatterlist *sg;
337 int i, offset, sglen;
338 int dma_len = 0, xfer_len = 0;
341 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
342 pxa_dma->sg_cpu, pxa_dma->sg_dma);
344 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
345 *sg_first_ofs, size);
347 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
348 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
349 &pxa_dma->sg_dma, GFP_KERNEL);
350 if (!pxa_dma->sg_cpu)
353 pxa_dma->sglen = sglen;
354 offset = *sg_first_ofs;
356 dev_dbg(pcdev->dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
357 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
360 for_each_sg(*sg_first, sg, sglen, i) {
361 dma_len = sg_dma_len(sg);
363 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
364 xfer_len = roundup(min(dma_len - offset, size), 8);
366 size = max(0, size - xfer_len);
368 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
369 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
370 pxa_dma->sg_cpu[i].dcmd =
371 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
372 pxa_dma->sg_cpu[i].ddadr =
373 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
375 dev_vdbg(pcdev->dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
376 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
377 sg_dma_address(sg) + offset, xfer_len);
384 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
385 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
388 * Handle 1 special case :
389 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
390 * to dma_len (end on PAGE boundary). In this case, the sg element
391 * for next plane should be the next after the last used to store the
392 * last scatter gather RAM page
394 if (xfer_len >= dma_len) {
395 *sg_first_ofs = xfer_len - dma_len;
396 *sg_first = sg_next(sg);
398 *sg_first_ofs = xfer_len;
405 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
406 struct videobuf_buffer *vb, enum v4l2_field field)
408 struct soc_camera_device *icd = vq->priv_data;
409 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
410 struct pxa_camera_dev *pcdev = ici->priv;
411 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
413 int size_y, size_u = 0, size_v = 0;
415 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
416 vb, vb->baddr, vb->bsize);
418 /* Added list head initialization on alloc */
419 WARN_ON(!list_empty(&vb->queue));
422 /* This can be useful if you want to see if we actually fill
423 * the buffer with something */
424 memset((void *)vb->baddr, 0xaa, vb->bsize);
427 BUG_ON(NULL == icd->current_fmt);
429 /* I think, in buf_prepare you only have to protect global data,
430 * the actual buffer is yours */
433 if (buf->fmt != icd->current_fmt ||
434 vb->width != icd->width ||
435 vb->height != icd->height ||
436 vb->field != field) {
437 buf->fmt = icd->current_fmt;
438 vb->width = icd->width;
439 vb->height = icd->height;
441 vb->state = VIDEOBUF_NEEDS_INIT;
444 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
445 if (0 != vb->baddr && vb->bsize < vb->size) {
450 if (vb->state == VIDEOBUF_NEEDS_INIT) {
453 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
454 struct scatterlist *sg;
456 ret = videobuf_iolock(vq, vb, NULL);
460 if (pcdev->channels == 3) {
462 size_u = size_v = size / 4;
469 /* init DMA for Y channel */
470 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
474 "DMA initialization for Y/RGB failed\n");
478 /* init DMA for U channel */
480 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
481 size_u, &sg, &next_ofs);
484 "DMA initialization for U failed\n");
488 /* init DMA for V channel */
490 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
491 size_v, &sg, &next_ofs);
494 "DMA initialization for V failed\n");
498 vb->state = VIDEOBUF_PREPARED;
502 buf->active_dma = DMA_Y;
503 if (pcdev->channels == 3)
504 buf->active_dma |= DMA_U | DMA_V;
509 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
510 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
512 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
513 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
515 free_buffer(vq, buf);
521 static void pxa_videobuf_queue(struct videobuf_queue *vq,
522 struct videobuf_buffer *vb)
524 struct soc_camera_device *icd = vq->priv_data;
525 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
526 struct pxa_camera_dev *pcdev = ici->priv;
527 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
528 struct pxa_buffer *active;
532 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
533 vb, vb->baddr, vb->bsize);
534 spin_lock_irqsave(&pcdev->lock, flags);
536 list_add_tail(&vb->queue, &pcdev->capture);
538 vb->state = VIDEOBUF_ACTIVE;
539 active = pcdev->active;
542 unsigned long cifr, cicr0;
544 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
545 __raw_writel(cifr, pcdev->base + CIFR);
547 for (i = 0; i < pcdev->channels; i++) {
548 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
549 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
550 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
555 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
556 __raw_writel(cicr0, pcdev->base + CICR0);
558 struct pxa_cam_dma *buf_dma;
559 struct pxa_cam_dma *act_dma;
562 for (i = 0; i < pcdev->channels; i++) {
563 buf_dma = &buf->dmas[i];
564 act_dma = &active->dmas[i];
565 nents = buf_dma->sglen;
567 /* Stop DMA engine */
568 DCSR(pcdev->dma_chans[i]) = 0;
570 /* Add the descriptors we just initialized to
571 the currently running chain */
572 pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
573 pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
575 /* Setup a dummy descriptor with the DMA engines current
578 buf_dma->sg_cpu[nents].dsadr =
579 pcdev->res->start + 0x28 + i*8; /* CIBRx */
580 buf_dma->sg_cpu[nents].dtadr =
581 DTADR(pcdev->dma_chans[i]);
582 buf_dma->sg_cpu[nents].dcmd =
583 DCMD(pcdev->dma_chans[i]);
585 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
586 /* The DMA engine is on the last
587 descriptor, set the next descriptors
588 address to the descriptors we just
590 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
592 buf_dma->sg_cpu[nents].ddadr =
593 DDADR(pcdev->dma_chans[i]);
596 /* The next descriptor is the dummy descriptor */
597 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
598 sizeof(struct pxa_dma_desc);
600 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
604 spin_unlock_irqrestore(&pcdev->lock, flags);
607 static void pxa_videobuf_release(struct videobuf_queue *vq,
608 struct videobuf_buffer *vb)
610 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
612 struct soc_camera_device *icd = vq->priv_data;
614 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
615 vb, vb->baddr, vb->bsize);
618 case VIDEOBUF_ACTIVE:
619 dev_dbg(&icd->dev, "%s (active)\n", __func__);
621 case VIDEOBUF_QUEUED:
622 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
624 case VIDEOBUF_PREPARED:
625 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
628 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
633 free_buffer(vq, buf);
636 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
637 struct videobuf_buffer *vb,
638 struct pxa_buffer *buf)
642 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
643 list_del_init(&vb->queue);
644 vb->state = VIDEOBUF_DONE;
645 do_gettimeofday(&vb->ts);
649 if (list_empty(&pcdev->capture)) {
650 pcdev->active = NULL;
651 DCSR(pcdev->dma_chans[0]) = 0;
652 DCSR(pcdev->dma_chans[1]) = 0;
653 DCSR(pcdev->dma_chans[2]) = 0;
655 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
656 __raw_writel(cicr0, pcdev->base + CICR0);
660 pcdev->active = list_entry(pcdev->capture.next,
661 struct pxa_buffer, vb.queue);
664 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
665 enum pxa_camera_active_dma act_dma)
667 struct pxa_buffer *buf;
669 u32 status, camera_status, overrun;
670 struct videobuf_buffer *vb;
671 unsigned long cifr, cicr0;
673 spin_lock_irqsave(&pcdev->lock, flags);
675 status = DCSR(channel);
676 DCSR(channel) = status | DCSR_ENDINTR;
678 if (status & DCSR_BUSERR) {
679 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
683 if (!(status & DCSR_ENDINTR)) {
684 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
685 "status: 0x%08x\n", status);
689 if (!pcdev->active) {
690 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
694 camera_status = __raw_readl(pcdev->base + CISR);
695 overrun = CISR_IFO_0;
696 if (pcdev->channels == 3)
697 overrun |= CISR_IFO_1 | CISR_IFO_2;
698 if (camera_status & overrun) {
699 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
700 /* Stop the Capture Interface */
701 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
702 __raw_writel(cicr0, pcdev->base + CICR0);
706 /* Reset the FIFOs */
707 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
708 __raw_writel(cifr, pcdev->base + CIFR);
709 /* Enable End-Of-Frame Interrupt */
710 cicr0 &= ~CICR0_EOFM;
711 __raw_writel(cicr0, pcdev->base + CICR0);
712 /* Restart the Capture Interface */
713 __raw_writel(cicr0 | CICR0_ENB, pcdev->base + CICR0);
717 vb = &pcdev->active->vb;
718 buf = container_of(vb, struct pxa_buffer, vb);
719 WARN_ON(buf->inwork || list_empty(&vb->queue));
720 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
721 vb, vb->baddr, vb->bsize);
723 buf->active_dma &= ~act_dma;
724 if (!buf->active_dma)
725 pxa_camera_wakeup(pcdev, vb, buf);
728 spin_unlock_irqrestore(&pcdev->lock, flags);
731 static void pxa_camera_dma_irq_y(int channel, void *data)
733 struct pxa_camera_dev *pcdev = data;
734 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
737 static void pxa_camera_dma_irq_u(int channel, void *data)
739 struct pxa_camera_dev *pcdev = data;
740 pxa_camera_dma_irq(channel, pcdev, DMA_U);
743 static void pxa_camera_dma_irq_v(int channel, void *data)
745 struct pxa_camera_dev *pcdev = data;
746 pxa_camera_dma_irq(channel, pcdev, DMA_V);
749 static struct videobuf_queue_ops pxa_videobuf_ops = {
750 .buf_setup = pxa_videobuf_setup,
751 .buf_prepare = pxa_videobuf_prepare,
752 .buf_queue = pxa_videobuf_queue,
753 .buf_release = pxa_videobuf_release,
756 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
757 struct soc_camera_device *icd)
759 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
760 struct pxa_camera_dev *pcdev = ici->priv;
762 /* We must pass NULL as dev pointer, then all pci_* dma operations
763 * transform to normal dma_* ones. */
764 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
765 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
766 sizeof(struct pxa_buffer), icd);
769 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
771 unsigned long mclk = pcdev->mclk;
773 unsigned long lcdclk;
775 lcdclk = clk_get_rate(pcdev->clk);
776 pcdev->ciclk = lcdclk;
778 /* mclk <= ciclk / 4 (27.4.2) */
779 if (mclk > lcdclk / 4) {
781 dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
784 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
785 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
787 /* If we're not supplying MCLK, leave it at 0 */
788 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
789 pcdev->mclk = lcdclk / (2 * (div + 1));
791 dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
792 "divisor %u\n", lcdclk, mclk, div);
797 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
800 /* We want a timeout > 1 pixel time, not ">=" */
801 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
803 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
806 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
808 struct pxacamera_platform_data *pdata = pcdev->pdata;
811 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
814 if (pdata && pdata->init) {
815 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
816 pdata->init(pcdev->dev);
819 /* disable all interrupts */
820 __raw_writel(0x3ff, pcdev->base + CICR0);
822 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
823 cicr4 |= CICR4_PCLK_EN;
824 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
825 cicr4 |= CICR4_MCLK_EN;
826 if (pcdev->platform_flags & PXA_CAMERA_PCP)
828 if (pcdev->platform_flags & PXA_CAMERA_HSP)
830 if (pcdev->platform_flags & PXA_CAMERA_VSP)
833 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
835 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
836 /* Initialise the timeout under the assumption pclk = mclk */
837 recalculate_fifo_timeout(pcdev, pcdev->mclk);
839 /* "Safe default" - 13MHz */
840 recalculate_fifo_timeout(pcdev, 13000000);
842 clk_enable(pcdev->clk);
845 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
847 clk_disable(pcdev->clk);
850 static irqreturn_t pxa_camera_irq(int irq, void *data)
852 struct pxa_camera_dev *pcdev = data;
853 unsigned long status, cicr0;
855 status = __raw_readl(pcdev->base + CISR);
856 dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
861 __raw_writel(status, pcdev->base + CISR);
863 if (status & CISR_EOF) {
865 for (i = 0; i < pcdev->channels; i++) {
866 DDADR(pcdev->dma_chans[i]) =
867 pcdev->active->dmas[i].sg_dma;
868 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
870 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
871 __raw_writel(cicr0, pcdev->base + CICR0);
878 * The following two functions absolutely depend on the fact, that
879 * there can be only one camera on PXA quick capture interface
880 * Called with .video_lock held
882 static int pxa_camera_add_device(struct soc_camera_device *icd)
884 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
885 struct pxa_camera_dev *pcdev = ici->priv;
893 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
896 pxa_camera_activate(pcdev);
897 ret = icd->ops->init(icd);
906 /* Called with .video_lock held */
907 static void pxa_camera_remove_device(struct soc_camera_device *icd)
909 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
910 struct pxa_camera_dev *pcdev = ici->priv;
912 BUG_ON(icd != pcdev->icd);
914 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
917 /* disable capture, disable interrupts */
918 __raw_writel(0x3ff, pcdev->base + CICR0);
920 /* Stop DMA engine */
921 DCSR(pcdev->dma_chans[0]) = 0;
922 DCSR(pcdev->dma_chans[1]) = 0;
923 DCSR(pcdev->dma_chans[2]) = 0;
925 icd->ops->release(icd);
927 pxa_camera_deactivate(pcdev);
932 static int test_platform_param(struct pxa_camera_dev *pcdev,
933 unsigned char buswidth, unsigned long *flags)
936 * Platform specified synchronization and pixel clock polarities are
937 * only a recommendation and are only used during probing. The PXA270
938 * quick capture interface supports both.
940 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
941 SOCAM_MASTER : SOCAM_SLAVE) |
942 SOCAM_HSYNC_ACTIVE_HIGH |
943 SOCAM_HSYNC_ACTIVE_LOW |
944 SOCAM_VSYNC_ACTIVE_HIGH |
945 SOCAM_VSYNC_ACTIVE_LOW |
946 SOCAM_DATA_ACTIVE_HIGH |
947 SOCAM_PCLK_SAMPLE_RISING |
948 SOCAM_PCLK_SAMPLE_FALLING;
950 /* If requested data width is supported by the platform, use it */
953 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
955 *flags |= SOCAM_DATAWIDTH_10;
958 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
960 *flags |= SOCAM_DATAWIDTH_9;
963 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
965 *flags |= SOCAM_DATAWIDTH_8;
974 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
976 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
977 struct pxa_camera_dev *pcdev = ici->priv;
978 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
979 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
980 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
985 camera_flags = icd->ops->query_bus_param(icd);
987 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
993 /* Make choises, based on platform preferences */
994 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
995 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
996 if (pcdev->platform_flags & PXA_CAMERA_HSP)
997 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
999 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1002 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1003 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1004 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1005 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1007 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1010 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1011 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1012 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1013 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1015 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1018 ret = icd->ops->set_bus_param(icd, common_flags);
1022 /* Datawidth is now guaranteed to be equal to one of the three values.
1023 * We fix bit-per-pixel equal to data-width... */
1024 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1025 case SOCAM_DATAWIDTH_10:
1029 case SOCAM_DATAWIDTH_9:
1034 /* Actually it can only be 8 now,
1035 * default is just to silence compiler warnings */
1036 case SOCAM_DATAWIDTH_8:
1041 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1042 cicr4 |= CICR4_PCLK_EN;
1043 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1044 cicr4 |= CICR4_MCLK_EN;
1045 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1047 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1049 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1052 cicr0 = __raw_readl(pcdev->base + CICR0);
1053 if (cicr0 & CICR0_ENB)
1054 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1056 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1059 case V4L2_PIX_FMT_YUV422P:
1060 pcdev->channels = 3;
1061 cicr1 |= CICR1_YCBCR_F;
1063 * Normally, pxa bus wants as input UYVY format. We allow all
1064 * reorderings of the YUV422 format, as no processing is done,
1065 * and the YUV stream is just passed through without any
1066 * transformation. Note that UYVY is the only format that
1067 * should be used if pxa framebuffer Overlay2 is used.
1069 case V4L2_PIX_FMT_UYVY:
1070 case V4L2_PIX_FMT_VYUY:
1071 case V4L2_PIX_FMT_YUYV:
1072 case V4L2_PIX_FMT_YVYU:
1073 cicr1 |= CICR1_COLOR_SP_VAL(2);
1075 case V4L2_PIX_FMT_RGB555:
1076 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1077 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1079 case V4L2_PIX_FMT_RGB565:
1080 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1085 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1086 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1087 cicr4 |= pcdev->mclk_divisor;
1089 __raw_writel(cicr1, pcdev->base + CICR1);
1090 __raw_writel(cicr2, pcdev->base + CICR2);
1091 __raw_writel(cicr3, pcdev->base + CICR3);
1092 __raw_writel(cicr4, pcdev->base + CICR4);
1094 /* CIF interrupts are not used, only DMA */
1095 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1096 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1097 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1098 __raw_writel(cicr0, pcdev->base + CICR0);
1103 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1104 unsigned char buswidth)
1106 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1107 struct pxa_camera_dev *pcdev = ici->priv;
1108 unsigned long bus_flags, camera_flags;
1109 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1114 camera_flags = icd->ops->query_bus_param(icd);
1116 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1119 static const struct soc_camera_data_format pxa_camera_formats[] = {
1121 .name = "Planar YUV422 16 bit",
1123 .fourcc = V4L2_PIX_FMT_YUV422P,
1124 .colorspace = V4L2_COLORSPACE_JPEG,
1128 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1130 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1131 struct pxa_camera_dev *pcdev = ici->priv;
1135 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1137 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1139 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1144 static int required_buswidth(const struct soc_camera_data_format *fmt)
1146 switch (fmt->fourcc) {
1147 case V4L2_PIX_FMT_UYVY:
1148 case V4L2_PIX_FMT_VYUY:
1149 case V4L2_PIX_FMT_YUYV:
1150 case V4L2_PIX_FMT_YVYU:
1151 case V4L2_PIX_FMT_RGB565:
1152 case V4L2_PIX_FMT_RGB555:
1159 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1160 struct soc_camera_format_xlate *xlate)
1162 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1163 int formats = 0, buswidth, ret;
1165 buswidth = required_buswidth(icd->formats + idx);
1167 if (!buswidth_supported(icd, buswidth))
1170 ret = pxa_camera_try_bus_param(icd, buswidth);
1174 switch (icd->formats[idx].fourcc) {
1175 case V4L2_PIX_FMT_UYVY:
1178 xlate->host_fmt = &pxa_camera_formats[0];
1179 xlate->cam_fmt = icd->formats + idx;
1180 xlate->buswidth = buswidth;
1182 dev_dbg(&ici->dev, "Providing format %s using %s\n",
1183 pxa_camera_formats[0].name,
1184 icd->formats[idx].name);
1186 case V4L2_PIX_FMT_VYUY:
1187 case V4L2_PIX_FMT_YUYV:
1188 case V4L2_PIX_FMT_YVYU:
1189 case V4L2_PIX_FMT_RGB565:
1190 case V4L2_PIX_FMT_RGB555:
1193 xlate->host_fmt = icd->formats + idx;
1194 xlate->cam_fmt = icd->formats + idx;
1195 xlate->buswidth = buswidth;
1197 dev_dbg(&ici->dev, "Providing format %s packed\n",
1198 icd->formats[idx].name);
1202 /* Generic pass-through */
1205 xlate->host_fmt = icd->formats + idx;
1206 xlate->cam_fmt = icd->formats + idx;
1207 xlate->buswidth = icd->formats[idx].depth;
1210 "Providing format %s in pass-through mode\n",
1211 icd->formats[idx].name);
1218 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1219 struct v4l2_rect *rect)
1221 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1222 struct pxa_camera_dev *pcdev = ici->priv;
1223 struct soc_camera_sense sense = {
1224 .master_clock = pcdev->mclk,
1225 .pixel_clock_max = pcdev->ciclk / 4,
1229 /* If PCLK is used to latch data from the sensor, check sense */
1230 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1231 icd->sense = &sense;
1233 ret = icd->ops->set_crop(icd, rect);
1238 dev_warn(&ici->dev, "Failed to crop to %ux%u@%u:%u\n",
1239 rect->width, rect->height, rect->left, rect->top);
1240 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1241 if (sense.pixel_clock > sense.pixel_clock_max) {
1243 "pixel clock %lu set by the camera too high!",
1247 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1253 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1254 struct v4l2_format *f)
1256 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1257 struct pxa_camera_dev *pcdev = ici->priv;
1258 const struct soc_camera_data_format *cam_fmt = NULL;
1259 const struct soc_camera_format_xlate *xlate = NULL;
1260 struct soc_camera_sense sense = {
1261 .master_clock = pcdev->mclk,
1262 .pixel_clock_max = pcdev->ciclk / 4,
1264 struct v4l2_pix_format *pix = &f->fmt.pix;
1265 struct v4l2_format cam_f = *f;
1268 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1270 dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat);
1274 cam_fmt = xlate->cam_fmt;
1276 /* If PCLK is used to latch data from the sensor, check sense */
1277 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1278 icd->sense = &sense;
1280 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1281 ret = icd->ops->set_fmt(icd, &cam_f);
1286 dev_warn(&ici->dev, "Failed to configure for format %x\n",
1288 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1289 if (sense.pixel_clock > sense.pixel_clock_max) {
1291 "pixel clock %lu set by the camera too high!",
1295 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1299 icd->buswidth = xlate->buswidth;
1300 icd->current_fmt = xlate->host_fmt;
1306 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1307 struct v4l2_format *f)
1309 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1310 const struct soc_camera_format_xlate *xlate;
1311 struct v4l2_pix_format *pix = &f->fmt.pix;
1312 __u32 pixfmt = pix->pixelformat;
1313 enum v4l2_field field;
1316 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1318 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1322 /* limit to pxa hardware capabilities */
1323 if (pix->height < 32)
1325 if (pix->height > 2048)
1327 if (pix->width < 48)
1329 if (pix->width > 2048)
1331 pix->width &= ~0x01;
1334 * YUV422P planar format requires images size to be a 16 bytes
1335 * multiple. If not, zeros will be inserted between Y and U planes, and
1336 * U and V planes, and YUV422P standard would be violated.
1338 if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
1339 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1340 pix->height = ALIGN(pix->height, YUV422P_X_Y_ALIGN);
1341 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1342 pix->width = ALIGN(pix->width, YUV422P_X_Y_ALIGN);
1345 pix->bytesperline = pix->width *
1346 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1347 pix->sizeimage = pix->height * pix->bytesperline;
1349 /* camera has to see its format, but the user the original one */
1350 pix->pixelformat = xlate->cam_fmt->fourcc;
1351 /* limit to sensor capabilities */
1352 ret = icd->ops->try_fmt(icd, f);
1353 pix->pixelformat = xlate->host_fmt->fourcc;
1357 if (field == V4L2_FIELD_ANY) {
1358 pix->field = V4L2_FIELD_NONE;
1359 } else if (field != V4L2_FIELD_NONE) {
1360 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1367 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1368 struct v4l2_requestbuffers *p)
1372 /* This is for locking debugging only. I removed spinlocks and now I
1373 * check whether .prepare is ever called on a linked buffer, or whether
1374 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1375 * it hadn't triggered */
1376 for (i = 0; i < p->count; i++) {
1377 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1378 struct pxa_buffer, vb);
1380 INIT_LIST_HEAD(&buf->vb.queue);
1386 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1388 struct soc_camera_file *icf = file->private_data;
1389 struct pxa_buffer *buf;
1391 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1394 poll_wait(file, &buf->vb.done, pt);
1396 if (buf->vb.state == VIDEOBUF_DONE ||
1397 buf->vb.state == VIDEOBUF_ERROR)
1398 return POLLIN|POLLRDNORM;
1403 static int pxa_camera_querycap(struct soc_camera_host *ici,
1404 struct v4l2_capability *cap)
1406 /* cap->name is set by the firendly caller:-> */
1407 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1408 cap->version = PXA_CAM_VERSION_CODE;
1409 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1414 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1416 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1417 struct pxa_camera_dev *pcdev = ici->priv;
1420 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1421 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1422 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1423 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1424 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1426 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1427 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1432 static int pxa_camera_resume(struct soc_camera_device *icd)
1434 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1435 struct pxa_camera_dev *pcdev = ici->priv;
1438 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1439 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1440 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1442 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1443 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1444 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1445 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1446 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1448 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1449 ret = pcdev->icd->ops->resume(pcdev->icd);
1451 /* Restart frame capture if active buffer exists */
1452 if (!ret && pcdev->active) {
1453 unsigned long cifr, cicr0;
1455 /* Reset the FIFOs */
1456 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1457 __raw_writel(cifr, pcdev->base + CIFR);
1459 cicr0 = __raw_readl(pcdev->base + CICR0);
1460 cicr0 &= ~CICR0_EOFM; /* Enable End-Of-Frame Interrupt */
1461 cicr0 |= CICR0_ENB; /* Restart the Capture Interface */
1462 __raw_writel(cicr0, pcdev->base + CICR0);
1468 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1469 .owner = THIS_MODULE,
1470 .add = pxa_camera_add_device,
1471 .remove = pxa_camera_remove_device,
1472 .suspend = pxa_camera_suspend,
1473 .resume = pxa_camera_resume,
1474 .set_crop = pxa_camera_set_crop,
1475 .get_formats = pxa_camera_get_formats,
1476 .set_fmt = pxa_camera_set_fmt,
1477 .try_fmt = pxa_camera_try_fmt,
1478 .init_videobuf = pxa_camera_init_videobuf,
1479 .reqbufs = pxa_camera_reqbufs,
1480 .poll = pxa_camera_poll,
1481 .querycap = pxa_camera_querycap,
1482 .set_bus_param = pxa_camera_set_bus_param,
1485 /* Should be allocated dynamically too, but we have only one. */
1486 static struct soc_camera_host pxa_soc_camera_host = {
1487 .drv_name = PXA_CAM_DRV_NAME,
1488 .ops = &pxa_soc_camera_host_ops,
1491 static int pxa_camera_probe(struct platform_device *pdev)
1493 struct pxa_camera_dev *pcdev;
1494 struct resource *res;
1499 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1500 irq = platform_get_irq(pdev, 0);
1501 if (!res || irq < 0) {
1506 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1508 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1513 pcdev->clk = clk_get(&pdev->dev, NULL);
1514 if (IS_ERR(pcdev->clk)) {
1515 err = PTR_ERR(pcdev->clk);
1519 dev_set_drvdata(&pdev->dev, pcdev);
1522 pcdev->pdata = pdev->dev.platform_data;
1523 pcdev->platform_flags = pcdev->pdata->flags;
1524 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1525 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1526 /* Platform hasn't set available data widths. This is bad.
1527 * Warn and use a default. */
1528 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1529 "data widths, using default 10 bit\n");
1530 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1532 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1534 dev_warn(&pdev->dev,
1535 "mclk == 0! Please, fix your platform data. "
1536 "Using default 20MHz\n");
1537 pcdev->mclk = 20000000;
1540 pcdev->dev = &pdev->dev;
1541 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1543 INIT_LIST_HEAD(&pcdev->capture);
1544 spin_lock_init(&pcdev->lock);
1547 * Request the regions.
1549 if (!request_mem_region(res->start, res->end - res->start + 1,
1550 PXA_CAM_DRV_NAME)) {
1555 base = ioremap(res->start, res->end - res->start + 1);
1564 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1565 pxa_camera_dma_irq_y, pcdev);
1567 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1570 pcdev->dma_chans[0] = err;
1571 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1573 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1574 pxa_camera_dma_irq_u, pcdev);
1576 dev_err(pcdev->dev, "Can't request DMA for U\n");
1577 goto exit_free_dma_y;
1579 pcdev->dma_chans[1] = err;
1580 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1582 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1583 pxa_camera_dma_irq_v, pcdev);
1585 dev_err(pcdev->dev, "Can't request DMA for V\n");
1586 goto exit_free_dma_u;
1588 pcdev->dma_chans[2] = err;
1589 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1591 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1592 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1593 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1596 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1599 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1603 pxa_soc_camera_host.priv = pcdev;
1604 pxa_soc_camera_host.dev.parent = &pdev->dev;
1605 pxa_soc_camera_host.nr = pdev->id;
1606 err = soc_camera_host_register(&pxa_soc_camera_host);
1613 free_irq(pcdev->irq, pcdev);
1615 pxa_free_dma(pcdev->dma_chans[2]);
1617 pxa_free_dma(pcdev->dma_chans[1]);
1619 pxa_free_dma(pcdev->dma_chans[0]);
1623 release_mem_region(res->start, res->end - res->start + 1);
1625 clk_put(pcdev->clk);
1632 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1634 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1635 struct resource *res;
1637 clk_put(pcdev->clk);
1639 pxa_free_dma(pcdev->dma_chans[0]);
1640 pxa_free_dma(pcdev->dma_chans[1]);
1641 pxa_free_dma(pcdev->dma_chans[2]);
1642 free_irq(pcdev->irq, pcdev);
1644 soc_camera_host_unregister(&pxa_soc_camera_host);
1646 iounmap(pcdev->base);
1649 release_mem_region(res->start, res->end - res->start + 1);
1653 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1658 static struct platform_driver pxa_camera_driver = {
1660 .name = PXA_CAM_DRV_NAME,
1662 .probe = pxa_camera_probe,
1663 .remove = __exit_p(pxa_camera_remove),
1667 static int __devinit pxa_camera_init(void)
1669 return platform_driver_register(&pxa_camera_driver);
1672 static void __exit pxa_camera_exit(void)
1674 platform_driver_unregister(&pxa_camera_driver);
1677 module_init(pxa_camera_init);
1678 module_exit(pxa_camera_exit);
1680 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1681 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1682 MODULE_LICENSE("GPL");