4 * Compaq ASIC3 support.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
19 #include <linux/version.h>
20 #include <linux/kernel.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h>
27 #include <linux/mfd/asic3.h>
30 void __iomem *mapping;
31 unsigned int bus_shift;
33 unsigned int irq_base;
36 struct gpio_chip gpio;
40 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
42 static inline void asic3_write_register(struct asic3 *asic,
43 unsigned int reg, u32 value)
45 iowrite16(value, asic->mapping +
46 (reg >> asic->bus_shift));
49 static inline u32 asic3_read_register(struct asic3 *asic,
52 return ioread16(asic->mapping +
53 (reg >> asic->bus_shift));
57 #define MAX_ASIC_ISR_LOOPS 20
58 #define ASIC3_GPIO_Base_INCR \
59 (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)
61 static void asic3_irq_flip_edge(struct asic3 *asic,
67 spin_lock_irqsave(&asic->lock, flags);
68 edge = asic3_read_register(asic,
69 base + ASIC3_GPIO_EdgeTrigger);
71 asic3_write_register(asic,
72 base + ASIC3_GPIO_EdgeTrigger, edge);
73 spin_unlock_irqrestore(&asic->lock, flags);
76 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
84 asic = desc->handler_data;
86 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
90 spin_lock_irqsave(&asic->lock, flags);
91 status = asic3_read_register(asic,
92 ASIC3_OFFSET(INTR, PIntStat));
93 spin_unlock_irqrestore(&asic->lock, flags);
95 /* Check all ten register bits */
96 if ((status & 0x3ff) == 0)
99 /* Handle GPIO IRQs */
100 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
101 if (status & (1 << bank)) {
102 unsigned long base, istat;
104 base = ASIC3_GPIO_A_Base
105 + bank * ASIC3_GPIO_Base_INCR;
107 spin_lock_irqsave(&asic->lock, flags);
108 istat = asic3_read_register(asic,
110 ASIC3_GPIO_IntStatus);
111 /* Clearing IntStatus */
112 asic3_write_register(asic,
114 ASIC3_GPIO_IntStatus, 0);
115 spin_unlock_irqrestore(&asic->lock, flags);
117 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
124 irqnr = asic->irq_base +
125 (ASIC3_GPIOS_PER_BANK * bank)
127 desc = irq_desc + irqnr;
128 desc->handle_irq(irqnr, desc);
129 if (asic->irq_bothedge[bank] & bit)
130 asic3_irq_flip_edge(asic, base,
136 /* Handle remaining IRQs in the status register */
137 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
138 /* They start at bit 4 and go up */
139 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
140 desc = irq_desc + + i;
141 desc->handle_irq(asic->irq_base + i,
147 if (iter >= MAX_ASIC_ISR_LOOPS)
148 printk(KERN_ERR "%s: interrupt processing overrun\n",
152 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
156 n = (irq - asic->irq_base) >> 4;
158 return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base));
161 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
163 return (irq - asic->irq_base) & 0xf;
166 static void asic3_mask_gpio_irq(unsigned int irq)
168 struct asic3 *asic = get_irq_chip_data(irq);
169 u32 val, bank, index;
172 bank = asic3_irq_to_bank(asic, irq);
173 index = asic3_irq_to_index(asic, irq);
175 spin_lock_irqsave(&asic->lock, flags);
176 val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
178 asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
179 spin_unlock_irqrestore(&asic->lock, flags);
182 static void asic3_mask_irq(unsigned int irq)
184 struct asic3 *asic = get_irq_chip_data(irq);
188 spin_lock_irqsave(&asic->lock, flags);
189 regval = asic3_read_register(asic,
193 regval &= ~(ASIC3_INTMASK_MASK0 <<
194 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
196 asic3_write_register(asic,
200 spin_unlock_irqrestore(&asic->lock, flags);
203 static void asic3_unmask_gpio_irq(unsigned int irq)
205 struct asic3 *asic = get_irq_chip_data(irq);
206 u32 val, bank, index;
209 bank = asic3_irq_to_bank(asic, irq);
210 index = asic3_irq_to_index(asic, irq);
212 spin_lock_irqsave(&asic->lock, flags);
213 val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
214 val &= ~(1 << index);
215 asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
216 spin_unlock_irqrestore(&asic->lock, flags);
219 static void asic3_unmask_irq(unsigned int irq)
221 struct asic3 *asic = get_irq_chip_data(irq);
225 spin_lock_irqsave(&asic->lock, flags);
226 regval = asic3_read_register(asic,
230 regval |= (ASIC3_INTMASK_MASK0 <<
231 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
233 asic3_write_register(asic,
237 spin_unlock_irqrestore(&asic->lock, flags);
240 static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
242 struct asic3 *asic = get_irq_chip_data(irq);
244 u16 trigger, level, edge, bit;
247 bank = asic3_irq_to_bank(asic, irq);
248 index = asic3_irq_to_index(asic, irq);
251 spin_lock_irqsave(&asic->lock, flags);
252 level = asic3_read_register(asic,
253 bank + ASIC3_GPIO_LevelTrigger);
254 edge = asic3_read_register(asic,
255 bank + ASIC3_GPIO_EdgeTrigger);
256 trigger = asic3_read_register(asic,
257 bank + ASIC3_GPIO_TriggerType);
258 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
260 if (type == IRQT_RISING) {
263 } else if (type == IRQT_FALLING) {
266 } else if (type == IRQT_BOTHEDGE) {
268 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
272 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
273 } else if (type == IRQT_LOW) {
276 } else if (type == IRQT_HIGH) {
281 * if type == IRQT_NOEDGE, we should mask interrupts, but
282 * be careful to not unmask them if mask was also called.
283 * Probably need internal state for mask.
285 printk(KERN_NOTICE "asic3: irq type not changed.\n");
287 asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger,
289 asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger,
291 asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType,
293 spin_unlock_irqrestore(&asic->lock, flags);
297 static struct irq_chip asic3_gpio_irq_chip = {
298 .name = "ASIC3-GPIO",
299 .ack = asic3_mask_gpio_irq,
300 .mask = asic3_mask_gpio_irq,
301 .unmask = asic3_unmask_gpio_irq,
302 .set_type = asic3_gpio_irq_type,
305 static struct irq_chip asic3_irq_chip = {
307 .ack = asic3_mask_irq,
308 .mask = asic3_mask_irq,
309 .unmask = asic3_unmask_irq,
312 static int asic3_irq_probe(struct platform_device *pdev)
314 struct asic3 *asic = platform_get_drvdata(pdev);
315 unsigned long clksel = 0;
316 unsigned int irq, irq_base;
318 asic->irq_nr = platform_get_irq(pdev, 0);
319 if (asic->irq_nr < 0)
322 /* turn on clock to IRQ controller */
323 clksel |= CLOCK_SEL_CX;
324 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
327 irq_base = asic->irq_base;
329 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
330 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
331 set_irq_chip(irq, &asic3_gpio_irq_chip);
333 set_irq_chip(irq, &asic3_irq_chip);
335 set_irq_chip_data(irq, asic);
336 set_irq_handler(irq, handle_level_irq);
337 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
340 asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask),
341 ASIC3_INTMASK_GINTMASK);
343 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
344 set_irq_type(asic->irq_nr, IRQT_RISING);
345 set_irq_data(asic->irq_nr, asic);
350 static void asic3_irq_remove(struct platform_device *pdev)
352 struct asic3 *asic = platform_get_drvdata(pdev);
353 unsigned int irq, irq_base;
355 irq_base = asic->irq_base;
357 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
358 set_irq_flags(irq, 0);
359 set_irq_handler(irq, NULL);
360 set_irq_chip(irq, NULL);
361 set_irq_chip_data(irq, NULL);
363 set_irq_chained_handler(asic->irq_nr, NULL);
367 static int asic3_gpio_direction(struct gpio_chip *chip,
368 unsigned offset, int out)
370 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
371 unsigned int gpio_base;
375 asic = container_of(chip, struct asic3, gpio);
376 gpio_base = ASIC3_GPIO_TO_BASE(offset);
378 if (gpio_base > ASIC3_GPIO_D_Base) {
379 printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
384 spin_lock_irqsave(&asic->lock, flags);
386 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Direction);
388 /* Input is 0, Output is 1 */
394 asic3_write_register(asic, gpio_base + ASIC3_GPIO_Direction, out_reg);
396 spin_unlock_irqrestore(&asic->lock, flags);
402 static int asic3_gpio_direction_input(struct gpio_chip *chip,
405 return asic3_gpio_direction(chip, offset, 0);
408 static int asic3_gpio_direction_output(struct gpio_chip *chip,
409 unsigned offset, int value)
411 return asic3_gpio_direction(chip, offset, 1);
414 static int asic3_gpio_get(struct gpio_chip *chip,
417 unsigned int gpio_base;
418 u32 mask = ASIC3_GPIO_TO_MASK(offset);
421 asic = container_of(chip, struct asic3, gpio);
422 gpio_base = ASIC3_GPIO_TO_BASE(offset);
424 if (gpio_base > ASIC3_GPIO_D_Base) {
425 printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
430 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_Status) & mask;
433 static void asic3_gpio_set(struct gpio_chip *chip,
434 unsigned offset, int value)
437 unsigned int gpio_base;
441 asic = container_of(chip, struct asic3, gpio);
442 gpio_base = ASIC3_GPIO_TO_BASE(offset);
444 if (gpio_base > ASIC3_GPIO_D_Base) {
445 printk(KERN_ERR "Invalid base (0x%x) for gpio %d\n",
450 mask = ASIC3_GPIO_TO_MASK(offset);
452 spin_lock_irqsave(&asic->lock, flags);
454 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_Out);
461 asic3_write_register(asic, gpio_base + ASIC3_GPIO_Out, out_reg);
463 spin_unlock_irqrestore(&asic->lock, flags);
468 static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base,
469 unsigned int function)
471 return asic3_read_register(asic, base + function);
474 static void asic3_set_gpio(struct asic3 *asic, unsigned int base,
475 unsigned int function, u32 bits, u32 val)
479 spin_lock_irqsave(&asic->lock, flags);
480 val |= (asic3_read_register(asic, base + function) & ~bits);
482 asic3_write_register(asic, base + function, val);
483 spin_unlock_irqrestore(&asic->lock, flags);
486 #define asic3_set_gpio_a(asic, fn, bits, val) \
487 asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)
488 #define asic3_set_gpio_b(asic, fn, bits, val) \
489 asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)
490 #define asic3_set_gpio_c(asic, fn, bits, val) \
491 asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)
492 #define asic3_set_gpio_d(asic, fn, bits, val) \
493 asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)
495 #define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \
497 asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \
498 asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \
499 asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \
500 asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \
504 static int asic3_gpio_probe(struct platform_device *pdev)
506 struct asic3_platform_data *pdata = pdev->dev.platform_data;
507 struct asic3 *asic = platform_get_drvdata(pdev);
509 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);
510 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);
511 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);
512 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);
514 asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff);
515 asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff);
516 asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff);
517 asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff);
520 asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init);
521 asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir);
522 asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata,
524 asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out);
525 asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata,
527 asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata,
529 asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata,
533 return gpiochip_add(&asic->gpio);
536 static int asic3_gpio_remove(struct platform_device *pdev)
538 struct asic3 *asic = platform_get_drvdata(pdev);
540 return gpiochip_remove(&asic->gpio);
545 static int asic3_probe(struct platform_device *pdev)
547 struct asic3_platform_data *pdata = pdev->dev.platform_data;
549 struct resource *mem;
550 unsigned long clksel;
553 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
555 printk(KERN_ERR "kzalloc failed\n");
559 spin_lock_init(&asic->lock);
560 platform_set_drvdata(pdev, asic);
561 asic->dev = &pdev->dev;
563 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
566 printk(KERN_ERR "asic3: no MEM resource\n");
571 asic->mapping = ioremap(mem->start, PAGE_SIZE);
572 if (!asic->mapping) {
574 printk(KERN_ERR "asic3: couldn't ioremap\n");
578 asic->irq_base = pdata->irq_base;
580 if (pdata && pdata->bus_shift)
581 asic->bus_shift = 2 - pdata->bus_shift;
586 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
588 ret = asic3_irq_probe(pdev);
590 printk(KERN_ERR "asic3: couldn't probe IRQs\n");
594 asic->gpio.base = pdata->gpio_base;
595 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
596 asic->gpio.get = asic3_gpio_get;
597 asic->gpio.set = asic3_gpio_set;
598 asic->gpio.direction_input = asic3_gpio_direction_input;
599 asic->gpio.direction_output = asic3_gpio_direction_output;
601 ret = asic3_gpio_probe(pdev);
603 printk(KERN_ERR "GPIO probe failed\n");
607 if (pdata->children) {
609 for (i = 0; i < pdata->n_children; i++) {
610 pdata->children[i]->dev.parent = &pdev->dev;
611 platform_device_register(pdata->children[i]);
615 printk(KERN_INFO "ASIC3 Core driver\n");
620 asic3_irq_remove(pdev);
623 iounmap(asic->mapping);
631 static int asic3_remove(struct platform_device *pdev)
634 struct asic3 *asic = platform_get_drvdata(pdev);
636 ret = asic3_gpio_remove(pdev);
639 asic3_irq_remove(pdev);
641 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
643 iounmap(asic->mapping);
650 static void asic3_shutdown(struct platform_device *pdev)
654 static struct platform_driver asic3_device_driver = {
658 .probe = asic3_probe,
659 .remove = __devexit_p(asic3_remove),
660 .shutdown = asic3_shutdown,
663 static int __init asic3_init(void)
666 retval = platform_driver_register(&asic3_device_driver);
670 subsys_initcall(asic3_init);