2 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why is a timer used to detect insert events?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
34 * So we use the timer to check the status manually.
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/platform_device.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/scatterlist.h>
44 #include <linux/leds.h>
45 #include <linux/mmc/host.h>
48 #include <asm/mach-au1x00/au1000.h>
49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1100_mmc.h>
55 #define DRIVER_NAME "au1xxx-mmc"
57 /* Set this to enable special debugging macros */
61 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
63 #define DBG(fmt, idx, args...)
66 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
68 u32 val = au_readl(HOST_CONFIG(host));
70 au_writel(val, HOST_CONFIG(host));
74 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
76 u32 val = au_readl(HOST_CONFIG2(host));
78 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
81 /* SEND_STOP will turn off clock control - this re-enables it */
82 val &= ~SD_CONFIG2_DF;
84 au_writel(val, HOST_CONFIG2(host));
88 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
90 u32 val = au_readl(HOST_CONFIG(host));
92 au_writel(val, HOST_CONFIG(host));
96 static inline void SEND_STOP(struct au1xmmc_host *host)
100 WARN_ON(host->status != HOST_S_DATA);
101 host->status = HOST_S_STOP;
103 config2 = au_readl(HOST_CONFIG2(host));
104 au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
107 /* Send the stop commmand */
108 au_writel(STOP_CMD, HOST_CMD(host));
111 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
113 if (host->platdata && host->platdata->set_power)
114 host->platdata->set_power(host->mmc, state);
117 static int au1xmmc_card_inserted(struct au1xmmc_host *host)
121 if (host->platdata && host->platdata->card_inserted)
122 ret = host->platdata->card_inserted(host->mmc);
124 ret = 1; /* assume there is a card */
129 static int au1xmmc_card_readonly(struct mmc_host *mmc)
131 struct au1xmmc_host *host = mmc_priv(mmc);
134 if (host->platdata && host->platdata->card_readonly)
135 ret = host->platdata->card_readonly(mmc);
137 ret = 0; /* assume card is read-write */
142 static void au1xmmc_finish_request(struct au1xmmc_host *host)
145 struct mmc_request *mrq = host->mrq;
148 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
154 host->pio.offset = 0;
157 host->status = HOST_S_IDLE;
159 mmc_request_done(host->mmc, mrq);
162 static void au1xmmc_tasklet_finish(unsigned long param)
164 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
165 au1xmmc_finish_request(host);
168 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
169 struct mmc_command *cmd, struct mmc_data *data)
171 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
173 switch (mmc_resp_type(cmd)) {
177 mmccmd |= SD_CMD_RT_1;
180 mmccmd |= SD_CMD_RT_1B;
183 mmccmd |= SD_CMD_RT_2;
186 mmccmd |= SD_CMD_RT_3;
189 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
195 if (data->flags & MMC_DATA_READ) {
196 if (data->blocks > 1)
197 mmccmd |= SD_CMD_CT_4;
199 mmccmd |= SD_CMD_CT_2;
200 } else if (data->flags & MMC_DATA_WRITE) {
201 if (data->blocks > 1)
202 mmccmd |= SD_CMD_CT_3;
204 mmccmd |= SD_CMD_CT_1;
208 au_writel(cmd->arg, HOST_CMDARG(host));
212 IRQ_OFF(host, SD_CONFIG_CR);
214 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
217 /* Wait for the command to go on the line */
220 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
224 /* Wait for the command to come back */
227 u32 status = au_readl(HOST_STATUS(host));
229 while(!(status & SD_STATUS_CR))
230 status = au_readl(HOST_STATUS(host));
232 /* Clear the CR status */
233 au_writel(SD_STATUS_CR, HOST_STATUS(host));
235 IRQ_ON(host, SD_CONFIG_CR);
241 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
244 struct mmc_request *mrq = host->mrq;
245 struct mmc_data *data;
248 WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
250 if (host->mrq == NULL)
253 data = mrq->cmd->data;
256 status = au_readl(HOST_STATUS(host));
258 /* The transaction is really over when the SD_STATUS_DB bit is clear */
260 while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
261 status = au_readl(HOST_STATUS(host));
264 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
266 /* Process any errors */
268 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
269 if (host->flags & HOST_F_XMIT)
270 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
273 data->error = -EILSEQ;
275 /* Clear the CRC bits */
276 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
278 data->bytes_xfered = 0;
281 if (host->flags & HOST_F_DMA) {
282 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
283 u32 chan = DMA_CHANNEL(host);
285 chan_tab_t *c = *((chan_tab_t **) chan);
286 au1x_dma_chan_t *cp = c->chan_ptr;
287 data->bytes_xfered = cp->ddma_bytecnt;
292 (data->blocks * data->blksz) -
296 au1xmmc_finish_request(host);
299 static void au1xmmc_tasklet_data(unsigned long param)
301 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
303 u32 status = au_readl(HOST_STATUS(host));
304 au1xmmc_data_complete(host, status);
307 #define AU1XMMC_MAX_TRANSFER 8
309 static void au1xmmc_send_pio(struct au1xmmc_host *host)
312 struct mmc_data *data = 0;
313 int sg_len, max, count = 0;
314 unsigned char *sg_ptr;
316 struct scatterlist *sg;
318 data = host->mrq->data;
320 if (!(host->flags & HOST_F_XMIT))
323 /* This is the pointer to the data buffer */
324 sg = &data->sg[host->pio.index];
325 sg_ptr = sg_virt(sg) + host->pio.offset;
327 /* This is the space left inside the buffer */
328 sg_len = data->sg[host->pio.index].length - host->pio.offset;
330 /* Check to if we need less then the size of the sg_buffer */
332 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
333 if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
335 for(count = 0; count < max; count++ ) {
338 status = au_readl(HOST_STATUS(host));
340 if (!(status & SD_STATUS_TH))
345 au_writel((unsigned long) val, HOST_TXPORT(host));
349 host->pio.len -= count;
350 host->pio.offset += count;
352 if (count == sg_len) {
354 host->pio.offset = 0;
357 if (host->pio.len == 0) {
358 IRQ_OFF(host, SD_CONFIG_TH);
360 if (host->flags & HOST_F_STOP)
363 tasklet_schedule(&host->data_task);
367 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
370 struct mmc_data *data = 0;
371 int sg_len = 0, max = 0, count = 0;
372 unsigned char *sg_ptr = 0;
374 struct scatterlist *sg;
376 data = host->mrq->data;
378 if (!(host->flags & HOST_F_RECV))
383 if (host->pio.index < host->dma.len) {
384 sg = &data->sg[host->pio.index];
385 sg_ptr = sg_virt(sg) + host->pio.offset;
387 /* This is the space left inside the buffer */
388 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
390 /* Check to if we need less then the size of the sg_buffer */
391 if (sg_len < max) max = sg_len;
394 if (max > AU1XMMC_MAX_TRANSFER)
395 max = AU1XMMC_MAX_TRANSFER;
397 for(count = 0; count < max; count++ ) {
399 status = au_readl(HOST_STATUS(host));
401 if (!(status & SD_STATUS_NE))
404 if (status & SD_STATUS_RC) {
405 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
406 host->pio.len, count);
410 if (status & SD_STATUS_RO) {
411 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
412 host->pio.len, count);
415 else if (status & SD_STATUS_RU) {
416 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
417 host->pio.len, count);
421 val = au_readl(HOST_RXPORT(host));
424 *sg_ptr++ = (unsigned char) (val & 0xFF);
427 host->pio.len -= count;
428 host->pio.offset += count;
430 if (sg_len && count == sg_len) {
432 host->pio.offset = 0;
435 if (host->pio.len == 0) {
436 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
437 IRQ_OFF(host, SD_CONFIG_NE);
439 if (host->flags & HOST_F_STOP)
442 tasklet_schedule(&host->data_task);
446 /* static void au1xmmc_cmd_complete
447 This is called when a command has been completed - grab the response
448 and check for errors. Then start the data transfer if it is indicated.
451 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
454 struct mmc_request *mrq = host->mrq;
455 struct mmc_command *cmd;
464 if (cmd->flags & MMC_RSP_PRESENT) {
465 if (cmd->flags & MMC_RSP_136) {
469 r[0] = au_readl(host->iobase + SD_RESP3);
470 r[1] = au_readl(host->iobase + SD_RESP2);
471 r[2] = au_readl(host->iobase + SD_RESP1);
472 r[3] = au_readl(host->iobase + SD_RESP0);
474 /* The CRC is omitted from the response, so really
475 * we only got 120 bytes, but the engine expects
476 * 128 bits, so we have to shift things up
479 for(i = 0; i < 4; i++) {
480 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
482 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
485 /* Techincally, we should be getting all 48 bits of
486 * the response (SD_RESP1 + SD_RESP2), but because
487 * our response omits the CRC, our data ends up
488 * being shifted 8 bits to the right. In this case,
489 * that means that the OSR data starts at bit 31,
490 * so we can just read RESP0 and return that
492 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
496 /* Figure out errors */
498 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
499 cmd->error = -EILSEQ;
501 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
503 if (!trans || cmd->error) {
505 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
506 tasklet_schedule(&host->finish_task);
510 host->status = HOST_S_DATA;
512 if (host->flags & HOST_F_DMA) {
513 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
514 u32 channel = DMA_CHANNEL(host);
516 /* Start the DMA as soon as the buffer gets something in it */
518 if (host->flags & HOST_F_RECV) {
519 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
521 while((status & mask) != mask)
522 status = au_readl(HOST_STATUS(host));
525 au1xxx_dbdma_start(channel);
530 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
533 unsigned int pbus = get_au1x00_speed();
534 unsigned int divisor;
538 divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
541 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
544 divisor = ((pbus / rate) / 2) - 1;
546 config = au_readl(HOST_CONFIG(host));
548 config &= ~(SD_CONFIG_DIV);
549 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
551 au_writel(config, HOST_CONFIG(host));
556 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
558 int datalen = data->blocks * data->blksz;
560 if (data->flags & MMC_DATA_READ)
561 host->flags |= HOST_F_RECV;
563 host->flags |= HOST_F_XMIT;
566 host->flags |= HOST_F_STOP;
568 host->dma.dir = DMA_BIDIRECTIONAL;
570 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
571 data->sg_len, host->dma.dir);
573 if (host->dma.len == 0)
576 au_writel(data->blksz - 1, HOST_BLKSIZE(host));
578 if (host->flags & HOST_F_DMA) {
579 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
581 u32 channel = DMA_CHANNEL(host);
583 au1xxx_dbdma_stop(channel);
585 for(i = 0; i < host->dma.len; i++) {
586 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
587 struct scatterlist *sg = &data->sg[i];
588 int sg_len = sg->length;
590 int len = (datalen > sg_len) ? sg_len : datalen;
592 if (i == host->dma.len - 1)
593 flags = DDMA_FLAGS_IE;
595 if (host->flags & HOST_F_XMIT){
596 ret = au1xxx_dbdma_put_source_flags(channel,
597 (void *) sg_virt(sg), len, flags);
600 ret = au1xxx_dbdma_put_dest_flags(channel,
601 (void *) sg_virt(sg),
614 host->pio.offset = 0;
615 host->pio.len = datalen;
617 if (host->flags & HOST_F_XMIT)
618 IRQ_ON(host, SD_CONFIG_TH);
620 IRQ_ON(host, SD_CONFIG_NE);
621 //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
627 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
632 /* static void au1xmmc_request
633 This actually starts a command or data transaction
636 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
639 struct au1xmmc_host *host = mmc_priv(mmc);
640 unsigned int flags = 0;
643 WARN_ON(irqs_disabled());
644 WARN_ON(host->status != HOST_S_IDLE);
647 host->status = HOST_S_CMD;
651 flags = mrq->data->flags;
652 ret = au1xmmc_prepare_data(host, mrq->data);
656 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
659 mrq->cmd->error = ret;
660 au1xmmc_finish_request(host);
664 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
667 /* Apply the clock */
668 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
671 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
674 au_writel(~0, HOST_STATUS(host));
677 au_writel(0, HOST_BLKSIZE(host));
678 au_writel(0x001fffff, HOST_TIMEOUT(host));
681 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
684 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
687 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
690 /* Configure interrupts */
691 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
696 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
698 struct au1xmmc_host *host = mmc_priv(mmc);
701 if (ios->power_mode == MMC_POWER_OFF)
702 au1xmmc_set_power(host, 0);
703 else if (ios->power_mode == MMC_POWER_ON) {
704 au1xmmc_set_power(host, 1);
707 if (ios->clock && ios->clock != host->clock) {
708 au1xmmc_set_clock(host, ios->clock);
709 host->clock = ios->clock;
712 config2 = au_readl(HOST_CONFIG2(host));
713 switch (ios->bus_width) {
714 case MMC_BUS_WIDTH_4:
715 config2 |= SD_CONFIG2_WB;
717 case MMC_BUS_WIDTH_1:
718 config2 &= ~SD_CONFIG2_WB;
721 au_writel(config2, HOST_CONFIG2(host));
725 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
726 #define STATUS_DATA_IN (SD_STATUS_NE)
727 #define STATUS_DATA_OUT (SD_STATUS_TH)
729 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
731 struct au1xmmc_host *host = dev_id;
734 status = au_readl(HOST_STATUS(host));
736 if (!(status & SD_STATUS_I))
737 return IRQ_NONE; /* not ours */
739 if (status & SD_STATUS_SI) /* SDIO */
740 mmc_signal_sdio_irq(host->mmc);
742 if (host->mrq && (status & STATUS_TIMEOUT)) {
743 if (status & SD_STATUS_RAT)
744 host->mrq->cmd->error = -ETIMEDOUT;
745 else if (status & SD_STATUS_DT)
746 host->mrq->data->error = -ETIMEDOUT;
748 /* In PIO mode, interrupts might still be enabled */
749 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
751 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
752 tasklet_schedule(&host->finish_task);
755 else if (status & SD_STATUS_DD) {
756 /* Sometimes we get a DD before a NE in PIO mode */
757 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
758 au1xmmc_receive_pio(host);
760 au1xmmc_data_complete(host, status);
761 /* tasklet_schedule(&host->data_task); */
765 else if (status & SD_STATUS_CR) {
766 if (host->status == HOST_S_CMD)
767 au1xmmc_cmd_complete(host, status);
769 } else if (!(host->flags & HOST_F_DMA)) {
770 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
771 au1xmmc_send_pio(host);
772 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
773 au1xmmc_receive_pio(host);
775 } else if (status & 0x203F3C70) {
776 DBG("Unhandled status %8.8x\n", host->pdev->id,
780 au_writel(status, HOST_STATUS(host));
786 #ifdef CONFIG_SOC_AU1200
787 /* 8bit memory DMA device */
788 static dbdev_tab_t au1xmmc_mem_dbdev = {
789 .dev_id = DSCR_CMD0_ALWAYS,
790 .dev_flags = DEV_FLAGS_ANYUSE,
793 .dev_physaddr = 0x00000000,
795 .dev_intpolarity = 0,
799 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
801 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
803 /* Avoid spurious interrupts */
807 if (host->flags & HOST_F_STOP)
810 tasklet_schedule(&host->data_task);
813 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
815 struct resource *res;
818 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
823 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
831 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
832 au1xmmc_dbdma_callback, (void *)host);
833 if (!host->tx_chan) {
834 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
838 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
839 au1xmmc_dbdma_callback, (void *)host);
840 if (!host->rx_chan) {
841 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
842 au1xxx_dbdma_chan_free(host->tx_chan);
846 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
847 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
849 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
850 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
852 /* DBDMA is good to go */
853 host->flags |= HOST_F_DMA;
858 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
860 if (host->flags & HOST_F_DMA) {
861 host->flags &= ~HOST_F_DMA;
862 au1xxx_dbdma_chan_free(host->tx_chan);
863 au1xxx_dbdma_chan_free(host->rx_chan);
868 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
870 struct au1xmmc_host *host = mmc_priv(mmc);
873 IRQ_ON(host, SD_CONFIG_SI);
875 IRQ_OFF(host, SD_CONFIG_SI);
878 static const struct mmc_host_ops au1xmmc_ops = {
879 .request = au1xmmc_request,
880 .set_ios = au1xmmc_set_ios,
881 .get_ro = au1xmmc_card_readonly,
882 .enable_sdio_irq = au1xmmc_enable_sdio_irq,
885 static void au1xmmc_poll_event(unsigned long arg)
887 struct au1xmmc_host *host = (struct au1xmmc_host *)arg;
888 int card = au1xmmc_card_inserted(host);
889 int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
891 if (card != controller) {
892 host->flags &= ~HOST_F_ACTIVE;
894 host->flags |= HOST_F_ACTIVE;
895 mmc_detect_change(host->mmc, 0);
899 if (host->mrq != NULL) {
900 u32 status = au_readl(HOST_STATUS(host));
901 DBG("PENDING - %8.8x\n", host->pdev->id, status);
904 mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
907 static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host)
909 init_timer(&host->timer);
910 host->timer.function = au1xmmc_poll_event;
911 host->timer.data = (unsigned long)host;
912 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
915 static int __devinit au1xmmc_probe(struct platform_device *pdev)
917 struct mmc_host *mmc;
918 struct au1xmmc_host *host;
922 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
924 dev_err(&pdev->dev, "no memory for mmc_host\n");
929 host = mmc_priv(mmc);
931 host->platdata = pdev->dev.platform_data;
935 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
937 dev_err(&pdev->dev, "no mmio defined\n");
941 host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
944 dev_err(&pdev->dev, "mmio already in use\n");
948 host->iobase = (unsigned long)ioremap(r->start, 0x3c);
950 dev_err(&pdev->dev, "cannot remap mmio\n");
954 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
956 dev_err(&pdev->dev, "no IRQ defined\n");
960 host->irq = r->start;
961 /* IRQ is shared among both SD controllers */
962 ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
965 dev_err(&pdev->dev, "cannot grab IRQ\n");
969 mmc->ops = &au1xmmc_ops;
972 mmc->f_max = 24000000;
974 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
975 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
977 mmc->max_blk_size = 2048;
978 mmc->max_blk_count = 512;
980 mmc->ocr_avail = AU1XMMC_OCR;
981 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
983 host->status = HOST_S_IDLE;
985 /* board-specific carddetect setup, if any */
986 if (host->platdata && host->platdata->cd_setup) {
987 ret = host->platdata->cd_setup(mmc, 1);
989 dev_err(&pdev->dev, "board CD setup failed\n");
993 /* poll the board-specific is-card-in-socket-? method */
994 au1xmmc_init_cd_poll_timer(host);
997 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
998 (unsigned long)host);
1000 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1001 (unsigned long)host);
1003 #ifdef CONFIG_SOC_AU1200
1004 ret = au1xmmc_dbdma_init(host);
1006 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
1009 #ifdef CONFIG_LEDS_CLASS
1010 if (host->platdata && host->platdata->led) {
1011 struct led_classdev *led = host->platdata->led;
1012 led->name = mmc_hostname(mmc);
1013 led->brightness = LED_OFF;
1014 led->default_trigger = mmc_hostname(mmc);
1015 ret = led_classdev_register(mmc_dev(mmc), led);
1021 au1xmmc_reset_controller(host);
1023 ret = mmc_add_host(mmc);
1025 dev_err(&pdev->dev, "cannot add mmc host\n");
1029 platform_set_drvdata(pdev, mmc);
1031 /* start the carddetect poll timer if necessary */
1032 if (!(host->platdata && host->platdata->cd_setup))
1033 add_timer(&host->timer);
1035 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1036 " (mode=%s)\n", pdev->id, host->iobase,
1037 host->flags & HOST_F_DMA ? "dma" : "pio");
1039 return 0; /* all ok */
1042 #ifdef CONFIG_LEDS_CLASS
1043 if (host->platdata && host->platdata->led)
1044 led_classdev_unregister(host->platdata->led);
1047 au_writel(0, HOST_ENABLE(host));
1048 au_writel(0, HOST_CONFIG(host));
1049 au_writel(0, HOST_CONFIG2(host));
1052 #ifdef CONFIG_SOC_AU1200
1053 au1xmmc_dbdma_shutdown(host);
1056 tasklet_kill(&host->data_task);
1057 tasklet_kill(&host->finish_task);
1059 if (host->platdata && host->platdata->cd_setup)
1060 host->platdata->cd_setup(mmc, 0);
1062 free_irq(host->irq, host);
1064 iounmap((void *)host->iobase);
1066 release_resource(host->ioarea);
1067 kfree(host->ioarea);
1074 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1076 struct mmc_host *mmc = platform_get_drvdata(pdev);
1077 struct au1xmmc_host *host;
1080 host = mmc_priv(mmc);
1082 mmc_remove_host(mmc);
1084 #ifdef CONFIG_LEDS_CLASS
1085 if (host->platdata && host->platdata->led)
1086 led_classdev_unregister(host->platdata->led);
1089 if (host->platdata && host->platdata->cd_setup)
1090 host->platdata->cd_setup(mmc, 0);
1092 del_timer_sync(&host->timer);
1094 au_writel(0, HOST_ENABLE(host));
1095 au_writel(0, HOST_CONFIG(host));
1096 au_writel(0, HOST_CONFIG2(host));
1099 tasklet_kill(&host->data_task);
1100 tasklet_kill(&host->finish_task);
1102 #ifdef CONFIG_SOC_AU1200
1103 au1xmmc_dbdma_shutdown(host);
1105 au1xmmc_set_power(host, 0);
1107 free_irq(host->irq, host);
1108 iounmap((void *)host->iobase);
1109 release_resource(host->ioarea);
1110 kfree(host->ioarea);
1117 static struct platform_driver au1xmmc_driver = {
1118 .probe = au1xmmc_probe,
1119 .remove = au1xmmc_remove,
1123 .name = DRIVER_NAME,
1124 .owner = THIS_MODULE,
1128 static int __init au1xmmc_init(void)
1130 #ifdef CONFIG_SOC_AU1200
1131 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1132 * of 8 bits. And since devices are shared, we need to create
1133 * our own to avoid freaking out other devices.
1135 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1137 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1139 return platform_driver_register(&au1xmmc_driver);
1142 static void __exit au1xmmc_exit(void)
1144 #ifdef CONFIG_SOC_AU1200
1146 au1xxx_ddma_del_device(memid);
1148 platform_driver_unregister(&au1xmmc_driver);
1151 module_init(au1xmmc_init);
1152 module_exit(au1xmmc_exit);
1154 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1155 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1156 MODULE_LICENSE("GPL");
1157 MODULE_ALIAS("platform:au1xxx-mmc");