2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
32 #include <asm/mach-types.h>
34 #include <asm/arch/board.h>
35 #include <asm/arch/mmc.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/dma.h>
38 #include <asm/arch/mux.h>
39 #include <asm/arch/fpga.h>
40 #include <asm/arch/tps65010.h>
41 #include <asm/arch/board-sx1.h>
43 #define OMAP_MMC_REG_CMD 0x00
44 #define OMAP_MMC_REG_ARGL 0x04
45 #define OMAP_MMC_REG_ARGH 0x08
46 #define OMAP_MMC_REG_CON 0x0c
47 #define OMAP_MMC_REG_STAT 0x10
48 #define OMAP_MMC_REG_IE 0x14
49 #define OMAP_MMC_REG_CTO 0x18
50 #define OMAP_MMC_REG_DTO 0x1c
51 #define OMAP_MMC_REG_DATA 0x20
52 #define OMAP_MMC_REG_BLEN 0x24
53 #define OMAP_MMC_REG_NBLK 0x28
54 #define OMAP_MMC_REG_BUF 0x2c
55 #define OMAP_MMC_REG_SDIO 0x34
56 #define OMAP_MMC_REG_REV 0x3c
57 #define OMAP_MMC_REG_RSP0 0x40
58 #define OMAP_MMC_REG_RSP1 0x44
59 #define OMAP_MMC_REG_RSP2 0x48
60 #define OMAP_MMC_REG_RSP3 0x4c
61 #define OMAP_MMC_REG_RSP4 0x50
62 #define OMAP_MMC_REG_RSP5 0x54
63 #define OMAP_MMC_REG_RSP6 0x58
64 #define OMAP_MMC_REG_RSP7 0x5c
65 #define OMAP_MMC_REG_IOSR 0x60
66 #define OMAP_MMC_REG_SYSC 0x64
67 #define OMAP_MMC_REG_SYSS 0x68
69 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
70 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
71 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
72 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
73 #define OMAP_MMC_STAT_A_FULL (1 << 10)
74 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
75 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
76 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
77 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
78 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
79 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
80 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
81 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
83 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
84 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
89 #define OMAP_MMC_CMDTYPE_BC 0
90 #define OMAP_MMC_CMDTYPE_BCR 1
91 #define OMAP_MMC_CMDTYPE_AC 2
92 #define OMAP_MMC_CMDTYPE_ADTC 3
95 #define DRIVER_NAME "mmci-omap"
97 /* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
99 #define OMAP_MMC_SWITCH_POLL_DELAY 500
101 struct mmc_omap_host;
103 struct mmc_omap_slot {
108 unsigned int fclk_freq;
111 struct work_struct switch_work;
112 struct timer_list switch_timer;
115 struct mmc_request *mrq;
116 struct mmc_omap_host *host;
117 struct mmc_host *mmc;
118 struct omap_mmc_slot_data *pdata;
121 struct mmc_omap_host {
124 struct mmc_request * mrq;
125 struct mmc_command * cmd;
126 struct mmc_data * data;
127 struct mmc_host * mmc;
129 unsigned char id; /* 16xx chips have 2 MMC blocks */
132 struct resource *mem_res;
133 void __iomem *virt_base;
134 unsigned int phys_base;
136 unsigned char bus_mode;
137 unsigned char hw_bus_mode;
142 u32 buffer_bytes_left;
143 u32 total_bytes_left;
146 unsigned brs_received:1, dma_done:1;
147 unsigned dma_is_read:1;
148 unsigned dma_in_use:1;
151 struct timer_list dma_timer;
156 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
157 struct mmc_omap_slot *current_slot;
158 spinlock_t slot_lock;
159 wait_queue_head_t slot_wq;
162 struct omap_mmc_platform_data *pdata;
165 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
167 struct mmc_omap_host *host = slot->host;
172 spin_lock_irqsave(&host->slot_lock, flags);
173 while (host->mmc != NULL) {
174 spin_unlock_irqrestore(&host->slot_lock, flags);
175 wait_event(host->slot_wq, host->mmc == NULL);
176 spin_lock_irqsave(&host->slot_lock, flags);
178 host->mmc = slot->mmc;
179 spin_unlock_irqrestore(&host->slot_lock, flags);
181 clk_enable(host->fclk);
182 if (host->current_slot != slot) {
183 if (host->pdata->switch_slot != NULL)
184 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
185 host->current_slot = slot;
188 /* Doing the dummy read here seems to work around some bug
189 * at least in OMAP24xx silicon where the command would not
190 * start after writing the CMD register. Sigh. */
191 OMAP_MMC_READ(host, CON);
193 OMAP_MMC_WRITE(host, CON, slot->saved_con);
196 static void mmc_omap_start_request(struct mmc_omap_host *host,
197 struct mmc_request *req);
199 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
201 struct mmc_omap_host *host = slot->host;
205 BUG_ON(slot == NULL || host->mmc == NULL);
206 clk_disable(host->fclk);
208 spin_lock_irqsave(&host->slot_lock, flags);
209 /* Check for any pending requests */
210 for (i = 0; i < host->nr_slots; i++) {
211 struct mmc_omap_slot *new_slot;
212 struct mmc_request *rq;
214 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
217 new_slot = host->slots[i];
218 /* The current slot should not have a request in queue */
219 BUG_ON(new_slot == host->current_slot);
221 host->mmc = new_slot->mmc;
222 spin_unlock_irqrestore(&host->slot_lock, flags);
223 mmc_omap_select_slot(new_slot, 1);
225 new_slot->mrq = NULL;
226 mmc_omap_start_request(host, rq);
231 wake_up(&host->slot_wq);
232 spin_unlock_irqrestore(&host->slot_lock, flags);
236 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
238 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
242 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
245 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
246 struct mmc_omap_slot *slot = mmc_priv(mmc);
248 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
252 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
254 /* Access to the R/O switch is required for production testing
257 mmc_omap_show_ro(struct device *dev, struct device_attribute *attr, char *buf)
259 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
260 struct mmc_omap_slot *slot = mmc_priv(mmc);
262 return sprintf(buf, "%d\n", slot->pdata->get_ro(mmc_dev(mmc),
266 static DEVICE_ATTR(ro, S_IRUGO, mmc_omap_show_ro, NULL);
269 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
272 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
273 struct mmc_omap_slot *slot = mmc_priv(mmc);
275 return sprintf(buf, "%s\n", slot->pdata->name);
278 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
281 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
292 /* Our hardware needs to know exact type */
293 switch (mmc_resp_type(cmd)) {
298 /* resp 1, 1b, 6, 7 */
308 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
312 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
313 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
314 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
315 cmdtype = OMAP_MMC_CMDTYPE_BC;
316 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
317 cmdtype = OMAP_MMC_CMDTYPE_BCR;
319 cmdtype = OMAP_MMC_CMDTYPE_AC;
322 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
324 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
327 if (cmd->flags & MMC_RSP_BUSY)
330 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
333 OMAP_MMC_WRITE(host, CTO, 200);
334 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
335 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
336 OMAP_MMC_WRITE(host, IE,
337 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
338 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
339 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
340 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
341 OMAP_MMC_STAT_END_OF_DATA);
342 OMAP_MMC_WRITE(host, CMD, cmdreg);
346 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
349 enum dma_data_direction dma_data_dir;
351 BUG_ON(host->dma_ch < 0);
353 omap_stop_dma(host->dma_ch);
354 /* Release DMA channel lazily */
355 mod_timer(&host->dma_timer, jiffies + HZ);
356 if (data->flags & MMC_DATA_WRITE)
357 dma_data_dir = DMA_TO_DEVICE;
359 dma_data_dir = DMA_FROM_DEVICE;
360 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
365 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
367 if (host->dma_in_use)
368 mmc_omap_release_dma(host, data, data->error);
373 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
374 * dozens of requests until the card finishes writing data.
375 * It'd be cheaper to just wait till an EOFB interrupt arrives...
379 struct mmc_host *mmc;
383 mmc_omap_release_slot(host->current_slot);
384 mmc_request_done(mmc, data->mrq);
388 mmc_omap_start_command(host, data->stop);
392 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
397 if (host->dma_in_use)
398 mmc_omap_release_dma(host, data, 1);
403 ie = OMAP_MMC_READ(host, IE);
404 OMAP_MMC_WRITE(host, IE, 0);
405 OMAP_MMC_WRITE(host, CMD, 1 << 7);
407 while (!(OMAP_MMC_READ(host, STAT) & OMAP_MMC_STAT_END_OF_CMD)) {
413 OMAP_MMC_WRITE(host, STAT, OMAP_MMC_STAT_END_OF_CMD);
414 OMAP_MMC_WRITE(host, IE, ie);
418 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
423 if (!host->dma_in_use) {
424 mmc_omap_xfer_done(host, data);
428 spin_lock_irqsave(&host->dma_lock, flags);
432 host->brs_received = 1;
433 spin_unlock_irqrestore(&host->dma_lock, flags);
435 mmc_omap_xfer_done(host, data);
439 mmc_omap_dma_timer(unsigned long data)
441 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
443 BUG_ON(host->dma_ch < 0);
444 omap_free_dma(host->dma_ch);
449 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
455 spin_lock_irqsave(&host->dma_lock, flags);
456 if (host->brs_received)
460 spin_unlock_irqrestore(&host->dma_lock, flags);
462 mmc_omap_xfer_done(host, data);
466 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
470 if (cmd->flags & MMC_RSP_PRESENT) {
471 if (cmd->flags & MMC_RSP_136) {
472 /* response type 2 */
474 OMAP_MMC_READ(host, RSP0) |
475 (OMAP_MMC_READ(host, RSP1) << 16);
477 OMAP_MMC_READ(host, RSP2) |
478 (OMAP_MMC_READ(host, RSP3) << 16);
480 OMAP_MMC_READ(host, RSP4) |
481 (OMAP_MMC_READ(host, RSP5) << 16);
483 OMAP_MMC_READ(host, RSP6) |
484 (OMAP_MMC_READ(host, RSP7) << 16);
486 /* response types 1, 1b, 3, 4, 5, 6 */
488 OMAP_MMC_READ(host, RSP6) |
489 (OMAP_MMC_READ(host, RSP7) << 16);
493 if (host->data == NULL || cmd->error) {
494 struct mmc_host *mmc;
496 if (host->data != NULL)
497 mmc_omap_abort_xfer(host, host->data);
500 mmc_omap_release_slot(host->current_slot);
501 mmc_request_done(mmc, cmd->mrq);
507 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
509 struct scatterlist *sg;
511 sg = host->data->sg + host->sg_idx;
512 host->buffer_bytes_left = sg->length;
513 host->buffer = sg_virt(sg);
514 if (host->buffer_bytes_left > host->total_bytes_left)
515 host->buffer_bytes_left = host->total_bytes_left;
520 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
524 if (host->buffer_bytes_left == 0) {
526 BUG_ON(host->sg_idx == host->sg_len);
527 mmc_omap_sg_to_buf(host);
530 if (n > host->buffer_bytes_left)
531 n = host->buffer_bytes_left;
532 host->buffer_bytes_left -= n;
533 host->total_bytes_left -= n;
534 host->data->bytes_xfered += n;
537 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
539 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
543 static inline void mmc_omap_report_irq(u16 status)
545 static const char *mmc_omap_status_bits[] = {
546 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
547 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
551 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
552 if (status & (1 << i)) {
555 printk("%s", mmc_omap_status_bits[i]);
560 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
562 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
568 if (host->cmd == NULL && host->data == NULL) {
569 status = OMAP_MMC_READ(host, STAT);
570 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
572 OMAP_MMC_WRITE(host, STAT, status);
573 OMAP_MMC_WRITE(host, IE, 0);
582 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
583 OMAP_MMC_WRITE(host, STAT, status);
584 #ifdef CONFIG_MMC_DEBUG
585 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
586 status, host->cmd != NULL ? host->cmd->opcode : -1);
587 mmc_omap_report_irq(status);
590 if (host->total_bytes_left) {
591 if ((status & OMAP_MMC_STAT_A_FULL) ||
592 (status & OMAP_MMC_STAT_END_OF_DATA))
593 mmc_omap_xfer_data(host, 0);
594 if (status & OMAP_MMC_STAT_A_EMPTY)
595 mmc_omap_xfer_data(host, 1);
598 if (status & OMAP_MMC_STAT_END_OF_DATA) {
602 if (status & OMAP_MMC_STAT_DATA_TOUT) {
603 dev_dbg(mmc_dev(host->mmc), "data timeout\n");
605 host->data->error = -ETIMEDOUT;
610 if (status & OMAP_MMC_STAT_DATA_CRC) {
612 host->data->error = -EILSEQ;
613 dev_dbg(mmc_dev(host->mmc),
614 "data CRC error, bytes left %d\n",
615 host->total_bytes_left);
618 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
622 if (status & OMAP_MMC_STAT_CMD_TOUT) {
623 /* Timeouts are routine with some commands */
625 struct mmc_omap_slot *slot =
627 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
632 !mmc_omap_cover_is_open(slot))
633 dev_err(mmc_dev(host->mmc),
634 "command timeout, CMD %d\n",
636 host->cmd->error = -ETIMEDOUT;
641 if (status & OMAP_MMC_STAT_CMD_CRC) {
643 dev_err(mmc_dev(host->mmc),
644 "command CRC error (CMD%d, arg 0x%08x)\n",
645 host->cmd->opcode, host->cmd->arg);
646 host->cmd->error = -EILSEQ;
649 dev_err(mmc_dev(host->mmc),
650 "command CRC error without cmd?\n");
653 if (status & OMAP_MMC_STAT_CARD_ERR) {
654 dev_dbg(mmc_dev(host->mmc),
655 "ignoring card status error (CMD%d)\n",
661 * NOTE: On 1610 the END_OF_CMD may come too early when
664 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
665 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
671 mmc_omap_cmd_done(host, host->cmd);
674 mmc_omap_xfer_done(host, host->data);
675 else if (end_transfer)
676 mmc_omap_end_of_data(host, host->data);
681 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
683 struct mmc_omap_host *host = dev_get_drvdata(dev);
685 BUG_ON(slot >= host->nr_slots);
687 /* Other subsystems can call in here before we're initialised. */
688 if (host->nr_slots == 0 || !host->slots[slot])
691 schedule_work(&host->slots[slot]->switch_work);
694 static void mmc_omap_switch_timer(unsigned long arg)
696 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
698 schedule_work(&slot->switch_work);
701 static void mmc_omap_cover_handler(struct work_struct *work)
703 struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
707 cover_open = mmc_omap_cover_is_open(slot);
708 if (cover_open != slot->cover_open) {
709 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
710 slot->cover_open = cover_open;
711 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
712 cover_open ? "open" : "closed");
714 mmc_detect_change(slot->mmc, slot->id);
717 /* Prepare to transfer the next segment of a scatterlist */
719 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
721 int dma_ch = host->dma_ch;
722 unsigned long data_addr;
725 struct scatterlist *sg = &data->sg[host->sg_idx];
730 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
732 count = sg_dma_len(sg);
734 if ((data->blocks == 1) && (count > data->blksz))
737 host->dma_len = count;
739 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
740 * Use 16 or 32 word frames when the blocksize is at least that large.
741 * Blocksize is usually 512 bytes; but not for some SD reads.
743 if (cpu_is_omap15xx() && frame > 32)
750 if (!(data->flags & MMC_DATA_WRITE)) {
751 buf = 0x800f | ((frame - 1) << 8);
753 if (cpu_class_is_omap1()) {
754 src_port = OMAP_DMA_PORT_TIPB;
755 dst_port = OMAP_DMA_PORT_EMIFF;
757 if (cpu_is_omap24xx())
758 sync_dev = OMAP24XX_DMA_MMC1_RX;
760 omap_set_dma_src_params(dma_ch, src_port,
761 OMAP_DMA_AMODE_CONSTANT,
763 omap_set_dma_dest_params(dma_ch, dst_port,
764 OMAP_DMA_AMODE_POST_INC,
765 sg_dma_address(sg), 0, 0);
766 omap_set_dma_dest_data_pack(dma_ch, 1);
767 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
769 buf = 0x0f80 | ((frame - 1) << 0);
771 if (cpu_class_is_omap1()) {
772 src_port = OMAP_DMA_PORT_EMIFF;
773 dst_port = OMAP_DMA_PORT_TIPB;
775 if (cpu_is_omap24xx())
776 sync_dev = OMAP24XX_DMA_MMC1_TX;
778 omap_set_dma_dest_params(dma_ch, dst_port,
779 OMAP_DMA_AMODE_CONSTANT,
781 omap_set_dma_src_params(dma_ch, src_port,
782 OMAP_DMA_AMODE_POST_INC,
783 sg_dma_address(sg), 0, 0);
784 omap_set_dma_src_data_pack(dma_ch, 1);
785 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
788 /* Max limit for DMA frame count is 0xffff */
789 BUG_ON(count > 0xffff);
791 OMAP_MMC_WRITE(host, BUF, buf);
792 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
793 frame, count, OMAP_DMA_SYNC_FRAME,
797 /* A scatterlist segment completed */
798 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
800 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
801 struct mmc_data *mmcdat = host->data;
803 if (unlikely(host->dma_ch < 0)) {
804 dev_err(mmc_dev(host->mmc),
805 "DMA callback while DMA not enabled\n");
808 /* FIXME: We really should do something to _handle_ the errors */
809 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
810 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
813 if (ch_status & OMAP_DMA_DROP_IRQ) {
814 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
817 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
820 mmcdat->bytes_xfered += host->dma_len;
822 if (host->sg_idx < host->sg_len) {
823 mmc_omap_prepare_dma(host, host->data);
824 omap_start_dma(host->dma_ch);
826 mmc_omap_dma_done(host, host->data);
829 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
831 const char *dev_name;
832 int sync_dev, dma_ch, is_read, r;
834 is_read = !(data->flags & MMC_DATA_WRITE);
835 del_timer_sync(&host->dma_timer);
836 if (host->dma_ch >= 0) {
837 if (is_read == host->dma_is_read)
839 omap_free_dma(host->dma_ch);
845 sync_dev = OMAP_DMA_MMC_RX;
846 dev_name = "MMC1 read";
848 sync_dev = OMAP_DMA_MMC2_RX;
849 dev_name = "MMC2 read";
853 sync_dev = OMAP_DMA_MMC_TX;
854 dev_name = "MMC1 write";
856 sync_dev = OMAP_DMA_MMC2_TX;
857 dev_name = "MMC2 write";
860 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
863 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
866 host->dma_ch = dma_ch;
867 host->dma_is_read = is_read;
872 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
876 reg = OMAP_MMC_READ(host, SDIO);
878 OMAP_MMC_WRITE(host, SDIO, reg);
879 /* Set maximum timeout */
880 OMAP_MMC_WRITE(host, CTO, 0xff);
883 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
888 /* Convert ns to clock cycles by assuming 20MHz frequency
889 * 1 cycle at 20MHz = 500 ns
891 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
893 /* Check if we need to use timeout multiplier register */
894 reg = OMAP_MMC_READ(host, SDIO);
895 if (timeout > 0xffff) {
900 OMAP_MMC_WRITE(host, SDIO, reg);
901 OMAP_MMC_WRITE(host, DTO, timeout);
905 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
907 struct mmc_data *data = req->data;
908 int i, use_dma, block_size;
913 OMAP_MMC_WRITE(host, BLEN, 0);
914 OMAP_MMC_WRITE(host, NBLK, 0);
915 OMAP_MMC_WRITE(host, BUF, 0);
916 host->dma_in_use = 0;
917 set_cmd_timeout(host, req);
921 block_size = data->blksz;
923 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
924 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
925 set_data_timeout(host, req);
927 /* cope with calling layer confusion; it issues "single
928 * block" writes using multi-block scatterlists.
930 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
932 /* Only do DMA for entire blocks */
933 use_dma = host->use_dma;
935 for (i = 0; i < sg_len; i++) {
936 if ((data->sg[i].length % block_size) != 0) {
945 if (mmc_omap_get_dma_channel(host, data) == 0) {
946 enum dma_data_direction dma_data_dir;
948 if (data->flags & MMC_DATA_WRITE)
949 dma_data_dir = DMA_TO_DEVICE;
951 dma_data_dir = DMA_FROM_DEVICE;
953 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
954 sg_len, dma_data_dir);
955 host->total_bytes_left = 0;
956 mmc_omap_prepare_dma(host, req->data);
957 host->brs_received = 0;
959 host->dma_in_use = 1;
966 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
967 host->total_bytes_left = data->blocks * block_size;
968 host->sg_len = sg_len;
969 mmc_omap_sg_to_buf(host);
970 host->dma_in_use = 0;
974 static void mmc_omap_start_request(struct mmc_omap_host *host,
975 struct mmc_request *req)
977 BUG_ON(host->mrq != NULL);
981 /* only touch fifo AFTER the controller readies it */
982 mmc_omap_prepare_data(host, req);
983 mmc_omap_start_command(host, req->cmd);
984 if (host->dma_in_use)
985 omap_start_dma(host->dma_ch);
986 BUG_ON(irqs_disabled());
989 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
991 struct mmc_omap_slot *slot = mmc_priv(mmc);
992 struct mmc_omap_host *host = slot->host;
995 spin_lock_irqsave(&host->slot_lock, flags);
996 if (host->mmc != NULL) {
997 BUG_ON(slot->mrq != NULL);
999 spin_unlock_irqrestore(&host->slot_lock, flags);
1003 spin_unlock_irqrestore(&host->slot_lock, flags);
1004 mmc_omap_select_slot(slot, 1);
1005 mmc_omap_start_request(host, req);
1008 static void innovator_fpga_socket_power(int on)
1010 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
1012 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
1013 OMAP1510_FPGA_POWER);
1015 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
1016 OMAP1510_FPGA_POWER);
1022 * Turn the socket power on/off. Innovator uses FPGA, most boards
1023 * probably use GPIO.
1025 static void mmc_omap_power(struct mmc_omap_host *host, int on)
1027 if (machine_is_sx1())
1028 sx1_setmmcpower(on);
1030 if (machine_is_omap_innovator())
1031 innovator_fpga_socket_power(1);
1032 else if (machine_is_omap_h2())
1033 tps65010_set_gpio_out_value(GPIO3, HIGH);
1034 else if (machine_is_omap_h3())
1035 /* GPIO 4 of TPS65010 sends SD_EN signal */
1036 tps65010_set_gpio_out_value(GPIO4, HIGH);
1037 else if (cpu_is_omap24xx()) {
1038 u16 reg = OMAP_MMC_READ(host, CON);
1039 OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
1041 if (host->power_pin >= 0)
1042 omap_set_gpio_dataout(host->power_pin, 1);
1044 if (machine_is_omap_innovator())
1045 innovator_fpga_socket_power(0);
1046 else if (machine_is_omap_h2())
1047 tps65010_set_gpio_out_value(GPIO3, LOW);
1048 else if (machine_is_omap_h3())
1049 tps65010_set_gpio_out_value(GPIO4, LOW);
1050 else if (cpu_is_omap24xx()) {
1051 u16 reg = OMAP_MMC_READ(host, CON);
1052 OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
1054 if (host->power_pin >= 0)
1055 omap_set_gpio_dataout(host->power_pin, 0);
1059 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1061 struct mmc_omap_slot *slot = mmc_priv(mmc);
1062 struct mmc_omap_host *host = slot->host;
1063 int func_clk_rate = clk_get_rate(host->fclk);
1066 if (ios->clock == 0)
1069 dsor = func_clk_rate / ios->clock;
1073 if (func_clk_rate / dsor > ios->clock)
1079 slot->fclk_freq = func_clk_rate / dsor;
1081 if (ios->bus_width == MMC_BUS_WIDTH_4)
1087 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1089 struct mmc_omap_slot *slot = mmc_priv(mmc);
1090 struct mmc_omap_host *host = slot->host;
1093 dsor = mmc_omap_calc_divisor(mmc, ios);
1094 host->bus_mode = ios->bus_mode;
1095 host->hw_bus_mode = host->bus_mode;
1097 switch (ios->power_mode) {
1099 mmc_omap_power(host, 0);
1102 /* Cannot touch dsor yet, just power up MMC */
1103 mmc_omap_power(host, 1);
1110 clk_enable(host->fclk);
1112 /* On insanely high arm_per frequencies something sometimes
1113 * goes somehow out of sync, and the POW bit is not being set,
1114 * which results in the while loop below getting stuck.
1115 * Writing to the CON register twice seems to do the trick. */
1116 for (i = 0; i < 2; i++)
1117 OMAP_MMC_WRITE(host, CON, dsor);
1118 if (ios->power_mode == MMC_POWER_ON) {
1119 /* Send clock cycles, poll completion */
1120 OMAP_MMC_WRITE(host, IE, 0);
1121 OMAP_MMC_WRITE(host, STAT, 0xffff);
1122 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1123 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1124 OMAP_MMC_WRITE(host, STAT, 1);
1126 clk_disable(host->fclk);
1129 static int mmc_omap_get_ro(struct mmc_host *mmc)
1131 struct mmc_omap_slot *slot = mmc_priv(mmc);
1133 if (slot->pdata->get_ro != NULL)
1134 return slot->pdata->get_ro(mmc_dev(mmc), slot->id);
1138 static const struct mmc_host_ops mmc_omap_ops = {
1139 .request = mmc_omap_request,
1140 .set_ios = mmc_omap_set_ios,
1141 .get_ro = mmc_omap_get_ro,
1144 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1146 struct mmc_omap_slot *slot = NULL;
1147 struct mmc_host *mmc;
1150 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1154 slot = mmc_priv(mmc);
1158 slot->pdata = &host->pdata->slots[id];
1160 host->slots[id] = slot;
1162 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_MMC_HIGHSPEED |
1163 MMC_CAP_SD_HIGHSPEED;
1164 if (host->pdata->conf.wire4)
1165 mmc->caps |= MMC_CAP_4_BIT_DATA;
1167 mmc->ops = &mmc_omap_ops;
1168 mmc->f_min = 400000;
1170 if (cpu_class_is_omap2())
1171 mmc->f_max = 48000000;
1173 mmc->f_max = 24000000;
1174 if (host->pdata->max_freq)
1175 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1176 mmc->ocr_avail = slot->pdata->ocr_mask;
1178 /* Use scatterlist DMA to reduce per-transfer costs.
1179 * NOTE max_seg_size assumption that small blocks aren't
1180 * normally used (except e.g. for reading SD registers).
1182 mmc->max_phys_segs = 32;
1183 mmc->max_hw_segs = 32;
1184 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1185 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1186 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1187 mmc->max_seg_size = mmc->max_req_size;
1189 r = mmc_add_host(mmc);
1193 if (slot->pdata->name != NULL) {
1194 r = device_create_file(&mmc->class_dev,
1195 &dev_attr_slot_name);
1197 goto err_remove_host;
1200 if (slot->pdata->get_cover_state != NULL) {
1201 r = device_create_file(&mmc->class_dev,
1202 &dev_attr_cover_switch);
1204 goto err_remove_slot_name;
1206 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1207 init_timer(&slot->switch_timer);
1208 slot->switch_timer.function = mmc_omap_switch_timer;
1209 slot->switch_timer.data = (unsigned long) slot;
1210 schedule_work(&slot->switch_work);
1213 if (slot->pdata->get_ro != NULL) {
1214 r = device_create_file(&mmc->class_dev,
1217 goto err_remove_cover_attr;
1222 err_remove_cover_attr:
1223 if (slot->pdata->get_cover_state != NULL)
1224 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1225 err_remove_slot_name:
1226 if (slot->pdata->name != NULL)
1227 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1229 mmc_remove_host(mmc);
1233 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1235 struct mmc_host *mmc = slot->mmc;
1237 if (slot->pdata->name != NULL)
1238 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1239 if (slot->pdata->get_cover_state != NULL)
1240 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1241 if (slot->pdata->get_ro != NULL)
1242 device_remove_file(&mmc->class_dev, &dev_attr_ro);
1244 del_timer_sync(&slot->switch_timer);
1245 flush_scheduled_work();
1247 mmc_remove_host(mmc);
1251 static int __init mmc_omap_probe(struct platform_device *pdev)
1253 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1254 struct mmc_omap_host *host = NULL;
1255 struct resource *res;
1259 if (pdata == NULL) {
1260 dev_err(&pdev->dev, "platform data missing\n");
1263 if (pdata->nr_slots == 0) {
1264 dev_err(&pdev->dev, "no slots\n");
1268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1269 irq = platform_get_irq(pdev, 0);
1270 if (res == NULL || irq < 0)
1273 res = request_mem_region(res->start, res->end - res->start + 1,
1278 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1281 goto err_free_mem_region;
1284 spin_lock_init(&host->dma_lock);
1285 init_timer(&host->dma_timer);
1286 spin_lock_init(&host->slot_lock);
1287 init_waitqueue_head(&host->slot_wq);
1289 host->dma_timer.function = mmc_omap_dma_timer;
1290 host->dma_timer.data = (unsigned long) host;
1292 host->pdata = pdata;
1293 host->dev = &pdev->dev;
1294 platform_set_drvdata(pdev, host);
1296 host->id = pdev->id;
1297 host->mem_res = res;
1304 host->phys_base = host->mem_res->start;
1305 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1307 if (cpu_is_omap24xx()) {
1308 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1309 if (IS_ERR(host->iclk))
1310 goto err_free_mmc_host;
1311 clk_enable(host->iclk);
1314 if (!cpu_is_omap24xx())
1315 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1317 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1319 if (IS_ERR(host->fclk)) {
1320 ret = PTR_ERR(host->fclk);
1324 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1328 if (pdata->init != NULL) {
1329 ret = pdata->init(&pdev->dev);
1334 host->nr_slots = pdata->nr_slots;
1335 for (i = 0; i < pdata->nr_slots; i++) {
1336 ret = mmc_omap_new_slot(host, i);
1339 mmc_omap_remove_slot(host->slots[i]);
1341 goto err_plat_cleanup;
1349 pdata->cleanup(&pdev->dev);
1351 free_irq(host->irq, host);
1353 clk_put(host->fclk);
1355 if (host->iclk != NULL) {
1356 clk_disable(host->iclk);
1357 clk_put(host->iclk);
1361 err_free_mem_region:
1362 release_mem_region(res->start, res->end - res->start + 1);
1366 static int mmc_omap_remove(struct platform_device *pdev)
1368 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1371 platform_set_drvdata(pdev, NULL);
1373 BUG_ON(host == NULL);
1375 for (i = 0; i < host->nr_slots; i++)
1376 mmc_omap_remove_slot(host->slots[i]);
1378 if (host->pdata->cleanup)
1379 host->pdata->cleanup(&pdev->dev);
1381 if (host->iclk && !IS_ERR(host->iclk))
1382 clk_put(host->iclk);
1383 if (host->fclk && !IS_ERR(host->fclk))
1384 clk_put(host->fclk);
1386 release_mem_region(pdev->resource[0].start,
1387 pdev->resource[0].end - pdev->resource[0].start + 1);
1395 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1398 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1400 if (host == NULL || host->suspended)
1403 for (i = 0; i < host->nr_slots; i++) {
1404 struct mmc_omap_slot *slot;
1406 slot = host->slots[i];
1407 ret = mmc_suspend_host(slot->mmc, mesg);
1410 slot = host->slots[i];
1411 mmc_resume_host(slot->mmc);
1416 host->suspended = 1;
1420 static int mmc_omap_resume(struct platform_device *pdev)
1423 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1425 if (host == NULL || !host->suspended)
1428 for (i = 0; i < host->nr_slots; i++) {
1429 struct mmc_omap_slot *slot;
1430 slot = host->slots[i];
1431 ret = mmc_resume_host(slot->mmc);
1435 host->suspended = 0;
1440 #define mmc_omap_suspend NULL
1441 #define mmc_omap_resume NULL
1444 static struct platform_driver mmc_omap_driver = {
1445 .probe = mmc_omap_probe,
1446 .remove = mmc_omap_remove,
1447 .suspend = mmc_omap_suspend,
1448 .resume = mmc_omap_resume,
1450 .name = DRIVER_NAME,
1454 static int __init mmc_omap_init(void)
1456 return platform_driver_register(&mmc_omap_driver);
1459 static void __exit mmc_omap_exit(void)
1461 platform_driver_unregister(&mmc_omap_driver);
1464 module_init(mmc_omap_init);
1465 module_exit(mmc_omap_exit);
1467 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1468 MODULE_LICENSE("GPL");
1469 MODULE_ALIAS(DRIVER_NAME);
1470 MODULE_AUTHOR("Juha Yrjölä");