2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/scatterlist.h>
18 #include <linux/mmc/host.h>
22 #define DRIVER_NAME "sdhci"
24 #define DBG(f, x...) \
25 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
27 static unsigned int debug_quirks = 0;
29 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
30 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
31 /* Controller doesn't like some resets when there is no card inserted. */
32 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
33 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
34 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
35 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
37 static const struct pci_device_id pci_ids[] __devinitdata = {
39 .vendor = PCI_VENDOR_ID_RICOH,
40 .device = PCI_DEVICE_ID_RICOH_R5C822,
41 .subvendor = PCI_VENDOR_ID_IBM,
42 .subdevice = PCI_ANY_ID,
43 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
44 SDHCI_QUIRK_FORCE_DMA,
48 .vendor = PCI_VENDOR_ID_RICOH,
49 .device = PCI_DEVICE_ID_RICOH_R5C822,
50 .subvendor = PCI_ANY_ID,
51 .subdevice = PCI_ANY_ID,
52 .driver_data = SDHCI_QUIRK_FORCE_DMA |
53 SDHCI_QUIRK_NO_CARD_NO_RESET,
57 .vendor = PCI_VENDOR_ID_TI,
58 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
59 .subvendor = PCI_ANY_ID,
60 .subdevice = PCI_ANY_ID,
61 .driver_data = SDHCI_QUIRK_FORCE_DMA,
65 .vendor = PCI_VENDOR_ID_ENE,
66 .device = PCI_DEVICE_ID_ENE_CB712_SD,
67 .subvendor = PCI_ANY_ID,
68 .subdevice = PCI_ANY_ID,
69 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
70 SDHCI_QUIRK_BROKEN_DMA,
74 .vendor = PCI_VENDOR_ID_ENE,
75 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
76 .subvendor = PCI_ANY_ID,
77 .subdevice = PCI_ANY_ID,
78 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
79 SDHCI_QUIRK_BROKEN_DMA,
83 .vendor = PCI_VENDOR_ID_ENE,
84 .device = PCI_DEVICE_ID_ENE_CB714_SD,
85 .subvendor = PCI_ANY_ID,
86 .subdevice = PCI_ANY_ID,
87 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
88 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
92 .vendor = PCI_VENDOR_ID_ENE,
93 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
94 .subvendor = PCI_ANY_ID,
95 .subdevice = PCI_ANY_ID,
96 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
100 { /* Generic SD host controller */
101 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
104 { /* end: all zeroes */ },
107 MODULE_DEVICE_TABLE(pci, pci_ids);
109 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
110 static void sdhci_finish_data(struct sdhci_host *);
112 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
113 static void sdhci_finish_command(struct sdhci_host *);
115 static void sdhci_dumpregs(struct sdhci_host *host)
117 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
119 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
120 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
121 readw(host->ioaddr + SDHCI_HOST_VERSION));
122 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
123 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
124 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
125 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
126 readl(host->ioaddr + SDHCI_ARGUMENT),
127 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
128 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_PRESENT_STATE),
130 readb(host->ioaddr + SDHCI_HOST_CONTROL));
131 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
132 readb(host->ioaddr + SDHCI_POWER_CONTROL),
133 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
134 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
135 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
136 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
137 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
138 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
139 readl(host->ioaddr + SDHCI_INT_STATUS));
140 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
141 readl(host->ioaddr + SDHCI_INT_ENABLE),
142 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
143 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
144 readw(host->ioaddr + SDHCI_ACMD12_ERR),
145 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
146 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
147 readl(host->ioaddr + SDHCI_CAPABILITIES),
148 readl(host->ioaddr + SDHCI_MAX_CURRENT));
150 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
153 /*****************************************************************************\
155 * Low level functions *
157 \*****************************************************************************/
159 static void sdhci_reset(struct sdhci_host *host, u8 mask)
161 unsigned long timeout;
163 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
164 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
169 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
171 if (mask & SDHCI_RESET_ALL)
174 /* Wait max 100 ms */
177 /* hw clears the bit when it's done */
178 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
180 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
181 mmc_hostname(host->mmc), (int)mask);
182 sdhci_dumpregs(host);
190 static void sdhci_init(struct sdhci_host *host)
194 sdhci_reset(host, SDHCI_RESET_ALL);
196 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
197 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
198 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
199 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
200 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
201 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
203 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
204 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
207 static void sdhci_activate_led(struct sdhci_host *host)
211 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
212 ctrl |= SDHCI_CTRL_LED;
213 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
216 static void sdhci_deactivate_led(struct sdhci_host *host)
220 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
221 ctrl &= ~SDHCI_CTRL_LED;
222 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
225 /*****************************************************************************\
229 \*****************************************************************************/
231 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
233 return sg_virt(host->cur_sg);
236 static inline int sdhci_next_sg(struct sdhci_host* host)
239 * Skip to next SG entry.
247 if (host->num_sg > 0) {
249 host->remain = host->cur_sg->length;
255 static void sdhci_read_block_pio(struct sdhci_host *host)
257 int blksize, chunk_remain;
262 DBG("PIO reading\n");
264 blksize = host->data->blksz;
268 buffer = sdhci_sg_to_buffer(host) + host->offset;
271 if (chunk_remain == 0) {
272 data = readl(host->ioaddr + SDHCI_BUFFER);
273 chunk_remain = min(blksize, 4);
276 size = min(host->remain, chunk_remain);
278 chunk_remain -= size;
280 host->offset += size;
281 host->remain -= size;
284 *buffer = data & 0xFF;
290 if (host->remain == 0) {
291 if (sdhci_next_sg(host) == 0) {
292 BUG_ON(blksize != 0);
295 buffer = sdhci_sg_to_buffer(host);
300 static void sdhci_write_block_pio(struct sdhci_host *host)
302 int blksize, chunk_remain;
307 DBG("PIO writing\n");
309 blksize = host->data->blksz;
314 buffer = sdhci_sg_to_buffer(host) + host->offset;
317 size = min(host->remain, chunk_remain);
319 chunk_remain -= size;
321 host->offset += size;
322 host->remain -= size;
326 data |= (u32)*buffer << 24;
331 if (chunk_remain == 0) {
332 writel(data, host->ioaddr + SDHCI_BUFFER);
333 chunk_remain = min(blksize, 4);
336 if (host->remain == 0) {
337 if (sdhci_next_sg(host) == 0) {
338 BUG_ON(blksize != 0);
341 buffer = sdhci_sg_to_buffer(host);
346 static void sdhci_transfer_pio(struct sdhci_host *host)
352 if (host->num_sg == 0)
355 if (host->data->flags & MMC_DATA_READ)
356 mask = SDHCI_DATA_AVAILABLE;
358 mask = SDHCI_SPACE_AVAILABLE;
360 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
361 if (host->data->flags & MMC_DATA_READ)
362 sdhci_read_block_pio(host);
364 sdhci_write_block_pio(host);
366 if (host->num_sg == 0)
370 DBG("PIO transfer complete.\n");
373 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
376 unsigned target_timeout, current_timeout;
384 BUG_ON(data->blksz * data->blocks > 524288);
385 BUG_ON(data->blksz > host->mmc->max_blk_size);
386 BUG_ON(data->blocks > 65535);
389 host->data_early = 0;
392 target_timeout = data->timeout_ns / 1000 +
393 data->timeout_clks / host->clock;
396 * Figure out needed cycles.
397 * We do this in steps in order to fit inside a 32 bit int.
398 * The first step is the minimum timeout, which will have a
399 * minimum resolution of 6 bits:
400 * (1) 2^13*1000 > 2^22,
401 * (2) host->timeout_clk < 2^16
406 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
407 while (current_timeout < target_timeout) {
409 current_timeout <<= 1;
415 printk(KERN_WARNING "%s: Too large timeout requested!\n",
416 mmc_hostname(host->mmc));
420 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
422 if (host->flags & SDHCI_USE_DMA) {
425 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
426 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
429 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
431 host->cur_sg = data->sg;
432 host->num_sg = data->sg_len;
435 host->remain = host->cur_sg->length;
438 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
439 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
440 host->ioaddr + SDHCI_BLOCK_SIZE);
441 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
444 static void sdhci_set_transfer_mode(struct sdhci_host *host,
445 struct mmc_data *data)
452 WARN_ON(!host->data);
454 mode = SDHCI_TRNS_BLK_CNT_EN;
455 if (data->blocks > 1)
456 mode |= SDHCI_TRNS_MULTI;
457 if (data->flags & MMC_DATA_READ)
458 mode |= SDHCI_TRNS_READ;
459 if (host->flags & SDHCI_USE_DMA)
460 mode |= SDHCI_TRNS_DMA;
462 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
465 static void sdhci_finish_data(struct sdhci_host *host)
467 struct mmc_data *data;
475 if (host->flags & SDHCI_USE_DMA) {
476 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
477 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
481 * Controller doesn't count down when in single block mode.
483 if (data->blocks == 1)
484 blocks = (data->error == 0) ? 0 : 1;
486 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
487 data->bytes_xfered = data->blksz * (data->blocks - blocks);
489 if (!data->error && blocks) {
490 printk(KERN_ERR "%s: Controller signalled completion even "
491 "though there were blocks left.\n",
492 mmc_hostname(host->mmc));
498 * The controller needs a reset of internal state machines
499 * upon error conditions.
502 sdhci_reset(host, SDHCI_RESET_CMD);
503 sdhci_reset(host, SDHCI_RESET_DATA);
506 sdhci_send_command(host, data->stop);
508 tasklet_schedule(&host->finish_tasklet);
511 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
515 unsigned long timeout;
522 mask = SDHCI_CMD_INHIBIT;
523 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
524 mask |= SDHCI_DATA_INHIBIT;
526 /* We shouldn't wait for data inihibit for stop commands, even
527 though they might use busy signaling */
528 if (host->mrq->data && (cmd == host->mrq->data->stop))
529 mask &= ~SDHCI_DATA_INHIBIT;
531 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
533 printk(KERN_ERR "%s: Controller never released "
534 "inhibit bit(s).\n", mmc_hostname(host->mmc));
535 sdhci_dumpregs(host);
537 tasklet_schedule(&host->finish_tasklet);
544 mod_timer(&host->timer, jiffies + 10 * HZ);
548 sdhci_prepare_data(host, cmd->data);
550 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
552 sdhci_set_transfer_mode(host, cmd->data);
554 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
555 printk(KERN_ERR "%s: Unsupported response type!\n",
556 mmc_hostname(host->mmc));
557 cmd->error = -EINVAL;
558 tasklet_schedule(&host->finish_tasklet);
562 if (!(cmd->flags & MMC_RSP_PRESENT))
563 flags = SDHCI_CMD_RESP_NONE;
564 else if (cmd->flags & MMC_RSP_136)
565 flags = SDHCI_CMD_RESP_LONG;
566 else if (cmd->flags & MMC_RSP_BUSY)
567 flags = SDHCI_CMD_RESP_SHORT_BUSY;
569 flags = SDHCI_CMD_RESP_SHORT;
571 if (cmd->flags & MMC_RSP_CRC)
572 flags |= SDHCI_CMD_CRC;
573 if (cmd->flags & MMC_RSP_OPCODE)
574 flags |= SDHCI_CMD_INDEX;
576 flags |= SDHCI_CMD_DATA;
578 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
579 host->ioaddr + SDHCI_COMMAND);
582 static void sdhci_finish_command(struct sdhci_host *host)
586 BUG_ON(host->cmd == NULL);
588 if (host->cmd->flags & MMC_RSP_PRESENT) {
589 if (host->cmd->flags & MMC_RSP_136) {
590 /* CRC is stripped so we need to do some shifting. */
591 for (i = 0;i < 4;i++) {
592 host->cmd->resp[i] = readl(host->ioaddr +
593 SDHCI_RESPONSE + (3-i)*4) << 8;
595 host->cmd->resp[i] |=
597 SDHCI_RESPONSE + (3-i)*4-1);
600 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
604 host->cmd->error = 0;
606 if (host->data && host->data_early)
607 sdhci_finish_data(host);
609 if (!host->cmd->data)
610 tasklet_schedule(&host->finish_tasklet);
615 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
619 unsigned long timeout;
621 if (clock == host->clock)
624 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
629 for (div = 1;div < 256;div *= 2) {
630 if ((host->max_clk / div) <= clock)
635 clk = div << SDHCI_DIVIDER_SHIFT;
636 clk |= SDHCI_CLOCK_INT_EN;
637 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
641 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
642 & SDHCI_CLOCK_INT_STABLE)) {
644 printk(KERN_ERR "%s: Internal clock never "
645 "stabilised.\n", mmc_hostname(host->mmc));
646 sdhci_dumpregs(host);
653 clk |= SDHCI_CLOCK_CARD_EN;
654 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
660 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
664 if (host->power == power)
667 if (power == (unsigned short)-1) {
668 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
673 * Spec says that we should clear the power reg before setting
674 * a new value. Some controllers don't seem to like this though.
676 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
677 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
679 pwr = SDHCI_POWER_ON;
681 switch (1 << power) {
682 case MMC_VDD_165_195:
683 pwr |= SDHCI_POWER_180;
687 pwr |= SDHCI_POWER_300;
691 pwr |= SDHCI_POWER_330;
697 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
703 /*****************************************************************************\
707 \*****************************************************************************/
709 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
711 struct sdhci_host *host;
714 host = mmc_priv(mmc);
716 spin_lock_irqsave(&host->lock, flags);
718 WARN_ON(host->mrq != NULL);
720 sdhci_activate_led(host);
724 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
725 host->mrq->cmd->error = -ENOMEDIUM;
726 tasklet_schedule(&host->finish_tasklet);
728 sdhci_send_command(host, mrq->cmd);
731 spin_unlock_irqrestore(&host->lock, flags);
734 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
736 struct sdhci_host *host;
740 host = mmc_priv(mmc);
742 spin_lock_irqsave(&host->lock, flags);
745 * Reset the chip on each power off.
746 * Should clear out any weird states.
748 if (ios->power_mode == MMC_POWER_OFF) {
749 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
753 sdhci_set_clock(host, ios->clock);
755 if (ios->power_mode == MMC_POWER_OFF)
756 sdhci_set_power(host, -1);
758 sdhci_set_power(host, ios->vdd);
760 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
762 if (ios->bus_width == MMC_BUS_WIDTH_4)
763 ctrl |= SDHCI_CTRL_4BITBUS;
765 ctrl &= ~SDHCI_CTRL_4BITBUS;
767 if (ios->timing == MMC_TIMING_SD_HS)
768 ctrl |= SDHCI_CTRL_HISPD;
770 ctrl &= ~SDHCI_CTRL_HISPD;
772 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
775 * Some (ENE) controllers go apeshit on some ios operation,
776 * signalling timeout and CRC errors even on CMD0. Resetting
777 * it on each ios seems to solve the problem.
779 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
780 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
783 spin_unlock_irqrestore(&host->lock, flags);
786 static int sdhci_get_ro(struct mmc_host *mmc)
788 struct sdhci_host *host;
792 host = mmc_priv(mmc);
794 spin_lock_irqsave(&host->lock, flags);
796 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
798 spin_unlock_irqrestore(&host->lock, flags);
800 return !(present & SDHCI_WRITE_PROTECT);
803 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
805 struct sdhci_host *host;
809 host = mmc_priv(mmc);
811 spin_lock_irqsave(&host->lock, flags);
813 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
815 ier &= ~SDHCI_INT_CARD_INT;
817 ier |= SDHCI_INT_CARD_INT;
819 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
820 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
824 spin_unlock_irqrestore(&host->lock, flags);
827 static const struct mmc_host_ops sdhci_ops = {
828 .request = sdhci_request,
829 .set_ios = sdhci_set_ios,
830 .get_ro = sdhci_get_ro,
831 .enable_sdio_irq = sdhci_enable_sdio_irq,
834 /*****************************************************************************\
838 \*****************************************************************************/
840 static void sdhci_tasklet_card(unsigned long param)
842 struct sdhci_host *host;
845 host = (struct sdhci_host*)param;
847 spin_lock_irqsave(&host->lock, flags);
849 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
851 printk(KERN_ERR "%s: Card removed during transfer!\n",
852 mmc_hostname(host->mmc));
853 printk(KERN_ERR "%s: Resetting controller.\n",
854 mmc_hostname(host->mmc));
856 sdhci_reset(host, SDHCI_RESET_CMD);
857 sdhci_reset(host, SDHCI_RESET_DATA);
859 host->mrq->cmd->error = -ENOMEDIUM;
860 tasklet_schedule(&host->finish_tasklet);
864 spin_unlock_irqrestore(&host->lock, flags);
866 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
869 static void sdhci_tasklet_finish(unsigned long param)
871 struct sdhci_host *host;
873 struct mmc_request *mrq;
875 host = (struct sdhci_host*)param;
877 spin_lock_irqsave(&host->lock, flags);
879 del_timer(&host->timer);
884 * The controller needs a reset of internal state machines
885 * upon error conditions.
887 if (mrq->cmd->error ||
888 (mrq->data && (mrq->data->error ||
889 (mrq->data->stop && mrq->data->stop->error)))) {
891 /* Some controllers need this kick or reset won't work here */
892 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
895 /* This is to force an update */
898 sdhci_set_clock(host, clock);
901 /* Spec says we should do both at the same time, but Ricoh
902 controllers do not like that. */
903 sdhci_reset(host, SDHCI_RESET_CMD);
904 sdhci_reset(host, SDHCI_RESET_DATA);
911 sdhci_deactivate_led(host);
914 spin_unlock_irqrestore(&host->lock, flags);
916 mmc_request_done(host->mmc, mrq);
919 static void sdhci_timeout_timer(unsigned long data)
921 struct sdhci_host *host;
924 host = (struct sdhci_host*)data;
926 spin_lock_irqsave(&host->lock, flags);
929 printk(KERN_ERR "%s: Timeout waiting for hardware "
930 "interrupt.\n", mmc_hostname(host->mmc));
931 sdhci_dumpregs(host);
934 host->data->error = -ETIMEDOUT;
935 sdhci_finish_data(host);
938 host->cmd->error = -ETIMEDOUT;
940 host->mrq->cmd->error = -ETIMEDOUT;
942 tasklet_schedule(&host->finish_tasklet);
947 spin_unlock_irqrestore(&host->lock, flags);
950 /*****************************************************************************\
952 * Interrupt handling *
954 \*****************************************************************************/
956 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
958 BUG_ON(intmask == 0);
961 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
962 "though no command operation was in progress.\n",
963 mmc_hostname(host->mmc), (unsigned)intmask);
964 sdhci_dumpregs(host);
968 if (intmask & SDHCI_INT_TIMEOUT)
969 host->cmd->error = -ETIMEDOUT;
970 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
972 host->cmd->error = -EILSEQ;
974 if (host->cmd->error)
975 tasklet_schedule(&host->finish_tasklet);
976 else if (intmask & SDHCI_INT_RESPONSE)
977 sdhci_finish_command(host);
980 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
982 BUG_ON(intmask == 0);
986 * A data end interrupt is sent together with the response
987 * for the stop command.
989 if (intmask & SDHCI_INT_DATA_END)
992 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
993 "though no data operation was in progress.\n",
994 mmc_hostname(host->mmc), (unsigned)intmask);
995 sdhci_dumpregs(host);
1000 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1001 host->data->error = -ETIMEDOUT;
1002 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1003 host->data->error = -EILSEQ;
1005 if (host->data->error)
1006 sdhci_finish_data(host);
1008 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1009 sdhci_transfer_pio(host);
1012 * We currently don't do anything fancy with DMA
1013 * boundaries, but as we can't disable the feature
1014 * we need to at least restart the transfer.
1016 if (intmask & SDHCI_INT_DMA_END)
1017 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1018 host->ioaddr + SDHCI_DMA_ADDRESS);
1020 if (intmask & SDHCI_INT_DATA_END) {
1023 * Data managed to finish before the
1024 * command completed. Make sure we do
1025 * things in the proper order.
1027 host->data_early = 1;
1029 sdhci_finish_data(host);
1035 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1038 struct sdhci_host* host = dev_id;
1042 spin_lock(&host->lock);
1044 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1046 if (!intmask || intmask == 0xffffffff) {
1051 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1053 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1054 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1055 host->ioaddr + SDHCI_INT_STATUS);
1056 tasklet_schedule(&host->card_tasklet);
1059 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1061 if (intmask & SDHCI_INT_CMD_MASK) {
1062 writel(intmask & SDHCI_INT_CMD_MASK,
1063 host->ioaddr + SDHCI_INT_STATUS);
1064 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1067 if (intmask & SDHCI_INT_DATA_MASK) {
1068 writel(intmask & SDHCI_INT_DATA_MASK,
1069 host->ioaddr + SDHCI_INT_STATUS);
1070 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1073 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1075 intmask &= ~SDHCI_INT_ERROR;
1077 if (intmask & SDHCI_INT_BUS_POWER) {
1078 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1079 mmc_hostname(host->mmc));
1080 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1083 intmask &= ~SDHCI_INT_BUS_POWER;
1085 if (intmask & SDHCI_INT_CARD_INT)
1088 intmask &= ~SDHCI_INT_CARD_INT;
1091 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1092 mmc_hostname(host->mmc), intmask);
1093 sdhci_dumpregs(host);
1095 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1098 result = IRQ_HANDLED;
1102 spin_unlock(&host->lock);
1105 * We have to delay this as it calls back into the driver.
1108 mmc_signal_sdio_irq(host->mmc);
1113 /*****************************************************************************\
1117 \*****************************************************************************/
1121 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1123 struct sdhci_chip *chip;
1126 chip = pci_get_drvdata(pdev);
1130 DBG("Suspending...\n");
1132 for (i = 0;i < chip->num_slots;i++) {
1133 if (!chip->hosts[i])
1135 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1137 for (i--;i >= 0;i--)
1138 mmc_resume_host(chip->hosts[i]->mmc);
1143 pci_save_state(pdev);
1144 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1146 for (i = 0;i < chip->num_slots;i++) {
1147 if (!chip->hosts[i])
1149 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1152 pci_disable_device(pdev);
1153 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1158 static int sdhci_resume (struct pci_dev *pdev)
1160 struct sdhci_chip *chip;
1163 chip = pci_get_drvdata(pdev);
1167 DBG("Resuming...\n");
1169 pci_set_power_state(pdev, PCI_D0);
1170 pci_restore_state(pdev);
1171 ret = pci_enable_device(pdev);
1175 for (i = 0;i < chip->num_slots;i++) {
1176 if (!chip->hosts[i])
1178 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1179 pci_set_master(pdev);
1180 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1181 IRQF_SHARED, chip->hosts[i]->slot_descr,
1185 sdhci_init(chip->hosts[i]);
1187 ret = mmc_resume_host(chip->hosts[i]->mmc);
1195 #else /* CONFIG_PM */
1197 #define sdhci_suspend NULL
1198 #define sdhci_resume NULL
1200 #endif /* CONFIG_PM */
1202 /*****************************************************************************\
1204 * Device probing/removal *
1206 \*****************************************************************************/
1208 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1211 unsigned int version;
1212 struct sdhci_chip *chip;
1213 struct mmc_host *mmc;
1214 struct sdhci_host *host;
1219 chip = pci_get_drvdata(pdev);
1222 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1226 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1228 if (first_bar > 5) {
1229 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1233 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1234 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1238 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1239 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1240 "You may experience problems.\n");
1243 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1244 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1248 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1249 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1253 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1257 host = mmc_priv(mmc);
1261 chip->hosts[slot] = host;
1263 host->bar = first_bar + slot;
1265 host->addr = pci_resource_start(pdev, host->bar);
1266 host->irq = pdev->irq;
1268 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1270 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1272 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1276 host->ioaddr = ioremap_nocache(host->addr,
1277 pci_resource_len(pdev, host->bar));
1278 if (!host->ioaddr) {
1283 sdhci_reset(host, SDHCI_RESET_ALL);
1285 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1286 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1288 printk(KERN_ERR "%s: Unknown controller version (%d). "
1289 "You may experience problems.\n", host->slot_descr,
1293 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1295 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1296 host->flags |= SDHCI_USE_DMA;
1297 else if (!(caps & SDHCI_CAN_DO_DMA))
1298 DBG("Controller doesn't have DMA capability\n");
1300 host->flags |= SDHCI_USE_DMA;
1302 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1303 (host->flags & SDHCI_USE_DMA)) {
1304 DBG("Disabling DMA as it is marked broken");
1305 host->flags &= ~SDHCI_USE_DMA;
1308 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1309 (host->flags & SDHCI_USE_DMA)) {
1310 printk(KERN_WARNING "%s: Will use DMA "
1311 "mode even though HW doesn't fully "
1312 "claim to support it.\n", host->slot_descr);
1315 if (host->flags & SDHCI_USE_DMA) {
1316 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1317 printk(KERN_WARNING "%s: No suitable DMA available. "
1318 "Falling back to PIO.\n", host->slot_descr);
1319 host->flags &= ~SDHCI_USE_DMA;
1323 if (host->flags & SDHCI_USE_DMA)
1324 pci_set_master(pdev);
1325 else /* XXX: Hack to get MMC layer to avoid highmem */
1329 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1330 if (host->max_clk == 0) {
1331 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1332 "frequency.\n", host->slot_descr);
1336 host->max_clk *= 1000000;
1339 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1340 if (host->timeout_clk == 0) {
1341 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1342 "frequency.\n", host->slot_descr);
1346 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1347 host->timeout_clk *= 1000;
1350 * Set host parameters.
1352 mmc->ops = &sdhci_ops;
1353 mmc->f_min = host->max_clk / 256;
1354 mmc->f_max = host->max_clk;
1355 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1357 if (caps & SDHCI_CAN_DO_HISPD)
1358 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1361 if (caps & SDHCI_CAN_VDD_330)
1362 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1363 if (caps & SDHCI_CAN_VDD_300)
1364 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1365 if (caps & SDHCI_CAN_VDD_180)
1366 mmc->ocr_avail |= MMC_VDD_165_195;
1368 if (mmc->ocr_avail == 0) {
1369 printk(KERN_ERR "%s: Hardware doesn't report any "
1370 "support voltages.\n", host->slot_descr);
1375 spin_lock_init(&host->lock);
1378 * Maximum number of segments. Hardware cannot do scatter lists.
1380 if (host->flags & SDHCI_USE_DMA)
1381 mmc->max_hw_segs = 1;
1383 mmc->max_hw_segs = 16;
1384 mmc->max_phys_segs = 16;
1387 * Maximum number of sectors in one transfer. Limited by DMA boundary
1390 mmc->max_req_size = 524288;
1393 * Maximum segment size. Could be one segment with the maximum number
1396 mmc->max_seg_size = mmc->max_req_size;
1399 * Maximum block size. This varies from controller to controller and
1400 * is specified in the capabilities register.
1402 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1403 if (mmc->max_blk_size >= 3) {
1404 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1406 mmc->max_blk_size = 512;
1408 mmc->max_blk_size = 512 << mmc->max_blk_size;
1411 * Maximum block count.
1413 mmc->max_blk_count = 65535;
1418 tasklet_init(&host->card_tasklet,
1419 sdhci_tasklet_card, (unsigned long)host);
1420 tasklet_init(&host->finish_tasklet,
1421 sdhci_tasklet_finish, (unsigned long)host);
1423 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1425 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1426 host->slot_descr, host);
1432 #ifdef CONFIG_MMC_DEBUG
1433 sdhci_dumpregs(host);
1440 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1441 host->addr, host->irq,
1442 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1447 tasklet_kill(&host->card_tasklet);
1448 tasklet_kill(&host->finish_tasklet);
1450 iounmap(host->ioaddr);
1452 pci_release_region(pdev, host->bar);
1459 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1461 struct sdhci_chip *chip;
1462 struct mmc_host *mmc;
1463 struct sdhci_host *host;
1465 chip = pci_get_drvdata(pdev);
1466 host = chip->hosts[slot];
1469 chip->hosts[slot] = NULL;
1471 mmc_remove_host(mmc);
1473 sdhci_reset(host, SDHCI_RESET_ALL);
1475 free_irq(host->irq, host);
1477 del_timer_sync(&host->timer);
1479 tasklet_kill(&host->card_tasklet);
1480 tasklet_kill(&host->finish_tasklet);
1482 iounmap(host->ioaddr);
1484 pci_release_region(pdev, host->bar);
1489 static int __devinit sdhci_probe(struct pci_dev *pdev,
1490 const struct pci_device_id *ent)
1494 struct sdhci_chip *chip;
1496 BUG_ON(pdev == NULL);
1497 BUG_ON(ent == NULL);
1499 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1501 printk(KERN_INFO DRIVER_NAME
1502 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1503 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1506 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1510 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1511 DBG("found %d slot(s)\n", slots);
1515 ret = pci_enable_device(pdev);
1519 chip = kzalloc(sizeof(struct sdhci_chip) +
1520 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1527 chip->quirks = ent->driver_data;
1530 chip->quirks = debug_quirks;
1532 chip->num_slots = slots;
1533 pci_set_drvdata(pdev, chip);
1535 for (i = 0;i < slots;i++) {
1536 ret = sdhci_probe_slot(pdev, i);
1538 for (i--;i >= 0;i--)
1539 sdhci_remove_slot(pdev, i);
1547 pci_set_drvdata(pdev, NULL);
1551 pci_disable_device(pdev);
1555 static void __devexit sdhci_remove(struct pci_dev *pdev)
1558 struct sdhci_chip *chip;
1560 chip = pci_get_drvdata(pdev);
1563 for (i = 0;i < chip->num_slots;i++)
1564 sdhci_remove_slot(pdev, i);
1566 pci_set_drvdata(pdev, NULL);
1571 pci_disable_device(pdev);
1574 static struct pci_driver sdhci_driver = {
1575 .name = DRIVER_NAME,
1576 .id_table = pci_ids,
1577 .probe = sdhci_probe,
1578 .remove = __devexit_p(sdhci_remove),
1579 .suspend = sdhci_suspend,
1580 .resume = sdhci_resume,
1583 /*****************************************************************************\
1585 * Driver init/exit *
1587 \*****************************************************************************/
1589 static int __init sdhci_drv_init(void)
1591 printk(KERN_INFO DRIVER_NAME
1592 ": Secure Digital Host Controller Interface driver\n");
1593 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1595 return pci_register_driver(&sdhci_driver);
1598 static void __exit sdhci_drv_exit(void)
1602 pci_unregister_driver(&sdhci_driver);
1605 module_init(sdhci_drv_init);
1606 module_exit(sdhci_drv_exit);
1608 module_param(debug_quirks, uint, 0444);
1610 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1611 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1612 MODULE_LICENSE("GPL");
1614 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");