drivers/mtd/nand/davinci_nand.c

   1 /*
   2  * davinci_nand.c - NAND Flash Driver for DaVinci family chips
   3  *
   4  * Copyright © 2006 Texas Instruments.
   5  *
   6  * Port to 2.6.23 Copyright © 2008 by:
   7  *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
   8  *   Troy Kisky <troy.kisky@boundarydevices.com>
   9  *   Dirk Behme <Dirk.Behme@gmail.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/init.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/err.h>
  31 #include <linux/clk.h>
  32 #include <linux/io.h>
  33 #include <linux/mtd/nand.h>
  34 #include <linux/mtd/partitions.h>
  35
  36 #include <mach/nand.h>
  37
  38 #include <asm/mach-types.h>
  39
  40
  41 #ifdef CONFIG_MTD_PARTITIONS
  42 static inline int mtd_has_partitions(void) { return 1; }
  43 #else
  44 static inline int mtd_has_partitions(void) { return 0; }
  45 #endif
  46
  47 #ifdef CONFIG_MTD_CMDLINE_PARTS
  48 static inline int mtd_has_cmdlinepart(void) { return 1; }
  49 #else
  50 static inline int mtd_has_cmdlinepart(void) { return 0; }
  51 #endif
  52
  53
  54 /*
  55  * This is a device driver for the NAND flash controller found on the
  56  * various DaVinci family chips.  It handles up to four SoC chipselects,
  57  * and some flavors of secondary chipselect (e.g. based on A12) as used
  58  * with multichip packages.
  59  *
  60  * The 1-bit ECC hardware is supported, but not yet the newer 4-bit ECC
  61  * available on chips like the DM355 and OMAP-L137 and needed with the
  62  * more error-prone MLC NAND chips.
  63  *
  64  * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
  65  * outputs in a "wire-AND" configuration, with no per-chip signals.
  66  */
  67 struct davinci_nand_info {
  68         struct mtd_info         mtd;
  69         struct nand_chip        chip;
  70
  71         struct device           *dev;
  72         struct clk              *clk;
  73         bool                    partitioned;
  74
  75         void __iomem            *base;
  76         void __iomem            *vaddr;
  77
  78         uint32_t                ioaddr;
  79         uint32_t                current_cs;
  80
  81         uint32_t                mask_chipsel;
  82         uint32_t                mask_ale;
  83         uint32_t                mask_cle;
  84
  85         uint32_t                core_chipsel;
  86 };
  87
  88 static DEFINE_SPINLOCK(davinci_nand_lock);
  89
  90 #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
  91
  92
  93 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
  94                 int offset)
  95 {
  96         return __raw_readl(info->base + offset);
  97 }
  98
  99 static inline void davinci_nand_writel(struct davinci_nand_info *info,
 100                 int offset, unsigned long value)
 101 {
 102         __raw_writel(value, info->base + offset);
 103 }
 104
 105 /*----------------------------------------------------------------------*/
 106
 107 /*
 108  * Access to hardware control lines:  ALE, CLE, secondary chipselect.
 109  */
 110
 111 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
 112                                    unsigned int ctrl)
 113 {
 114         struct davinci_nand_info        *info = to_davinci_nand(mtd);
 115         uint32_t                        addr = info->current_cs;
 116         struct nand_chip                *nand = mtd->priv;
 117
 118         /* Did the control lines change? */
 119         if (ctrl & NAND_CTRL_CHANGE) {
 120                 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
 121                         addr |= info->mask_cle;
 122                 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
 123                         addr |= info->mask_ale;
 124
 125                 nand->IO_ADDR_W = (void __iomem __force *)addr;
 126         }
 127
 128         if (cmd != NAND_CMD_NONE)
 129                 iowrite8(cmd, nand->IO_ADDR_W);
 130 }
 131
 132 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
 133 {
 134         struct davinci_nand_info        *info = to_davinci_nand(mtd);
 135         uint32_t                        addr = info->ioaddr;
 136
 137         /* maybe kick in a second chipselect */
 138         if (chip > 0)
 139                 addr |= info->mask_chipsel;
 140         info->current_cs = addr;
 141
 142         info->chip.IO_ADDR_W = (void __iomem __force *)addr;
 143         info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
 144 }
 145
 146 /*----------------------------------------------------------------------*/
 147
 148 /*
 149  * 1-bit hardware ECC ... context maintained for each core chipselect
 150  */
 151
 152 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
 153 {
 154         struct davinci_nand_info *info = to_davinci_nand(mtd);
 155
 156         return davinci_nand_readl(info, NANDF1ECC_OFFSET
 157                         + 4 * info->core_chipsel);
 158 }
 159
 160 static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
 161 {
 162         struct davinci_nand_info *info;
 163         uint32_t nandcfr;
 164         unsigned long flags;
 165
 166         info = to_davinci_nand(mtd);
 167
 168         /* Reset ECC hardware */
 169         nand_davinci_readecc_1bit(mtd);
 170
 171         spin_lock_irqsave(&davinci_nand_lock, flags);
 172
 173         /* Restart ECC hardware */
 174         nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
 175         nandcfr |= BIT(8 + info->core_chipsel);
 176         davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
 177
 178         spin_unlock_irqrestore(&davinci_nand_lock, flags);
 179 }
 180
 181 /*
 182  * Read hardware ECC value and pack into three bytes
 183  */
 184 static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
 185                                       const u_char *dat, u_char *ecc_code)
 186 {
 187         unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
 188         unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
 189
 190         /* invert so that erased block ecc is correct */
 191         ecc24 = ~ecc24;
 192         ecc_code[0] = (u_char)(ecc24);
 193         ecc_code[1] = (u_char)(ecc24 >> 8);
 194         ecc_code[2] = (u_char)(ecc24 >> 16);
 195
 196         return 0;
 197 }
 198
 199 static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
 200                                      u_char *read_ecc, u_char *calc_ecc)
 201 {
 202         struct nand_chip *chip = mtd->priv;
 203         uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
 204                                           (read_ecc[2] << 16);
 205         uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
 206                                           (calc_ecc[2] << 16);
 207         uint32_t diff = eccCalc ^ eccNand;
 208
 209         if (diff) {
 210                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
 211                         /* Correctable error */
 212                         if ((diff >> (12 + 3)) < chip->ecc.size) {
 213                                 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
 214                                 return 1;
 215                         } else {
 216                                 return -1;
 217                         }
 218                 } else if (!(diff & (diff - 1))) {
 219                         /* Single bit ECC error in the ECC itself,
 220                          * nothing to fix */
 221                         return 1;
 222                 } else {
 223                         /* Uncorrectable error */
 224                         return -1;
 225                 }
 226
 227         }
 228         return 0;
 229 }
 230
 231 /*----------------------------------------------------------------------*/
 232
 233 /*
 234  * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
 235  * how these chips are normally wired.  This translates to both 8 and 16
 236  * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
 237  *
 238  * For now we assume that configuration, or any other one which ignores
 239  * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
 240  * and have that transparently morphed into multiple NAND operations.
 241  */
 242 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 243 {
 244         struct nand_chip *chip = mtd->priv;
 245
 246         if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
 247                 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
 248         else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
 249                 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
 250         else
 251                 ioread8_rep(chip->IO_ADDR_R, buf, len);
 252 }
 253
 254 static void nand_davinci_write_buf(struct mtd_info *mtd,
 255                 const uint8_t *buf, int len)
 256 {
 257         struct nand_chip *chip = mtd->priv;
 258
 259         if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
 260                 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
 261         else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
 262                 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
 263         else
 264                 iowrite8_rep(chip->IO_ADDR_R, buf, len);
 265 }
 266
 267 /*
 268  * Check hardware register for wait status. Returns 1 if device is ready,
 269  * 0 if it is still busy.
 270  */
 271 static int nand_davinci_dev_ready(struct mtd_info *mtd)
 272 {
 273         struct davinci_nand_info *info = to_davinci_nand(mtd);
 274
 275         return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
 276 }
 277
 278 static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info)
 279 {
 280         uint32_t regval, a1cr;
 281
 282         /*
 283          * NAND FLASH timings @ PLL1 == 459 MHz
 284          *  - AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz
 285          *  - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
 286          */
 287         regval = 0
 288                 | (0 << 31)           /* selectStrobe */
 289                 | (0 << 30)           /* extWait (never with NAND) */
 290                 | (1 << 26)           /* writeSetup      10 ns */
 291                 | (3 << 20)           /* writeStrobe     40 ns */
 292                 | (1 << 17)           /* writeHold       10 ns */
 293                 | (0 << 13)           /* readSetup       10 ns */
 294                 | (3 << 7)            /* readStrobe      60 ns */
 295                 | (0 << 4)            /* readHold        10 ns */
 296                 | (3 << 2)            /* turnAround      ?? ns */
 297                 | (0 << 0)            /* asyncSize       8-bit bus */
 298                 ;
 299         a1cr = davinci_nand_readl(info, A1CR_OFFSET);
 300         if (a1cr != regval) {
 301                 dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \
 302                        "reg to 0x%08x, was 0x%08x, should be done by " \
 303                        "bootloader.\n", regval, a1cr);
 304                 davinci_nand_writel(info, A1CR_OFFSET, regval);
 305         }
 306 }
 307
 308 /*----------------------------------------------------------------------*/
 309
 310 static int __init nand_davinci_probe(struct platform_device *pdev)
 311 {
 312         struct davinci_nand_pdata       *pdata = pdev->dev.platform_data;
 313         struct davinci_nand_info        *info;
 314         struct resource                 *res1;
 315         struct resource                 *res2;
 316         void __iomem                    *vaddr;
 317         void __iomem                    *base;
 318         int                             ret;
 319         uint32_t                        val;
 320         nand_ecc_modes_t                ecc_mode;
 321
 322         /* which external chipselect will we be managing? */
 323         if (pdev->id < 0 || pdev->id > 3)
 324                 return -ENODEV;
 325
 326         info = kzalloc(sizeof(*info), GFP_KERNEL);
 327         if (!info) {
 328                 dev_err(&pdev->dev, "unable to allocate memory\n");
 329                 ret = -ENOMEM;
 330                 goto err_nomem;
 331         }
 332
 333         platform_set_drvdata(pdev, info);
 334
 335         res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 336         res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 337         if (!res1 || !res2) {
 338                 dev_err(&pdev->dev, "resource missing\n");
 339                 ret = -EINVAL;
 340                 goto err_nomem;
 341         }
 342
 343         vaddr = ioremap(res1->start, res1->end - res1->start);
 344         base = ioremap(res2->start, res2->end - res2->start);
 345         if (!vaddr || !base) {
 346                 dev_err(&pdev->dev, "ioremap failed\n");
 347                 ret = -EINVAL;
 348                 goto err_ioremap;
 349         }
 350
 351         info->dev               = &pdev->dev;
 352         info->base              = base;
 353         info->vaddr             = vaddr;
 354
 355         info->mtd.priv          = &info->chip;
 356         info->mtd.name          = dev_name(&pdev->dev);
 357         info->mtd.owner         = THIS_MODULE;
 358
 359         info->chip.IO_ADDR_R    = vaddr;
 360         info->chip.IO_ADDR_W    = vaddr;
 361         info->chip.chip_delay   = 0;
 362         info->chip.select_chip  = nand_davinci_select_chip;
 363
 364         /* options such as NAND_USE_FLASH_BBT or 16-bit widths */
 365         info->chip.options      = pdata ? pdata->options : 0;
 366
 367         info->ioaddr            = (uint32_t __force) vaddr;
 368
 369         info->current_cs        = info->ioaddr;
 370         info->core_chipsel      = pdev->id;
 371         info->mask_chipsel      = pdata->mask_chipsel;
 372
 373         /* use nandboot-capable ALE/CLE masks by default */
 374         if (pdata && pdata->mask_ale)
 375                 info->mask_ale  = pdata->mask_cle;
 376         else
 377                 info->mask_ale  = MASK_ALE;
 378         if (pdata && pdata->mask_cle)
 379                 info->mask_cle  = pdata->mask_cle;
 380         else
 381                 info->mask_cle  = MASK_CLE;
 382
 383         /* Set address of hardware control function */
 384         info->chip.cmd_ctrl     = nand_davinci_hwcontrol;
 385         info->chip.dev_ready    = nand_davinci_dev_ready;
 386
 387         /* Speed up buffer I/O */
 388         info->chip.read_buf     = nand_davinci_read_buf;
 389         info->chip.write_buf    = nand_davinci_write_buf;
 390
 391         /* use board-specific ECC config; else, the best available */
 392         if (pdata)
 393                 ecc_mode = pdata->ecc_mode;
 394         else
 395                 ecc_mode = NAND_ECC_HW;
 396
 397         switch (ecc_mode) {
 398         case NAND_ECC_NONE:
 399         case NAND_ECC_SOFT:
 400                 break;
 401         case NAND_ECC_HW:
 402                 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
 403                 info->chip.ecc.correct = nand_davinci_correct_1bit;
 404                 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
 405                 info->chip.ecc.size = 512;
 406                 info->chip.ecc.bytes = 3;
 407                 break;
 408         case NAND_ECC_HW_SYNDROME:
 409                 /* FIXME implement */
 410                 info->chip.ecc.size = 512;
 411                 info->chip.ecc.bytes = 10;
 412
 413                 dev_warn(&pdev->dev, "4-bit ECC nyet supported\n");
 414                 /* FALL THROUGH */
 415         default:
 416                 ret = -EINVAL;
 417                 goto err_ecc;
 418         }
 419         info->chip.ecc.mode = ecc_mode;
 420
 421         info->clk = clk_get(&pdev->dev, "AEMIFCLK");
 422         if (IS_ERR(info->clk)) {
 423                 ret = PTR_ERR(info->clk);
 424                 dev_dbg(&pdev->dev, "unable to get AEMIFCLK, err %d\n", ret);
 425                 goto err_clk;
 426         }
 427
 428         ret = clk_enable(info->clk);
 429         if (ret < 0) {
 430                 dev_dbg(&pdev->dev, "unable to enable AEMIFCLK, err %d\n", ret);
 431                 goto err_clk_enable;
 432         }
 433
 434         /* EMIF timings should normally be set by the boot loader,
 435          * especially after boot-from-NAND.  The *only* reason to
 436          * have this special casing for the DM6446 EVM is to work
 437          * with boot-from-NOR ... with CS0 manually re-jumpered
 438          * (after startup) so it addresses the NAND flash, not NOR.
 439          * Even for dev boards, that's unusually rude...
 440          */
 441         if (machine_is_davinci_evm())
 442                 nand_dm6446evm_flash_init(info);
 443
 444         spin_lock_irq(&davinci_nand_lock);
 445
 446         /* put CSxNAND into NAND mode */
 447         val = davinci_nand_readl(info, NANDFCR_OFFSET);
 448         val |= BIT(info->core_chipsel);
 449         davinci_nand_writel(info, NANDFCR_OFFSET, val);
 450
 451         spin_unlock_irq(&davinci_nand_lock);
 452
 453         /* Scan to find existence of the device(s) */
 454         ret = nand_scan(&info->mtd, pdata->mask_chipsel ? 2 : 1);
 455         if (ret < 0) {
 456                 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
 457                 goto err_scan;
 458         }
 459
 460         if (mtd_has_partitions()) {
 461                 struct mtd_partition    *mtd_parts = NULL;
 462                 int                     mtd_parts_nb = 0;
 463
 464                 if (mtd_has_cmdlinepart()) {
 465                         static const char *probes[] __initconst =
 466                                 { "cmdlinepart", NULL };
 467
 468                         const char              *master_name;
 469
 470                         /* Set info->mtd.name = 0 temporarily */
 471                         master_name             = info->mtd.name;
 472                         info->mtd.name          = (char *)0;
 473
 474                         /* info->mtd.name == 0, means: don't bother checking
 475                            <mtd-id> */
 476                         mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
 477                                                             &mtd_parts, 0);
 478
 479                         /* Restore info->mtd.name */
 480                         info->mtd.name = master_name;
 481                 }
 482
 483                 if (mtd_parts_nb <= 0 && pdata) {
 484                         mtd_parts = pdata->parts;
 485                         mtd_parts_nb = pdata->nr_parts;
 486                 }
 487
 488                 /* Register any partitions */
 489                 if (mtd_parts_nb > 0) {
 490                         ret = add_mtd_partitions(&info->mtd,
 491                                         mtd_parts, mtd_parts_nb);
 492                         if (ret == 0)
 493                                 info->partitioned = true;
 494                 }
 495
 496         } else if (pdata && pdata->nr_parts) {
 497                 dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
 498                                 pdata->nr_parts, info->mtd.name);
 499         }
 500
 501         /* If there's no partition info, just package the whole chip
 502          * as a single MTD device.
 503          */
 504         if (!info->partitioned)
 505                 ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;
 506
 507         if (ret < 0)
 508                 goto err_scan;
 509
 510         val = davinci_nand_readl(info, NRCSR_OFFSET);
 511         dev_info(&pdev->dev, "controller rev. %d.%d\n",
 512                (val >> 8) & 0xff, val & 0xff);
 513
 514         return 0;
 515
 516 err_scan:
 517         clk_disable(info->clk);
 518
 519 err_clk_enable:
 520         clk_put(info->clk);
 521
 522 err_ecc:
 523 err_clk:
 524 err_ioremap:
 525         if (base)
 526                 iounmap(base);
 527         if (vaddr)
 528                 iounmap(vaddr);
 529
 530 err_nomem:
 531         kfree(info);
 532         return ret;
 533 }
 534
 535 static int __exit nand_davinci_remove(struct platform_device *pdev)
 536 {
 537         struct davinci_nand_info *info = platform_get_drvdata(pdev);
 538         int status;
 539
 540         if (mtd_has_partitions() && info->partitioned)
 541                 status = del_mtd_partitions(&info->mtd);
 542         else
 543                 status = del_mtd_device(&info->mtd);
 544
 545         iounmap(info->base);
 546         iounmap(info->vaddr);
 547
 548         nand_release(&info->mtd);
 549
 550         clk_disable(info->clk);
 551         clk_put(info->clk);
 552
 553         kfree(info);
 554
 555         return 0;
 556 }
 557
 558 static struct platform_driver nand_davinci_driver = {
 559         .remove         = __exit_p(nand_davinci_remove),
 560         .driver         = {
 561                 .name   = "davinci_nand",
 562         },
 563 };
 564 MODULE_ALIAS("platform:davinci_nand");
 565
 566 static int __init nand_davinci_init(void)
 567 {
 568         return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
 569 }
 570 module_init(nand_davinci_init);
 571
 572 static void __exit nand_davinci_exit(void)
 573 {
 574         platform_driver_unregister(&nand_davinci_driver);
 575 }
 576 module_exit(nand_davinci_exit);
 577
 578 MODULE_LICENSE("GPL");
 579 MODULE_AUTHOR("Texas Instruments");
 580 MODULE_DESCRIPTION("Davinci NAND flash driver");
 581