2 * drivers/mtd/nand/omap2.c
4 * Copyright (c) 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
5 * Copyright (c) 2004 Micron Technology Inc.
6 * Copyright (c) 2004 David Brownell
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
23 #include <mach/gpmc.h>
24 #include <mach/nand.h>
26 #define GPMC_IRQ_STATUS 0x18
27 #define GPMC_ECC_CONFIG 0x1F4
28 #define GPMC_ECC_CONTROL 0x1F8
29 #define GPMC_ECC_SIZE_CONFIG 0x1FC
30 #define GPMC_ECC1_RESULT 0x200
32 #define DRIVER_NAME "omap2-nand"
33 #define NAND_IO_SIZE SZ_4K
37 #define NAND_WP_BIT 0x00000010
38 #define WR_RD_PIN_MONITORING 0x00600000
40 #define GPMC_BUF_FULL 0x00000001
41 #define GPMC_BUF_EMPTY 0x00000000
43 #define NAND_Ecc_P1e (1 << 0)
44 #define NAND_Ecc_P2e (1 << 1)
45 #define NAND_Ecc_P4e (1 << 2)
46 #define NAND_Ecc_P8e (1 << 3)
47 #define NAND_Ecc_P16e (1 << 4)
48 #define NAND_Ecc_P32e (1 << 5)
49 #define NAND_Ecc_P64e (1 << 6)
50 #define NAND_Ecc_P128e (1 << 7)
51 #define NAND_Ecc_P256e (1 << 8)
52 #define NAND_Ecc_P512e (1 << 9)
53 #define NAND_Ecc_P1024e (1 << 10)
54 #define NAND_Ecc_P2048e (1 << 11)
56 #define NAND_Ecc_P1o (1 << 16)
57 #define NAND_Ecc_P2o (1 << 17)
58 #define NAND_Ecc_P4o (1 << 18)
59 #define NAND_Ecc_P8o (1 << 19)
60 #define NAND_Ecc_P16o (1 << 20)
61 #define NAND_Ecc_P32o (1 << 21)
62 #define NAND_Ecc_P64o (1 << 22)
63 #define NAND_Ecc_P128o (1 << 23)
64 #define NAND_Ecc_P256o (1 << 24)
65 #define NAND_Ecc_P512o (1 << 25)
66 #define NAND_Ecc_P1024o (1 << 26)
67 #define NAND_Ecc_P2048o (1 << 27)
69 #define TF(value) (value ? 1 : 0)
71 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
72 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
73 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
74 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
75 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
76 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
77 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
78 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
80 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
81 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
82 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
83 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
84 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
85 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
86 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
87 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
89 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
90 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
91 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
92 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
93 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
94 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
95 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
96 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
98 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
99 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
100 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
101 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
102 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
103 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
104 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
105 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
107 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
108 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
110 #ifdef CONFIG_MTD_PARTITIONS
111 static const char *part_probes[] = { "cmdlinepart", NULL };
114 struct omap_nand_info {
115 struct nand_hw_control controller;
116 struct omap_nand_platform_data *pdata;
118 struct mtd_partition *parts;
119 struct nand_chip nand;
120 struct platform_device *pdev;
123 unsigned long phys_base;
124 void __iomem *gpmc_cs_baseaddr;
125 void __iomem *gpmc_baseaddr;
129 * omap_nand_wp - This function enable or disable the Write Protect feature on
131 * @mtd: MTD device structure
134 static void omap_nand_wp(struct mtd_info *mtd, int mode)
136 struct omap_nand_info *info = container_of(mtd,
137 struct omap_nand_info, mtd);
139 unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG);
142 config &= ~(NAND_WP_BIT); /* WP is ON */
144 config |= (NAND_WP_BIT); /* WP is OFF */
146 __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG));
150 * hardware specific access to control-lines
151 * NOTE: boards may use different bits for these!!
154 * NAND_NCE: bit 0 - don't care
155 * NAND_CLE: bit 1 -> Command Latch
156 * NAND_ALE: bit 2 -> Address Latch
158 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
160 struct omap_nand_info *info = container_of(mtd,
161 struct omap_nand_info, mtd);
163 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
164 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
165 GPMC_CS_NAND_COMMAND;
166 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
170 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
171 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
172 GPMC_CS_NAND_ADDRESS;
173 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
177 case NAND_CTRL_CHANGE | NAND_NCE:
178 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
180 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
185 if (cmd != NAND_CMD_NONE)
186 __raw_writeb(cmd, info->nand.IO_ADDR_W);
190 * omap_read_buf16 - read data from NAND controller into buffer
191 * @mtd: MTD device structure
192 * @buf: buffer to store date
193 * @len: number of bytes to read
195 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
197 struct nand_chip *nand = mtd->priv;
199 __raw_readsl(nand->IO_ADDR_R, buf, len / 2);
203 * omap_write_buf16 - write buffer to NAND controller
204 * @mtd: MTD device structure
206 * @len: number of bytes to write
208 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
210 struct omap_nand_info *info = container_of(mtd,
211 struct omap_nand_info, mtd);
212 u16 *p = (u16 *) buf;
214 /* FIXME try bursts of writesw() or DMA ... */
218 writew(*p++, info->nand.IO_ADDR_W);
220 while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
221 GPMC_STATUS) & GPMC_BUF_FULL));
225 * omap_verify_buf - Verify chip data against buffer
226 * @mtd: MTD device structure
227 * @buf: buffer containing the data to compare
228 * @len: number of bytes to compare
230 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
232 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
234 u16 *p = (u16 *) buf;
240 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
247 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
249 * omap_hwecc_init-Initialize the Hardware ECC for NAND flash in GPMC controller
250 * @mtd: MTD device structure
252 static void omap_hwecc_init(struct mtd_info *mtd)
254 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
256 register struct nand_chip *chip = mtd->priv;
257 unsigned long val = 0x0;
259 /* Read from ECC Control Register */
260 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL);
261 /* Clear all ECC | Enable Reg1 */
262 val = ((0x00000001<<8) | 0x00000001);
263 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
265 /* Read from ECC Size Config Register */
266 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
267 /* ECCSIZE1=512 | Select eccResultsize[0-3] */
268 val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
269 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
273 * gen_true_ecc - This function will generate true ECC value, which can be used
274 * when correcting data read from NAND flash memory core
275 * @ecc_buf: buffer to store ecc code
277 static void gen_true_ecc(u8 *ecc_buf)
279 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
280 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
282 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
283 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
284 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
285 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
286 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
287 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
291 * omap_compare_ecc - This function compares two ECC's and indicates if there
292 * is an error. If the error can be corrected it will be corrected to the
294 * @ecc_data1: ecc code from nand spare area
295 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
296 * @page_data: page data
298 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
299 u8 *ecc_data2, /* read from register */
303 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
304 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
311 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
313 gen_true_ecc(ecc_data1);
314 gen_true_ecc(ecc_data2);
316 for (i = 0; i <= 2; i++) {
317 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
318 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
321 for (i = 0; i < 8; i++) {
322 tmp0_bit[i] = *ecc_data1 % 2;
323 *ecc_data1 = *ecc_data1 / 2;
326 for (i = 0; i < 8; i++) {
327 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
328 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
331 for (i = 0; i < 8; i++) {
332 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
333 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
336 for (i = 0; i < 8; i++) {
337 comp0_bit[i] = *ecc_data2 % 2;
338 *ecc_data2 = *ecc_data2 / 2;
341 for (i = 0; i < 8; i++) {
342 comp1_bit[i] = *(ecc_data2 + 1) % 2;
343 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
346 for (i = 0; i < 8; i++) {
347 comp2_bit[i] = *(ecc_data2 + 2) % 2;
348 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
351 for (i = 0; i < 6; i++)
352 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
354 for (i = 0; i < 8; i++)
355 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
357 for (i = 0; i < 8; i++)
358 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
360 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
361 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
363 for (i = 0; i < 24; i++)
364 ecc_sum += ecc_bit[i];
368 /* Not reached because this function is not called if
369 * ECC values are equal
374 /* Uncorrectable error */
375 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
379 /* UN-Correctable error */
380 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
384 /* Correctable error */
385 find_byte = (ecc_bit[23] << 8) +
395 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
397 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
398 "offset: %d, bit: %d\n", find_byte, find_bit);
400 page_data[find_byte] ^= (1 << find_bit);
405 if (ecc_data2[0] == 0 &&
410 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
416 * omap_correct_data - Compares the ecc read from nand spare area with ECC
417 * registers values and corrects one bit error if it has occured
418 * @mtd: MTD device structure
420 * @read_ecc: ecc read from nand flash
421 * @calc_ecc: ecc read from ECC registers
423 static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
424 u_char * read_ecc, u_char * calc_ecc)
426 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
428 int blockCnt = 0, i = 0, ret = 0;
430 /* Ex NAND_ECC_HW12_2048 */
431 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
432 (info->nand.ecc.size == 2048))
437 for (i = 0; i < blockCnt; i++) {
438 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
439 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
440 if (ret < 0) return ret;
450 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
451 * Using noninverted ECC can be considered ugly since writing a blank
452 * page ie. padding will clear the ECC bytes. This is no problem as long
453 * nobody is trying to write data on the seemingly unused page. Reading
454 * an erased page will produce an ECC mismatch between generated and read
455 * ECC bytes that has to be dealt with separately.
456 * @mtd: MTD device structure
457 * @dat: The pointer to data on which ecc is computed
458 * @ecc_code: The ecc_code buffer
460 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
463 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
465 unsigned long val = 0x0;
468 /* Start Reading from HW ECC1_Result = 0x200 */
469 reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
470 val = __raw_readl(reg);
471 *ecc_code++ = val; /* P128e, ..., P1e */
472 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
473 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
474 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
481 * omap_enable_hwecc - This function enables the hardware ecc functionality
482 * @mtd: MTD device structure
483 * @mode: Read/Write mode
485 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
487 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
489 register struct nand_chip *chip = mtd->priv;
490 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
491 unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
495 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
496 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
497 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
499 case NAND_ECC_READSYN :
500 __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
501 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
502 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
504 case NAND_ECC_WRITE :
505 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
506 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
507 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
510 DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
515 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
520 * omap_wait - Wait function is called during Program and erase
521 * operations and the way it is called from MTD layer, we should wait
522 * till the NAND chip is ready after the programming/erase operation
524 * @mtd: MTD device structure
525 * @chip: NAND Chip structure
527 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
529 register struct nand_chip *this = mtd->priv;
530 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
534 this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
535 GPMC_CS_NAND_COMMAND;
536 this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
538 while (!(status & 0x40)) {
539 __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
540 status = __raw_readb(this->IO_ADDR_R);
546 * omap_dev_ready - calls the platform specific dev_ready function
547 * @mtd: MTD device structure
549 static int omap_dev_ready(struct mtd_info *mtd)
551 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
553 unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS);
555 if ((val & 0x100) == 0x100) {
556 /* Clear IRQ Interrupt */
559 __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS);
561 unsigned int cnt = 0;
562 while (cnt++ < 0x1FF) {
563 if ((val & 0x100) == 0x100)
565 val = __raw_readl(info->gpmc_baseaddr +
573 static int __devinit omap_nand_probe(struct platform_device *pdev)
575 struct omap_nand_info *info;
576 struct omap_nand_platform_data *pdata;
581 pdata = pdev->dev.platform_data;
583 dev_err(&pdev->dev, "platform data missing\n");
587 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
588 if (!info) return -ENOMEM;
590 platform_set_drvdata(pdev, info);
592 spin_lock_init(&info->controller.lock);
593 init_waitqueue_head(&info->controller.wq);
597 info->gpmc_cs = pdata->cs;
598 info->gpmc_baseaddr = pdata->gpmc_baseaddr;
599 info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr;
601 info->mtd.priv = &info->nand;
602 info->mtd.name = pdev->dev.bus_id;
603 info->mtd.owner = THIS_MODULE;
605 err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base);
607 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
611 /* Enable RD PIN Monitoring Reg */
612 if (pdata->dev_ready) {
613 val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
614 val |= WR_RD_PIN_MONITORING;
615 gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
618 val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
620 val |= (0xc & 0xf) << 8;
621 gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
623 /* NAND write protect off */
624 omap_nand_wp(&info->mtd, NAND_WP_OFF);
626 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
627 pdev->dev.driver->name)) {
632 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
633 if (!info->nand.IO_ADDR_R) {
635 goto out_release_mem_region;
637 info->nand.controller = &info->controller;
639 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
640 info->nand.cmd_ctrl = omap_hwcontrol;
642 /* REVISIT: only supports 16-bit NAND flash */
644 info->nand.read_buf = omap_read_buf16;
645 info->nand.write_buf = omap_write_buf16;
646 info->nand.verify_buf = omap_verify_buf;
649 * If RDY/BSY line is connected to OMAP then use the omap ready funcrtion
650 * and the generic nand_wait function which reads the status register
651 * after monitoring the RDY/BSY line.Otherwise use a standard chip delay
652 * which is slightly more than tR (AC Timing) of the NAND device and read
653 * status register until you get a failure or success
655 if (pdata->dev_ready) {
656 info->nand.dev_ready = omap_dev_ready;
657 info->nand.chip_delay = 0;
659 info->nand.waitfunc = omap_wait;
660 info->nand.chip_delay = 50;
663 info->nand.options |= NAND_SKIP_BBTSCAN;
664 if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
666 info->nand.options |= NAND_BUSWIDTH_16;
668 #ifdef CONFIG_MTD_NAND_OMAP_HWECC
669 info->nand.ecc.bytes = 3;
670 info->nand.ecc.size = 512;
671 info->nand.ecc.calculate = omap_calculate_ecc;
672 info->nand.ecc.hwctl = omap_enable_hwecc;
673 info->nand.ecc.correct = omap_correct_data;
674 info->nand.ecc.mode = NAND_ECC_HW;
677 omap_hwecc_init(&info->mtd);
679 info->nand.ecc.mode = NAND_ECC_SOFT;
682 /* DIP switches on some boards change between 8 and 16 bit
683 * bus widths for flash. Try the other width if the first try fails.
685 if (nand_scan(&info->mtd, 1)) {
686 info->nand.options ^= NAND_BUSWIDTH_16;
687 if (nand_scan(&info->mtd, 1)) {
689 goto out_release_mem_region;
693 #ifdef CONFIG_MTD_PARTITIONS
694 err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
696 add_mtd_partitions(&info->mtd, info->parts, err);
697 else if (pdata->parts)
698 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
701 add_mtd_device(&info->mtd);
703 platform_set_drvdata(pdev, &info->mtd);
707 out_release_mem_region:
708 release_mem_region(info->phys_base, NAND_IO_SIZE);
710 gpmc_cs_free(info->gpmc_cs);
717 static int omap_nand_remove(struct platform_device *pdev)
719 struct mtd_info *mtd = platform_get_drvdata(pdev);
720 struct omap_nand_info *info = mtd->priv;
722 platform_set_drvdata(pdev, NULL);
723 /* Release NAND device, its internal structures and partitions */
724 nand_release(&info->mtd);
725 iounmap(info->nand.IO_ADDR_R);
730 static struct platform_driver omap_nand_driver = {
731 .probe = omap_nand_probe,
732 .remove = omap_nand_remove,
735 .owner = THIS_MODULE,
738 MODULE_ALIAS(DRIVER_NAME);
740 static int __init omap_nand_init(void)
742 printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
743 return platform_driver_register(&omap_nand_driver);
746 static void __exit omap_nand_exit(void)
748 platform_driver_unregister(&omap_nand_driver);
751 module_init(omap_nand_init);
752 module_exit(omap_nand_exit);
754 MODULE_LICENSE("GPL");
755 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");