2 * drivers/mtd/nand/omap2.c
4 * Copyright (c) 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
5 * Copyright (c) 2004 Micron Technology Inc.
6 * Copyright (c) 2004 David Brownell
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/partitions.h>
23 #include <asm/arch/gpmc.h>
24 #include <asm/arch/nand.h>
26 #define GPMC_IRQ_STATUS 0x18
27 #define GPMC_ECC_CONFIG 0x1F4
28 #define GPMC_ECC_CONTROL 0x1F8
29 #define GPMC_ECC_SIZE_CONFIG 0x1FC
30 #define GPMC_ECC1_RESULT 0x200
32 #define DRIVER_NAME "omap2-nand"
33 #define NAND_IO_SIZE SZ_4K
37 #define NAND_WP_BIT 0x00000010
38 #define WR_RD_PIN_MONITORING 0x00600000
40 #define GPMC_BUF_FULL 0x00000001
41 #define GPMC_BUF_EMPTY 0x00000000
43 #define NAND_Ecc_P1e (1 << 0)
44 #define NAND_Ecc_P2e (1 << 1)
45 #define NAND_Ecc_P4e (1 << 2)
46 #define NAND_Ecc_P8e (1 << 3)
47 #define NAND_Ecc_P16e (1 << 4)
48 #define NAND_Ecc_P32e (1 << 5)
49 #define NAND_Ecc_P64e (1 << 6)
50 #define NAND_Ecc_P128e (1 << 7)
51 #define NAND_Ecc_P256e (1 << 8)
52 #define NAND_Ecc_P512e (1 << 9)
53 #define NAND_Ecc_P1024e (1 << 10)
54 #define NAND_Ecc_P2048e (1 << 11)
56 #define NAND_Ecc_P1o (1 << 16)
57 #define NAND_Ecc_P2o (1 << 17)
58 #define NAND_Ecc_P4o (1 << 18)
59 #define NAND_Ecc_P8o (1 << 19)
60 #define NAND_Ecc_P16o (1 << 20)
61 #define NAND_Ecc_P32o (1 << 21)
62 #define NAND_Ecc_P64o (1 << 22)
63 #define NAND_Ecc_P128o (1 << 23)
64 #define NAND_Ecc_P256o (1 << 24)
65 #define NAND_Ecc_P512o (1 << 25)
66 #define NAND_Ecc_P1024o (1 << 26)
67 #define NAND_Ecc_P2048o (1 << 27)
69 #define TF(value) (value ? 1 : 0)
71 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
72 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
73 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
74 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
75 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
76 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
77 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
78 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
80 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
81 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
82 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
83 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
84 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
85 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
86 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
87 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
89 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
90 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
91 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
92 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
93 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
94 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
95 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
96 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
98 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
99 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
100 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
101 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
102 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
103 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
104 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
105 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
107 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
108 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
110 #ifdef CONFIG_MTD_PARTITIONS
111 static const char *part_probes[] = { "cmdlinepart", NULL };
114 static int hw_ecc = 1;
116 /* new oob placement block for use with hardware ecc generation */
117 static struct nand_ecclayout omap_hw_eccoob = {
119 .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
120 .oobfree = {{16, 32}, {33, 63} },
123 struct omap_nand_info {
124 struct nand_hw_control controller;
125 struct omap_nand_platform_data *pdata;
127 struct mtd_partition *parts;
128 struct nand_chip nand;
129 struct platform_device *pdev;
132 unsigned long phys_base;
133 void __iomem *gpmc_cs_baseaddr;
134 void __iomem *gpmc_baseaddr;
136 static void omap_nand_wp(struct mtd_info *mtd, int mode)
138 struct omap_nand_info *info = container_of(mtd,
139 struct omap_nand_info, mtd);
141 unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG);
144 config &= ~(NAND_WP_BIT); /* WP is ON */
146 config |= (NAND_WP_BIT); /* WP is OFF */
148 __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG));
152 * hardware specific access to control-lines
153 * NOTE: boards may use different bits for these!!
156 * NAND_NCE: bit 0 - don't care
157 * NAND_CLE: bit 1 -> Command Latch
158 * NAND_ALE: bit 2 -> Address Latch
160 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
162 struct omap_nand_info *info = container_of(mtd,
163 struct omap_nand_info, mtd);
165 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
166 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
167 GPMC_CS_NAND_COMMAND;
168 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
172 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
173 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
174 GPMC_CS_NAND_ADDRESS;
175 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
179 case NAND_CTRL_CHANGE | NAND_NCE:
180 info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
182 info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
187 if (cmd != NAND_CMD_NONE)
188 __raw_writeb(cmd, info->nand.IO_ADDR_W);
192 * omap_read_buf - read data from NAND controller into buffer
193 * @mtd: MTD device structure
194 * @buf: buffer to store date
195 * @len: number of bytes to read
197 static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len)
199 struct omap_nand_info *info = container_of(mtd,
200 struct omap_nand_info, mtd);
201 u16 *p = (u16 *) buf;
206 *p++ = cpu_to_le16(readw(info->nand.IO_ADDR_R));
210 * omap_write_buf - write buffer to NAND controller
211 * @mtd: MTD device structure
213 * @len: number of bytes to write
215 static void omap_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
217 struct omap_nand_info *info = container_of(mtd,
218 struct omap_nand_info, mtd);
219 u16 *p = (u16 *) buf;
224 writew(cpu_to_le16(*p++), info->nand.IO_ADDR_W);
226 while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
227 GPMC_STATUS) & GPMC_BUF_FULL));
231 * omap_verify_buf - Verify chip data against buffer
232 * @mtd: MTD device structure
233 * @buf: buffer containing the data to compare
234 * @len: number of bytes to compare
236 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
238 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
240 u16 *p = (u16 *) buf;
246 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
253 static void omap_hwecc_init(struct mtd_info *mtd)
255 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
257 unsigned long val = 0x0;
259 /* Read from ECC Control Register */
260 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL);
261 /* Clear all ECC | Enable Reg1 */
262 val = ((0x00000001<<8) | 0x00000001);
263 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
265 /* Read from ECC Size Config Register */
266 val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
267 /* ECCSIZE1=512 | ECCSIZE0=8bytes | Select eccResultsize[0123] */
268 val = ((0x000000FF<<22) | (0x00000003<<12) | (0x0000000F));
269 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
275 * This function will generate true ECC value, which can be used
276 * when correcting data read from NAND flash memory core
278 static void gen_true_ecc(u8 *ecc_buf)
280 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
281 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
283 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
284 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
285 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
286 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
287 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
288 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
292 * This function compares two ECC's and indicates if there is an error.
293 * If the error can be corrected it will be corrected to the buffer
295 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
296 u8 *ecc_data2, /* read from register */
300 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
301 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
308 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
310 gen_true_ecc(ecc_data1);
311 gen_true_ecc(ecc_data2);
313 for (i = 0; i <= 2; i++) {
314 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
315 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
318 for (i = 0; i < 8; i++) {
319 tmp0_bit[i] = *ecc_data1 % 2;
320 *ecc_data1 = *ecc_data1 / 2;
323 for (i = 0; i < 8; i++) {
324 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
325 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
328 for (i = 0; i < 8; i++) {
329 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
330 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
333 for (i = 0; i < 8; i++) {
334 comp0_bit[i] = *ecc_data2 % 2;
335 *ecc_data2 = *ecc_data2 / 2;
338 for (i = 0; i < 8; i++) {
339 comp1_bit[i] = *(ecc_data2 + 1) % 2;
340 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
343 for (i = 0; i < 8; i++) {
344 comp2_bit[i] = *(ecc_data2 + 2) % 2;
345 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
348 for (i = 0; i < 6; i++)
349 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
351 for (i = 0; i < 8; i++)
352 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
354 for (i = 0; i < 8; i++)
355 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
357 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
358 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
360 for (i = 0; i < 24; i++)
361 ecc_sum += ecc_bit[i];
365 /* Not reached because this function is not called if
366 * ECC values are equal
371 /* Uncorrectable error */
372 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
376 /* UN-Correctable error */
377 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
381 /* Correctable error */
382 find_byte = (ecc_bit[23] << 8) +
392 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
394 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
395 "offset: %d, bit: %d\n", find_byte, find_bit);
397 page_data[find_byte] ^= (1 << find_bit);
402 if (ecc_data2[0] == 0 &&
407 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
412 static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
413 u_char * read_ecc, u_char * calc_ecc)
415 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
417 int blockCnt = 0, i = 0, ret = 0;
419 /* Ex NAND_ECC_HW12_2048 */
420 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
421 (info->nand.ecc.size == 2048))
426 for (i = 0; i < blockCnt; i++) {
427 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
428 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
429 if (ret < 0) return ret;
439 ** Generate non-inverted ECC bytes.
441 ** Using noninverted ECC can be considered ugly since writing a blank
442 ** page ie. padding will clear the ECC bytes. This is no problem as long
443 ** nobody is trying to write data on the seemingly unused page.
445 ** Reading an erased page will produce an ECC mismatch between
446 ** generated and read ECC bytes that has to be dealt with separately.
448 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
451 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
453 unsigned long val = 0x0;
454 unsigned long reg, n;
456 /* Ex NAND_ECC_HW12_2048 */
457 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
458 (info->nand.ecc.size == 2048))
463 /* Start Reading from HW ECC1_Result = 0x200 */
464 reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
466 val = __raw_readl(reg);
467 *ecc_code++ = val; /* P128e, ..., P1e */
468 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
469 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
470 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
475 } /* omap_calculate_ecc */
477 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
479 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
481 unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
485 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
486 /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
487 val = (1 << 7) | (0x0) | (0x1) ;
489 case NAND_ECC_READSYN :
490 __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
491 /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
492 val = (1 << 7) | (0x0) | (0x1) ;
494 case NAND_ECC_WRITE :
495 __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
496 /* ECC 16 bit col) | ( CS 0 ) | ECC Enable */
497 val = (1 << 7) | (0x0) | (0x1) ;
500 DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
505 __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
508 static int omap_dev_ready(struct mtd_info *mtd)
510 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
512 unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS);
514 if ((val & 0x100) == 0x100) {
515 /* Clear IRQ Interrupt */
518 __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS);
520 unsigned int cnt = 0;
521 while (cnt++ < 0x1FF) {
522 if ((val & 0x100) == 0x100)
524 val = __raw_readl(info->gpmc_baseaddr +
532 static int __devinit omap_nand_probe(struct platform_device *pdev)
534 struct omap_nand_info *info;
535 struct omap_nand_platform_data *pdata;
540 pdata = pdev->dev.platform_data;
542 dev_err(&pdev->dev, "platform data missing\n");
546 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
547 if (!info) return -ENOMEM;
549 platform_set_drvdata(pdev, info);
551 spin_lock_init(&info->controller.lock);
552 init_waitqueue_head(&info->controller.wq);
556 info->gpmc_cs = pdata->cs;
557 info->gpmc_baseaddr = pdata->gpmc_baseaddr;
558 info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr;
560 info->mtd.priv = &info->nand;
561 info->mtd.name = pdev->dev.bus_id;
562 info->mtd.owner = THIS_MODULE;
564 err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base);
566 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
570 /* Enable RD PIN Monitoring Reg */
571 val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
572 val |= WR_RD_PIN_MONITORING;
573 gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
575 val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
577 val |= (0xc & 0xf) << 8;
578 gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
580 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
581 pdev->dev.driver->name)) {
586 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
587 if (!info->nand.IO_ADDR_R) {
589 goto out_release_mem_region;
591 info->nand.controller = &info->controller;
593 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
594 info->nand.cmd_ctrl = omap_hwcontrol;
596 info->nand.read_buf = omap_read_buf;
597 info->nand.write_buf = omap_write_buf;
598 info->nand.verify_buf = omap_verify_buf;
600 info->nand.dev_ready = omap_dev_ready;
601 info->nand.chip_delay = 0;
604 info->nand.options = NAND_BUSWIDTH_16;
605 info->nand.options |= NAND_SKIP_BBTSCAN;
609 omap_hwecc_init(&info->mtd);
611 info->nand.ecc.calculate = omap_calculate_ecc;
612 info->nand.ecc.hwctl = omap_enable_hwecc;
613 info->nand.ecc.correct = omap_correct_data;
614 info->nand.ecc.mode = NAND_ECC_HW;
615 info->nand.ecc.bytes = 12;
616 info->nand.ecc.size = 2048;
617 info->nand.ecc.layout = &omap_hw_eccoob;
620 info->nand.ecc.mode = NAND_ECC_SOFT;
624 /* DIP switches on some boards change between 8 and 16 bit
625 * bus widths for flash. Try the other width if the first try fails.
627 if (nand_scan(&info->mtd, 1)) {
628 info->nand.options ^= NAND_BUSWIDTH_16;
629 if (nand_scan(&info->mtd, 1)) {
631 goto out_release_mem_region;
635 #ifdef CONFIG_MTD_PARTITIONS
636 err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
638 add_mtd_partitions(&info->mtd, info->parts, err);
639 else if (err < 0 && pdata->parts)
640 add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
643 add_mtd_device(&info->mtd);
645 omap_nand_wp(&info->mtd, NAND_WP_OFF);
647 platform_set_drvdata(pdev, &info->mtd);
651 out_release_mem_region:
652 release_mem_region(info->phys_base, NAND_IO_SIZE);
654 gpmc_cs_free(info->gpmc_cs);
661 static int omap_nand_remove(struct platform_device *pdev)
663 struct mtd_info *mtd = platform_get_drvdata(pdev);
664 struct omap_nand_info *info = mtd->priv;
666 platform_set_drvdata(pdev, NULL);
667 /* Release NAND device, its internal structures and partitions */
668 nand_release(&info->mtd);
669 iounmap(info->nand.IO_ADDR_R);
674 static struct platform_driver omap_nand_driver = {
675 .probe = omap_nand_probe,
676 .remove = omap_nand_remove,
679 .owner = THIS_MODULE,
682 MODULE_ALIAS(DRIVER_NAME);
684 static int __init omap_nand_init(void)
686 printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
687 return platform_driver_register(&omap_nand_driver);
690 static void __exit omap_nand_exit(void)
692 platform_driver_unregister(&omap_nand_driver);
695 module_init(omap_nand_init);
696 module_exit(omap_nand_exit);
698 MODULE_LICENSE("GPL");
699 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");