2 * linux/drivers/mtd/onenand/omap2.c
4 * OneNAND driver for OMAP2
6 * Copyright (C) 2005-2006 Nokia Corporation
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
9 * IRQ and DMA support written by Timo Teras
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; see the file COPYING. If not, write to the Free Software
22 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
37 #include <asm/mach/flash.h>
38 #include <asm/arch/gpmc.h>
39 #include <asm/arch/onenand.h>
40 #include <asm/arch/gpio.h>
41 #include <asm/arch/gpmc.h>
42 #include <asm/arch/pm.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/dma-mapping.h>
46 #include <asm/arch/dma.h>
48 #include <asm/arch/board.h>
50 #define DRIVER_NAME "omap2-onenand"
52 #define ONENAND_IO_SIZE SZ_128K
53 #define ONENAND_BUFRAM_SIZE (1024 * 5)
55 struct omap2_onenand {
56 struct platform_device *pdev;
58 unsigned long phys_base;
61 struct mtd_partition *parts;
62 struct onenand_chip onenand;
63 struct completion irq_done;
64 struct completion dma_done;
67 int (*setup)(void __iomem *base, int freq);
70 static unsigned short omap2_onenand_readw(void __iomem *addr)
75 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
80 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
82 struct omap2_onenand *info = data;
84 complete(&info->dma_done);
87 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
89 struct omap2_onenand *info = dev_id;
91 complete(&info->irq_done);
96 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
98 struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
99 unsigned int interrupt = 0;
101 unsigned long timeout;
104 if (state == FL_RESETING) {
107 for (i = 0; i < 20; i++) {
109 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
110 if (interrupt & ONENAND_INT_MASTER)
113 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
114 if (ctrl & ONENAND_CTRL_ERROR) {
115 printk(KERN_ERR "onenand_wait: reset error! ctrl 0x%04x intr 0x%04x\n", ctrl, interrupt);
118 if (!(interrupt & ONENAND_INT_RESET)) {
119 printk(KERN_ERR "onenand_wait: reset timeout! ctrl 0x%04x intr 0x%04x\n", ctrl, interrupt);
125 if (state != FL_READING) {
127 /* Turn interrupts on */
128 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
129 syscfg |= ONENAND_SYS_CFG1_IOBE;
130 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
132 INIT_COMPLETION(info->irq_done);
133 if (info->gpio_irq) {
134 result = omap_get_gpio_datain(info->gpio_irq);
136 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
137 printk(KERN_ERR "onenand_wait: gpio error, state = %d, ctrl = 0x%04x\n", state, ctrl);
146 result = wait_for_completion_timeout(&info->irq_done,
147 msecs_to_jiffies(20));
149 /* Timeout after 20ms */
150 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
151 if (ctrl & ONENAND_CTRL_ONGO) {
152 /* The operation seems to be still going - so give it some more time */
156 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
157 printk(KERN_ERR "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
160 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
161 if ((interrupt & ONENAND_INT_MASTER) == 0)
162 printk(KERN_WARNING "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
166 /* Turn interrupts off */
167 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
168 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
169 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
171 timeout = jiffies + msecs_to_jiffies(20);
172 while (time_before(jiffies, timeout)) {
173 if (omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT) &
179 /* To get correct interrupt status in timeout case */
180 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
181 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
183 if (ctrl & ONENAND_CTRL_ERROR) {
184 printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl);
185 if (ctrl & ONENAND_CTRL_LOCK)
186 printk(KERN_ERR "onenand_erase: Device is write protected!!!\n");
191 printk(KERN_WARNING "onenand_wait: unexpected controller status = 0x%04x state = %d interrupt = 0x%04x\n", ctrl, state, interrupt);
193 if (interrupt & ONENAND_INT_READ) {
194 int ecc = omap2_onenand_readw(info->onenand.base + ONENAND_REG_ECC_STATUS);
196 if (ecc & ONENAND_ECC_2BIT_ALL) {
197 printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
198 mtd->ecc_stats.failed++;
200 } else if (ecc & ONENAND_ECC_1BIT_ALL)
201 printk(KERN_NOTICE "onenand_wait: correctable ECC error = 0x%04x\n", ecc);
202 mtd->ecc_stats.corrected++;
204 } else if (state == FL_READING) {
205 printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
212 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
214 struct onenand_chip *this = mtd->priv;
216 if (ONENAND_CURRENT_BUFFERRAM(this)) {
217 if (area == ONENAND_DATARAM)
218 return mtd->writesize;
219 if (area == ONENAND_SPARERAM)
226 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
227 unsigned char *buffer, int offset,
230 struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
231 struct onenand_chip *this = mtd->priv;
232 dma_addr_t dma_src, dma_dst;
235 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
236 if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
237 (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
238 (count < 1024) || (count & 3)) {
239 memcpy(buffer, (void *)(this->base + bram_offset), count);
243 dma_src = info->phys_base + bram_offset;
244 dma_dst = dma_map_single(&info->pdev->dev, buffer, count, DMA_FROM_DEVICE);
245 if (dma_mapping_error(dma_dst)) {
246 dev_err(&info->pdev->dev,
247 "Couldn't DMA map a %d byte buffer\n",
252 omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S32,
253 count / 4, 1, 0, 0, 0);
254 omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
256 omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
259 INIT_COMPLETION(info->dma_done);
261 omap_start_dma(info->dma_channel);
262 wait_for_completion(&info->dma_done);
265 dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
270 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
271 const unsigned char *buffer, int offset,
274 struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
275 struct onenand_chip *this = mtd->priv;
276 dma_addr_t dma_src, dma_dst;
279 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
280 if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
281 (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
282 (count < 1024) || (count & 3)) {
283 memcpy((void *)(this->base + bram_offset), buffer, count);
287 dma_src = dma_map_single(&info->pdev->dev, (void *) buffer, count,
289 dma_dst = info->phys_base + bram_offset;
290 if (dma_mapping_error(dma_dst)) {
291 dev_err(&info->pdev->dev,
292 "Couldn't DMA map a %d byte buffer\n",
297 omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S16,
298 count / 2, 1, 0, 0, 0);
299 omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
301 omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
304 INIT_COMPLETION(info->dma_done);
305 omap_start_dma(info->dma_channel);
306 wait_for_completion(&info->dma_done);
308 dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
313 static struct platform_driver omap2_onenand_driver;
315 static int __adjust_timing(struct device *dev, void *data)
318 struct omap2_onenand *info;
320 info = dev_get_drvdata(dev);
322 BUG_ON(info->setup == NULL);
324 /* DMA is not in use so this is all that is needed */
325 ret = info->setup(info->onenand.base, info->freq);
330 int omap2_onenand_rephase(void)
332 return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
333 NULL, __adjust_timing);
336 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
338 struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
340 /* With certain content in the buffer RAM, the OMAP boot ROM code
341 * can recognize the flash chip incorrectly. Zero it out before
344 memset(info->onenand.base, 0, ONENAND_BUFRAM_SIZE);
347 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
349 struct omap_onenand_platform_data *pdata;
350 struct omap2_onenand *info;
353 pdata = pdev->dev.platform_data;
355 dev_err(&pdev->dev, "platform data missing\n");
359 info = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
363 init_completion(&info->irq_done);
364 init_completion(&info->dma_done);
365 info->gpmc_cs = pdata->cs;
366 info->gpio_irq = pdata->gpio_irq;
367 info->dma_channel = pdata->dma_channel;
368 if (info->dma_channel < 0) {
369 /* if -1, don't use DMA */
373 r = gpmc_cs_request(info->gpmc_cs, ONENAND_IO_SIZE, &info->phys_base);
375 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
379 if (request_mem_region(info->phys_base, ONENAND_IO_SIZE,
380 pdev->dev.driver->name) == NULL) {
381 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
382 info->phys_base, ONENAND_IO_SIZE);
386 info->onenand.base = ioremap(info->phys_base, ONENAND_IO_SIZE);
387 if (info->onenand.base == NULL) {
389 goto err_release_mem_region;
392 if (pdata->onenand_setup != NULL) {
393 r = pdata->onenand_setup(info->onenand.base, info->freq);
395 dev_err(&pdev->dev, "Onenand platform setup failed: %d\n", r);
398 info->setup = pdata->onenand_setup;
401 if (info->gpio_irq) {
402 if ((r = omap_request_gpio(info->gpio_irq)) < 0) {
403 dev_err(&pdev->dev, "Failed to request GPIO%d for OneNAND\n",
407 omap_set_gpio_direction(info->gpio_irq, 1);
409 if ((r = request_irq(OMAP_GPIO_IRQ(info->gpio_irq),
410 omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
411 pdev->dev.driver->name, info)) < 0)
412 goto err_release_gpio;
415 if (info->dma_channel >= 0) {
416 r = omap_request_dma(0, pdev->dev.driver->name,
417 omap2_onenand_dma_cb, (void *) info,
420 omap_set_dma_write_mode(info->dma_channel, OMAP_DMA_WRITE_NON_POSTED);
421 omap_set_dma_src_data_pack(info->dma_channel, 1);
422 omap_set_dma_src_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
423 omap_set_dma_dest_data_pack(info->dma_channel, 1);
424 omap_set_dma_dest_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
427 "failed to allocate DMA for OneNAND, using PIO instead\n");
428 info->dma_channel = -1;
432 dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual base %p\n",
433 info->gpmc_cs, info->phys_base, info->onenand.base);
436 info->mtd.name = pdev->dev.bus_id;
437 info->mtd.priv = &info->onenand;
438 info->mtd.owner = THIS_MODULE;
440 if (info->dma_channel >= 0) {
441 info->onenand.wait = omap2_onenand_wait;
442 info->onenand.read_bufferram = omap2_onenand_read_bufferram;
443 info->onenand.write_bufferram = omap2_onenand_write_bufferram;
446 if ((r = onenand_scan(&info->mtd, 1)) < 0)
447 goto err_release_dma;
449 switch ((info->onenand.version_id >> 4) & 0xf) {
464 #ifdef CONFIG_MTD_PARTITIONS
465 if (pdata->parts != NULL)
466 r = add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
469 r = add_mtd_device(&info->mtd);
471 goto err_release_onenand;
473 platform_set_drvdata(pdev, info);
478 onenand_release(&info->mtd);
480 if (info->dma_channel != -1)
481 omap_free_dma(info->dma_channel);
483 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
486 omap_free_gpio(info->gpio_irq);
488 iounmap(info->onenand.base);
489 err_release_mem_region:
490 release_mem_region(info->phys_base, ONENAND_IO_SIZE);
492 gpmc_cs_free(info->gpmc_cs);
499 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
501 struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
503 BUG_ON(info == NULL);
505 #ifdef CONFIG_MTD_PARTITIONS
507 del_mtd_partitions(&info->mtd);
509 del_mtd_device(&info->mtd);
511 del_mtd_device(&info->mtd);
514 onenand_release(&info->mtd);
515 if (info->dma_channel != -1)
516 omap_free_dma(info->dma_channel);
517 omap2_onenand_shutdown(pdev);
518 platform_set_drvdata(pdev, NULL);
519 if (info->gpio_irq) {
520 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
521 omap_free_gpio(info->gpio_irq);
523 iounmap(info->onenand.base);
524 release_mem_region(info->phys_base, ONENAND_IO_SIZE);
530 static struct platform_driver omap2_onenand_driver = {
531 .probe = omap2_onenand_probe,
532 .remove = omap2_onenand_remove,
533 .shutdown = omap2_onenand_shutdown,
536 .owner = THIS_MODULE,
540 static int __init omap2_onenand_init(void)
542 printk(KERN_INFO "OMAP2 OneNAND driver initializing\n");
543 return platform_driver_register(&omap2_onenand_driver);
546 static void __exit omap2_onenand_exit(void)
548 platform_driver_unregister(&omap2_onenand_driver);
551 module_init(omap2_onenand_init);
552 module_exit(omap2_onenand_exit);
554 MODULE_ALIAS(DRIVER_NAME);
555 MODULE_LICENSE("GPL");
556 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
557 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2");