1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
32 #define DRV_NAME "3c59x"
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
46 static int rx_copybreak = 200;
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
63 #define tx_interrupt_mitigation 1
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
68 static int vortex_debug = VORTEX_DEBUG;
70 static int vortex_debug = 1;
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
79 #include <linux/ioport.h>
80 #include <linux/slab.h>
81 #include <linux/interrupt.h>
82 #include <linux/pci.h>
83 #include <linux/mii.h>
84 #include <linux/init.h>
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/highmem.h>
90 #include <linux/eisa.h>
91 #include <linux/bitops.h>
92 #include <linux/jiffies.h>
93 #include <asm/irq.h> /* For NR_IRQS only. */
95 #include <asm/uaccess.h>
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
100 #define RUN_AT(x) (jiffies + (x))
102 #include <linux/delay.h>
105 static char version[] __devinitdata =
106 DRV_NAME ": Donald Becker and others.\n";
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
113 /* Operational parameter that usually are not changed. */
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
127 #define PFX DRV_NAME ": "
134 I. Board Compatibility
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
145 II. Board-specific settings
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
155 III. Driver operation
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
270 /* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
274 static struct vortex_chip_info {
279 } vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
281 PCI_USES_MASTER, IS_VORTEX, 32, },
282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
283 PCI_USES_MASTER, IS_VORTEX, 32, },
284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
285 PCI_USES_MASTER, IS_VORTEX, 32, },
286 {"3c595 Vortex 100baseTx",
287 PCI_USES_MASTER, IS_VORTEX, 32, },
288 {"3c595 Vortex 100baseT4",
289 PCI_USES_MASTER, IS_VORTEX, 32, },
291 {"3c595 Vortex 100base-MII",
292 PCI_USES_MASTER, IS_VORTEX, 32, },
293 {"3c900 Boomerang 10baseT",
294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
295 {"3c900 Boomerang 10Mbps Combo",
296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
299 {"3c900 Cyclone 10Mbps Combo",
300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
304 {"3c900B-FL Cyclone 10base-FL",
305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
306 {"3c905 Boomerang 100baseTx",
307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
308 {"3c905 Boomerang 100baseT4",
309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
310 {"3c905B Cyclone 100baseTx",
311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 10/100/BNC",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
315 {"3c905B-FX Cyclone 100baseFx",
316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
326 {"3cSOHO100-TX Hurricane",
327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
328 {"3c555 Laptop Hurricane",
329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
330 {"3c556 Laptop Tornado",
331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
333 {"3c556B Laptop Hurricane",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
339 {"3c575 Boomerang CardBus",
340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
341 {"3CCFE575BT Cyclone CardBus",
342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
361 {"3c982 Hydra Dual Port A",
362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
364 {"3c982 Hydra Dual Port B",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
368 {"3c920B-EMB-WNM Tornado",
369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
371 {NULL,}, /* NULL terminated list. */
375 static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
422 {0,} /* 0 terminated list. */
424 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
427 /* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
434 #define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
436 #define EL3_STATUS 0x0e
438 /* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
456 /* The SetRxFilter command accepts the following classes: */
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
460 /* Bits in the general status register. */
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
470 /* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
482 enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
487 /* EEPROM locations. */
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
494 enum Window2 { /* Window 2. */
497 enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
501 #define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
504 #define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
508 #define RAM_SIZE(v) BFEXT(v, 0, 3)
509 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
510 #define RAM_SPEED(v) BFEXT(v, 4, 2)
511 #define ROM_SIZE(v) BFEXT(v, 6, 2)
512 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
513 #define XCVR(v) BFEXT(v, 20, 4)
514 #define AUTOSELECT(v) BFEXT(v, 24, 1)
516 enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
519 enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
525 enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
529 /* Boomerang bus master control registers. */
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
535 /* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540 struct boom_rx_desc {
541 u32 next; /* Last entry points to 0. */
543 u32 addr; /* Up to 63 addr/len pairs possible. */
544 s32 length; /* Set LAST_FRAG to indicate last pair. */
546 /* Values for the Rx status entry. */
547 enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555 #define DO_ZEROCOPY 1
557 #define DO_ZEROCOPY 0
560 struct boom_tx_desc {
561 u32 next; /* Last entry points to 0. */
562 s32 status; /* bits 0:12 length, others see below. */
567 } frag[1+MAX_SKB_FRAGS];
574 /* Values for the Tx status entry. */
575 enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
581 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
582 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
584 struct vortex_extra_stats {
585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
592 struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
608 /* PCI configuration space information. */
609 struct device *gendev;
610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
623 full_duplex:1, autoselect:1,
624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
650 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
652 #define DEVICE_PCI(dev) NULL
655 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
658 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
660 #define DEVICE_EISA(dev) NULL
663 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
665 /* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
673 static const struct media_table {
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
694 const char str[ETH_GSTRING_LEN];
695 } ethtool_stats_keys[] = {
697 { "tx_max_collisions" },
698 { "tx_multiple_collisions" },
699 { "tx_single_collisions" },
703 /* number of ETHTOOL_GSTATS u64's */
704 #define VORTEX_NUM_STATS 5
706 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
707 int chip_idx, int card_idx);
708 static int vortex_up(struct net_device *dev);
709 static void vortex_down(struct net_device *dev, int final);
710 static int vortex_open(struct net_device *dev);
711 static void mdio_sync(void __iomem *ioaddr, int bits);
712 static int mdio_read(struct net_device *dev, int phy_id, int location);
713 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714 static void vortex_timer(unsigned long arg);
715 static void rx_oom_timer(unsigned long arg);
716 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718 static int vortex_rx(struct net_device *dev);
719 static int boomerang_rx(struct net_device *dev);
720 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
721 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
722 static int vortex_close(struct net_device *dev);
723 static void dump_tx_ring(struct net_device *dev);
724 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
725 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726 static void set_rx_mode(struct net_device *dev);
728 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
730 static void vortex_tx_timeout(struct net_device *dev);
731 static void acpi_set_WOL(struct net_device *dev);
732 static const struct ethtool_ops vortex_ethtool_ops;
733 static void set_8021q_mode(struct net_device *dev, int enable);
735 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736 /* Option count limit only -- unlimited interfaces are supported. */
738 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
743 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
744 static int global_options = -1;
745 static int global_full_duplex = -1;
746 static int global_enable_wol = -1;
747 static int global_use_mmio = -1;
749 /* Variables to work-around the Compaq PCI BIOS32 problem. */
750 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751 static struct net_device *compaq_net_device;
753 static int vortex_cards_found;
755 module_param(debug, int, 0);
756 module_param(global_options, int, 0);
757 module_param_array(options, int, NULL, 0);
758 module_param(global_full_duplex, int, 0);
759 module_param_array(full_duplex, int, NULL, 0);
760 module_param_array(hw_checksums, int, NULL, 0);
761 module_param_array(flow_ctrl, int, NULL, 0);
762 module_param(global_enable_wol, int, 0);
763 module_param_array(enable_wol, int, NULL, 0);
764 module_param(rx_copybreak, int, 0);
765 module_param(max_interrupt_work, int, 0);
766 module_param(compaq_ioaddr, int, 0);
767 module_param(compaq_irq, int, 0);
768 module_param(compaq_device_id, int, 0);
769 module_param(watchdog, int, 0);
770 module_param(global_use_mmio, int, 0);
771 module_param_array(use_mmio, int, NULL, 0);
772 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
776 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
777 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
780 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
781 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
787 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
790 #ifdef CONFIG_NET_POLL_CONTROLLER
791 static void poll_vortex(struct net_device *dev)
793 struct vortex_private *vp = netdev_priv(dev);
795 local_irq_save(flags);
796 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
797 local_irq_restore(flags);
803 static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
805 struct net_device *dev = pci_get_drvdata(pdev);
807 if (dev && dev->priv) {
808 if (netif_running(dev)) {
809 netif_device_detach(dev);
812 pci_save_state(pdev);
813 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
814 free_irq(dev->irq, dev);
815 pci_disable_device(pdev);
816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
821 static int vortex_resume(struct pci_dev *pdev)
823 struct net_device *dev = pci_get_drvdata(pdev);
824 struct vortex_private *vp = netdev_priv(dev);
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
830 err = pci_enable_device(pdev);
832 printk(KERN_WARNING "%s: Could not enable device \n",
836 pci_set_master(pdev);
837 if (request_irq(dev->irq, vp->full_bus_master_rx ?
838 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
839 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
840 pci_disable_device(pdev);
843 if (netif_running(dev)) {
844 err = vortex_up(dev);
848 netif_device_attach(dev);
854 #endif /* CONFIG_PM */
857 static struct eisa_device_id vortex_eisa_ids[] = {
858 { "TCM5920", CH_3C592 },
859 { "TCM5970", CH_3C597 },
862 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
864 static int __init vortex_eisa_probe(struct device *device)
866 void __iomem *ioaddr;
867 struct eisa_device *edev;
869 edev = to_eisa_device(device);
871 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
874 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
876 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
877 edev->id.driver_data, vortex_cards_found)) {
878 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
882 vortex_cards_found++;
887 static int __devexit vortex_eisa_remove(struct device *device)
889 struct eisa_device *edev;
890 struct net_device *dev;
891 struct vortex_private *vp;
892 void __iomem *ioaddr;
894 edev = to_eisa_device(device);
895 dev = eisa_get_drvdata(edev);
898 printk("vortex_eisa_remove called for Compaq device!\n");
902 vp = netdev_priv(dev);
905 unregister_netdev(dev);
906 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
907 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
913 static struct eisa_driver vortex_eisa_driver = {
914 .id_table = vortex_eisa_ids,
917 .probe = vortex_eisa_probe,
918 .remove = __devexit_p(vortex_eisa_remove)
922 #endif /* CONFIG_EISA */
924 /* returns count found (>= 0), or negative on error */
925 static int __init vortex_eisa_init(void)
928 int orig_cards_found = vortex_cards_found;
933 err = eisa_driver_register (&vortex_eisa_driver);
936 * Because of the way EISA bus is probed, we cannot assume
937 * any device have been found when we exit from
938 * eisa_driver_register (the bus root driver may not be
939 * initialized yet). So we blindly assume something was
940 * found, and let the sysfs magic happend...
946 /* Special code to work-around the Compaq PCI BIOS32 problem. */
948 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
949 compaq_irq, compaq_device_id, vortex_cards_found++);
952 return vortex_cards_found - orig_cards_found + eisa_found;
955 /* returns count (>= 0), or negative on error */
956 static int __devinit vortex_init_one(struct pci_dev *pdev,
957 const struct pci_device_id *ent)
959 int rc, unit, pci_bar;
960 struct vortex_chip_info *vci;
961 void __iomem *ioaddr;
963 /* wake up and enable device */
964 rc = pci_enable_device(pdev);
968 unit = vortex_cards_found;
970 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
971 /* Determine the default if the user didn't override us */
972 vci = &vortex_info_tbl[ent->driver_data];
973 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
974 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
975 pci_bar = use_mmio[unit] ? 1 : 0;
977 pci_bar = global_use_mmio ? 1 : 0;
979 ioaddr = pci_iomap(pdev, pci_bar, 0);
980 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
981 ioaddr = pci_iomap(pdev, 0, 0);
983 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
984 ent->driver_data, unit);
986 pci_disable_device(pdev);
990 vortex_cards_found++;
997 * Start up the PCI/EISA device which is described by *gendev.
998 * Return 0 on success.
1000 * NOTE: pdev can be NULL, for the case of a Compaq device
1002 static int __devinit vortex_probe1(struct device *gendev,
1003 void __iomem *ioaddr, int irq,
1004 int chip_idx, int card_idx)
1006 struct vortex_private *vp;
1008 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1010 struct net_device *dev;
1011 static int printed_version;
1012 int retval, print_info;
1013 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1014 char *print_name = "3c59x";
1015 struct pci_dev *pdev = NULL;
1016 struct eisa_device *edev = NULL;
1018 if (!printed_version) {
1020 printed_version = 1;
1024 if ((pdev = DEVICE_PCI(gendev))) {
1025 print_name = pci_name(pdev);
1028 if ((edev = DEVICE_EISA(gendev))) {
1029 print_name = edev->dev.bus_id;
1033 dev = alloc_etherdev(sizeof(*vp));
1036 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1039 SET_MODULE_OWNER(dev);
1040 SET_NETDEV_DEV(dev, gendev);
1041 vp = netdev_priv(dev);
1043 option = global_options;
1045 /* The lower four bits are the media type. */
1046 if (dev->mem_start) {
1048 * The 'options' param is passed in as the third arg to the
1049 * LILO 'ether=' argument for non-modular use
1051 option = dev->mem_start;
1053 else if (card_idx < MAX_UNITS) {
1054 if (options[card_idx] >= 0)
1055 option = options[card_idx];
1059 if (option & 0x8000)
1061 if (option & 0x4000)
1063 if (option & 0x0400)
1067 print_info = (vortex_debug > 1);
1069 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1071 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1073 pdev ? "PCI" : "EISA",
1077 dev->base_addr = (unsigned long)ioaddr;
1080 vp->ioaddr = ioaddr;
1081 vp->large_frames = mtu > 1500;
1082 vp->drv_flags = vci->drv_flags;
1083 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1084 vp->io_size = vci->io_size;
1085 vp->card_idx = card_idx;
1087 /* module list only for Compaq device */
1088 if (gendev == NULL) {
1089 compaq_net_device = dev;
1092 /* PCI-only startup logic */
1094 /* EISA resources already marked, so only PCI needs to do this here */
1095 /* Ignore return value, because Cardbus drivers already allocate for us */
1096 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1097 vp->must_free_region = 1;
1099 /* enable bus-mastering if necessary */
1100 if (vci->flags & PCI_USES_MASTER)
1101 pci_set_master(pdev);
1103 if (vci->drv_flags & IS_VORTEX) {
1105 u8 new_latency = 248;
1107 /* Check the PCI latency value. On the 3c590 series the latency timer
1108 must be set to the maximum value to avoid data corruption that occurs
1109 when the timer expires during a transfer. This bug exists the Vortex
1111 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1112 if (pci_latency < new_latency) {
1113 printk(KERN_INFO "%s: Overriding PCI latency"
1114 " timer (CFLT) setting of %d, new value is %d.\n",
1115 print_name, pci_latency, new_latency);
1116 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1121 spin_lock_init(&vp->lock);
1122 vp->gendev = gendev;
1124 vp->mii.mdio_read = mdio_read;
1125 vp->mii.mdio_write = mdio_write;
1126 vp->mii.phy_id_mask = 0x1f;
1127 vp->mii.reg_num_mask = 0x1f;
1129 /* Makes sure rings are at least 16 byte aligned. */
1130 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1131 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1134 if (vp->rx_ring == 0)
1137 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1138 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1140 /* if we are a PCI driver, we store info in pdev->driver_data
1141 * instead of a module list */
1143 pci_set_drvdata(pdev, dev);
1145 eisa_set_drvdata(edev, dev);
1147 vp->media_override = 7;
1149 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1150 if (vp->media_override != 7)
1152 vp->full_duplex = (option & 0x200) ? 1 : 0;
1153 vp->bus_master = (option & 16) ? 1 : 0;
1156 if (global_full_duplex > 0)
1157 vp->full_duplex = 1;
1158 if (global_enable_wol > 0)
1161 if (card_idx < MAX_UNITS) {
1162 if (full_duplex[card_idx] > 0)
1163 vp->full_duplex = 1;
1164 if (flow_ctrl[card_idx] > 0)
1166 if (enable_wol[card_idx] > 0)
1170 vp->mii.force_media = vp->full_duplex;
1171 vp->options = option;
1172 /* Read the station address from the EEPROM. */
1177 if (vci->drv_flags & EEPROM_8BIT)
1179 else if (vci->drv_flags & EEPROM_OFFSET)
1180 base = EEPROM_Read + 0x30;
1184 for (i = 0; i < 0x40; i++) {
1186 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1187 /* Pause for at least 162 us. for the read to take place. */
1188 for (timer = 10; timer >= 0; timer--) {
1190 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1193 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1196 for (i = 0; i < 0x18; i++)
1197 checksum ^= eeprom[i];
1198 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1199 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1201 checksum ^= eeprom[i++];
1202 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1204 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1205 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1206 for (i = 0; i < 3; i++)
1207 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1208 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1210 for (i = 0; i < 6; i++)
1211 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1213 /* Unfortunately an all zero eeprom passes the checksum and this
1214 gets found in the wild in failure cases. Crypto is hard 8) */
1215 if (!is_valid_ether_addr(dev->dev_addr)) {
1217 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1218 goto free_ring; /* With every pack */
1221 for (i = 0; i < 6; i++)
1222 iowrite8(dev->dev_addr[i], ioaddr + i);
1225 printk(", IRQ %d\n", dev->irq);
1226 /* Tell them about an invalid IRQ. */
1227 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1228 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1232 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1234 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1235 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1236 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1240 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1243 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1244 if (!vp->cb_fn_base) {
1250 printk(KERN_INFO "%s: CardBus functions mapped "
1253 (unsigned long long)pci_resource_start(pdev, 2),
1258 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1259 if (vp->drv_flags & INVERT_LED_PWR)
1261 if (vp->drv_flags & INVERT_MII_PWR)
1263 iowrite16(n, ioaddr + Wn2_ResetOptions);
1264 if (vp->drv_flags & WNO_XCVR_PWR) {
1266 iowrite16(0x0800, ioaddr);
1270 /* Extract our information from the EEPROM data. */
1271 vp->info1 = eeprom[13];
1272 vp->info2 = eeprom[15];
1273 vp->capabilities = eeprom[16];
1275 if (vp->info1 & 0x8000) {
1276 vp->full_duplex = 1;
1278 printk(KERN_INFO "Full duplex capable\n");
1282 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1283 unsigned int config;
1285 vp->available_media = ioread16(ioaddr + Wn3_Options);
1286 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1287 vp->available_media = 0x40;
1288 config = ioread32(ioaddr + Wn3_Config);
1290 printk(KERN_DEBUG " Internal config register is %4.4x, "
1291 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1292 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1293 8 << RAM_SIZE(config),
1294 RAM_WIDTH(config) ? "word" : "byte",
1295 ram_split[RAM_SPLIT(config)],
1296 AUTOSELECT(config) ? "autoselect/" : "",
1297 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1298 media_tbl[XCVR(config)].name);
1300 vp->default_media = XCVR(config);
1301 if (vp->default_media == XCVR_NWAY)
1303 vp->autoselect = AUTOSELECT(config);
1306 if (vp->media_override != 7) {
1307 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1308 print_name, vp->media_override,
1309 media_tbl[vp->media_override].name);
1310 dev->if_port = vp->media_override;
1312 dev->if_port = vp->default_media;
1314 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1315 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1316 int phy, phy_idx = 0;
1318 mii_preamble_required++;
1319 if (vp->drv_flags & EXTRA_PREAMBLE)
1320 mii_preamble_required++;
1321 mdio_sync(ioaddr, 32);
1322 mdio_read(dev, 24, MII_BMSR);
1323 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1324 int mii_status, phyx;
1327 * For the 3c905CX we look at index 24 first, because it bogusly
1328 * reports an external PHY at all indices
1336 mii_status = mdio_read(dev, phyx, MII_BMSR);
1337 if (mii_status && mii_status != 0xffff) {
1338 vp->phys[phy_idx++] = phyx;
1340 printk(KERN_INFO " MII transceiver found at address %d,"
1341 " status %4x.\n", phyx, mii_status);
1343 if ((mii_status & 0x0040) == 0)
1344 mii_preamble_required++;
1347 mii_preamble_required--;
1349 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1352 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1353 if (vp->full_duplex) {
1354 /* Only advertise the FD media types. */
1355 vp->advertising &= ~0x02A0;
1356 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1359 vp->mii.phy_id = vp->phys[0];
1362 if (vp->capabilities & CapBusMaster) {
1363 vp->full_bus_master_tx = 1;
1365 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1366 (vp->info2 & 1) ? "early" : "whole-frame" );
1368 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1369 vp->bus_master = 0; /* AKPM: vortex only */
1372 /* The 3c59x-specific entries in the device structure. */
1373 dev->open = vortex_open;
1374 if (vp->full_bus_master_tx) {
1375 dev->hard_start_xmit = boomerang_start_xmit;
1376 /* Actually, it still should work with iommu. */
1377 if (card_idx < MAX_UNITS &&
1378 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1379 hw_checksums[card_idx] == 1)) {
1380 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1383 dev->hard_start_xmit = vortex_start_xmit;
1387 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1389 (dev->features & NETIF_F_SG) ? "en":"dis",
1390 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1393 dev->stop = vortex_close;
1394 dev->get_stats = vortex_get_stats;
1396 dev->do_ioctl = vortex_ioctl;
1398 dev->ethtool_ops = &vortex_ethtool_ops;
1399 dev->set_multicast_list = set_rx_mode;
1400 dev->tx_timeout = vortex_tx_timeout;
1401 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1402 #ifdef CONFIG_NET_POLL_CONTROLLER
1403 dev->poll_controller = poll_vortex;
1406 vp->pm_state_valid = 1;
1407 pci_save_state(VORTEX_PCI(vp));
1410 retval = register_netdev(dev);
1415 pci_free_consistent(pdev,
1416 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1417 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1421 if (vp->must_free_region)
1422 release_region(dev->base_addr, vci->io_size);
1424 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1430 issue_and_wait(struct net_device *dev, int cmd)
1432 struct vortex_private *vp = netdev_priv(dev);
1433 void __iomem *ioaddr = vp->ioaddr;
1436 iowrite16(cmd, ioaddr + EL3_CMD);
1437 for (i = 0; i < 2000; i++) {
1438 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1442 /* OK, that didn't work. Do it the slow way. One second */
1443 for (i = 0; i < 100000; i++) {
1444 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1445 if (vortex_debug > 1)
1446 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1447 dev->name, cmd, i * 10);
1452 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1453 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1457 vortex_set_duplex(struct net_device *dev)
1459 struct vortex_private *vp = netdev_priv(dev);
1460 void __iomem *ioaddr = vp->ioaddr;
1462 printk(KERN_INFO "%s: setting %s-duplex.\n",
1463 dev->name, (vp->full_duplex) ? "full" : "half");
1466 /* Set the full-duplex bit. */
1467 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1468 (vp->large_frames ? 0x40 : 0) |
1469 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1471 ioaddr + Wn3_MAC_Ctrl);
1474 static void vortex_check_media(struct net_device *dev, unsigned int init)
1476 struct vortex_private *vp = netdev_priv(dev);
1477 unsigned int ok_to_print = 0;
1479 if (vortex_debug > 3)
1482 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1483 vp->full_duplex = vp->mii.full_duplex;
1484 vortex_set_duplex(dev);
1486 vortex_set_duplex(dev);
1491 vortex_up(struct net_device *dev)
1493 struct vortex_private *vp = netdev_priv(dev);
1494 void __iomem *ioaddr = vp->ioaddr;
1495 unsigned int config;
1496 int i, mii_reg1, mii_reg5, err;
1498 if (VORTEX_PCI(vp)) {
1499 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1500 if (vp->pm_state_valid)
1501 pci_restore_state(VORTEX_PCI(vp));
1502 err = pci_enable_device(VORTEX_PCI(vp));
1504 printk(KERN_WARNING "%s: Could not enable device \n",
1510 /* Before initializing select the active media port. */
1512 config = ioread32(ioaddr + Wn3_Config);
1514 if (vp->media_override != 7) {
1515 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1516 dev->name, vp->media_override,
1517 media_tbl[vp->media_override].name);
1518 dev->if_port = vp->media_override;
1519 } else if (vp->autoselect) {
1521 if (vortex_debug > 1)
1522 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1523 dev->name, dev->if_port);
1524 dev->if_port = XCVR_NWAY;
1526 /* Find first available media type, starting with 100baseTx. */
1527 dev->if_port = XCVR_100baseTx;
1528 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1529 dev->if_port = media_tbl[dev->if_port].next;
1530 if (vortex_debug > 1)
1531 printk(KERN_INFO "%s: first available media type: %s\n",
1532 dev->name, media_tbl[dev->if_port].name);
1535 dev->if_port = vp->default_media;
1536 if (vortex_debug > 1)
1537 printk(KERN_INFO "%s: using default media %s\n",
1538 dev->name, media_tbl[dev->if_port].name);
1541 init_timer(&vp->timer);
1542 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1543 vp->timer.data = (unsigned long)dev;
1544 vp->timer.function = vortex_timer; /* timer handler */
1545 add_timer(&vp->timer);
1547 init_timer(&vp->rx_oom_timer);
1548 vp->rx_oom_timer.data = (unsigned long)dev;
1549 vp->rx_oom_timer.function = rx_oom_timer;
1551 if (vortex_debug > 1)
1552 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1553 dev->name, media_tbl[dev->if_port].name);
1555 vp->full_duplex = vp->mii.force_media;
1556 config = BFINS(config, dev->if_port, 20, 4);
1557 if (vortex_debug > 6)
1558 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1559 iowrite32(config, ioaddr + Wn3_Config);
1561 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1563 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1564 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1565 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1566 vp->mii.full_duplex = vp->full_duplex;
1568 vortex_check_media(dev, 1);
1571 vortex_set_duplex(dev);
1573 issue_and_wait(dev, TxReset);
1575 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1577 issue_and_wait(dev, RxReset|0x04);
1580 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1582 if (vortex_debug > 1) {
1584 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1585 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1588 /* Set the station address and mask in window 2 each time opened. */
1590 for (i = 0; i < 6; i++)
1591 iowrite8(dev->dev_addr[i], ioaddr + i);
1592 for (; i < 12; i+=2)
1593 iowrite16(0, ioaddr + i);
1595 if (vp->cb_fn_base) {
1596 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1597 if (vp->drv_flags & INVERT_LED_PWR)
1599 if (vp->drv_flags & INVERT_MII_PWR)
1601 iowrite16(n, ioaddr + Wn2_ResetOptions);
1604 if (dev->if_port == XCVR_10base2)
1605 /* Start the thinnet transceiver. We should really wait 50ms...*/
1606 iowrite16(StartCoax, ioaddr + EL3_CMD);
1607 if (dev->if_port != XCVR_NWAY) {
1609 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1610 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1613 /* Switch to the stats window, and clear all stats by reading. */
1614 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1616 for (i = 0; i < 10; i++)
1617 ioread8(ioaddr + i);
1618 ioread16(ioaddr + 10);
1619 ioread16(ioaddr + 12);
1620 /* New: On the Vortex we must also clear the BadSSD counter. */
1622 ioread8(ioaddr + 12);
1623 /* ..and on the Boomerang we enable the extra statistics bits. */
1624 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1626 /* Switch to register set 7 for normal use. */
1629 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1630 vp->cur_rx = vp->dirty_rx = 0;
1631 /* Initialize the RxEarly register as recommended. */
1632 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1633 iowrite32(0x0020, ioaddr + PktStatus);
1634 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1636 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1637 vp->cur_tx = vp->dirty_tx = 0;
1638 if (vp->drv_flags & IS_BOOMERANG)
1639 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1640 /* Clear the Rx, Tx rings. */
1641 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1642 vp->rx_ring[i].status = 0;
1643 for (i = 0; i < TX_RING_SIZE; i++)
1644 vp->tx_skbuff[i] = NULL;
1645 iowrite32(0, ioaddr + DownListPtr);
1647 /* Set receiver mode: presumably accept b-case and phys addr only. */
1649 /* enable 802.1q tagged frames */
1650 set_8021q_mode(dev, 1);
1651 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1653 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1654 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1655 /* Allow status bits to be seen. */
1656 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1657 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1658 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1659 (vp->bus_master ? DMADone : 0);
1660 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1661 (vp->full_bus_master_rx ? 0 : RxComplete) |
1662 StatsFull | HostError | TxComplete | IntReq
1663 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1664 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1665 /* Ack all pending events, and set active indicator mask. */
1666 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1668 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1669 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1670 iowrite32(0x8000, vp->cb_fn_base + 4);
1671 netif_start_queue (dev);
1677 vortex_open(struct net_device *dev)
1679 struct vortex_private *vp = netdev_priv(dev);
1683 /* Use the now-standard shared IRQ implementation. */
1684 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1685 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1686 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1690 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1691 if (vortex_debug > 2)
1692 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1693 for (i = 0; i < RX_RING_SIZE; i++) {
1694 struct sk_buff *skb;
1695 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1696 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1697 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1698 skb = dev_alloc_skb(PKT_BUF_SZ);
1699 vp->rx_skbuff[i] = skb;
1701 break; /* Bad news! */
1702 skb->dev = dev; /* Mark as being used by this device. */
1703 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1704 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1706 if (i != RX_RING_SIZE) {
1708 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1709 for (j = 0; j < i; j++) {
1710 if (vp->rx_skbuff[j]) {
1711 dev_kfree_skb(vp->rx_skbuff[j]);
1712 vp->rx_skbuff[j] = NULL;
1718 /* Wrap the ring. */
1719 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1722 retval = vortex_up(dev);
1727 free_irq(dev->irq, dev);
1729 if (vortex_debug > 1)
1730 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1736 vortex_timer(unsigned long data)
1738 struct net_device *dev = (struct net_device *)data;
1739 struct vortex_private *vp = netdev_priv(dev);
1740 void __iomem *ioaddr = vp->ioaddr;
1741 int next_tick = 60*HZ;
1743 int media_status, old_window;
1745 if (vortex_debug > 2) {
1746 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1747 dev->name, media_tbl[dev->if_port].name);
1748 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1751 disable_irq_lockdep(dev->irq);
1752 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1754 media_status = ioread16(ioaddr + Wn4_Media);
1755 switch (dev->if_port) {
1756 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1757 if (media_status & Media_LnkBeat) {
1758 netif_carrier_on(dev);
1760 if (vortex_debug > 1)
1761 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1762 dev->name, media_tbl[dev->if_port].name, media_status);
1764 netif_carrier_off(dev);
1765 if (vortex_debug > 1) {
1766 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1767 dev->name, media_tbl[dev->if_port].name, media_status);
1771 case XCVR_MII: case XCVR_NWAY:
1774 spin_lock_bh(&vp->lock);
1775 vortex_check_media(dev, 0);
1776 spin_unlock_bh(&vp->lock);
1779 default: /* Other media types handled by Tx timeouts. */
1780 if (vortex_debug > 1)
1781 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1782 dev->name, media_tbl[dev->if_port].name, media_status);
1786 if (!netif_carrier_ok(dev))
1790 goto leave_media_alone;
1793 unsigned int config;
1796 dev->if_port = media_tbl[dev->if_port].next;
1797 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1798 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1799 dev->if_port = vp->default_media;
1800 if (vortex_debug > 1)
1801 printk(KERN_DEBUG "%s: Media selection failing, using default "
1803 dev->name, media_tbl[dev->if_port].name);
1805 if (vortex_debug > 1)
1806 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1808 dev->name, media_tbl[dev->if_port].name);
1809 next_tick = media_tbl[dev->if_port].wait;
1811 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1812 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1815 config = ioread32(ioaddr + Wn3_Config);
1816 config = BFINS(config, dev->if_port, 20, 4);
1817 iowrite32(config, ioaddr + Wn3_Config);
1819 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1821 if (vortex_debug > 1)
1822 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1823 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1827 if (vortex_debug > 2)
1828 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1829 dev->name, media_tbl[dev->if_port].name);
1831 EL3WINDOW(old_window);
1832 enable_irq_lockdep(dev->irq);
1833 mod_timer(&vp->timer, RUN_AT(next_tick));
1835 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1839 static void vortex_tx_timeout(struct net_device *dev)
1841 struct vortex_private *vp = netdev_priv(dev);
1842 void __iomem *ioaddr = vp->ioaddr;
1844 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1845 dev->name, ioread8(ioaddr + TxStatus),
1846 ioread16(ioaddr + EL3_STATUS));
1848 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1849 ioread16(ioaddr + Wn4_NetDiag),
1850 ioread16(ioaddr + Wn4_Media),
1851 ioread32(ioaddr + PktStatus),
1852 ioread16(ioaddr + Wn4_FIFODiag));
1853 /* Slight code bloat to be user friendly. */
1854 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1855 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1856 " network cable problem?\n", dev->name);
1857 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1858 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1859 " IRQ blocked by another device?\n", dev->name);
1860 /* Bad idea here.. but we might as well handle a few events. */
1863 * Block interrupts because vortex_interrupt does a bare spin_lock()
1865 unsigned long flags;
1866 local_irq_save(flags);
1867 if (vp->full_bus_master_tx)
1868 boomerang_interrupt(dev->irq, dev);
1870 vortex_interrupt(dev->irq, dev);
1871 local_irq_restore(flags);
1875 if (vortex_debug > 0)
1878 issue_and_wait(dev, TxReset);
1880 vp->stats.tx_errors++;
1881 if (vp->full_bus_master_tx) {
1882 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
1883 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1884 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1885 ioaddr + DownListPtr);
1886 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1887 netif_wake_queue (dev);
1888 if (vp->drv_flags & IS_BOOMERANG)
1889 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1890 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1892 vp->stats.tx_dropped++;
1893 netif_wake_queue(dev);
1896 /* Issue Tx Enable */
1897 iowrite16(TxEnable, ioaddr + EL3_CMD);
1898 dev->trans_start = jiffies;
1900 /* Switch to register set 7 for normal use. */
1905 * Handle uncommon interrupt sources. This is a separate routine to minimize
1909 vortex_error(struct net_device *dev, int status)
1911 struct vortex_private *vp = netdev_priv(dev);
1912 void __iomem *ioaddr = vp->ioaddr;
1913 int do_tx_reset = 0, reset_mask = 0;
1914 unsigned char tx_status = 0;
1916 if (vortex_debug > 2) {
1917 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1920 if (status & TxComplete) { /* Really "TxError" for us. */
1921 tx_status = ioread8(ioaddr + TxStatus);
1922 /* Presumably a tx-timeout. We must merely re-enable. */
1923 if (vortex_debug > 2
1924 || (tx_status != 0x88 && vortex_debug > 0)) {
1925 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1926 dev->name, tx_status);
1927 if (tx_status == 0x82) {
1928 printk(KERN_ERR "Probably a duplex mismatch. See "
1929 "Documentation/networking/vortex.txt\n");
1933 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1934 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
1935 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1936 iowrite8(0, ioaddr + TxStatus);
1937 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1939 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1941 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1942 } else { /* Merely re-enable the transmitter. */
1943 iowrite16(TxEnable, ioaddr + EL3_CMD);
1947 if (status & RxEarly) { /* Rx early is unused. */
1949 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1951 if (status & StatsFull) { /* Empty statistics. */
1952 static int DoneDidThat;
1953 if (vortex_debug > 4)
1954 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1955 update_stats(ioaddr, dev);
1956 /* HACK: Disable statistics as an interrupt source. */
1957 /* This occurs when we have the wrong media type! */
1958 if (DoneDidThat == 0 &&
1959 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1960 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1961 "stats as an interrupt source.\n", dev->name);
1963 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1964 vp->intr_enable &= ~StatsFull;
1969 if (status & IntReq) { /* Restore all interrupt sources. */
1970 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1971 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1973 if (status & HostError) {
1976 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1977 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1978 dev->name, fifo_diag);
1979 /* Adapter failure requires Tx/Rx reset and reinit. */
1980 if (vp->full_bus_master_tx) {
1981 int bus_status = ioread32(ioaddr + PktStatus);
1982 /* 0x80000000 PCI master abort. */
1983 /* 0x40000000 PCI target abort. */
1985 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1987 /* In this case, blow the card away */
1988 /* Must not enter D3 or we can't legally issue the reset! */
1989 vortex_down(dev, 0);
1990 issue_and_wait(dev, TotalReset | 0xff);
1991 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1992 } else if (fifo_diag & 0x0400)
1994 if (fifo_diag & 0x3000) {
1995 /* Reset Rx fifo and upload logic */
1996 issue_and_wait(dev, RxReset|0x07);
1997 /* Set the Rx filter to the current state. */
1999 /* enable 802.1q VLAN tagged frames */
2000 set_8021q_mode(dev, 1);
2001 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2002 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2007 issue_and_wait(dev, TxReset|reset_mask);
2008 iowrite16(TxEnable, ioaddr + EL3_CMD);
2009 if (!vp->full_bus_master_tx)
2010 netif_wake_queue(dev);
2015 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2017 struct vortex_private *vp = netdev_priv(dev);
2018 void __iomem *ioaddr = vp->ioaddr;
2020 /* Put out the doubleword header... */
2021 iowrite32(skb->len, ioaddr + TX_FIFO);
2022 if (vp->bus_master) {
2023 /* Set the bus-master controller to transfer the packet. */
2024 int len = (skb->len + 3) & ~3;
2025 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2026 ioaddr + Wn7_MasterAddr);
2027 iowrite16(len, ioaddr + Wn7_MasterLen);
2029 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2030 /* netif_wake_queue() will be called at the DMADone interrupt. */
2032 /* ... and the packet rounded to a doubleword. */
2033 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2034 dev_kfree_skb (skb);
2035 if (ioread16(ioaddr + TxFree) > 1536) {
2036 netif_start_queue (dev); /* AKPM: redundant? */
2038 /* Interrupt us when the FIFO has room for max-sized packet. */
2039 netif_stop_queue(dev);
2040 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2044 dev->trans_start = jiffies;
2046 /* Clear the Tx status stack. */
2051 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2052 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2053 if (vortex_debug > 2)
2054 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2055 dev->name, tx_status);
2056 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2057 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2058 if (tx_status & 0x30) {
2059 issue_and_wait(dev, TxReset);
2061 iowrite16(TxEnable, ioaddr + EL3_CMD);
2063 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2070 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2072 struct vortex_private *vp = netdev_priv(dev);
2073 void __iomem *ioaddr = vp->ioaddr;
2074 /* Calculate the next Tx descriptor entry. */
2075 int entry = vp->cur_tx % TX_RING_SIZE;
2076 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2077 unsigned long flags;
2079 if (vortex_debug > 6) {
2080 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2081 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2082 dev->name, vp->cur_tx);
2085 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2086 if (vortex_debug > 0)
2087 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2089 netif_stop_queue(dev);
2093 vp->tx_skbuff[entry] = skb;
2095 vp->tx_ring[entry].next = 0;
2097 if (skb->ip_summed != CHECKSUM_PARTIAL)
2098 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2100 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2102 if (!skb_shinfo(skb)->nr_frags) {
2103 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2104 skb->len, PCI_DMA_TODEVICE));
2105 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2109 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2110 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2111 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2113 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2114 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2116 vp->tx_ring[entry].frag[i+1].addr =
2117 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2118 (void*)page_address(frag->page) + frag->page_offset,
2119 frag->size, PCI_DMA_TODEVICE));
2121 if (i == skb_shinfo(skb)->nr_frags-1)
2122 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2124 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2128 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2129 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2130 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2133 spin_lock_irqsave(&vp->lock, flags);
2134 /* Wait for the stall to complete. */
2135 issue_and_wait(dev, DownStall);
2136 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2137 if (ioread32(ioaddr + DownListPtr) == 0) {
2138 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2139 vp->queued_packet++;
2143 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2144 netif_stop_queue (dev);
2145 } else { /* Clear previous interrupt enable. */
2146 #if defined(tx_interrupt_mitigation)
2147 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2148 * were selected, this would corrupt DN_COMPLETE. No?
2150 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2153 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2154 spin_unlock_irqrestore(&vp->lock, flags);
2155 dev->trans_start = jiffies;
2159 /* The interrupt handler does all of the Rx thread work and cleans up
2160 after the Tx thread. */
2163 * This is the ISR for the vortex series chips.
2164 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2168 vortex_interrupt(int irq, void *dev_id)
2170 struct net_device *dev = dev_id;
2171 struct vortex_private *vp = netdev_priv(dev);
2172 void __iomem *ioaddr;
2174 int work_done = max_interrupt_work;
2177 ioaddr = vp->ioaddr;
2178 spin_lock(&vp->lock);
2180 status = ioread16(ioaddr + EL3_STATUS);
2182 if (vortex_debug > 6)
2183 printk("vortex_interrupt(). status=0x%4x\n", status);
2185 if ((status & IntLatch) == 0)
2186 goto handler_exit; /* No interrupt: shared IRQs cause this */
2189 if (status & IntReq) {
2190 status |= vp->deferred;
2194 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2197 if (vortex_debug > 4)
2198 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2199 dev->name, status, ioread8(ioaddr + Timer));
2202 if (vortex_debug > 5)
2203 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2205 if (status & RxComplete)
2208 if (status & TxAvailable) {
2209 if (vortex_debug > 5)
2210 printk(KERN_DEBUG " TX room bit was handled.\n");
2211 /* There's room in the FIFO for a full-sized packet. */
2212 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2213 netif_wake_queue (dev);
2216 if (status & DMADone) {
2217 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2218 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2219 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2220 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2221 if (ioread16(ioaddr + TxFree) > 1536) {
2223 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2224 * insufficient FIFO room, the TxAvailable test will succeed and call
2225 * netif_wake_queue()
2227 netif_wake_queue(dev);
2228 } else { /* Interrupt when FIFO has room for max-sized packet. */
2229 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2230 netif_stop_queue(dev);
2234 /* Check for all uncommon interrupts at once. */
2235 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2236 if (status == 0xffff)
2238 vortex_error(dev, status);
2241 if (--work_done < 0) {
2242 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2243 "%4.4x.\n", dev->name, status);
2244 /* Disable all pending interrupts. */
2246 vp->deferred |= status;
2247 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2249 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2250 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2251 /* The timer will reenable interrupts. */
2252 mod_timer(&vp->timer, jiffies + 1*HZ);
2255 /* Acknowledge the IRQ. */
2256 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2257 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2259 if (vortex_debug > 4)
2260 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2263 spin_unlock(&vp->lock);
2264 return IRQ_RETVAL(handled);
2268 * This is the ISR for the boomerang series chips.
2269 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2273 boomerang_interrupt(int irq, void *dev_id)
2275 struct net_device *dev = dev_id;
2276 struct vortex_private *vp = netdev_priv(dev);
2277 void __iomem *ioaddr;
2279 int work_done = max_interrupt_work;
2281 ioaddr = vp->ioaddr;
2284 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2285 * and boomerang_start_xmit
2287 spin_lock(&vp->lock);
2289 status = ioread16(ioaddr + EL3_STATUS);
2291 if (vortex_debug > 6)
2292 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2294 if ((status & IntLatch) == 0)
2295 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2297 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2298 if (vortex_debug > 1)
2299 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2303 if (status & IntReq) {
2304 status |= vp->deferred;
2308 if (vortex_debug > 4)
2309 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2310 dev->name, status, ioread8(ioaddr + Timer));
2312 if (vortex_debug > 5)
2313 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2315 if (status & UpComplete) {
2316 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2317 if (vortex_debug > 5)
2318 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2322 if (status & DownComplete) {
2323 unsigned int dirty_tx = vp->dirty_tx;
2325 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2326 while (vp->cur_tx - dirty_tx > 0) {
2327 int entry = dirty_tx % TX_RING_SIZE;
2328 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2329 if (ioread32(ioaddr + DownListPtr) ==
2330 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2331 break; /* It still hasn't been processed. */
2333 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2334 break; /* It still hasn't been processed. */
2337 if (vp->tx_skbuff[entry]) {
2338 struct sk_buff *skb = vp->tx_skbuff[entry];
2341 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2342 pci_unmap_single(VORTEX_PCI(vp),
2343 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2344 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2347 pci_unmap_single(VORTEX_PCI(vp),
2348 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2350 dev_kfree_skb_irq(skb);
2351 vp->tx_skbuff[entry] = NULL;
2353 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2355 /* vp->stats.tx_packets++; Counted below. */
2358 vp->dirty_tx = dirty_tx;
2359 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2360 if (vortex_debug > 6)
2361 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2362 netif_wake_queue (dev);
2366 /* Check for all uncommon interrupts at once. */
2367 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2368 vortex_error(dev, status);
2370 if (--work_done < 0) {
2371 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2372 "%4.4x.\n", dev->name, status);
2373 /* Disable all pending interrupts. */
2375 vp->deferred |= status;
2376 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2378 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2379 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2380 /* The timer will reenable interrupts. */
2381 mod_timer(&vp->timer, jiffies + 1*HZ);
2384 /* Acknowledge the IRQ. */
2385 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2386 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2387 iowrite32(0x8000, vp->cb_fn_base + 4);
2389 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2391 if (vortex_debug > 4)
2392 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2395 spin_unlock(&vp->lock);
2399 static int vortex_rx(struct net_device *dev)
2401 struct vortex_private *vp = netdev_priv(dev);
2402 void __iomem *ioaddr = vp->ioaddr;
2406 if (vortex_debug > 5)
2407 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2408 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2409 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2410 if (rx_status & 0x4000) { /* Error, update stats. */
2411 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2412 if (vortex_debug > 2)
2413 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2414 vp->stats.rx_errors++;
2415 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2416 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2417 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2418 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2419 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2421 /* The packet length: up to 4.5K!. */
2422 int pkt_len = rx_status & 0x1fff;
2423 struct sk_buff *skb;
2425 skb = dev_alloc_skb(pkt_len + 5);
2426 if (vortex_debug > 4)
2427 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2428 pkt_len, rx_status);
2430 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2431 /* 'skb_put()' points to the start of sk_buff data area. */
2432 if (vp->bus_master &&
2433 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2434 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2435 pkt_len, PCI_DMA_FROMDEVICE);
2436 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2437 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2438 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2439 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2441 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2443 ioread32_rep(ioaddr + RX_FIFO,
2444 skb_put(skb, pkt_len),
2445 (pkt_len + 3) >> 2);
2447 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2448 skb->protocol = eth_type_trans(skb, dev);
2450 dev->last_rx = jiffies;
2451 vp->stats.rx_packets++;
2452 /* Wait a limited time to go to next packet. */
2453 for (i = 200; i >= 0; i--)
2454 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2457 } else if (vortex_debug > 0)
2458 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2459 "size %d.\n", dev->name, pkt_len);
2460 vp->stats.rx_dropped++;
2462 issue_and_wait(dev, RxDiscard);
2469 boomerang_rx(struct net_device *dev)
2471 struct vortex_private *vp = netdev_priv(dev);
2472 int entry = vp->cur_rx % RX_RING_SIZE;
2473 void __iomem *ioaddr = vp->ioaddr;
2475 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2477 if (vortex_debug > 5)
2478 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2480 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2481 if (--rx_work_limit < 0)
2483 if (rx_status & RxDError) { /* Error, update stats. */
2484 unsigned char rx_error = rx_status >> 16;
2485 if (vortex_debug > 2)
2486 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2487 vp->stats.rx_errors++;
2488 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2489 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2490 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2491 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2492 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2494 /* The packet length: up to 4.5K!. */
2495 int pkt_len = rx_status & 0x1fff;
2496 struct sk_buff *skb;
2497 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2499 if (vortex_debug > 4)
2500 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2501 pkt_len, rx_status);
2503 /* Check if the packet is long enough to just accept without
2504 copying to a properly sized skbuff. */
2505 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2506 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2507 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2508 /* 'skb_put()' points to the start of sk_buff data area. */
2509 memcpy(skb_put(skb, pkt_len),
2510 vp->rx_skbuff[entry]->data,
2512 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2515 /* Pass up the skbuff already on the Rx ring. */
2516 skb = vp->rx_skbuff[entry];
2517 vp->rx_skbuff[entry] = NULL;
2518 skb_put(skb, pkt_len);
2519 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2522 skb->protocol = eth_type_trans(skb, dev);
2523 { /* Use hardware checksum info. */
2524 int csum_bits = rx_status & 0xee000000;
2526 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2527 csum_bits == (IPChksumValid | UDPChksumValid))) {
2528 skb->ip_summed = CHECKSUM_UNNECESSARY;
2533 dev->last_rx = jiffies;
2534 vp->stats.rx_packets++;
2536 entry = (++vp->cur_rx) % RX_RING_SIZE;
2538 /* Refill the Rx ring buffers. */
2539 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2540 struct sk_buff *skb;
2541 entry = vp->dirty_rx % RX_RING_SIZE;
2542 if (vp->rx_skbuff[entry] == NULL) {
2543 skb = dev_alloc_skb(PKT_BUF_SZ);
2545 static unsigned long last_jif;
2546 if (time_after(jiffies, last_jif + 10 * HZ)) {
2547 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2550 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2551 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2552 break; /* Bad news! */
2554 skb->dev = dev; /* Mark as being used by this device. */
2555 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2556 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2557 vp->rx_skbuff[entry] = skb;
2559 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2560 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2566 * If we've hit a total OOM refilling the Rx ring we poll once a second
2567 * for some memory. Otherwise there is no way to restart the rx process.
2570 rx_oom_timer(unsigned long arg)
2572 struct net_device *dev = (struct net_device *)arg;
2573 struct vortex_private *vp = netdev_priv(dev);
2575 spin_lock_irq(&vp->lock);
2576 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2578 if (vortex_debug > 1) {
2579 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2580 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2582 spin_unlock_irq(&vp->lock);
2586 vortex_down(struct net_device *dev, int final_down)
2588 struct vortex_private *vp = netdev_priv(dev);
2589 void __iomem *ioaddr = vp->ioaddr;
2591 netif_stop_queue (dev);
2593 del_timer_sync(&vp->rx_oom_timer);
2594 del_timer_sync(&vp->timer);
2596 /* Turn off statistics ASAP. We update vp->stats below. */
2597 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2599 /* Disable the receiver and transmitter. */
2600 iowrite16(RxDisable, ioaddr + EL3_CMD);
2601 iowrite16(TxDisable, ioaddr + EL3_CMD);
2603 /* Disable receiving 802.1q tagged frames */
2604 set_8021q_mode(dev, 0);
2606 if (dev->if_port == XCVR_10base2)
2607 /* Turn off thinnet power. Green! */
2608 iowrite16(StopCoax, ioaddr + EL3_CMD);
2610 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2612 update_stats(ioaddr, dev);
2613 if (vp->full_bus_master_rx)
2614 iowrite32(0, ioaddr + UpListPtr);
2615 if (vp->full_bus_master_tx)
2616 iowrite32(0, ioaddr + DownListPtr);
2618 if (final_down && VORTEX_PCI(vp)) {
2619 vp->pm_state_valid = 1;
2620 pci_save_state(VORTEX_PCI(vp));
2626 vortex_close(struct net_device *dev)
2628 struct vortex_private *vp = netdev_priv(dev);
2629 void __iomem *ioaddr = vp->ioaddr;
2632 if (netif_device_present(dev))
2633 vortex_down(dev, 1);
2635 if (vortex_debug > 1) {
2636 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2637 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2638 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2639 " tx_queued %d Rx pre-checksummed %d.\n",
2640 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2644 if (vp->rx_csumhits &&
2645 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2646 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2647 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2648 "not using them!\n", dev->name);
2652 free_irq(dev->irq, dev);
2654 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2655 for (i = 0; i < RX_RING_SIZE; i++)
2656 if (vp->rx_skbuff[i]) {
2657 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2658 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2659 dev_kfree_skb(vp->rx_skbuff[i]);
2660 vp->rx_skbuff[i] = NULL;
2663 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2664 for (i = 0; i < TX_RING_SIZE; i++) {
2665 if (vp->tx_skbuff[i]) {
2666 struct sk_buff *skb = vp->tx_skbuff[i];
2670 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2671 pci_unmap_single(VORTEX_PCI(vp),
2672 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2673 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2676 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2679 vp->tx_skbuff[i] = NULL;
2688 dump_tx_ring(struct net_device *dev)
2690 if (vortex_debug > 0) {
2691 struct vortex_private *vp = netdev_priv(dev);
2692 void __iomem *ioaddr = vp->ioaddr;
2694 if (vp->full_bus_master_tx) {
2696 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2698 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2699 vp->full_bus_master_tx,
2700 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2701 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2702 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2703 ioread32(ioaddr + DownListPtr),
2704 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2705 issue_and_wait(dev, DownStall);
2706 for (i = 0; i < TX_RING_SIZE; i++) {
2707 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2710 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2712 le32_to_cpu(vp->tx_ring[i].length),
2714 le32_to_cpu(vp->tx_ring[i].status));
2717 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2722 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2724 struct vortex_private *vp = netdev_priv(dev);
2725 void __iomem *ioaddr = vp->ioaddr;
2726 unsigned long flags;
2728 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2729 spin_lock_irqsave (&vp->lock, flags);
2730 update_stats(ioaddr, dev);
2731 spin_unlock_irqrestore (&vp->lock, flags);
2736 /* Update statistics.
2737 Unlike with the EL3 we need not worry about interrupts changing
2738 the window setting from underneath us, but we must still guard
2739 against a race condition with a StatsUpdate interrupt updating the
2740 table. This is done by checking that the ASM (!) code generated uses
2741 atomic updates with '+='.
2743 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2745 struct vortex_private *vp = netdev_priv(dev);
2746 int old_window = ioread16(ioaddr + EL3_CMD);
2748 if (old_window == 0xffff) /* Chip suspended or ejected. */
2750 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2751 /* Switch to the stats window, and read everything. */
2753 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2754 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2755 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2756 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2757 vp->stats.tx_packets += ioread8(ioaddr + 6);
2758 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2759 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
2760 /* Don't bother with register 9, an extension of registers 6&7.
2761 If we do use the 6&7 values the atomic update assumption above
2763 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2764 vp->stats.tx_bytes += ioread16(ioaddr + 12);
2765 /* Extra stats for get_ethtool_stats() */
2766 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2767 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
2768 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
2770 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2772 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2773 + vp->xstats.tx_single_collisions
2774 + vp->xstats.tx_max_collisions;
2777 u8 up = ioread8(ioaddr + 13);
2778 vp->stats.rx_bytes += (up & 0x0f) << 16;
2779 vp->stats.tx_bytes += (up & 0xf0) << 12;
2782 EL3WINDOW(old_window >> 13);
2786 static int vortex_nway_reset(struct net_device *dev)
2788 struct vortex_private *vp = netdev_priv(dev);
2789 void __iomem *ioaddr = vp->ioaddr;
2790 unsigned long flags;
2793 spin_lock_irqsave(&vp->lock, flags);
2795 rc = mii_nway_restart(&vp->mii);
2796 spin_unlock_irqrestore(&vp->lock, flags);
2800 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2802 struct vortex_private *vp = netdev_priv(dev);
2803 void __iomem *ioaddr = vp->ioaddr;
2804 unsigned long flags;
2807 spin_lock_irqsave(&vp->lock, flags);
2809 rc = mii_ethtool_gset(&vp->mii, cmd);
2810 spin_unlock_irqrestore(&vp->lock, flags);
2814 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2816 struct vortex_private *vp = netdev_priv(dev);
2817 void __iomem *ioaddr = vp->ioaddr;
2818 unsigned long flags;
2821 spin_lock_irqsave(&vp->lock, flags);
2823 rc = mii_ethtool_sset(&vp->mii, cmd);
2824 spin_unlock_irqrestore(&vp->lock, flags);
2828 static u32 vortex_get_msglevel(struct net_device *dev)
2830 return vortex_debug;
2833 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2838 static int vortex_get_stats_count(struct net_device *dev)
2840 return VORTEX_NUM_STATS;
2843 static void vortex_get_ethtool_stats(struct net_device *dev,
2844 struct ethtool_stats *stats, u64 *data)
2846 struct vortex_private *vp = netdev_priv(dev);
2847 void __iomem *ioaddr = vp->ioaddr;
2848 unsigned long flags;
2850 spin_lock_irqsave(&vp->lock, flags);
2851 update_stats(ioaddr, dev);
2852 spin_unlock_irqrestore(&vp->lock, flags);
2854 data[0] = vp->xstats.tx_deferred;
2855 data[1] = vp->xstats.tx_max_collisions;
2856 data[2] = vp->xstats.tx_multiple_collisions;
2857 data[3] = vp->xstats.tx_single_collisions;
2858 data[4] = vp->xstats.rx_bad_ssd;
2862 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2864 switch (stringset) {
2866 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2874 static void vortex_get_drvinfo(struct net_device *dev,
2875 struct ethtool_drvinfo *info)
2877 struct vortex_private *vp = netdev_priv(dev);
2879 strcpy(info->driver, DRV_NAME);
2880 if (VORTEX_PCI(vp)) {
2881 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2883 if (VORTEX_EISA(vp))
2884 sprintf(info->bus_info, vp->gendev->bus_id);
2886 sprintf(info->bus_info, "EISA 0x%lx %d",
2887 dev->base_addr, dev->irq);
2891 static const struct ethtool_ops vortex_ethtool_ops = {
2892 .get_drvinfo = vortex_get_drvinfo,
2893 .get_strings = vortex_get_strings,
2894 .get_msglevel = vortex_get_msglevel,
2895 .set_msglevel = vortex_set_msglevel,
2896 .get_ethtool_stats = vortex_get_ethtool_stats,
2897 .get_stats_count = vortex_get_stats_count,
2898 .get_settings = vortex_get_settings,
2899 .set_settings = vortex_set_settings,
2900 .get_link = ethtool_op_get_link,
2901 .nway_reset = vortex_nway_reset,
2906 * Must power the device up to do MDIO operations
2908 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2911 struct vortex_private *vp = netdev_priv(dev);
2912 void __iomem *ioaddr = vp->ioaddr;
2913 unsigned long flags;
2917 state = VORTEX_PCI(vp)->current_state;
2919 /* The kernel core really should have pci_get_power_state() */
2922 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2923 spin_lock_irqsave(&vp->lock, flags);
2925 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2926 spin_unlock_irqrestore(&vp->lock, flags);
2928 pci_set_power_state(VORTEX_PCI(vp), state);
2935 /* Pre-Cyclone chips have no documented multicast filter, so the only
2936 multicast setting is to receive all multicast frames. At least
2937 the chip has a very clean way to set the mode, unlike many others. */
2938 static void set_rx_mode(struct net_device *dev)
2940 struct vortex_private *vp = netdev_priv(dev);
2941 void __iomem *ioaddr = vp->ioaddr;
2944 if (dev->flags & IFF_PROMISC) {
2945 if (vortex_debug > 3)
2946 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2947 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2948 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2949 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2951 new_mode = SetRxFilter | RxStation | RxBroadcast;
2953 iowrite16(new_mode, ioaddr + EL3_CMD);
2956 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2957 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2958 Note that this must be done after each RxReset due to some backwards
2959 compatibility logic in the Cyclone and Tornado ASICs */
2961 /* The Ethernet Type used for 802.1q tagged frames */
2962 #define VLAN_ETHER_TYPE 0x8100
2964 static void set_8021q_mode(struct net_device *dev, int enable)
2966 struct vortex_private *vp = netdev_priv(dev);
2967 void __iomem *ioaddr = vp->ioaddr;
2968 int old_window = ioread16(ioaddr + EL3_CMD);
2971 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2972 /* cyclone and tornado chipsets can recognize 802.1q
2973 * tagged frames and treat them correctly */
2975 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2977 max_pkt_size += 4; /* 802.1Q VLAN tag */
2980 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
2982 /* set VlanEtherType to let the hardware checksumming
2983 treat tagged frames correctly */
2985 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
2987 /* on older cards we have to enable large frames */
2989 vp->large_frames = dev->mtu > 1500 || enable;
2992 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
2993 if (vp->large_frames)
2997 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3000 EL3WINDOW(old_window);
3004 static void set_8021q_mode(struct net_device *dev, int enable)
3011 /* MII transceiver control section.
3012 Read and write the MII registers using software-generated serial
3013 MDIO protocol. See the MII specifications or DP83840A data sheet
3016 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3017 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3018 "overclocking" issues. */
3019 #define mdio_delay() ioread32(mdio_addr)
3021 #define MDIO_SHIFT_CLK 0x01
3022 #define MDIO_DIR_WRITE 0x04
3023 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3024 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3025 #define MDIO_DATA_READ 0x02
3026 #define MDIO_ENB_IN 0x00
3028 /* Generate the preamble required for initial synchronization and
3029 a few older transceivers. */
3030 static void mdio_sync(void __iomem *ioaddr, int bits)
3032 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3034 /* Establish sync by sending at least 32 logic ones. */
3035 while (-- bits >= 0) {
3036 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
3038 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3043 static int mdio_read(struct net_device *dev, int phy_id, int location)
3046 struct vortex_private *vp = netdev_priv(dev);
3047 void __iomem *ioaddr = vp->ioaddr;
3048 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3049 unsigned int retval = 0;
3050 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3052 if (mii_preamble_required)
3053 mdio_sync(ioaddr, 32);
3055 /* Shift the read command bits out. */
3056 for (i = 14; i >= 0; i--) {
3057 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3058 iowrite16(dataval, mdio_addr);
3060 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3063 /* Read the two transition, 16 data, and wire-idle bits. */
3064 for (i = 19; i > 0; i--) {
3065 iowrite16(MDIO_ENB_IN, mdio_addr);
3067 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3068 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3071 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3074 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3076 struct vortex_private *vp = netdev_priv(dev);
3077 void __iomem *ioaddr = vp->ioaddr;
3078 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3079 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3082 if (mii_preamble_required)
3083 mdio_sync(ioaddr, 32);
3085 /* Shift the command bits out. */
3086 for (i = 31; i >= 0; i--) {
3087 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3088 iowrite16(dataval, mdio_addr);
3090 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3093 /* Leave the interface idle. */
3094 for (i = 1; i >= 0; i--) {
3095 iowrite16(MDIO_ENB_IN, mdio_addr);
3097 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3103 /* ACPI: Advanced Configuration and Power Interface. */
3104 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3105 static void acpi_set_WOL(struct net_device *dev)
3107 struct vortex_private *vp = netdev_priv(dev);
3108 void __iomem *ioaddr = vp->ioaddr;
3110 if (vp->enable_wol) {
3111 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3113 iowrite16(2, ioaddr + 0x0c);
3114 /* The RxFilter must accept the WOL frames. */
3115 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3116 iowrite16(RxEnable, ioaddr + EL3_CMD);
3118 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3120 /* Change the power state to D3; RxEnable doesn't take effect. */
3121 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3126 static void __devexit vortex_remove_one(struct pci_dev *pdev)
3128 struct net_device *dev = pci_get_drvdata(pdev);
3129 struct vortex_private *vp;
3132 printk("vortex_remove_one called for Compaq device!\n");
3136 vp = netdev_priv(dev);
3139 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3141 unregister_netdev(dev);
3143 if (VORTEX_PCI(vp)) {
3144 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3145 if (vp->pm_state_valid)
3146 pci_restore_state(VORTEX_PCI(vp));
3147 pci_disable_device(VORTEX_PCI(vp));
3149 /* Should really use issue_and_wait() here */
3150 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3151 vp->ioaddr + EL3_CMD);
3153 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3155 pci_free_consistent(pdev,
3156 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3157 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3160 if (vp->must_free_region)
3161 release_region(dev->base_addr, vp->io_size);
3166 static struct pci_driver vortex_driver = {
3168 .probe = vortex_init_one,
3169 .remove = __devexit_p(vortex_remove_one),
3170 .id_table = vortex_pci_tbl,
3172 .suspend = vortex_suspend,
3173 .resume = vortex_resume,
3178 static int vortex_have_pci;
3179 static int vortex_have_eisa;
3182 static int __init vortex_init(void)
3184 int pci_rc, eisa_rc;
3186 pci_rc = pci_register_driver(&vortex_driver);
3187 eisa_rc = vortex_eisa_init();
3190 vortex_have_pci = 1;
3192 vortex_have_eisa = 1;
3194 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3198 static void __exit vortex_eisa_cleanup(void)
3200 struct vortex_private *vp;
3201 void __iomem *ioaddr;
3204 /* Take care of the EISA devices */
3205 eisa_driver_unregister(&vortex_eisa_driver);
3208 if (compaq_net_device) {
3209 vp = compaq_net_device->priv;
3210 ioaddr = ioport_map(compaq_net_device->base_addr,
3213 unregister_netdev(compaq_net_device);
3214 iowrite16(TotalReset, ioaddr + EL3_CMD);
3215 release_region(compaq_net_device->base_addr,
3218 free_netdev(compaq_net_device);
3223 static void __exit vortex_cleanup(void)
3225 if (vortex_have_pci)
3226 pci_unregister_driver(&vortex_driver);
3227 if (vortex_have_eisa)
3228 vortex_eisa_cleanup();
3232 module_init(vortex_init);
3233 module_exit(vortex_cleanup);