1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Linux Kernel Additions:
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
93 - Added 802.3x MAC-layer flow control support
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
198 #define DRV_NAME "3c59x"
199 #define DRV_VERSION "LK1.1.19"
200 #define DRV_RELDATE "10 Nov 2002"
204 /* A few values that may be tweaked. */
205 /* Keep the ring sizes a power of two for efficiency. */
206 #define TX_RING_SIZE 16
207 #define RX_RING_SIZE 32
208 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
210 /* "Knobs" that adjust features and parameters. */
211 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
212 Setting to > 1512 effectively disables this feature. */
214 static int rx_copybreak = 200;
216 /* ARM systems perform better by disregarding the bus-master
217 transfer capability of these cards. -- rmk */
218 static int rx_copybreak = 1513;
220 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
221 static const int mtu = 1500;
222 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
223 static int max_interrupt_work = 32;
224 /* Tx timeout interval (millisecs) */
225 static int watchdog = 5000;
227 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
228 * of possible Tx stalls if the system is blocking interrupts
229 * somewhere else. Undefine this to disable.
231 #define tx_interrupt_mitigation 1
233 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
234 #define vortex_debug debug
236 static int vortex_debug = VORTEX_DEBUG;
238 static int vortex_debug = 1;
241 #include <linux/config.h>
242 #include <linux/module.h>
243 #include <linux/kernel.h>
244 #include <linux/string.h>
245 #include <linux/timer.h>
246 #include <linux/errno.h>
247 #include <linux/in.h>
248 #include <linux/ioport.h>
249 #include <linux/slab.h>
250 #include <linux/interrupt.h>
251 #include <linux/pci.h>
252 #include <linux/mii.h>
253 #include <linux/init.h>
254 #include <linux/netdevice.h>
255 #include <linux/etherdevice.h>
256 #include <linux/skbuff.h>
257 #include <linux/ethtool.h>
258 #include <linux/highmem.h>
259 #include <linux/eisa.h>
260 #include <linux/bitops.h>
261 #include <linux/jiffies.h>
262 #include <asm/irq.h> /* For NR_IRQS only. */
264 #include <asm/uaccess.h>
266 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
267 This is only in the support-all-kernels source code. */
269 #define RUN_AT(x) (jiffies + (x))
271 #include <linux/delay.h>
274 static char version[] __devinitdata =
275 DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
277 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
278 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "
279 DRV_VERSION " " DRV_RELDATE);
280 MODULE_LICENSE("GPL");
281 MODULE_VERSION(DRV_VERSION);
284 /* Operational parameter that usually are not changed. */
286 /* The Vortex size is twice that of the original EtherLinkIII series: the
287 runtime register window, window 1, is now always mapped in.
288 The Boomerang size is twice as large as the Vortex -- it has additional
289 bus master control registers. */
290 #define VORTEX_TOTAL_SIZE 0x20
291 #define BOOMERANG_TOTAL_SIZE 0x40
293 /* Set iff a MII transceiver on any interface requires mdio preamble.
294 This only set with the original DP83840 on older 3c905 boards, so the extra
295 code size of a per-interface flag is not worthwhile. */
296 static char mii_preamble_required;
298 #define PFX DRV_NAME ": "
305 I. Board Compatibility
307 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
308 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
309 versions of the FastEtherLink cards. The supported product IDs are
310 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
312 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
313 with the kernel source or available from
314 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
316 II. Board-specific settings
318 PCI bus devices are configured by the system at boot time, so no jumpers
319 need to be set on the board. The system BIOS should be set to assign the
320 PCI INTA signal to an otherwise unused system IRQ line.
322 The EEPROM settings for media type and forced-full-duplex are observed.
323 The EEPROM media type should be left at the default "autoselect" unless using
324 10base2 or AUI connections which cannot be reliably detected.
326 III. Driver operation
328 The 3c59x series use an interface that's very similar to the previous 3c5x9
329 series. The primary interface is two programmed-I/O FIFOs, with an
330 alternate single-contiguous-region bus-master transfer (see next).
332 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
333 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
334 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
335 programmed-I/O interface that has been removed in 'B' and subsequent board
338 One extension that is advertised in a very large font is that the adapters
339 are capable of being bus masters. On the Vortex chip this capability was
340 only for a single contiguous region making it far less useful than the full
341 bus master capability. There is a significant performance impact of taking
342 an extra interrupt or polling for the completion of each transfer, as well
343 as difficulty sharing the single transfer engine between the transmit and
344 receive threads. Using DMA transfers is a win only with large blocks or
345 with the flawed versions of the Intel Orion motherboard PCI controller.
347 The Boomerang chip's full-bus-master interface is useful, and has the
348 currently-unused advantages over other similar chips that queued transmit
349 packets may be reordered and receive buffer groups are associated with a
352 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
353 Rather than a fixed intermediate receive buffer, this scheme allocates
354 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
355 the copying breakpoint: it is chosen to trade-off the memory wasted by
356 passing the full-sized skbuff to the queue layer for all frames vs. the
357 copying cost of copying a frame to a correctly-sized skbuff.
359 IIIC. Synchronization
360 The driver runs as two independent, single-threaded flows of control. One
361 is the send-packet routine, which enforces single-threaded use by the
362 dev->tbusy flag. The other thread is the interrupt handler, which is single
363 threaded by the hardware and other software.
367 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
368 3c590, 3c595, and 3c900 boards.
369 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
370 the EISA version is called "Demon". According to Terry these names come
371 from rides at the local amusement park.
373 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
374 This driver only supports ethernet packets because of the skbuff allocation
378 /* This table drives the PCI probe routines. It's mostly boilerplate in all
379 of the drivers, and will likely be provided by some future kernel.
382 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
383 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
386 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
387 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
388 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
389 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
390 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
391 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
442 /* note: this array directly indexed by above enums, and MUST
443 * be kept in sync with both the enums above, and the PCI device
446 static struct vortex_chip_info {
451 } vortex_info_tbl[] __devinitdata = {
452 {"3c590 Vortex 10Mbps",
453 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
454 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
455 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
456 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
457 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
458 {"3c595 Vortex 100baseTx",
459 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
460 {"3c595 Vortex 100baseT4",
461 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
463 {"3c595 Vortex 100base-MII",
464 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
465 {"3c900 Boomerang 10baseT",
466 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
467 {"3c900 Boomerang 10Mbps Combo",
468 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
469 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
470 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
471 {"3c900 Cyclone 10Mbps Combo",
472 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
474 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
475 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
476 {"3c900B-FL Cyclone 10base-FL",
477 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
478 {"3c905 Boomerang 100baseTx",
479 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
480 {"3c905 Boomerang 100baseT4",
481 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
482 {"3c905B Cyclone 100baseTx",
483 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
485 {"3c905B Cyclone 10/100/BNC",
486 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
487 {"3c905B-FX Cyclone 100baseFx",
488 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
490 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
491 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
492 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
494 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
497 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
498 {"3cSOHO100-TX Hurricane",
499 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
500 {"3c555 Laptop Hurricane",
501 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
502 {"3c556 Laptop Tornado",
503 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
505 {"3c556B Laptop Hurricane",
506 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
507 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
509 {"3c575 [Megahertz] 10/100 LAN CardBus",
510 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
511 {"3c575 Boomerang CardBus",
512 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
513 {"3CCFE575BT Cyclone CardBus",
514 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
515 INVERT_LED_PWR|HAS_HWCKSM, 128, },
516 {"3CCFE575CT Tornado CardBus",
517 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
518 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
519 {"3CCFE656 Cyclone CardBus",
520 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
521 INVERT_LED_PWR|HAS_HWCKSM, 128, },
523 {"3CCFEM656B Cyclone+Winmodem CardBus",
524 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
525 INVERT_LED_PWR|HAS_HWCKSM, 128, },
526 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
527 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
528 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
529 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
530 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
532 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
533 {"3c982 Hydra Dual Port A",
534 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
536 {"3c982 Hydra Dual Port B",
537 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
539 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
540 {"3c920B-EMB-WNM Tornado",
541 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
543 {NULL,}, /* NULL terminated list. */
547 static struct pci_device_id vortex_pci_tbl[] = {
548 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
549 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
550 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
551 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
552 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
554 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
555 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
556 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
557 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
558 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
560 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
561 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
562 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
563 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
564 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
566 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
567 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
568 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
569 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
570 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
571 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
573 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
574 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
575 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
576 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
577 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
579 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
580 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
581 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
582 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
583 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
585 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
586 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
587 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
588 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
589 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
591 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
592 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
594 {0,} /* 0 terminated list. */
596 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
599 /* Operational definitions.
600 These are not used by other compilation units and thus are not
601 exported in a ".h" file.
603 First the windows. There are eight register windows, with the command
604 and status registers available in each.
606 #define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
608 #define EL3_STATUS 0x0e
610 /* The top five bits written to EL3_CMD are a command, the lower
611 11 bits are the parameter, if applicable.
612 Note that 11 parameters bits was fine for ethernet, but the new chip
613 can handle FDDI length frames (~4500 octets) and now parameters count
614 32-bit 'Dwords' rather than octets. */
617 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
618 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
619 UpStall = 6<<11, UpUnstall = (6<<11)+1,
620 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
621 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
622 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
623 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
624 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
625 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
626 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
628 /* The SetRxFilter command accepts the following classes: */
630 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
632 /* Bits in the general status register. */
634 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
635 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
636 IntReq = 0x0040, StatsFull = 0x0080,
637 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
638 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
639 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
642 /* Register window 1 offsets, the window used in normal operation.
643 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
645 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
646 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
647 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
650 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
651 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
652 IntrStatus=0x0E, /* Valid in all windows. */
654 enum Win0_EEPROM_bits {
655 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
656 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
657 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
659 /* EEPROM locations. */
661 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
662 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
663 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
664 DriverTune=13, Checksum=15};
666 enum Window2 { /* Window 2. */
669 enum Window3 { /* Window 3: MAC/config bits. */
670 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
673 #define BFEXT(value, offset, bitcount) \
674 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
676 #define BFINS(lhs, rhs, offset, bitcount) \
677 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
678 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
680 #define RAM_SIZE(v) BFEXT(v, 0, 3)
681 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
682 #define RAM_SPEED(v) BFEXT(v, 4, 2)
683 #define ROM_SIZE(v) BFEXT(v, 6, 2)
684 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
685 #define XCVR(v) BFEXT(v, 20, 4)
686 #define AUTOSELECT(v) BFEXT(v, 24, 1)
688 enum Window4 { /* Window 4: Xcvr/media bits. */
689 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
691 enum Win4_Media_bits {
692 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
693 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
694 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
695 Media_LnkBeat = 0x0800,
697 enum Window7 { /* Window 7: Bus Master control. */
698 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
699 Wn7_MasterStatus = 12,
701 /* Boomerang bus master control registers. */
703 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
704 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
707 /* The Rx and Tx descriptor lists.
708 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
709 alignment contraint on tx_ring[] and rx_ring[]. */
710 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
711 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
712 struct boom_rx_desc {
713 u32 next; /* Last entry points to 0. */
715 u32 addr; /* Up to 63 addr/len pairs possible. */
716 s32 length; /* Set LAST_FRAG to indicate last pair. */
718 /* Values for the Rx status entry. */
719 enum rx_desc_status {
720 RxDComplete=0x00008000, RxDError=0x4000,
721 /* See boomerang_rx() for actual error bits */
722 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
723 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
727 #define DO_ZEROCOPY 1
729 #define DO_ZEROCOPY 0
732 struct boom_tx_desc {
733 u32 next; /* Last entry points to 0. */
734 s32 status; /* bits 0:12 length, others see below. */
739 } frag[1+MAX_SKB_FRAGS];
746 /* Values for the Tx status entry. */
747 enum tx_desc_status {
748 CRCDisable=0x2000, TxDComplete=0x8000,
749 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
750 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
753 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
754 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
756 struct vortex_extra_stats {
757 unsigned long tx_deferred;
758 unsigned long tx_max_collisions;
759 unsigned long tx_multiple_collisions;
760 unsigned long tx_single_collisions;
761 unsigned long rx_bad_ssd;
764 struct vortex_private {
765 /* The Rx and Tx rings should be quad-word-aligned. */
766 struct boom_rx_desc* rx_ring;
767 struct boom_tx_desc* tx_ring;
768 dma_addr_t rx_ring_dma;
769 dma_addr_t tx_ring_dma;
770 /* The addresses of transmit- and receive-in-place skbuffs. */
771 struct sk_buff* rx_skbuff[RX_RING_SIZE];
772 struct sk_buff* tx_skbuff[TX_RING_SIZE];
773 unsigned int cur_rx, cur_tx; /* The next free ring entry */
774 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
775 struct net_device_stats stats; /* Generic stats */
776 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
777 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
778 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
780 /* PCI configuration space information. */
781 struct device *gendev;
782 void __iomem *ioaddr; /* IO address space */
783 void __iomem *cb_fn_base; /* CardBus function status addr space. */
785 /* Some values here only for performance evaluation and path-coverage */
786 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
789 /* The remainder are related to chip state, mostly media selection. */
790 struct timer_list timer; /* Media selection timer. */
791 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
792 int options; /* User-settable misc. driver options. */
793 unsigned int media_override:4, /* Passed-in media type. */
794 default_media:4, /* Read from the EEPROM/Wn3_Config. */
795 full_duplex:1, force_fd:1, autoselect:1,
796 bus_master:1, /* Vortex can only do a fragment bus-m. */
797 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
798 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
799 partner_flow_ctrl:1, /* Partner supports flow control */
801 enable_wol:1, /* Wake-on-LAN is enabled */
802 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
805 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
806 large_frames:1; /* accept large frames */
810 u16 available_media; /* From Wn3_Options. */
811 u16 capabilities, info1, info2; /* Various, from EEPROM. */
812 u16 advertising; /* NWay media advertisement */
813 unsigned char phys[2]; /* MII device addresses. */
814 u16 deferred; /* Resend these interrupts when we
815 * bale from the ISR */
816 u16 io_size; /* Size of PCI region (for release_region) */
817 spinlock_t lock; /* Serialise access to device & its vortex_private */
818 struct mii_if_info mii; /* MII lib hooks/info */
822 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
824 #define DEVICE_PCI(dev) NULL
827 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
830 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
832 #define DEVICE_EISA(dev) NULL
835 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
837 /* The action to take with a media selection timer tick.
838 Note that we deviate from the 3Com order by checking 10base2 before AUI.
841 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
842 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
845 static const struct media_table {
847 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
848 mask:8, /* The transceiver-present bit in Wn3_Config.*/
849 next:8; /* The media type to try next. */
850 int wait; /* Time before we check media status. */
852 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
853 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
854 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
855 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
856 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
857 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
858 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
859 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
860 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
861 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
862 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
866 const char str[ETH_GSTRING_LEN];
867 } ethtool_stats_keys[] = {
869 { "tx_max_collisions" },
870 { "tx_multiple_collisions" },
871 { "tx_single_collisions" },
875 /* number of ETHTOOL_GSTATS u64's */
876 #define VORTEX_NUM_STATS 5
878 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
879 int chip_idx, int card_idx);
880 static void vortex_up(struct net_device *dev);
881 static void vortex_down(struct net_device *dev, int final);
882 static int vortex_open(struct net_device *dev);
883 static void mdio_sync(void __iomem *ioaddr, int bits);
884 static int mdio_read(struct net_device *dev, int phy_id, int location);
885 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
886 static void vortex_timer(unsigned long arg);
887 static void rx_oom_timer(unsigned long arg);
888 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
889 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
890 static int vortex_rx(struct net_device *dev);
891 static int boomerang_rx(struct net_device *dev);
892 static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
893 static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
894 static int vortex_close(struct net_device *dev);
895 static void dump_tx_ring(struct net_device *dev);
896 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
897 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
898 static void set_rx_mode(struct net_device *dev);
900 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
902 static void vortex_tx_timeout(struct net_device *dev);
903 static void acpi_set_WOL(struct net_device *dev);
904 static struct ethtool_ops vortex_ethtool_ops;
905 static void set_8021q_mode(struct net_device *dev, int enable);
908 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
909 /* Option count limit only -- unlimited interfaces are supported. */
911 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
912 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
913 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
914 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
915 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
916 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
917 static int global_options = -1;
918 static int global_full_duplex = -1;
919 static int global_enable_wol = -1;
920 static int global_use_mmio = -1;
922 /* #define dev_alloc_skb dev_alloc_skb_debug */
924 /* Variables to work-around the Compaq PCI BIOS32 problem. */
925 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
926 static struct net_device *compaq_net_device;
928 static int vortex_cards_found;
930 module_param(debug, int, 0);
931 module_param(global_options, int, 0);
932 module_param_array(options, int, NULL, 0);
933 module_param(global_full_duplex, int, 0);
934 module_param_array(full_duplex, int, NULL, 0);
935 module_param_array(hw_checksums, int, NULL, 0);
936 module_param_array(flow_ctrl, int, NULL, 0);
937 module_param(global_enable_wol, int, 0);
938 module_param_array(enable_wol, int, NULL, 0);
939 module_param(rx_copybreak, int, 0);
940 module_param(max_interrupt_work, int, 0);
941 module_param(compaq_ioaddr, int, 0);
942 module_param(compaq_irq, int, 0);
943 module_param(compaq_device_id, int, 0);
944 module_param(watchdog, int, 0);
945 module_param(global_use_mmio, int, 0);
946 module_param_array(use_mmio, int, NULL, 0);
947 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
948 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
949 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
950 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
951 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
952 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
953 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
954 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
955 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
956 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
957 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
958 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
959 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
960 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
961 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
962 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
963 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
965 #ifdef CONFIG_NET_POLL_CONTROLLER
966 static void poll_vortex(struct net_device *dev)
968 struct vortex_private *vp = netdev_priv(dev);
970 local_save_flags(flags);
972 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
973 local_irq_restore(flags);
979 static int vortex_suspend (struct pci_dev *pdev, pm_message_t state)
981 struct net_device *dev = pci_get_drvdata(pdev);
983 if (dev && dev->priv) {
984 if (netif_running(dev)) {
985 netif_device_detach(dev);
988 pci_save_state(pdev);
989 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
990 free_irq(dev->irq, dev);
991 pci_disable_device(pdev);
992 pci_set_power_state(pdev, pci_choose_state(pdev, state));
997 static int vortex_resume (struct pci_dev *pdev)
999 struct net_device *dev = pci_get_drvdata(pdev);
1000 struct vortex_private *vp = netdev_priv(dev);
1003 pci_set_power_state(pdev, PCI_D0);
1004 pci_restore_state(pdev);
1005 pci_enable_device(pdev);
1006 pci_set_master(pdev);
1007 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1008 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev)) {
1009 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1010 pci_disable_device(pdev);
1013 if (netif_running(dev)) {
1015 netif_device_attach(dev);
1021 #endif /* CONFIG_PM */
1024 static struct eisa_device_id vortex_eisa_ids[] = {
1025 { "TCM5920", CH_3C592 },
1026 { "TCM5970", CH_3C597 },
1030 static int vortex_eisa_probe (struct device *device);
1031 static int vortex_eisa_remove (struct device *device);
1033 static struct eisa_driver vortex_eisa_driver = {
1034 .id_table = vortex_eisa_ids,
1037 .probe = vortex_eisa_probe,
1038 .remove = vortex_eisa_remove
1042 static int vortex_eisa_probe (struct device *device)
1044 void __iomem *ioaddr;
1045 struct eisa_device *edev;
1047 edev = to_eisa_device (device);
1049 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1052 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
1054 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1055 edev->id.driver_data, vortex_cards_found)) {
1056 release_region (edev->base_addr, VORTEX_TOTAL_SIZE);
1060 vortex_cards_found++;
1065 static int vortex_eisa_remove (struct device *device)
1067 struct eisa_device *edev;
1068 struct net_device *dev;
1069 struct vortex_private *vp;
1070 void __iomem *ioaddr;
1072 edev = to_eisa_device (device);
1073 dev = eisa_get_drvdata (edev);
1076 printk("vortex_eisa_remove called for Compaq device!\n");
1080 vp = netdev_priv(dev);
1081 ioaddr = vp->ioaddr;
1083 unregister_netdev (dev);
1084 iowrite16 (TotalReset|0x14, ioaddr + EL3_CMD);
1085 release_region (dev->base_addr, VORTEX_TOTAL_SIZE);
1092 /* returns count found (>= 0), or negative on error */
1093 static int __init vortex_eisa_init (void)
1096 int orig_cards_found = vortex_cards_found;
1101 err = eisa_driver_register (&vortex_eisa_driver);
1104 * Because of the way EISA bus is probed, we cannot assume
1105 * any device have been found when we exit from
1106 * eisa_driver_register (the bus root driver may not be
1107 * initialized yet). So we blindly assume something was
1108 * found, and let the sysfs magic happend...
1114 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1115 if (compaq_ioaddr) {
1116 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
1117 compaq_irq, compaq_device_id, vortex_cards_found++);
1120 return vortex_cards_found - orig_cards_found + eisa_found;
1123 /* returns count (>= 0), or negative on error */
1124 static int __devinit vortex_init_one (struct pci_dev *pdev,
1125 const struct pci_device_id *ent)
1127 int rc, unit, pci_bar;
1128 struct vortex_chip_info *vci;
1129 void __iomem *ioaddr;
1131 /* wake up and enable device */
1132 rc = pci_enable_device (pdev);
1136 unit = vortex_cards_found;
1138 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1139 /* Determine the default if the user didn't override us */
1140 vci = &vortex_info_tbl[ent->driver_data];
1141 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1142 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1143 pci_bar = use_mmio[unit] ? 1 : 0;
1145 pci_bar = global_use_mmio ? 1 : 0;
1147 ioaddr = pci_iomap(pdev, pci_bar, 0);
1148 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1149 ioaddr = pci_iomap(pdev, 0, 0);
1151 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1152 ent->driver_data, unit);
1154 pci_disable_device (pdev);
1158 vortex_cards_found++;
1165 * Start up the PCI/EISA device which is described by *gendev.
1166 * Return 0 on success.
1168 * NOTE: pdev can be NULL, for the case of a Compaq device
1170 static int __devinit vortex_probe1(struct device *gendev,
1171 void __iomem *ioaddr, int irq,
1172 int chip_idx, int card_idx)
1174 struct vortex_private *vp;
1176 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1178 struct net_device *dev;
1179 static int printed_version;
1180 int retval, print_info;
1181 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1182 char *print_name = "3c59x";
1183 struct pci_dev *pdev = NULL;
1184 struct eisa_device *edev = NULL;
1186 if (!printed_version) {
1188 printed_version = 1;
1192 if ((pdev = DEVICE_PCI(gendev))) {
1193 print_name = pci_name(pdev);
1196 if ((edev = DEVICE_EISA(gendev))) {
1197 print_name = edev->dev.bus_id;
1201 dev = alloc_etherdev(sizeof(*vp));
1204 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1207 SET_MODULE_OWNER(dev);
1208 SET_NETDEV_DEV(dev, gendev);
1209 vp = netdev_priv(dev);
1211 option = global_options;
1213 /* The lower four bits are the media type. */
1214 if (dev->mem_start) {
1216 * The 'options' param is passed in as the third arg to the
1217 * LILO 'ether=' argument for non-modular use
1219 option = dev->mem_start;
1221 else if (card_idx < MAX_UNITS) {
1222 if (options[card_idx] >= 0)
1223 option = options[card_idx];
1227 if (option & 0x8000)
1229 if (option & 0x4000)
1231 if (option & 0x0400)
1235 print_info = (vortex_debug > 1);
1237 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1239 printk(KERN_INFO "%s: 3Com %s %s at %p. Vers " DRV_VERSION "\n",
1241 pdev ? "PCI" : "EISA",
1245 dev->base_addr = (unsigned long)ioaddr;
1248 vp->ioaddr = ioaddr;
1249 vp->large_frames = mtu > 1500;
1250 vp->drv_flags = vci->drv_flags;
1251 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1252 vp->io_size = vci->io_size;
1253 vp->card_idx = card_idx;
1255 /* module list only for Compaq device */
1256 if (gendev == NULL) {
1257 compaq_net_device = dev;
1260 /* PCI-only startup logic */
1262 /* EISA resources already marked, so only PCI needs to do this here */
1263 /* Ignore return value, because Cardbus drivers already allocate for us */
1264 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1265 vp->must_free_region = 1;
1267 /* enable bus-mastering if necessary */
1268 if (vci->flags & PCI_USES_MASTER)
1269 pci_set_master (pdev);
1271 if (vci->drv_flags & IS_VORTEX) {
1273 u8 new_latency = 248;
1275 /* Check the PCI latency value. On the 3c590 series the latency timer
1276 must be set to the maximum value to avoid data corruption that occurs
1277 when the timer expires during a transfer. This bug exists the Vortex
1279 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1280 if (pci_latency < new_latency) {
1281 printk(KERN_INFO "%s: Overriding PCI latency"
1282 " timer (CFLT) setting of %d, new value is %d.\n",
1283 print_name, pci_latency, new_latency);
1284 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1289 spin_lock_init(&vp->lock);
1290 vp->gendev = gendev;
1292 vp->mii.mdio_read = mdio_read;
1293 vp->mii.mdio_write = mdio_write;
1294 vp->mii.phy_id_mask = 0x1f;
1295 vp->mii.reg_num_mask = 0x1f;
1297 /* Makes sure rings are at least 16 byte aligned. */
1298 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1299 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1302 if (vp->rx_ring == 0)
1305 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1306 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1308 /* if we are a PCI driver, we store info in pdev->driver_data
1309 * instead of a module list */
1311 pci_set_drvdata(pdev, dev);
1313 eisa_set_drvdata (edev, dev);
1315 vp->media_override = 7;
1317 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1318 if (vp->media_override != 7)
1320 vp->full_duplex = (option & 0x200) ? 1 : 0;
1321 vp->bus_master = (option & 16) ? 1 : 0;
1324 if (global_full_duplex > 0)
1325 vp->full_duplex = 1;
1326 if (global_enable_wol > 0)
1329 if (card_idx < MAX_UNITS) {
1330 if (full_duplex[card_idx] > 0)
1331 vp->full_duplex = 1;
1332 if (flow_ctrl[card_idx] > 0)
1334 if (enable_wol[card_idx] > 0)
1338 vp->mii.force_media = vp->full_duplex;
1339 vp->options = option;
1340 /* Read the station address from the EEPROM. */
1345 if (vci->drv_flags & EEPROM_8BIT)
1347 else if (vci->drv_flags & EEPROM_OFFSET)
1348 base = EEPROM_Read + 0x30;
1352 for (i = 0; i < 0x40; i++) {
1354 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1355 /* Pause for at least 162 us. for the read to take place. */
1356 for (timer = 10; timer >= 0; timer--) {
1358 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1361 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1364 for (i = 0; i < 0x18; i++)
1365 checksum ^= eeprom[i];
1366 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1367 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1369 checksum ^= eeprom[i++];
1370 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1372 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1373 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1374 for (i = 0; i < 3; i++)
1375 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1376 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1378 for (i = 0; i < 6; i++)
1379 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1381 /* Unfortunately an all zero eeprom passes the checksum and this
1382 gets found in the wild in failure cases. Crypto is hard 8) */
1383 if (!is_valid_ether_addr(dev->dev_addr)) {
1385 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1386 goto free_ring; /* With every pack */
1389 for (i = 0; i < 6; i++)
1390 iowrite8(dev->dev_addr[i], ioaddr + i);
1394 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1397 printk(", IRQ %d\n", dev->irq);
1398 /* Tell them about an invalid IRQ. */
1399 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1400 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1405 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1407 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1408 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1409 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1413 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1416 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1417 if (!vp->cb_fn_base) {
1423 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
1424 print_name, pci_resource_start(pdev, 2),
1429 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1430 if (vp->drv_flags & INVERT_LED_PWR)
1432 if (vp->drv_flags & INVERT_MII_PWR)
1434 iowrite16(n, ioaddr + Wn2_ResetOptions);
1435 if (vp->drv_flags & WNO_XCVR_PWR) {
1437 iowrite16(0x0800, ioaddr);
1441 /* Extract our information from the EEPROM data. */
1442 vp->info1 = eeprom[13];
1443 vp->info2 = eeprom[15];
1444 vp->capabilities = eeprom[16];
1446 if (vp->info1 & 0x8000) {
1447 vp->full_duplex = 1;
1449 printk(KERN_INFO "Full duplex capable\n");
1453 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1454 unsigned int config;
1456 vp->available_media = ioread16(ioaddr + Wn3_Options);
1457 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1458 vp->available_media = 0x40;
1459 config = ioread32(ioaddr + Wn3_Config);
1461 printk(KERN_DEBUG " Internal config register is %4.4x, "
1462 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1463 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1464 8 << RAM_SIZE(config),
1465 RAM_WIDTH(config) ? "word" : "byte",
1466 ram_split[RAM_SPLIT(config)],
1467 AUTOSELECT(config) ? "autoselect/" : "",
1468 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1469 media_tbl[XCVR(config)].name);
1471 vp->default_media = XCVR(config);
1472 if (vp->default_media == XCVR_NWAY)
1474 vp->autoselect = AUTOSELECT(config);
1477 if (vp->media_override != 7) {
1478 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1479 print_name, vp->media_override,
1480 media_tbl[vp->media_override].name);
1481 dev->if_port = vp->media_override;
1483 dev->if_port = vp->default_media;
1485 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1486 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1487 int phy, phy_idx = 0;
1489 mii_preamble_required++;
1490 if (vp->drv_flags & EXTRA_PREAMBLE)
1491 mii_preamble_required++;
1492 mdio_sync(ioaddr, 32);
1493 mdio_read(dev, 24, MII_BMSR);
1494 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1495 int mii_status, phyx;
1498 * For the 3c905CX we look at index 24 first, because it bogusly
1499 * reports an external PHY at all indices
1507 mii_status = mdio_read(dev, phyx, MII_BMSR);
1508 if (mii_status && mii_status != 0xffff) {
1509 vp->phys[phy_idx++] = phyx;
1511 printk(KERN_INFO " MII transceiver found at address %d,"
1512 " status %4x.\n", phyx, mii_status);
1514 if ((mii_status & 0x0040) == 0)
1515 mii_preamble_required++;
1518 mii_preamble_required--;
1520 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1523 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1524 if (vp->full_duplex) {
1525 /* Only advertise the FD media types. */
1526 vp->advertising &= ~0x02A0;
1527 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1530 vp->mii.phy_id = vp->phys[0];
1533 if (vp->capabilities & CapBusMaster) {
1534 vp->full_bus_master_tx = 1;
1536 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1537 (vp->info2 & 1) ? "early" : "whole-frame" );
1539 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1540 vp->bus_master = 0; /* AKPM: vortex only */
1543 /* The 3c59x-specific entries in the device structure. */
1544 dev->open = vortex_open;
1545 if (vp->full_bus_master_tx) {
1546 dev->hard_start_xmit = boomerang_start_xmit;
1547 /* Actually, it still should work with iommu. */
1548 if (card_idx < MAX_UNITS &&
1549 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1550 hw_checksums[card_idx] == 1)) {
1551 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1554 dev->hard_start_xmit = vortex_start_xmit;
1558 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1560 (dev->features & NETIF_F_SG) ? "en":"dis",
1561 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1564 dev->stop = vortex_close;
1565 dev->get_stats = vortex_get_stats;
1567 dev->do_ioctl = vortex_ioctl;
1569 dev->ethtool_ops = &vortex_ethtool_ops;
1570 dev->set_multicast_list = set_rx_mode;
1571 dev->tx_timeout = vortex_tx_timeout;
1572 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1573 #ifdef CONFIG_NET_POLL_CONTROLLER
1574 dev->poll_controller = poll_vortex;
1577 vp->pm_state_valid = 1;
1578 pci_save_state(VORTEX_PCI(vp));
1581 retval = register_netdev(dev);
1586 pci_free_consistent(pdev,
1587 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1588 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1592 if (vp->must_free_region)
1593 release_region(dev->base_addr, vci->io_size);
1595 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1601 issue_and_wait(struct net_device *dev, int cmd)
1603 struct vortex_private *vp = netdev_priv(dev);
1604 void __iomem *ioaddr = vp->ioaddr;
1607 iowrite16(cmd, ioaddr + EL3_CMD);
1608 for (i = 0; i < 2000; i++) {
1609 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1613 /* OK, that didn't work. Do it the slow way. One second */
1614 for (i = 0; i < 100000; i++) {
1615 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1616 if (vortex_debug > 1)
1617 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1618 dev->name, cmd, i * 10);
1623 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1624 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1628 vortex_set_duplex(struct net_device *dev)
1630 struct vortex_private *vp = netdev_priv(dev);
1631 void __iomem *ioaddr = vp->ioaddr;
1633 printk(KERN_INFO "%s: setting %s-duplex.\n",
1634 dev->name, (vp->full_duplex) ? "full" : "half");
1637 /* Set the full-duplex bit. */
1638 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1639 (vp->large_frames ? 0x40 : 0) |
1640 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1642 ioaddr + Wn3_MAC_Ctrl);
1644 issue_and_wait(dev, TxReset);
1646 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1648 issue_and_wait(dev, RxReset|0x04);
1651 static void vortex_check_media(struct net_device *dev, unsigned int init)
1653 struct vortex_private *vp = netdev_priv(dev);
1654 unsigned int ok_to_print = 0;
1656 if (vortex_debug > 3)
1659 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1660 vp->full_duplex = vp->mii.full_duplex;
1661 vortex_set_duplex(dev);
1663 vortex_set_duplex(dev);
1668 vortex_up(struct net_device *dev)
1670 struct vortex_private *vp = netdev_priv(dev);
1671 void __iomem *ioaddr = vp->ioaddr;
1672 unsigned int config;
1675 if (VORTEX_PCI(vp)) {
1676 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1677 if (vp->pm_state_valid)
1678 pci_restore_state(VORTEX_PCI(vp));
1679 pci_enable_device(VORTEX_PCI(vp));
1682 /* Before initializing select the active media port. */
1684 config = ioread32(ioaddr + Wn3_Config);
1686 if (vp->media_override != 7) {
1687 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1688 dev->name, vp->media_override,
1689 media_tbl[vp->media_override].name);
1690 dev->if_port = vp->media_override;
1691 } else if (vp->autoselect) {
1693 if (vortex_debug > 1)
1694 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1695 dev->name, dev->if_port);
1696 dev->if_port = XCVR_NWAY;
1698 /* Find first available media type, starting with 100baseTx. */
1699 dev->if_port = XCVR_100baseTx;
1700 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1701 dev->if_port = media_tbl[dev->if_port].next;
1702 if (vortex_debug > 1)
1703 printk(KERN_INFO "%s: first available media type: %s\n",
1704 dev->name, media_tbl[dev->if_port].name);
1707 dev->if_port = vp->default_media;
1708 if (vortex_debug > 1)
1709 printk(KERN_INFO "%s: using default media %s\n",
1710 dev->name, media_tbl[dev->if_port].name);
1713 init_timer(&vp->timer);
1714 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1715 vp->timer.data = (unsigned long)dev;
1716 vp->timer.function = vortex_timer; /* timer handler */
1717 add_timer(&vp->timer);
1719 init_timer(&vp->rx_oom_timer);
1720 vp->rx_oom_timer.data = (unsigned long)dev;
1721 vp->rx_oom_timer.function = rx_oom_timer;
1723 if (vortex_debug > 1)
1724 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1725 dev->name, media_tbl[dev->if_port].name);
1727 vp->full_duplex = vp->mii.force_media;
1728 config = BFINS(config, dev->if_port, 20, 4);
1729 if (vortex_debug > 6)
1730 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1731 iowrite32(config, ioaddr + Wn3_Config);
1733 netif_carrier_off(dev);
1734 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1736 vortex_check_media(dev, 1);
1739 vortex_set_duplex(dev);
1742 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1744 if (vortex_debug > 1) {
1746 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1747 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1750 /* Set the station address and mask in window 2 each time opened. */
1752 for (i = 0; i < 6; i++)
1753 iowrite8(dev->dev_addr[i], ioaddr + i);
1754 for (; i < 12; i+=2)
1755 iowrite16(0, ioaddr + i);
1757 if (vp->cb_fn_base) {
1758 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1759 if (vp->drv_flags & INVERT_LED_PWR)
1761 if (vp->drv_flags & INVERT_MII_PWR)
1763 iowrite16(n, ioaddr + Wn2_ResetOptions);
1766 if (dev->if_port == XCVR_10base2)
1767 /* Start the thinnet transceiver. We should really wait 50ms...*/
1768 iowrite16(StartCoax, ioaddr + EL3_CMD);
1769 if (dev->if_port != XCVR_NWAY) {
1771 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1772 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1775 /* Switch to the stats window, and clear all stats by reading. */
1776 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1778 for (i = 0; i < 10; i++)
1779 ioread8(ioaddr + i);
1780 ioread16(ioaddr + 10);
1781 ioread16(ioaddr + 12);
1782 /* New: On the Vortex we must also clear the BadSSD counter. */
1784 ioread8(ioaddr + 12);
1785 /* ..and on the Boomerang we enable the extra statistics bits. */
1786 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1788 /* Switch to register set 7 for normal use. */
1791 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1792 vp->cur_rx = vp->dirty_rx = 0;
1793 /* Initialize the RxEarly register as recommended. */
1794 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1795 iowrite32(0x0020, ioaddr + PktStatus);
1796 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1798 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1799 vp->cur_tx = vp->dirty_tx = 0;
1800 if (vp->drv_flags & IS_BOOMERANG)
1801 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1802 /* Clear the Rx, Tx rings. */
1803 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1804 vp->rx_ring[i].status = 0;
1805 for (i = 0; i < TX_RING_SIZE; i++)
1806 vp->tx_skbuff[i] = NULL;
1807 iowrite32(0, ioaddr + DownListPtr);
1809 /* Set receiver mode: presumably accept b-case and phys addr only. */
1811 /* enable 802.1q tagged frames */
1812 set_8021q_mode(dev, 1);
1813 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1815 // issue_and_wait(dev, SetTxStart|0x07ff);
1816 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1817 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1818 /* Allow status bits to be seen. */
1819 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1820 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1821 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1822 (vp->bus_master ? DMADone : 0);
1823 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1824 (vp->full_bus_master_rx ? 0 : RxComplete) |
1825 StatsFull | HostError | TxComplete | IntReq
1826 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1827 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1828 /* Ack all pending events, and set active indicator mask. */
1829 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1831 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1832 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1833 iowrite32(0x8000, vp->cb_fn_base + 4);
1834 netif_start_queue (dev);
1838 vortex_open(struct net_device *dev)
1840 struct vortex_private *vp = netdev_priv(dev);
1844 /* Use the now-standard shared IRQ implementation. */
1845 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1846 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1847 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1851 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1852 if (vortex_debug > 2)
1853 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1854 for (i = 0; i < RX_RING_SIZE; i++) {
1855 struct sk_buff *skb;
1856 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1857 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1858 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1859 skb = dev_alloc_skb(PKT_BUF_SZ);
1860 vp->rx_skbuff[i] = skb;
1862 break; /* Bad news! */
1863 skb->dev = dev; /* Mark as being used by this device. */
1864 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1865 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1867 if (i != RX_RING_SIZE) {
1869 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1870 for (j = 0; j < i; j++) {
1871 if (vp->rx_skbuff[j]) {
1872 dev_kfree_skb(vp->rx_skbuff[j]);
1873 vp->rx_skbuff[j] = NULL;
1879 /* Wrap the ring. */
1880 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1887 free_irq(dev->irq, dev);
1889 if (vortex_debug > 1)
1890 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1895 vortex_timer(unsigned long data)
1897 struct net_device *dev = (struct net_device *)data;
1898 struct vortex_private *vp = netdev_priv(dev);
1899 void __iomem *ioaddr = vp->ioaddr;
1900 int next_tick = 60*HZ;
1902 int media_status, old_window;
1904 if (vortex_debug > 2) {
1905 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1906 dev->name, media_tbl[dev->if_port].name);
1907 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1911 goto leave_media_alone;
1912 disable_irq(dev->irq);
1913 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1915 media_status = ioread16(ioaddr + Wn4_Media);
1916 switch (dev->if_port) {
1917 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1918 if (media_status & Media_LnkBeat) {
1919 netif_carrier_on(dev);
1921 if (vortex_debug > 1)
1922 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1923 dev->name, media_tbl[dev->if_port].name, media_status);
1925 netif_carrier_off(dev);
1926 if (vortex_debug > 1) {
1927 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1928 dev->name, media_tbl[dev->if_port].name, media_status);
1932 case XCVR_MII: case XCVR_NWAY:
1935 spin_lock_bh(&vp->lock);
1936 vortex_check_media(dev, 0);
1937 spin_unlock_bh(&vp->lock);
1940 default: /* Other media types handled by Tx timeouts. */
1941 if (vortex_debug > 1)
1942 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1943 dev->name, media_tbl[dev->if_port].name, media_status);
1947 if (!netif_carrier_ok(dev))
1951 unsigned int config;
1954 dev->if_port = media_tbl[dev->if_port].next;
1955 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1956 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1957 dev->if_port = vp->default_media;
1958 if (vortex_debug > 1)
1959 printk(KERN_DEBUG "%s: Media selection failing, using default "
1961 dev->name, media_tbl[dev->if_port].name);
1963 if (vortex_debug > 1)
1964 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1966 dev->name, media_tbl[dev->if_port].name);
1967 next_tick = media_tbl[dev->if_port].wait;
1969 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1970 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1973 config = ioread32(ioaddr + Wn3_Config);
1974 config = BFINS(config, dev->if_port, 20, 4);
1975 iowrite32(config, ioaddr + Wn3_Config);
1977 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1979 if (vortex_debug > 1)
1980 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1981 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1983 EL3WINDOW(old_window);
1984 enable_irq(dev->irq);
1987 if (vortex_debug > 2)
1988 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1989 dev->name, media_tbl[dev->if_port].name);
1991 mod_timer(&vp->timer, RUN_AT(next_tick));
1993 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1997 static void vortex_tx_timeout(struct net_device *dev)
1999 struct vortex_private *vp = netdev_priv(dev);
2000 void __iomem *ioaddr = vp->ioaddr;
2002 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
2003 dev->name, ioread8(ioaddr + TxStatus),
2004 ioread16(ioaddr + EL3_STATUS));
2006 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
2007 ioread16(ioaddr + Wn4_NetDiag),
2008 ioread16(ioaddr + Wn4_Media),
2009 ioread32(ioaddr + PktStatus),
2010 ioread16(ioaddr + Wn4_FIFODiag));
2011 /* Slight code bloat to be user friendly. */
2012 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
2013 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
2014 " network cable problem?\n", dev->name);
2015 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
2016 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
2017 " IRQ blocked by another device?\n", dev->name);
2018 /* Bad idea here.. but we might as well handle a few events. */
2021 * Block interrupts because vortex_interrupt does a bare spin_lock()
2023 unsigned long flags;
2024 local_irq_save(flags);
2025 if (vp->full_bus_master_tx)
2026 boomerang_interrupt(dev->irq, dev, NULL);
2028 vortex_interrupt(dev->irq, dev, NULL);
2029 local_irq_restore(flags);
2033 if (vortex_debug > 0)
2036 issue_and_wait(dev, TxReset);
2038 vp->stats.tx_errors++;
2039 if (vp->full_bus_master_tx) {
2040 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
2041 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
2042 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
2043 ioaddr + DownListPtr);
2044 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
2045 netif_wake_queue (dev);
2046 if (vp->drv_flags & IS_BOOMERANG)
2047 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
2048 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2050 vp->stats.tx_dropped++;
2051 netif_wake_queue(dev);
2054 /* Issue Tx Enable */
2055 iowrite16(TxEnable, ioaddr + EL3_CMD);
2056 dev->trans_start = jiffies;
2058 /* Switch to register set 7 for normal use. */
2063 * Handle uncommon interrupt sources. This is a separate routine to minimize
2067 vortex_error(struct net_device *dev, int status)
2069 struct vortex_private *vp = netdev_priv(dev);
2070 void __iomem *ioaddr = vp->ioaddr;
2071 int do_tx_reset = 0, reset_mask = 0;
2072 unsigned char tx_status = 0;
2074 if (vortex_debug > 2) {
2075 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
2078 if (status & TxComplete) { /* Really "TxError" for us. */
2079 tx_status = ioread8(ioaddr + TxStatus);
2080 /* Presumably a tx-timeout. We must merely re-enable. */
2081 if (vortex_debug > 2
2082 || (tx_status != 0x88 && vortex_debug > 0)) {
2083 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2084 dev->name, tx_status);
2085 if (tx_status == 0x82) {
2086 printk(KERN_ERR "Probably a duplex mismatch. See "
2087 "Documentation/networking/vortex.txt\n");
2091 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2092 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2093 iowrite8(0, ioaddr + TxStatus);
2094 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2096 } else if (tx_status & 0x08) { /* maxCollisions */
2097 vp->xstats.tx_max_collisions++;
2098 if (vp->drv_flags & MAX_COLLISION_RESET) {
2100 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2102 } else { /* Merely re-enable the transmitter. */
2103 iowrite16(TxEnable, ioaddr + EL3_CMD);
2107 if (status & RxEarly) { /* Rx early is unused. */
2109 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2111 if (status & StatsFull) { /* Empty statistics. */
2112 static int DoneDidThat;
2113 if (vortex_debug > 4)
2114 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2115 update_stats(ioaddr, dev);
2116 /* HACK: Disable statistics as an interrupt source. */
2117 /* This occurs when we have the wrong media type! */
2118 if (DoneDidThat == 0 &&
2119 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2120 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2121 "stats as an interrupt source.\n", dev->name);
2123 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
2124 vp->intr_enable &= ~StatsFull;
2129 if (status & IntReq) { /* Restore all interrupt sources. */
2130 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2131 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2133 if (status & HostError) {
2136 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
2137 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2138 dev->name, fifo_diag);
2139 /* Adapter failure requires Tx/Rx reset and reinit. */
2140 if (vp->full_bus_master_tx) {
2141 int bus_status = ioread32(ioaddr + PktStatus);
2142 /* 0x80000000 PCI master abort. */
2143 /* 0x40000000 PCI target abort. */
2145 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2147 /* In this case, blow the card away */
2148 /* Must not enter D3 or we can't legally issue the reset! */
2149 vortex_down(dev, 0);
2150 issue_and_wait(dev, TotalReset | 0xff);
2151 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2152 } else if (fifo_diag & 0x0400)
2154 if (fifo_diag & 0x3000) {
2155 /* Reset Rx fifo and upload logic */
2156 issue_and_wait(dev, RxReset|0x07);
2157 /* Set the Rx filter to the current state. */
2159 /* enable 802.1q VLAN tagged frames */
2160 set_8021q_mode(dev, 1);
2161 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2162 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2167 issue_and_wait(dev, TxReset|reset_mask);
2168 iowrite16(TxEnable, ioaddr + EL3_CMD);
2169 if (!vp->full_bus_master_tx)
2170 netif_wake_queue(dev);
2175 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2177 struct vortex_private *vp = netdev_priv(dev);
2178 void __iomem *ioaddr = vp->ioaddr;
2180 /* Put out the doubleword header... */
2181 iowrite32(skb->len, ioaddr + TX_FIFO);
2182 if (vp->bus_master) {
2183 /* Set the bus-master controller to transfer the packet. */
2184 int len = (skb->len + 3) & ~3;
2185 iowrite32( vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2186 ioaddr + Wn7_MasterAddr);
2187 iowrite16(len, ioaddr + Wn7_MasterLen);
2189 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2190 /* netif_wake_queue() will be called at the DMADone interrupt. */
2192 /* ... and the packet rounded to a doubleword. */
2193 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2194 dev_kfree_skb (skb);
2195 if (ioread16(ioaddr + TxFree) > 1536) {
2196 netif_start_queue (dev); /* AKPM: redundant? */
2198 /* Interrupt us when the FIFO has room for max-sized packet. */
2199 netif_stop_queue(dev);
2200 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2204 dev->trans_start = jiffies;
2206 /* Clear the Tx status stack. */
2211 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2212 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2213 if (vortex_debug > 2)
2214 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2215 dev->name, tx_status);
2216 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2217 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2218 if (tx_status & 0x30) {
2219 issue_and_wait(dev, TxReset);
2221 iowrite16(TxEnable, ioaddr + EL3_CMD);
2223 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2230 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2232 struct vortex_private *vp = netdev_priv(dev);
2233 void __iomem *ioaddr = vp->ioaddr;
2234 /* Calculate the next Tx descriptor entry. */
2235 int entry = vp->cur_tx % TX_RING_SIZE;
2236 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2237 unsigned long flags;
2239 if (vortex_debug > 6) {
2240 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2241 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2242 dev->name, vp->cur_tx);
2245 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2246 if (vortex_debug > 0)
2247 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2249 netif_stop_queue(dev);
2253 vp->tx_skbuff[entry] = skb;
2255 vp->tx_ring[entry].next = 0;
2257 if (skb->ip_summed != CHECKSUM_HW)
2258 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2260 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2262 if (!skb_shinfo(skb)->nr_frags) {
2263 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2264 skb->len, PCI_DMA_TODEVICE));
2265 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2269 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2270 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2271 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2273 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2274 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2276 vp->tx_ring[entry].frag[i+1].addr =
2277 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2278 (void*)page_address(frag->page) + frag->page_offset,
2279 frag->size, PCI_DMA_TODEVICE));
2281 if (i == skb_shinfo(skb)->nr_frags-1)
2282 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2284 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2288 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2289 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2290 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2293 spin_lock_irqsave(&vp->lock, flags);
2294 /* Wait for the stall to complete. */
2295 issue_and_wait(dev, DownStall);
2296 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2297 if (ioread32(ioaddr + DownListPtr) == 0) {
2298 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2299 vp->queued_packet++;
2303 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2304 netif_stop_queue (dev);
2305 } else { /* Clear previous interrupt enable. */
2306 #if defined(tx_interrupt_mitigation)
2307 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2308 * were selected, this would corrupt DN_COMPLETE. No?
2310 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2313 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2314 spin_unlock_irqrestore(&vp->lock, flags);
2315 dev->trans_start = jiffies;
2319 /* The interrupt handler does all of the Rx thread work and cleans up
2320 after the Tx thread. */
2323 * This is the ISR for the vortex series chips.
2324 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2328 vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2330 struct net_device *dev = dev_id;
2331 struct vortex_private *vp = netdev_priv(dev);
2332 void __iomem *ioaddr;
2334 int work_done = max_interrupt_work;
2337 ioaddr = vp->ioaddr;
2338 spin_lock(&vp->lock);
2340 status = ioread16(ioaddr + EL3_STATUS);
2342 if (vortex_debug > 6)
2343 printk("vortex_interrupt(). status=0x%4x\n", status);
2345 if ((status & IntLatch) == 0)
2346 goto handler_exit; /* No interrupt: shared IRQs cause this */
2349 if (status & IntReq) {
2350 status |= vp->deferred;
2354 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2357 if (vortex_debug > 4)
2358 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2359 dev->name, status, ioread8(ioaddr + Timer));
2362 if (vortex_debug > 5)
2363 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2365 if (status & RxComplete)
2368 if (status & TxAvailable) {
2369 if (vortex_debug > 5)
2370 printk(KERN_DEBUG " TX room bit was handled.\n");
2371 /* There's room in the FIFO for a full-sized packet. */
2372 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2373 netif_wake_queue (dev);
2376 if (status & DMADone) {
2377 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2378 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2379 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2380 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2381 if (ioread16(ioaddr + TxFree) > 1536) {
2383 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2384 * insufficient FIFO room, the TxAvailable test will succeed and call
2385 * netif_wake_queue()
2387 netif_wake_queue(dev);
2388 } else { /* Interrupt when FIFO has room for max-sized packet. */
2389 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2390 netif_stop_queue(dev);
2394 /* Check for all uncommon interrupts at once. */
2395 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2396 if (status == 0xffff)
2398 vortex_error(dev, status);
2401 if (--work_done < 0) {
2402 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2403 "%4.4x.\n", dev->name, status);
2404 /* Disable all pending interrupts. */
2406 vp->deferred |= status;
2407 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2409 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2410 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2411 /* The timer will reenable interrupts. */
2412 mod_timer(&vp->timer, jiffies + 1*HZ);
2415 /* Acknowledge the IRQ. */
2416 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2417 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2419 if (vortex_debug > 4)
2420 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2423 spin_unlock(&vp->lock);
2424 return IRQ_RETVAL(handled);
2428 * This is the ISR for the boomerang series chips.
2429 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2433 boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2435 struct net_device *dev = dev_id;
2436 struct vortex_private *vp = netdev_priv(dev);
2437 void __iomem *ioaddr;
2439 int work_done = max_interrupt_work;
2441 ioaddr = vp->ioaddr;
2444 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2445 * and boomerang_start_xmit
2447 spin_lock(&vp->lock);
2449 status = ioread16(ioaddr + EL3_STATUS);
2451 if (vortex_debug > 6)
2452 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2454 if ((status & IntLatch) == 0)
2455 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2457 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2458 if (vortex_debug > 1)
2459 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2463 if (status & IntReq) {
2464 status |= vp->deferred;
2468 if (vortex_debug > 4)
2469 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2470 dev->name, status, ioread8(ioaddr + Timer));
2472 if (vortex_debug > 5)
2473 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2475 if (status & UpComplete) {
2476 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2477 if (vortex_debug > 5)
2478 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2482 if (status & DownComplete) {
2483 unsigned int dirty_tx = vp->dirty_tx;
2485 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2486 while (vp->cur_tx - dirty_tx > 0) {
2487 int entry = dirty_tx % TX_RING_SIZE;
2488 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2489 if (ioread32(ioaddr + DownListPtr) ==
2490 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2491 break; /* It still hasn't been processed. */
2493 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2494 break; /* It still hasn't been processed. */
2497 if (vp->tx_skbuff[entry]) {
2498 struct sk_buff *skb = vp->tx_skbuff[entry];
2501 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2502 pci_unmap_single(VORTEX_PCI(vp),
2503 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2504 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2507 pci_unmap_single(VORTEX_PCI(vp),
2508 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2510 dev_kfree_skb_irq(skb);
2511 vp->tx_skbuff[entry] = NULL;
2513 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2515 /* vp->stats.tx_packets++; Counted below. */
2518 vp->dirty_tx = dirty_tx;
2519 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2520 if (vortex_debug > 6)
2521 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2522 netif_wake_queue (dev);
2526 /* Check for all uncommon interrupts at once. */
2527 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2528 vortex_error(dev, status);
2530 if (--work_done < 0) {
2531 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2532 "%4.4x.\n", dev->name, status);
2533 /* Disable all pending interrupts. */
2535 vp->deferred |= status;
2536 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2538 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2539 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2540 /* The timer will reenable interrupts. */
2541 mod_timer(&vp->timer, jiffies + 1*HZ);
2544 /* Acknowledge the IRQ. */
2545 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2546 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2547 iowrite32(0x8000, vp->cb_fn_base + 4);
2549 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2551 if (vortex_debug > 4)
2552 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2555 spin_unlock(&vp->lock);
2559 static int vortex_rx(struct net_device *dev)
2561 struct vortex_private *vp = netdev_priv(dev);
2562 void __iomem *ioaddr = vp->ioaddr;
2566 if (vortex_debug > 5)
2567 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2568 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2569 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2570 if (rx_status & 0x4000) { /* Error, update stats. */
2571 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2572 if (vortex_debug > 2)
2573 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2574 vp->stats.rx_errors++;
2575 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2576 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2577 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2578 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2579 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2581 /* The packet length: up to 4.5K!. */
2582 int pkt_len = rx_status & 0x1fff;
2583 struct sk_buff *skb;
2585 skb = dev_alloc_skb(pkt_len + 5);
2586 if (vortex_debug > 4)
2587 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2588 pkt_len, rx_status);
2591 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2592 /* 'skb_put()' points to the start of sk_buff data area. */
2593 if (vp->bus_master &&
2594 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2595 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2596 pkt_len, PCI_DMA_FROMDEVICE);
2597 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2598 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2599 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2600 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2602 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2604 ioread32_rep(ioaddr + RX_FIFO,
2605 skb_put(skb, pkt_len),
2606 (pkt_len + 3) >> 2);
2608 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2609 skb->protocol = eth_type_trans(skb, dev);
2611 dev->last_rx = jiffies;
2612 vp->stats.rx_packets++;
2613 /* Wait a limited time to go to next packet. */
2614 for (i = 200; i >= 0; i--)
2615 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2618 } else if (vortex_debug > 0)
2619 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2620 "size %d.\n", dev->name, pkt_len);
2621 vp->stats.rx_dropped++;
2623 issue_and_wait(dev, RxDiscard);
2630 boomerang_rx(struct net_device *dev)
2632 struct vortex_private *vp = netdev_priv(dev);
2633 int entry = vp->cur_rx % RX_RING_SIZE;
2634 void __iomem *ioaddr = vp->ioaddr;
2636 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2638 if (vortex_debug > 5)
2639 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2641 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2642 if (--rx_work_limit < 0)
2644 if (rx_status & RxDError) { /* Error, update stats. */
2645 unsigned char rx_error = rx_status >> 16;
2646 if (vortex_debug > 2)
2647 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2648 vp->stats.rx_errors++;
2649 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2650 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2651 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2652 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2653 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2655 /* The packet length: up to 4.5K!. */
2656 int pkt_len = rx_status & 0x1fff;
2657 struct sk_buff *skb;
2658 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2660 if (vortex_debug > 4)
2661 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2662 pkt_len, rx_status);
2664 /* Check if the packet is long enough to just accept without
2665 copying to a properly sized skbuff. */
2666 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2668 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2669 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2670 /* 'skb_put()' points to the start of sk_buff data area. */
2671 memcpy(skb_put(skb, pkt_len),
2672 vp->rx_skbuff[entry]->data,
2674 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2677 /* Pass up the skbuff already on the Rx ring. */
2678 skb = vp->rx_skbuff[entry];
2679 vp->rx_skbuff[entry] = NULL;
2680 skb_put(skb, pkt_len);
2681 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2684 skb->protocol = eth_type_trans(skb, dev);
2685 { /* Use hardware checksum info. */
2686 int csum_bits = rx_status & 0xee000000;
2688 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2689 csum_bits == (IPChksumValid | UDPChksumValid))) {
2690 skb->ip_summed = CHECKSUM_UNNECESSARY;
2695 dev->last_rx = jiffies;
2696 vp->stats.rx_packets++;
2698 entry = (++vp->cur_rx) % RX_RING_SIZE;
2700 /* Refill the Rx ring buffers. */
2701 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2702 struct sk_buff *skb;
2703 entry = vp->dirty_rx % RX_RING_SIZE;
2704 if (vp->rx_skbuff[entry] == NULL) {
2705 skb = dev_alloc_skb(PKT_BUF_SZ);
2707 static unsigned long last_jif;
2708 if (time_after(jiffies, last_jif + 10 * HZ)) {
2709 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2712 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2713 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2714 break; /* Bad news! */
2716 skb->dev = dev; /* Mark as being used by this device. */
2717 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2718 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2719 vp->rx_skbuff[entry] = skb;
2721 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2722 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2728 * If we've hit a total OOM refilling the Rx ring we poll once a second
2729 * for some memory. Otherwise there is no way to restart the rx process.
2732 rx_oom_timer(unsigned long arg)
2734 struct net_device *dev = (struct net_device *)arg;
2735 struct vortex_private *vp = netdev_priv(dev);
2737 spin_lock_irq(&vp->lock);
2738 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2740 if (vortex_debug > 1) {
2741 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2742 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2744 spin_unlock_irq(&vp->lock);
2748 vortex_down(struct net_device *dev, int final_down)
2750 struct vortex_private *vp = netdev_priv(dev);
2751 void __iomem *ioaddr = vp->ioaddr;
2753 netif_stop_queue (dev);
2755 del_timer_sync(&vp->rx_oom_timer);
2756 del_timer_sync(&vp->timer);
2758 /* Turn off statistics ASAP. We update vp->stats below. */
2759 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2761 /* Disable the receiver and transmitter. */
2762 iowrite16(RxDisable, ioaddr + EL3_CMD);
2763 iowrite16(TxDisable, ioaddr + EL3_CMD);
2765 /* Disable receiving 802.1q tagged frames */
2766 set_8021q_mode(dev, 0);
2768 if (dev->if_port == XCVR_10base2)
2769 /* Turn off thinnet power. Green! */
2770 iowrite16(StopCoax, ioaddr + EL3_CMD);
2772 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2774 update_stats(ioaddr, dev);
2775 if (vp->full_bus_master_rx)
2776 iowrite32(0, ioaddr + UpListPtr);
2777 if (vp->full_bus_master_tx)
2778 iowrite32(0, ioaddr + DownListPtr);
2780 if (final_down && VORTEX_PCI(vp)) {
2781 vp->pm_state_valid = 1;
2782 pci_save_state(VORTEX_PCI(vp));
2788 vortex_close(struct net_device *dev)
2790 struct vortex_private *vp = netdev_priv(dev);
2791 void __iomem *ioaddr = vp->ioaddr;
2794 if (netif_device_present(dev))
2795 vortex_down(dev, 1);
2797 if (vortex_debug > 1) {
2798 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2799 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2800 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2801 " tx_queued %d Rx pre-checksummed %d.\n",
2802 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2806 if (vp->rx_csumhits &&
2807 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2808 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2809 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2810 "not using them!\n", dev->name);
2814 free_irq(dev->irq, dev);
2816 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2817 for (i = 0; i < RX_RING_SIZE; i++)
2818 if (vp->rx_skbuff[i]) {
2819 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2820 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2821 dev_kfree_skb(vp->rx_skbuff[i]);
2822 vp->rx_skbuff[i] = NULL;
2825 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2826 for (i = 0; i < TX_RING_SIZE; i++) {
2827 if (vp->tx_skbuff[i]) {
2828 struct sk_buff *skb = vp->tx_skbuff[i];
2832 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2833 pci_unmap_single(VORTEX_PCI(vp),
2834 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2835 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2838 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2841 vp->tx_skbuff[i] = NULL;
2850 dump_tx_ring(struct net_device *dev)
2852 if (vortex_debug > 0) {
2853 struct vortex_private *vp = netdev_priv(dev);
2854 void __iomem *ioaddr = vp->ioaddr;
2856 if (vp->full_bus_master_tx) {
2858 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2860 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2861 vp->full_bus_master_tx,
2862 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2863 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2864 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2865 ioread32(ioaddr + DownListPtr),
2866 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2867 issue_and_wait(dev, DownStall);
2868 for (i = 0; i < TX_RING_SIZE; i++) {
2869 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2872 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2874 le32_to_cpu(vp->tx_ring[i].length),
2876 le32_to_cpu(vp->tx_ring[i].status));
2879 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2884 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2886 struct vortex_private *vp = netdev_priv(dev);
2887 void __iomem *ioaddr = vp->ioaddr;
2888 unsigned long flags;
2890 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2891 spin_lock_irqsave (&vp->lock, flags);
2892 update_stats(ioaddr, dev);
2893 spin_unlock_irqrestore (&vp->lock, flags);
2898 /* Update statistics.
2899 Unlike with the EL3 we need not worry about interrupts changing
2900 the window setting from underneath us, but we must still guard
2901 against a race condition with a StatsUpdate interrupt updating the
2902 table. This is done by checking that the ASM (!) code generated uses
2903 atomic updates with '+='.
2905 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2907 struct vortex_private *vp = netdev_priv(dev);
2908 int old_window = ioread16(ioaddr + EL3_CMD);
2910 if (old_window == 0xffff) /* Chip suspended or ejected. */
2912 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2913 /* Switch to the stats window, and read everything. */
2915 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2916 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2917 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2918 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2919 vp->stats.tx_packets += ioread8(ioaddr + 6);
2920 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2921 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
2922 /* Don't bother with register 9, an extension of registers 6&7.
2923 If we do use the 6&7 values the atomic update assumption above
2925 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2926 vp->stats.tx_bytes += ioread16(ioaddr + 12);
2927 /* Extra stats for get_ethtool_stats() */
2928 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2929 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
2930 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
2932 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2934 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2935 + vp->xstats.tx_single_collisions
2936 + vp->xstats.tx_max_collisions;
2939 u8 up = ioread8(ioaddr + 13);
2940 vp->stats.rx_bytes += (up & 0x0f) << 16;
2941 vp->stats.tx_bytes += (up & 0xf0) << 12;
2944 EL3WINDOW(old_window >> 13);
2948 static int vortex_nway_reset(struct net_device *dev)
2950 struct vortex_private *vp = netdev_priv(dev);
2951 void __iomem *ioaddr = vp->ioaddr;
2952 unsigned long flags;
2955 spin_lock_irqsave(&vp->lock, flags);
2957 rc = mii_nway_restart(&vp->mii);
2958 spin_unlock_irqrestore(&vp->lock, flags);
2962 static u32 vortex_get_link(struct net_device *dev)
2964 struct vortex_private *vp = netdev_priv(dev);
2965 void __iomem *ioaddr = vp->ioaddr;
2966 unsigned long flags;
2969 spin_lock_irqsave(&vp->lock, flags);
2971 rc = mii_link_ok(&vp->mii);
2972 spin_unlock_irqrestore(&vp->lock, flags);
2976 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2978 struct vortex_private *vp = netdev_priv(dev);
2979 void __iomem *ioaddr = vp->ioaddr;
2980 unsigned long flags;
2983 spin_lock_irqsave(&vp->lock, flags);
2985 rc = mii_ethtool_gset(&vp->mii, cmd);
2986 spin_unlock_irqrestore(&vp->lock, flags);
2990 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2992 struct vortex_private *vp = netdev_priv(dev);
2993 void __iomem *ioaddr = vp->ioaddr;
2994 unsigned long flags;
2997 spin_lock_irqsave(&vp->lock, flags);
2999 rc = mii_ethtool_sset(&vp->mii, cmd);
3000 spin_unlock_irqrestore(&vp->lock, flags);
3004 static u32 vortex_get_msglevel(struct net_device *dev)
3006 return vortex_debug;
3009 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
3014 static int vortex_get_stats_count(struct net_device *dev)
3016 return VORTEX_NUM_STATS;
3019 static void vortex_get_ethtool_stats(struct net_device *dev,
3020 struct ethtool_stats *stats, u64 *data)
3022 struct vortex_private *vp = netdev_priv(dev);
3023 void __iomem *ioaddr = vp->ioaddr;
3024 unsigned long flags;
3026 spin_lock_irqsave(&vp->lock, flags);
3027 update_stats(ioaddr, dev);
3028 spin_unlock_irqrestore(&vp->lock, flags);
3030 data[0] = vp->xstats.tx_deferred;
3031 data[1] = vp->xstats.tx_max_collisions;
3032 data[2] = vp->xstats.tx_multiple_collisions;
3033 data[3] = vp->xstats.tx_single_collisions;
3034 data[4] = vp->xstats.rx_bad_ssd;
3038 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3040 switch (stringset) {
3042 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
3050 static void vortex_get_drvinfo(struct net_device *dev,
3051 struct ethtool_drvinfo *info)
3053 struct vortex_private *vp = netdev_priv(dev);
3055 strcpy(info->driver, DRV_NAME);
3056 strcpy(info->version, DRV_VERSION);
3057 if (VORTEX_PCI(vp)) {
3058 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
3060 if (VORTEX_EISA(vp))
3061 sprintf(info->bus_info, vp->gendev->bus_id);
3063 sprintf(info->bus_info, "EISA 0x%lx %d",
3064 dev->base_addr, dev->irq);
3068 static struct ethtool_ops vortex_ethtool_ops = {
3069 .get_drvinfo = vortex_get_drvinfo,
3070 .get_strings = vortex_get_strings,
3071 .get_msglevel = vortex_get_msglevel,
3072 .set_msglevel = vortex_set_msglevel,
3073 .get_ethtool_stats = vortex_get_ethtool_stats,
3074 .get_stats_count = vortex_get_stats_count,
3075 .get_settings = vortex_get_settings,
3076 .set_settings = vortex_set_settings,
3077 .get_link = vortex_get_link,
3078 .nway_reset = vortex_nway_reset,
3079 .get_perm_addr = ethtool_op_get_perm_addr,
3084 * Must power the device up to do MDIO operations
3086 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3089 struct vortex_private *vp = netdev_priv(dev);
3090 void __iomem *ioaddr = vp->ioaddr;
3091 unsigned long flags;
3095 state = VORTEX_PCI(vp)->current_state;
3097 /* The kernel core really should have pci_get_power_state() */
3100 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3101 spin_lock_irqsave(&vp->lock, flags);
3103 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3104 spin_unlock_irqrestore(&vp->lock, flags);
3106 pci_set_power_state(VORTEX_PCI(vp), state);
3113 /* Pre-Cyclone chips have no documented multicast filter, so the only
3114 multicast setting is to receive all multicast frames. At least
3115 the chip has a very clean way to set the mode, unlike many others. */
3116 static void set_rx_mode(struct net_device *dev)
3118 struct vortex_private *vp = netdev_priv(dev);
3119 void __iomem *ioaddr = vp->ioaddr;
3122 if (dev->flags & IFF_PROMISC) {
3123 if (vortex_debug > 0)
3124 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
3125 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3126 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
3127 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3129 new_mode = SetRxFilter | RxStation | RxBroadcast;
3131 iowrite16(new_mode, ioaddr + EL3_CMD);
3134 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3135 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3136 Note that this must be done after each RxReset due to some backwards
3137 compatibility logic in the Cyclone and Tornado ASICs */
3139 /* The Ethernet Type used for 802.1q tagged frames */
3140 #define VLAN_ETHER_TYPE 0x8100
3142 static void set_8021q_mode(struct net_device *dev, int enable)
3144 struct vortex_private *vp = netdev_priv(dev);
3145 void __iomem *ioaddr = vp->ioaddr;
3146 int old_window = ioread16(ioaddr + EL3_CMD);
3149 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3150 /* cyclone and tornado chipsets can recognize 802.1q
3151 * tagged frames and treat them correctly */
3153 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3155 max_pkt_size += 4; /* 802.1Q VLAN tag */
3158 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
3160 /* set VlanEtherType to let the hardware checksumming
3161 treat tagged frames correctly */
3163 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
3165 /* on older cards we have to enable large frames */
3167 vp->large_frames = dev->mtu > 1500 || enable;
3170 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
3171 if (vp->large_frames)
3175 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3178 EL3WINDOW(old_window);
3182 static void set_8021q_mode(struct net_device *dev, int enable)
3189 /* MII transceiver control section.
3190 Read and write the MII registers using software-generated serial
3191 MDIO protocol. See the MII specifications or DP83840A data sheet
3194 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3195 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3196 "overclocking" issues. */
3197 #define mdio_delay() ioread32(mdio_addr)
3199 #define MDIO_SHIFT_CLK 0x01
3200 #define MDIO_DIR_WRITE 0x04
3201 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3202 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3203 #define MDIO_DATA_READ 0x02
3204 #define MDIO_ENB_IN 0x00
3206 /* Generate the preamble required for initial synchronization and
3207 a few older transceivers. */
3208 static void mdio_sync(void __iomem *ioaddr, int bits)
3210 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3212 /* Establish sync by sending at least 32 logic ones. */
3213 while (-- bits >= 0) {
3214 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
3216 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3221 static int mdio_read(struct net_device *dev, int phy_id, int location)
3224 struct vortex_private *vp = netdev_priv(dev);
3225 void __iomem *ioaddr = vp->ioaddr;
3226 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3227 unsigned int retval = 0;
3228 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3230 if (mii_preamble_required)
3231 mdio_sync(ioaddr, 32);
3233 /* Shift the read command bits out. */
3234 for (i = 14; i >= 0; i--) {
3235 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3236 iowrite16(dataval, mdio_addr);
3238 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3241 /* Read the two transition, 16 data, and wire-idle bits. */
3242 for (i = 19; i > 0; i--) {
3243 iowrite16(MDIO_ENB_IN, mdio_addr);
3245 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3246 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3249 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3252 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3254 struct vortex_private *vp = netdev_priv(dev);
3255 void __iomem *ioaddr = vp->ioaddr;
3256 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3257 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3260 if (mii_preamble_required)
3261 mdio_sync(ioaddr, 32);
3263 /* Shift the command bits out. */
3264 for (i = 31; i >= 0; i--) {
3265 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3266 iowrite16(dataval, mdio_addr);
3268 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3271 /* Leave the interface idle. */
3272 for (i = 1; i >= 0; i--) {
3273 iowrite16(MDIO_ENB_IN, mdio_addr);
3275 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3281 /* ACPI: Advanced Configuration and Power Interface. */
3282 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3283 static void acpi_set_WOL(struct net_device *dev)
3285 struct vortex_private *vp = netdev_priv(dev);
3286 void __iomem *ioaddr = vp->ioaddr;
3288 if (vp->enable_wol) {
3289 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3291 iowrite16(2, ioaddr + 0x0c);
3292 /* The RxFilter must accept the WOL frames. */
3293 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3294 iowrite16(RxEnable, ioaddr + EL3_CMD);
3296 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3298 /* Change the power state to D3; RxEnable doesn't take effect. */
3299 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3304 static void __devexit vortex_remove_one (struct pci_dev *pdev)
3306 struct net_device *dev = pci_get_drvdata(pdev);
3307 struct vortex_private *vp;
3310 printk("vortex_remove_one called for Compaq device!\n");
3314 vp = netdev_priv(dev);
3317 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3319 unregister_netdev(dev);
3321 if (VORTEX_PCI(vp)) {
3322 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3323 if (vp->pm_state_valid)
3324 pci_restore_state(VORTEX_PCI(vp));
3325 pci_disable_device(VORTEX_PCI(vp));
3327 /* Should really use issue_and_wait() here */
3328 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3329 vp->ioaddr + EL3_CMD);
3331 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3333 pci_free_consistent(pdev,
3334 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3335 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3338 if (vp->must_free_region)
3339 release_region(dev->base_addr, vp->io_size);
3344 static struct pci_driver vortex_driver = {
3346 .probe = vortex_init_one,
3347 .remove = __devexit_p(vortex_remove_one),
3348 .id_table = vortex_pci_tbl,
3350 .suspend = vortex_suspend,
3351 .resume = vortex_resume,
3356 static int vortex_have_pci;
3357 static int vortex_have_eisa;
3360 static int __init vortex_init (void)
3362 int pci_rc, eisa_rc;
3364 pci_rc = pci_module_init(&vortex_driver);
3365 eisa_rc = vortex_eisa_init();
3368 vortex_have_pci = 1;
3370 vortex_have_eisa = 1;
3372 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3376 static void __exit vortex_eisa_cleanup (void)
3378 struct vortex_private *vp;
3379 void __iomem *ioaddr;
3382 /* Take care of the EISA devices */
3383 eisa_driver_unregister (&vortex_eisa_driver);
3386 if (compaq_net_device) {
3387 vp = compaq_net_device->priv;
3388 ioaddr = ioport_map(compaq_net_device->base_addr,
3391 unregister_netdev (compaq_net_device);
3392 iowrite16 (TotalReset, ioaddr + EL3_CMD);
3393 release_region(compaq_net_device->base_addr,
3396 free_netdev (compaq_net_device);
3401 static void __exit vortex_cleanup (void)
3403 if (vortex_have_pci)
3404 pci_unregister_driver (&vortex_driver);
3405 if (vortex_have_eisa)
3406 vortex_eisa_cleanup ();
3410 module_init(vortex_init);
3411 module_exit(vortex_cleanup);