1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50 #include <linux/log2.h>
56 #define FW_BUF_SIZE 0x10000
58 #define DRV_MODULE_NAME "bnx2"
59 #define PFX DRV_MODULE_NAME ": "
60 #define DRV_MODULE_VERSION "1.8.0"
61 #define DRV_MODULE_RELDATE "Aug 14, 2008"
63 #define RUN_AT(x) (jiffies + (x))
65 /* Time in jiffies before concluding the transmitter is hung. */
66 #define TX_TIMEOUT (5*HZ)
68 static char version[] __devinitdata =
69 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
76 static int disable_msi = 0;
78 module_param(disable_msi, int, 0);
79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
94 /* indexed by board_t, above */
97 } board_info[] __devinitdata = {
98 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
99 { "HP NC370T Multifunction Gigabit Server Adapter" },
100 { "HP NC370i Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
102 { "HP NC370F Multifunction Gigabit Server Adapter" },
103 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
105 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
106 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
107 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
110 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
111 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
112 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
114 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
120 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
129 { PCI_VENDOR_ID_BROADCOM, 0x163b,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
134 static struct flash_spec flash_table[] =
136 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
137 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
139 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
140 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
141 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
143 /* Expansion entry 0001 */
144 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
145 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
146 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 /* Saifun SA25F010 (non-buffered flash) */
149 /* strap, cfg1, & write1 need updates */
150 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
151 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
153 "Non-buffered flash (128kB)"},
154 /* Saifun SA25F020 (non-buffered flash) */
155 /* strap, cfg1, & write1 need updates */
156 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
159 "Non-buffered flash (256kB)"},
160 /* Expansion entry 0100 */
161 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
162 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
163 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
165 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
166 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
169 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
170 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
171 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
172 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
173 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
174 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
175 /* Saifun SA25F005 (non-buffered flash) */
176 /* strap, cfg1, & write1 need updates */
177 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
180 "Non-buffered flash (64kB)"},
182 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
183 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
184 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
186 /* Expansion entry 1001 */
187 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
191 /* Expansion entry 1010 */
192 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
196 /* ATMEL AT45DB011B (buffered flash) */
197 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
198 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
199 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
200 "Buffered flash (128kB)"},
201 /* Expansion entry 1100 */
202 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 /* Expansion entry 1101 */
207 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 /* Ateml Expansion entry 1110 */
212 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
215 "Entry 1110 (Atmel)"},
216 /* ATMEL AT45DB021B (buffered flash) */
217 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
218 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
219 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
220 "Buffered flash (256kB)"},
223 static struct flash_spec flash_5709 = {
224 .flags = BNX2_NV_BUFFERED,
225 .page_bits = BCM5709_FLASH_PAGE_BITS,
226 .page_size = BCM5709_FLASH_PAGE_SIZE,
227 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
228 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
229 .name = "5709 Buffered flash (256kB)",
232 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
234 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
240 /* The ring uses 256 indices for 255 entries, one of them
241 * needs to be skipped.
243 diff = txr->tx_prod - txr->tx_cons;
244 if (unlikely(diff >= TX_DESC_CNT)) {
246 if (diff == TX_DESC_CNT)
247 diff = MAX_TX_DESC_CNT;
249 return (bp->tx_ring_size - diff);
253 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
257 spin_lock_bh(&bp->indirect_lock);
258 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
259 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
260 spin_unlock_bh(&bp->indirect_lock);
265 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
267 spin_lock_bh(&bp->indirect_lock);
268 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
269 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
270 spin_unlock_bh(&bp->indirect_lock);
274 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
276 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
280 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
282 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
286 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
289 spin_lock_bh(&bp->indirect_lock);
290 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
293 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
294 REG_WR(bp, BNX2_CTX_CTX_CTRL,
295 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
296 for (i = 0; i < 5; i++) {
297 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
298 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
303 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
304 REG_WR(bp, BNX2_CTX_DATA, val);
306 spin_unlock_bh(&bp->indirect_lock);
310 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
315 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
316 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
319 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
320 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
325 val1 = (bp->phy_addr << 21) | (reg << 16) |
326 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
327 BNX2_EMAC_MDIO_COMM_START_BUSY;
328 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
330 for (i = 0; i < 50; i++) {
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
338 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
344 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
353 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
354 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
357 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
358 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
367 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
372 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
373 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
376 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
377 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
382 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
383 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
384 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
385 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
387 for (i = 0; i < 50; i++) {
390 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
391 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
397 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
402 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
403 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
406 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
407 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
416 bnx2_disable_int(struct bnx2 *bp)
419 struct bnx2_napi *bnapi;
421 for (i = 0; i < bp->irq_nvecs; i++) {
422 bnapi = &bp->bnx2_napi[i];
423 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
424 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
426 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
430 bnx2_enable_int(struct bnx2 *bp)
433 struct bnx2_napi *bnapi;
435 for (i = 0; i < bp->irq_nvecs; i++) {
436 bnapi = &bp->bnx2_napi[i];
438 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
439 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
440 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
441 bnapi->last_status_idx);
443 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
444 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
445 bnapi->last_status_idx);
447 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
451 bnx2_disable_int_sync(struct bnx2 *bp)
455 atomic_inc(&bp->intr_sem);
456 bnx2_disable_int(bp);
457 for (i = 0; i < bp->irq_nvecs; i++)
458 synchronize_irq(bp->irq_tbl[i].vector);
462 bnx2_napi_disable(struct bnx2 *bp)
466 for (i = 0; i < bp->irq_nvecs; i++)
467 napi_disable(&bp->bnx2_napi[i].napi);
471 bnx2_napi_enable(struct bnx2 *bp)
475 for (i = 0; i < bp->irq_nvecs; i++)
476 napi_enable(&bp->bnx2_napi[i].napi);
480 bnx2_netif_stop(struct bnx2 *bp)
482 bnx2_disable_int_sync(bp);
483 if (netif_running(bp->dev)) {
484 bnx2_napi_disable(bp);
485 netif_tx_disable(bp->dev);
486 bp->dev->trans_start = jiffies; /* prevent tx timeout */
491 bnx2_netif_start(struct bnx2 *bp)
493 if (atomic_dec_and_test(&bp->intr_sem)) {
494 if (netif_running(bp->dev)) {
495 netif_tx_wake_all_queues(bp->dev);
496 bnx2_napi_enable(bp);
503 bnx2_free_tx_mem(struct bnx2 *bp)
507 for (i = 0; i < bp->num_tx_rings; i++) {
508 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
509 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
511 if (txr->tx_desc_ring) {
512 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
514 txr->tx_desc_mapping);
515 txr->tx_desc_ring = NULL;
517 kfree(txr->tx_buf_ring);
518 txr->tx_buf_ring = NULL;
523 bnx2_free_rx_mem(struct bnx2 *bp)
527 for (i = 0; i < bp->num_rx_rings; i++) {
528 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
529 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
532 for (j = 0; j < bp->rx_max_ring; j++) {
533 if (rxr->rx_desc_ring[j])
534 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
535 rxr->rx_desc_ring[j],
536 rxr->rx_desc_mapping[j]);
537 rxr->rx_desc_ring[j] = NULL;
539 if (rxr->rx_buf_ring)
540 vfree(rxr->rx_buf_ring);
541 rxr->rx_buf_ring = NULL;
543 for (j = 0; j < bp->rx_max_pg_ring; j++) {
544 if (rxr->rx_pg_desc_ring[j])
545 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
546 rxr->rx_pg_desc_ring[i],
547 rxr->rx_pg_desc_mapping[i]);
548 rxr->rx_pg_desc_ring[i] = NULL;
551 vfree(rxr->rx_pg_ring);
552 rxr->rx_pg_ring = NULL;
557 bnx2_alloc_tx_mem(struct bnx2 *bp)
561 for (i = 0; i < bp->num_tx_rings; i++) {
562 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
563 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
565 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
566 if (txr->tx_buf_ring == NULL)
570 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
571 &txr->tx_desc_mapping);
572 if (txr->tx_desc_ring == NULL)
579 bnx2_alloc_rx_mem(struct bnx2 *bp)
583 for (i = 0; i < bp->num_rx_rings; i++) {
584 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
585 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
589 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
590 if (rxr->rx_buf_ring == NULL)
593 memset(rxr->rx_buf_ring, 0,
594 SW_RXBD_RING_SIZE * bp->rx_max_ring);
596 for (j = 0; j < bp->rx_max_ring; j++) {
597 rxr->rx_desc_ring[j] =
598 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
599 &rxr->rx_desc_mapping[j]);
600 if (rxr->rx_desc_ring[j] == NULL)
605 if (bp->rx_pg_ring_size) {
606 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
608 if (rxr->rx_pg_ring == NULL)
611 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
615 for (j = 0; j < bp->rx_max_pg_ring; j++) {
616 rxr->rx_pg_desc_ring[j] =
617 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
618 &rxr->rx_pg_desc_mapping[j]);
619 if (rxr->rx_pg_desc_ring[j] == NULL)
628 bnx2_free_mem(struct bnx2 *bp)
631 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
633 bnx2_free_tx_mem(bp);
634 bnx2_free_rx_mem(bp);
636 for (i = 0; i < bp->ctx_pages; i++) {
637 if (bp->ctx_blk[i]) {
638 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
640 bp->ctx_blk_mapping[i]);
641 bp->ctx_blk[i] = NULL;
644 if (bnapi->status_blk.msi) {
645 pci_free_consistent(bp->pdev, bp->status_stats_size,
646 bnapi->status_blk.msi,
647 bp->status_blk_mapping);
648 bnapi->status_blk.msi = NULL;
649 bp->stats_blk = NULL;
654 bnx2_alloc_mem(struct bnx2 *bp)
656 int i, status_blk_size, err;
657 struct bnx2_napi *bnapi;
660 /* Combine status and statistics blocks into one allocation. */
661 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
662 if (bp->flags & BNX2_FLAG_MSIX_CAP)
663 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
664 BNX2_SBLK_MSIX_ALIGN_SIZE);
665 bp->status_stats_size = status_blk_size +
666 sizeof(struct statistics_block);
668 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
669 &bp->status_blk_mapping);
670 if (status_blk == NULL)
673 memset(status_blk, 0, bp->status_stats_size);
675 bnapi = &bp->bnx2_napi[0];
676 bnapi->status_blk.msi = status_blk;
677 bnapi->hw_tx_cons_ptr =
678 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
679 bnapi->hw_rx_cons_ptr =
680 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
681 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
682 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
683 struct status_block_msix *sblk;
685 bnapi = &bp->bnx2_napi[i];
687 sblk = (void *) (status_blk +
688 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
689 bnapi->status_blk.msix = sblk;
690 bnapi->hw_tx_cons_ptr =
691 &sblk->status_tx_quick_consumer_index;
692 bnapi->hw_rx_cons_ptr =
693 &sblk->status_rx_quick_consumer_index;
694 bnapi->int_num = i << 24;
698 bp->stats_blk = status_blk + status_blk_size;
700 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
702 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
703 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
704 if (bp->ctx_pages == 0)
706 for (i = 0; i < bp->ctx_pages; i++) {
707 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
709 &bp->ctx_blk_mapping[i]);
710 if (bp->ctx_blk[i] == NULL)
715 err = bnx2_alloc_rx_mem(bp);
719 err = bnx2_alloc_tx_mem(bp);
731 bnx2_report_fw_link(struct bnx2 *bp)
733 u32 fw_link_status = 0;
735 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
741 switch (bp->line_speed) {
743 if (bp->duplex == DUPLEX_HALF)
744 fw_link_status = BNX2_LINK_STATUS_10HALF;
746 fw_link_status = BNX2_LINK_STATUS_10FULL;
749 if (bp->duplex == DUPLEX_HALF)
750 fw_link_status = BNX2_LINK_STATUS_100HALF;
752 fw_link_status = BNX2_LINK_STATUS_100FULL;
755 if (bp->duplex == DUPLEX_HALF)
756 fw_link_status = BNX2_LINK_STATUS_1000HALF;
758 fw_link_status = BNX2_LINK_STATUS_1000FULL;
761 if (bp->duplex == DUPLEX_HALF)
762 fw_link_status = BNX2_LINK_STATUS_2500HALF;
764 fw_link_status = BNX2_LINK_STATUS_2500FULL;
768 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
771 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
773 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
774 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
776 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
777 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
778 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
780 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
784 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
786 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
790 bnx2_xceiver_str(struct bnx2 *bp)
792 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
793 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
798 bnx2_report_link(struct bnx2 *bp)
801 netif_carrier_on(bp->dev);
802 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
803 bnx2_xceiver_str(bp));
805 printk("%d Mbps ", bp->line_speed);
807 if (bp->duplex == DUPLEX_FULL)
808 printk("full duplex");
810 printk("half duplex");
813 if (bp->flow_ctrl & FLOW_CTRL_RX) {
814 printk(", receive ");
815 if (bp->flow_ctrl & FLOW_CTRL_TX)
816 printk("& transmit ");
819 printk(", transmit ");
821 printk("flow control ON");
826 netif_carrier_off(bp->dev);
827 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
828 bnx2_xceiver_str(bp));
831 bnx2_report_fw_link(bp);
835 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
837 u32 local_adv, remote_adv;
840 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
841 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
843 if (bp->duplex == DUPLEX_FULL) {
844 bp->flow_ctrl = bp->req_flow_ctrl;
849 if (bp->duplex != DUPLEX_FULL) {
853 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
854 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
857 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
858 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
859 bp->flow_ctrl |= FLOW_CTRL_TX;
860 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
861 bp->flow_ctrl |= FLOW_CTRL_RX;
865 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
866 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
868 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
869 u32 new_local_adv = 0;
870 u32 new_remote_adv = 0;
872 if (local_adv & ADVERTISE_1000XPAUSE)
873 new_local_adv |= ADVERTISE_PAUSE_CAP;
874 if (local_adv & ADVERTISE_1000XPSE_ASYM)
875 new_local_adv |= ADVERTISE_PAUSE_ASYM;
876 if (remote_adv & ADVERTISE_1000XPAUSE)
877 new_remote_adv |= ADVERTISE_PAUSE_CAP;
878 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
879 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
881 local_adv = new_local_adv;
882 remote_adv = new_remote_adv;
885 /* See Table 28B-3 of 802.3ab-1999 spec. */
886 if (local_adv & ADVERTISE_PAUSE_CAP) {
887 if(local_adv & ADVERTISE_PAUSE_ASYM) {
888 if (remote_adv & ADVERTISE_PAUSE_CAP) {
889 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
891 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
892 bp->flow_ctrl = FLOW_CTRL_RX;
896 if (remote_adv & ADVERTISE_PAUSE_CAP) {
897 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
901 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
902 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
903 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
905 bp->flow_ctrl = FLOW_CTRL_TX;
911 bnx2_5709s_linkup(struct bnx2 *bp)
917 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
918 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
919 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
921 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
922 bp->line_speed = bp->req_line_speed;
923 bp->duplex = bp->req_duplex;
926 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
928 case MII_BNX2_GP_TOP_AN_SPEED_10:
929 bp->line_speed = SPEED_10;
931 case MII_BNX2_GP_TOP_AN_SPEED_100:
932 bp->line_speed = SPEED_100;
934 case MII_BNX2_GP_TOP_AN_SPEED_1G:
935 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
936 bp->line_speed = SPEED_1000;
938 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
939 bp->line_speed = SPEED_2500;
942 if (val & MII_BNX2_GP_TOP_AN_FD)
943 bp->duplex = DUPLEX_FULL;
945 bp->duplex = DUPLEX_HALF;
950 bnx2_5708s_linkup(struct bnx2 *bp)
955 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
956 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
957 case BCM5708S_1000X_STAT1_SPEED_10:
958 bp->line_speed = SPEED_10;
960 case BCM5708S_1000X_STAT1_SPEED_100:
961 bp->line_speed = SPEED_100;
963 case BCM5708S_1000X_STAT1_SPEED_1G:
964 bp->line_speed = SPEED_1000;
966 case BCM5708S_1000X_STAT1_SPEED_2G5:
967 bp->line_speed = SPEED_2500;
970 if (val & BCM5708S_1000X_STAT1_FD)
971 bp->duplex = DUPLEX_FULL;
973 bp->duplex = DUPLEX_HALF;
979 bnx2_5706s_linkup(struct bnx2 *bp)
981 u32 bmcr, local_adv, remote_adv, common;
984 bp->line_speed = SPEED_1000;
986 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
987 if (bmcr & BMCR_FULLDPLX) {
988 bp->duplex = DUPLEX_FULL;
991 bp->duplex = DUPLEX_HALF;
994 if (!(bmcr & BMCR_ANENABLE)) {
998 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
999 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1001 common = local_adv & remote_adv;
1002 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1004 if (common & ADVERTISE_1000XFULL) {
1005 bp->duplex = DUPLEX_FULL;
1008 bp->duplex = DUPLEX_HALF;
1016 bnx2_copper_linkup(struct bnx2 *bp)
1020 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1021 if (bmcr & BMCR_ANENABLE) {
1022 u32 local_adv, remote_adv, common;
1024 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1027 common = local_adv & (remote_adv >> 2);
1028 if (common & ADVERTISE_1000FULL) {
1029 bp->line_speed = SPEED_1000;
1030 bp->duplex = DUPLEX_FULL;
1032 else if (common & ADVERTISE_1000HALF) {
1033 bp->line_speed = SPEED_1000;
1034 bp->duplex = DUPLEX_HALF;
1037 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1040 common = local_adv & remote_adv;
1041 if (common & ADVERTISE_100FULL) {
1042 bp->line_speed = SPEED_100;
1043 bp->duplex = DUPLEX_FULL;
1045 else if (common & ADVERTISE_100HALF) {
1046 bp->line_speed = SPEED_100;
1047 bp->duplex = DUPLEX_HALF;
1049 else if (common & ADVERTISE_10FULL) {
1050 bp->line_speed = SPEED_10;
1051 bp->duplex = DUPLEX_FULL;
1053 else if (common & ADVERTISE_10HALF) {
1054 bp->line_speed = SPEED_10;
1055 bp->duplex = DUPLEX_HALF;
1064 if (bmcr & BMCR_SPEED100) {
1065 bp->line_speed = SPEED_100;
1068 bp->line_speed = SPEED_10;
1070 if (bmcr & BMCR_FULLDPLX) {
1071 bp->duplex = DUPLEX_FULL;
1074 bp->duplex = DUPLEX_HALF;
1082 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1084 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1086 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1090 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091 u32 lo_water, hi_water;
1093 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1096 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097 if (lo_water >= bp->rx_ring_size)
1100 hi_water = bp->rx_ring_size / 4;
1102 if (hi_water <= lo_water)
1105 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1110 else if (hi_water == 0)
1112 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1114 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1118 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1123 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1126 bnx2_init_rx_context(bp, cid);
1131 bnx2_set_mac_link(struct bnx2 *bp)
1135 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137 (bp->duplex == DUPLEX_HALF)) {
1138 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1141 /* Configure the EMAC mode register. */
1142 val = REG_RD(bp, BNX2_EMAC_MODE);
1144 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1145 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1146 BNX2_EMAC_MODE_25G_MODE);
1149 switch (bp->line_speed) {
1151 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1157 val |= BNX2_EMAC_MODE_PORT_MII;
1160 val |= BNX2_EMAC_MODE_25G_MODE;
1163 val |= BNX2_EMAC_MODE_PORT_GMII;
1168 val |= BNX2_EMAC_MODE_PORT_GMII;
1171 /* Set the MAC to operate in the appropriate duplex mode. */
1172 if (bp->duplex == DUPLEX_HALF)
1173 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174 REG_WR(bp, BNX2_EMAC_MODE, val);
1176 /* Enable/disable rx PAUSE. */
1177 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1179 if (bp->flow_ctrl & FLOW_CTRL_RX)
1180 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1183 /* Enable/disable tx PAUSE. */
1184 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1187 if (bp->flow_ctrl & FLOW_CTRL_TX)
1188 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1191 /* Acknowledge the interrupt. */
1192 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1194 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1195 bnx2_init_all_rx_contexts(bp);
1199 bnx2_enable_bmsr1(struct bnx2 *bp)
1201 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1202 (CHIP_NUM(bp) == CHIP_NUM_5709))
1203 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1204 MII_BNX2_BLK_ADDR_GP_STATUS);
1208 bnx2_disable_bmsr1(struct bnx2 *bp)
1210 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1211 (CHIP_NUM(bp) == CHIP_NUM_5709))
1212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1217 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1222 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1225 if (bp->autoneg & AUTONEG_SPEED)
1226 bp->advertising |= ADVERTISED_2500baseX_Full;
1228 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1229 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1231 bnx2_read_phy(bp, bp->mii_up1, &up1);
1232 if (!(up1 & BCM5708S_UP1_2G5)) {
1233 up1 |= BCM5708S_UP1_2G5;
1234 bnx2_write_phy(bp, bp->mii_up1, up1);
1238 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1239 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1240 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1246 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1251 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1254 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1255 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1257 bnx2_read_phy(bp, bp->mii_up1, &up1);
1258 if (up1 & BCM5708S_UP1_2G5) {
1259 up1 &= ~BCM5708S_UP1_2G5;
1260 bnx2_write_phy(bp, bp->mii_up1, up1);
1264 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1265 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1266 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1272 bnx2_enable_forced_2g5(struct bnx2 *bp)
1276 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1279 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1282 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1283 MII_BNX2_BLK_ADDR_SERDES_DIG);
1284 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1285 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1286 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1287 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1289 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1290 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1291 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1293 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1294 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1295 bmcr |= BCM5708S_BMCR_FORCE_2500;
1298 if (bp->autoneg & AUTONEG_SPEED) {
1299 bmcr &= ~BMCR_ANENABLE;
1300 if (bp->req_duplex == DUPLEX_FULL)
1301 bmcr |= BMCR_FULLDPLX;
1303 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1307 bnx2_disable_forced_2g5(struct bnx2 *bp)
1311 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1314 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1317 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1318 MII_BNX2_BLK_ADDR_SERDES_DIG);
1319 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1320 val &= ~MII_BNX2_SD_MISC1_FORCE;
1321 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1323 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1324 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1325 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1327 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1328 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1329 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1332 if (bp->autoneg & AUTONEG_SPEED)
1333 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1334 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1338 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1342 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1343 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1345 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1347 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1351 bnx2_set_link(struct bnx2 *bp)
1356 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1361 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1364 link_up = bp->link_up;
1366 bnx2_enable_bmsr1(bp);
1367 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1368 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1369 bnx2_disable_bmsr1(bp);
1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1372 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1375 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1376 bnx2_5706s_force_link_dn(bp, 0);
1377 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1379 val = REG_RD(bp, BNX2_EMAC_STATUS);
1381 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1382 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1383 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1385 if ((val & BNX2_EMAC_STATUS_LINK) &&
1386 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1387 bmsr |= BMSR_LSTATUS;
1389 bmsr &= ~BMSR_LSTATUS;
1392 if (bmsr & BMSR_LSTATUS) {
1395 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1396 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1397 bnx2_5706s_linkup(bp);
1398 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1399 bnx2_5708s_linkup(bp);
1400 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1401 bnx2_5709s_linkup(bp);
1404 bnx2_copper_linkup(bp);
1406 bnx2_resolve_flow_ctrl(bp);
1409 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1410 (bp->autoneg & AUTONEG_SPEED))
1411 bnx2_disable_forced_2g5(bp);
1413 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1416 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1417 bmcr |= BMCR_ANENABLE;
1418 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1420 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1425 if (bp->link_up != link_up) {
1426 bnx2_report_link(bp);
1429 bnx2_set_mac_link(bp);
1435 bnx2_reset_phy(struct bnx2 *bp)
1440 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1442 #define PHY_RESET_MAX_WAIT 100
1443 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1446 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1447 if (!(reg & BMCR_RESET)) {
1452 if (i == PHY_RESET_MAX_WAIT) {
1459 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1463 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1464 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1466 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1467 adv = ADVERTISE_1000XPAUSE;
1470 adv = ADVERTISE_PAUSE_CAP;
1473 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1474 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1475 adv = ADVERTISE_1000XPSE_ASYM;
1478 adv = ADVERTISE_PAUSE_ASYM;
1481 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1482 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1483 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1486 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1492 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1495 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1497 u32 speed_arg = 0, pause_adv;
1499 pause_adv = bnx2_phy_get_pause_adv(bp);
1501 if (bp->autoneg & AUTONEG_SPEED) {
1502 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1503 if (bp->advertising & ADVERTISED_10baseT_Half)
1504 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1505 if (bp->advertising & ADVERTISED_10baseT_Full)
1506 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1507 if (bp->advertising & ADVERTISED_100baseT_Half)
1508 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1509 if (bp->advertising & ADVERTISED_100baseT_Full)
1510 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1511 if (bp->advertising & ADVERTISED_1000baseT_Full)
1512 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1513 if (bp->advertising & ADVERTISED_2500baseX_Full)
1514 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1516 if (bp->req_line_speed == SPEED_2500)
1517 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1518 else if (bp->req_line_speed == SPEED_1000)
1519 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1520 else if (bp->req_line_speed == SPEED_100) {
1521 if (bp->req_duplex == DUPLEX_FULL)
1522 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1524 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1525 } else if (bp->req_line_speed == SPEED_10) {
1526 if (bp->req_duplex == DUPLEX_FULL)
1527 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1529 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1533 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1534 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1535 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1536 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1538 if (port == PORT_TP)
1539 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1540 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1542 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1544 spin_unlock_bh(&bp->phy_lock);
1545 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1546 spin_lock_bh(&bp->phy_lock);
1552 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1557 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1558 return (bnx2_setup_remote_phy(bp, port));
1560 if (!(bp->autoneg & AUTONEG_SPEED)) {
1562 int force_link_down = 0;
1564 if (bp->req_line_speed == SPEED_2500) {
1565 if (!bnx2_test_and_enable_2g5(bp))
1566 force_link_down = 1;
1567 } else if (bp->req_line_speed == SPEED_1000) {
1568 if (bnx2_test_and_disable_2g5(bp))
1569 force_link_down = 1;
1571 bnx2_read_phy(bp, bp->mii_adv, &adv);
1572 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1574 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1575 new_bmcr = bmcr & ~BMCR_ANENABLE;
1576 new_bmcr |= BMCR_SPEED1000;
1578 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1579 if (bp->req_line_speed == SPEED_2500)
1580 bnx2_enable_forced_2g5(bp);
1581 else if (bp->req_line_speed == SPEED_1000) {
1582 bnx2_disable_forced_2g5(bp);
1583 new_bmcr &= ~0x2000;
1586 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1587 if (bp->req_line_speed == SPEED_2500)
1588 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1590 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1593 if (bp->req_duplex == DUPLEX_FULL) {
1594 adv |= ADVERTISE_1000XFULL;
1595 new_bmcr |= BMCR_FULLDPLX;
1598 adv |= ADVERTISE_1000XHALF;
1599 new_bmcr &= ~BMCR_FULLDPLX;
1601 if ((new_bmcr != bmcr) || (force_link_down)) {
1602 /* Force a link down visible on the other side */
1604 bnx2_write_phy(bp, bp->mii_adv, adv &
1605 ~(ADVERTISE_1000XFULL |
1606 ADVERTISE_1000XHALF));
1607 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1608 BMCR_ANRESTART | BMCR_ANENABLE);
1611 netif_carrier_off(bp->dev);
1612 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1613 bnx2_report_link(bp);
1615 bnx2_write_phy(bp, bp->mii_adv, adv);
1616 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1618 bnx2_resolve_flow_ctrl(bp);
1619 bnx2_set_mac_link(bp);
1624 bnx2_test_and_enable_2g5(bp);
1626 if (bp->advertising & ADVERTISED_1000baseT_Full)
1627 new_adv |= ADVERTISE_1000XFULL;
1629 new_adv |= bnx2_phy_get_pause_adv(bp);
1631 bnx2_read_phy(bp, bp->mii_adv, &adv);
1632 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1634 bp->serdes_an_pending = 0;
1635 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1636 /* Force a link down visible on the other side */
1638 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1639 spin_unlock_bh(&bp->phy_lock);
1641 spin_lock_bh(&bp->phy_lock);
1644 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1645 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1647 /* Speed up link-up time when the link partner
1648 * does not autonegotiate which is very common
1649 * in blade servers. Some blade servers use
1650 * IPMI for kerboard input and it's important
1651 * to minimize link disruptions. Autoneg. involves
1652 * exchanging base pages plus 3 next pages and
1653 * normally completes in about 120 msec.
1655 bp->current_interval = SERDES_AN_TIMEOUT;
1656 bp->serdes_an_pending = 1;
1657 mod_timer(&bp->timer, jiffies + bp->current_interval);
1659 bnx2_resolve_flow_ctrl(bp);
1660 bnx2_set_mac_link(bp);
1666 #define ETHTOOL_ALL_FIBRE_SPEED \
1667 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1668 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1669 (ADVERTISED_1000baseT_Full)
1671 #define ETHTOOL_ALL_COPPER_SPEED \
1672 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1673 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1674 ADVERTISED_1000baseT_Full)
1676 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1677 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1679 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1682 bnx2_set_default_remote_link(struct bnx2 *bp)
1686 if (bp->phy_port == PORT_TP)
1687 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1689 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1691 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1692 bp->req_line_speed = 0;
1693 bp->autoneg |= AUTONEG_SPEED;
1694 bp->advertising = ADVERTISED_Autoneg;
1695 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1696 bp->advertising |= ADVERTISED_10baseT_Half;
1697 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1698 bp->advertising |= ADVERTISED_10baseT_Full;
1699 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1700 bp->advertising |= ADVERTISED_100baseT_Half;
1701 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1702 bp->advertising |= ADVERTISED_100baseT_Full;
1703 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1704 bp->advertising |= ADVERTISED_1000baseT_Full;
1705 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1706 bp->advertising |= ADVERTISED_2500baseX_Full;
1709 bp->advertising = 0;
1710 bp->req_duplex = DUPLEX_FULL;
1711 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1712 bp->req_line_speed = SPEED_10;
1713 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1714 bp->req_duplex = DUPLEX_HALF;
1716 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1717 bp->req_line_speed = SPEED_100;
1718 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1719 bp->req_duplex = DUPLEX_HALF;
1721 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1722 bp->req_line_speed = SPEED_1000;
1723 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1724 bp->req_line_speed = SPEED_2500;
1729 bnx2_set_default_link(struct bnx2 *bp)
1731 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1732 bnx2_set_default_remote_link(bp);
1736 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1737 bp->req_line_speed = 0;
1738 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1741 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1743 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1744 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1745 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1747 bp->req_line_speed = bp->line_speed = SPEED_1000;
1748 bp->req_duplex = DUPLEX_FULL;
1751 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1755 bnx2_send_heart_beat(struct bnx2 *bp)
1760 spin_lock(&bp->indirect_lock);
1761 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1762 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1763 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1764 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1765 spin_unlock(&bp->indirect_lock);
1769 bnx2_remote_phy_event(struct bnx2 *bp)
1772 u8 link_up = bp->link_up;
1775 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1777 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1778 bnx2_send_heart_beat(bp);
1780 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1782 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1788 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1789 bp->duplex = DUPLEX_FULL;
1791 case BNX2_LINK_STATUS_10HALF:
1792 bp->duplex = DUPLEX_HALF;
1793 case BNX2_LINK_STATUS_10FULL:
1794 bp->line_speed = SPEED_10;
1796 case BNX2_LINK_STATUS_100HALF:
1797 bp->duplex = DUPLEX_HALF;
1798 case BNX2_LINK_STATUS_100BASE_T4:
1799 case BNX2_LINK_STATUS_100FULL:
1800 bp->line_speed = SPEED_100;
1802 case BNX2_LINK_STATUS_1000HALF:
1803 bp->duplex = DUPLEX_HALF;
1804 case BNX2_LINK_STATUS_1000FULL:
1805 bp->line_speed = SPEED_1000;
1807 case BNX2_LINK_STATUS_2500HALF:
1808 bp->duplex = DUPLEX_HALF;
1809 case BNX2_LINK_STATUS_2500FULL:
1810 bp->line_speed = SPEED_2500;
1818 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1819 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1820 if (bp->duplex == DUPLEX_FULL)
1821 bp->flow_ctrl = bp->req_flow_ctrl;
1823 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1824 bp->flow_ctrl |= FLOW_CTRL_TX;
1825 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1826 bp->flow_ctrl |= FLOW_CTRL_RX;
1829 old_port = bp->phy_port;
1830 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1831 bp->phy_port = PORT_FIBRE;
1833 bp->phy_port = PORT_TP;
1835 if (old_port != bp->phy_port)
1836 bnx2_set_default_link(bp);
1839 if (bp->link_up != link_up)
1840 bnx2_report_link(bp);
1842 bnx2_set_mac_link(bp);
1846 bnx2_set_remote_link(struct bnx2 *bp)
1850 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1852 case BNX2_FW_EVT_CODE_LINK_EVENT:
1853 bnx2_remote_phy_event(bp);
1855 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1857 bnx2_send_heart_beat(bp);
1864 bnx2_setup_copper_phy(struct bnx2 *bp)
1869 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1871 if (bp->autoneg & AUTONEG_SPEED) {
1872 u32 adv_reg, adv1000_reg;
1873 u32 new_adv_reg = 0;
1874 u32 new_adv1000_reg = 0;
1876 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1877 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1878 ADVERTISE_PAUSE_ASYM);
1880 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1881 adv1000_reg &= PHY_ALL_1000_SPEED;
1883 if (bp->advertising & ADVERTISED_10baseT_Half)
1884 new_adv_reg |= ADVERTISE_10HALF;
1885 if (bp->advertising & ADVERTISED_10baseT_Full)
1886 new_adv_reg |= ADVERTISE_10FULL;
1887 if (bp->advertising & ADVERTISED_100baseT_Half)
1888 new_adv_reg |= ADVERTISE_100HALF;
1889 if (bp->advertising & ADVERTISED_100baseT_Full)
1890 new_adv_reg |= ADVERTISE_100FULL;
1891 if (bp->advertising & ADVERTISED_1000baseT_Full)
1892 new_adv1000_reg |= ADVERTISE_1000FULL;
1894 new_adv_reg |= ADVERTISE_CSMA;
1896 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1898 if ((adv1000_reg != new_adv1000_reg) ||
1899 (adv_reg != new_adv_reg) ||
1900 ((bmcr & BMCR_ANENABLE) == 0)) {
1902 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1903 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1904 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1907 else if (bp->link_up) {
1908 /* Flow ctrl may have changed from auto to forced */
1909 /* or vice-versa. */
1911 bnx2_resolve_flow_ctrl(bp);
1912 bnx2_set_mac_link(bp);
1918 if (bp->req_line_speed == SPEED_100) {
1919 new_bmcr |= BMCR_SPEED100;
1921 if (bp->req_duplex == DUPLEX_FULL) {
1922 new_bmcr |= BMCR_FULLDPLX;
1924 if (new_bmcr != bmcr) {
1927 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1928 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1930 if (bmsr & BMSR_LSTATUS) {
1931 /* Force link down */
1932 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1933 spin_unlock_bh(&bp->phy_lock);
1935 spin_lock_bh(&bp->phy_lock);
1937 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1941 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1943 /* Normally, the new speed is setup after the link has
1944 * gone down and up again. In some cases, link will not go
1945 * down so we need to set up the new speed here.
1947 if (bmsr & BMSR_LSTATUS) {
1948 bp->line_speed = bp->req_line_speed;
1949 bp->duplex = bp->req_duplex;
1950 bnx2_resolve_flow_ctrl(bp);
1951 bnx2_set_mac_link(bp);
1954 bnx2_resolve_flow_ctrl(bp);
1955 bnx2_set_mac_link(bp);
1961 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1963 if (bp->loopback == MAC_LOOPBACK)
1966 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1967 return (bnx2_setup_serdes_phy(bp, port));
1970 return (bnx2_setup_copper_phy(bp));
1975 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1979 bp->mii_bmcr = MII_BMCR + 0x10;
1980 bp->mii_bmsr = MII_BMSR + 0x10;
1981 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1982 bp->mii_adv = MII_ADVERTISE + 0x10;
1983 bp->mii_lpa = MII_LPA + 0x10;
1984 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1986 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1987 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1989 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1993 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1995 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1996 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1997 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1998 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2000 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2001 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2002 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2003 val |= BCM5708S_UP1_2G5;
2005 val &= ~BCM5708S_UP1_2G5;
2006 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2008 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2009 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2010 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2011 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2013 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2015 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2016 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2017 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2019 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2025 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2032 bp->mii_up1 = BCM5708S_UP1;
2034 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2035 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2036 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2038 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2039 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2040 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2042 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2043 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2044 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2046 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2047 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2048 val |= BCM5708S_UP1_2G5;
2049 bnx2_write_phy(bp, BCM5708S_UP1, val);
2052 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2053 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2054 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2055 /* increase tx signal amplitude */
2056 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2057 BCM5708S_BLK_ADDR_TX_MISC);
2058 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2059 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2060 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2061 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2064 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2065 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2070 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2071 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2072 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2073 BCM5708S_BLK_ADDR_TX_MISC);
2074 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2075 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2076 BCM5708S_BLK_ADDR_DIG);
2083 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2088 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2090 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2091 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2093 if (bp->dev->mtu > 1500) {
2096 /* Set extended packet length bit */
2097 bnx2_write_phy(bp, 0x18, 0x7);
2098 bnx2_read_phy(bp, 0x18, &val);
2099 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2101 bnx2_write_phy(bp, 0x1c, 0x6c00);
2102 bnx2_read_phy(bp, 0x1c, &val);
2103 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2108 bnx2_write_phy(bp, 0x18, 0x7);
2109 bnx2_read_phy(bp, 0x18, &val);
2110 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2112 bnx2_write_phy(bp, 0x1c, 0x6c00);
2113 bnx2_read_phy(bp, 0x1c, &val);
2114 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2121 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2128 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2129 bnx2_write_phy(bp, 0x18, 0x0c00);
2130 bnx2_write_phy(bp, 0x17, 0x000a);
2131 bnx2_write_phy(bp, 0x15, 0x310b);
2132 bnx2_write_phy(bp, 0x17, 0x201f);
2133 bnx2_write_phy(bp, 0x15, 0x9506);
2134 bnx2_write_phy(bp, 0x17, 0x401f);
2135 bnx2_write_phy(bp, 0x15, 0x14e2);
2136 bnx2_write_phy(bp, 0x18, 0x0400);
2139 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2140 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2141 MII_BNX2_DSP_EXPAND_REG | 0x8);
2142 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2144 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2147 if (bp->dev->mtu > 1500) {
2148 /* Set extended packet length bit */
2149 bnx2_write_phy(bp, 0x18, 0x7);
2150 bnx2_read_phy(bp, 0x18, &val);
2151 bnx2_write_phy(bp, 0x18, val | 0x4000);
2153 bnx2_read_phy(bp, 0x10, &val);
2154 bnx2_write_phy(bp, 0x10, val | 0x1);
2157 bnx2_write_phy(bp, 0x18, 0x7);
2158 bnx2_read_phy(bp, 0x18, &val);
2159 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2161 bnx2_read_phy(bp, 0x10, &val);
2162 bnx2_write_phy(bp, 0x10, val & ~0x1);
2165 /* ethernet@wirespeed */
2166 bnx2_write_phy(bp, 0x18, 0x7007);
2167 bnx2_read_phy(bp, 0x18, &val);
2168 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2174 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2179 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2180 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2182 bp->mii_bmcr = MII_BMCR;
2183 bp->mii_bmsr = MII_BMSR;
2184 bp->mii_bmsr1 = MII_BMSR;
2185 bp->mii_adv = MII_ADVERTISE;
2186 bp->mii_lpa = MII_LPA;
2188 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2190 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2193 bnx2_read_phy(bp, MII_PHYSID1, &val);
2194 bp->phy_id = val << 16;
2195 bnx2_read_phy(bp, MII_PHYSID2, &val);
2196 bp->phy_id |= val & 0xffff;
2198 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2199 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2200 rc = bnx2_init_5706s_phy(bp, reset_phy);
2201 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2202 rc = bnx2_init_5708s_phy(bp, reset_phy);
2203 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2204 rc = bnx2_init_5709s_phy(bp, reset_phy);
2207 rc = bnx2_init_copper_phy(bp, reset_phy);
2212 rc = bnx2_setup_phy(bp, bp->phy_port);
2218 bnx2_set_mac_loopback(struct bnx2 *bp)
2222 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2223 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2224 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2225 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2230 static int bnx2_test_link(struct bnx2 *);
2233 bnx2_set_phy_loopback(struct bnx2 *bp)
2238 spin_lock_bh(&bp->phy_lock);
2239 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2241 spin_unlock_bh(&bp->phy_lock);
2245 for (i = 0; i < 10; i++) {
2246 if (bnx2_test_link(bp) == 0)
2251 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2252 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2253 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2254 BNX2_EMAC_MODE_25G_MODE);
2256 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2257 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2263 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2269 msg_data |= bp->fw_wr_seq;
2271 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2276 /* wait for an acknowledgement. */
2277 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2280 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2282 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2285 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2288 /* If we timed out, inform the firmware that this is the case. */
2289 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2291 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2294 msg_data &= ~BNX2_DRV_MSG_CODE;
2295 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2297 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2302 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2309 bnx2_init_5709_context(struct bnx2 *bp)
2314 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2315 val |= (BCM_PAGE_BITS - 8) << 16;
2316 REG_WR(bp, BNX2_CTX_COMMAND, val);
2317 for (i = 0; i < 10; i++) {
2318 val = REG_RD(bp, BNX2_CTX_COMMAND);
2319 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2323 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2326 for (i = 0; i < bp->ctx_pages; i++) {
2330 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2334 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2335 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2336 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2337 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2338 (u64) bp->ctx_blk_mapping[i] >> 32);
2339 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2340 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2341 for (j = 0; j < 10; j++) {
2343 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2344 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2348 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2357 bnx2_init_context(struct bnx2 *bp)
2363 u32 vcid_addr, pcid_addr, offset;
2368 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2371 vcid_addr = GET_PCID_ADDR(vcid);
2373 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2378 pcid_addr = GET_PCID_ADDR(new_vcid);
2381 vcid_addr = GET_CID_ADDR(vcid);
2382 pcid_addr = vcid_addr;
2385 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2386 vcid_addr += (i << PHY_CTX_SHIFT);
2387 pcid_addr += (i << PHY_CTX_SHIFT);
2389 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2390 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2392 /* Zero out the context. */
2393 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2394 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2400 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2406 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2407 if (good_mbuf == NULL) {
2408 printk(KERN_ERR PFX "Failed to allocate memory in "
2409 "bnx2_alloc_bad_rbuf\n");
2413 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2414 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2418 /* Allocate a bunch of mbufs and save the good ones in an array. */
2419 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2420 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2421 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2422 BNX2_RBUF_COMMAND_ALLOC_REQ);
2424 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2426 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2428 /* The addresses with Bit 9 set are bad memory blocks. */
2429 if (!(val & (1 << 9))) {
2430 good_mbuf[good_mbuf_cnt] = (u16) val;
2434 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2437 /* Free the good ones back to the mbuf pool thus discarding
2438 * all the bad ones. */
2439 while (good_mbuf_cnt) {
2442 val = good_mbuf[good_mbuf_cnt];
2443 val = (val << 9) | val | 1;
2445 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2452 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2456 val = (mac_addr[0] << 8) | mac_addr[1];
2458 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2460 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2461 (mac_addr[4] << 8) | mac_addr[5];
2463 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2467 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2470 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2471 struct rx_bd *rxbd =
2472 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2473 struct page *page = alloc_page(GFP_ATOMIC);
2477 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2478 PCI_DMA_FROMDEVICE);
2480 pci_unmap_addr_set(rx_pg, mapping, mapping);
2481 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2482 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2487 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2489 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2490 struct page *page = rx_pg->page;
2495 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2496 PCI_DMA_FROMDEVICE);
2503 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2505 struct sk_buff *skb;
2506 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2508 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2509 unsigned long align;
2511 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2516 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2517 skb_reserve(skb, BNX2_RX_ALIGN - align);
2519 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2520 PCI_DMA_FROMDEVICE);
2523 pci_unmap_addr_set(rx_buf, mapping, mapping);
2525 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2526 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2528 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2534 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2536 struct status_block *sblk = bnapi->status_blk.msi;
2537 u32 new_link_state, old_link_state;
2540 new_link_state = sblk->status_attn_bits & event;
2541 old_link_state = sblk->status_attn_bits_ack & event;
2542 if (new_link_state != old_link_state) {
2544 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2546 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2554 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2556 spin_lock(&bp->phy_lock);
2558 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2560 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2561 bnx2_set_remote_link(bp);
2563 spin_unlock(&bp->phy_lock);
2568 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2572 /* Tell compiler that status block fields can change. */
2574 cons = *bnapi->hw_tx_cons_ptr;
2575 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2581 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2583 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2584 u16 hw_cons, sw_cons, sw_ring_cons;
2585 int tx_pkt = 0, index;
2586 struct netdev_queue *txq;
2588 index = (bnapi - bp->bnx2_napi);
2589 txq = netdev_get_tx_queue(bp->dev, index);
2591 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2592 sw_cons = txr->tx_cons;
2594 while (sw_cons != hw_cons) {
2595 struct sw_bd *tx_buf;
2596 struct sk_buff *skb;
2599 sw_ring_cons = TX_RING_IDX(sw_cons);
2601 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2604 /* partial BD completions possible with TSO packets */
2605 if (skb_is_gso(skb)) {
2606 u16 last_idx, last_ring_idx;
2608 last_idx = sw_cons +
2609 skb_shinfo(skb)->nr_frags + 1;
2610 last_ring_idx = sw_ring_cons +
2611 skb_shinfo(skb)->nr_frags + 1;
2612 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2615 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2620 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2621 skb_headlen(skb), PCI_DMA_TODEVICE);
2624 last = skb_shinfo(skb)->nr_frags;
2626 for (i = 0; i < last; i++) {
2627 sw_cons = NEXT_TX_BD(sw_cons);
2629 pci_unmap_page(bp->pdev,
2631 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2633 skb_shinfo(skb)->frags[i].size,
2637 sw_cons = NEXT_TX_BD(sw_cons);
2641 if (tx_pkt == budget)
2644 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2647 txr->hw_tx_cons = hw_cons;
2648 txr->tx_cons = sw_cons;
2650 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2651 * before checking for netif_tx_queue_stopped(). Without the
2652 * memory barrier, there is a small possibility that bnx2_start_xmit()
2653 * will miss it and cause the queue to be stopped forever.
2657 if (unlikely(netif_tx_queue_stopped(txq)) &&
2658 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2659 __netif_tx_lock(txq, smp_processor_id());
2660 if ((netif_tx_queue_stopped(txq)) &&
2661 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2662 netif_tx_wake_queue(txq);
2663 __netif_tx_unlock(txq);
2670 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2671 struct sk_buff *skb, int count)
2673 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2674 struct rx_bd *cons_bd, *prod_bd;
2677 u16 hw_prod = rxr->rx_pg_prod, prod;
2678 u16 cons = rxr->rx_pg_cons;
2680 for (i = 0; i < count; i++) {
2681 prod = RX_PG_RING_IDX(hw_prod);
2683 prod_rx_pg = &rxr->rx_pg_ring[prod];
2684 cons_rx_pg = &rxr->rx_pg_ring[cons];
2685 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2686 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2688 if (i == 0 && skb) {
2690 struct skb_shared_info *shinfo;
2692 shinfo = skb_shinfo(skb);
2694 page = shinfo->frags[shinfo->nr_frags].page;
2695 shinfo->frags[shinfo->nr_frags].page = NULL;
2696 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2697 PCI_DMA_FROMDEVICE);
2698 cons_rx_pg->page = page;
2699 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2703 prod_rx_pg->page = cons_rx_pg->page;
2704 cons_rx_pg->page = NULL;
2705 pci_unmap_addr_set(prod_rx_pg, mapping,
2706 pci_unmap_addr(cons_rx_pg, mapping));
2708 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2709 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2712 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2713 hw_prod = NEXT_RX_BD(hw_prod);
2715 rxr->rx_pg_prod = hw_prod;
2716 rxr->rx_pg_cons = cons;
2720 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2721 struct sk_buff *skb, u16 cons, u16 prod)
2723 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2724 struct rx_bd *cons_bd, *prod_bd;
2726 cons_rx_buf = &rxr->rx_buf_ring[cons];
2727 prod_rx_buf = &rxr->rx_buf_ring[prod];
2729 pci_dma_sync_single_for_device(bp->pdev,
2730 pci_unmap_addr(cons_rx_buf, mapping),
2731 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2733 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2735 prod_rx_buf->skb = skb;
2740 pci_unmap_addr_set(prod_rx_buf, mapping,
2741 pci_unmap_addr(cons_rx_buf, mapping));
2743 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2744 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2745 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2746 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2750 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2751 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2755 u16 prod = ring_idx & 0xffff;
2757 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2758 if (unlikely(err)) {
2759 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2761 unsigned int raw_len = len + 4;
2762 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2764 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2769 skb_reserve(skb, BNX2_RX_OFFSET);
2770 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2771 PCI_DMA_FROMDEVICE);
2777 unsigned int i, frag_len, frag_size, pages;
2778 struct sw_pg *rx_pg;
2779 u16 pg_cons = rxr->rx_pg_cons;
2780 u16 pg_prod = rxr->rx_pg_prod;
2782 frag_size = len + 4 - hdr_len;
2783 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2784 skb_put(skb, hdr_len);
2786 for (i = 0; i < pages; i++) {
2787 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2788 if (unlikely(frag_len <= 4)) {
2789 unsigned int tail = 4 - frag_len;
2791 rxr->rx_pg_cons = pg_cons;
2792 rxr->rx_pg_prod = pg_prod;
2793 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2800 &skb_shinfo(skb)->frags[i - 1];
2802 skb->data_len -= tail;
2803 skb->truesize -= tail;
2807 rx_pg = &rxr->rx_pg_ring[pg_cons];
2809 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2810 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2815 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2818 err = bnx2_alloc_rx_page(bp, rxr,
2819 RX_PG_RING_IDX(pg_prod));
2820 if (unlikely(err)) {
2821 rxr->rx_pg_cons = pg_cons;
2822 rxr->rx_pg_prod = pg_prod;
2823 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2828 frag_size -= frag_len;
2829 skb->data_len += frag_len;
2830 skb->truesize += frag_len;
2831 skb->len += frag_len;
2833 pg_prod = NEXT_RX_BD(pg_prod);
2834 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2836 rxr->rx_pg_prod = pg_prod;
2837 rxr->rx_pg_cons = pg_cons;
2843 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2847 /* Tell compiler that status block fields can change. */
2849 cons = *bnapi->hw_rx_cons_ptr;
2850 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2856 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2858 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2859 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2860 struct l2_fhdr *rx_hdr;
2861 int rx_pkt = 0, pg_ring_used = 0;
2863 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2864 sw_cons = rxr->rx_cons;
2865 sw_prod = rxr->rx_prod;
2867 /* Memory barrier necessary as speculative reads of the rx
2868 * buffer can be ahead of the index in the status block
2871 while (sw_cons != hw_cons) {
2872 unsigned int len, hdr_len;
2874 struct sw_bd *rx_buf;
2875 struct sk_buff *skb;
2876 dma_addr_t dma_addr;
2878 int hw_vlan __maybe_unused = 0;
2880 sw_ring_cons = RX_RING_IDX(sw_cons);
2881 sw_ring_prod = RX_RING_IDX(sw_prod);
2883 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2888 dma_addr = pci_unmap_addr(rx_buf, mapping);
2890 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2891 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2892 PCI_DMA_FROMDEVICE);
2894 rx_hdr = (struct l2_fhdr *) skb->data;
2895 len = rx_hdr->l2_fhdr_pkt_len;
2897 if ((status = rx_hdr->l2_fhdr_status) &
2898 (L2_FHDR_ERRORS_BAD_CRC |
2899 L2_FHDR_ERRORS_PHY_DECODE |
2900 L2_FHDR_ERRORS_ALIGNMENT |
2901 L2_FHDR_ERRORS_TOO_SHORT |
2902 L2_FHDR_ERRORS_GIANT_FRAME)) {
2904 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2909 if (status & L2_FHDR_STATUS_SPLIT) {
2910 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2912 } else if (len > bp->rx_jumbo_thresh) {
2913 hdr_len = bp->rx_jumbo_thresh;
2919 if (len <= bp->rx_copy_thresh) {
2920 struct sk_buff *new_skb;
2922 new_skb = netdev_alloc_skb(bp->dev, len + 6);
2923 if (new_skb == NULL) {
2924 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2930 skb_copy_from_linear_data_offset(skb,
2932 new_skb->data, len + 6);
2933 skb_reserve(new_skb, 6);
2934 skb_put(new_skb, len);
2936 bnx2_reuse_rx_skb(bp, rxr, skb,
2937 sw_ring_cons, sw_ring_prod);
2940 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2941 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2944 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2945 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2946 vtag = rx_hdr->l2_fhdr_vlan_tag;
2953 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2956 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2957 ve->h_vlan_proto = htons(ETH_P_8021Q);
2958 ve->h_vlan_TCI = htons(vtag);
2963 skb->protocol = eth_type_trans(skb, bp->dev);
2965 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2966 (ntohs(skb->protocol) != 0x8100)) {
2973 skb->ip_summed = CHECKSUM_NONE;
2975 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2976 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2978 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2979 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2980 skb->ip_summed = CHECKSUM_UNNECESSARY;
2985 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
2988 netif_receive_skb(skb);
2990 bp->dev->last_rx = jiffies;
2994 sw_cons = NEXT_RX_BD(sw_cons);
2995 sw_prod = NEXT_RX_BD(sw_prod);
2997 if ((rx_pkt == budget))
3000 /* Refresh hw_cons to see if there is new work */
3001 if (sw_cons == hw_cons) {
3002 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3006 rxr->rx_cons = sw_cons;
3007 rxr->rx_prod = sw_prod;
3010 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3012 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3014 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3022 /* MSI ISR - The only difference between this and the INTx ISR
3023 * is that the MSI interrupt is always serviced.
3026 bnx2_msi(int irq, void *dev_instance)
3028 struct bnx2_napi *bnapi = dev_instance;
3029 struct bnx2 *bp = bnapi->bp;
3030 struct net_device *dev = bp->dev;
3032 prefetch(bnapi->status_blk.msi);
3033 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3034 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3035 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3037 /* Return here if interrupt is disabled. */
3038 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3041 netif_rx_schedule(dev, &bnapi->napi);
3047 bnx2_msi_1shot(int irq, void *dev_instance)
3049 struct bnx2_napi *bnapi = dev_instance;
3050 struct bnx2 *bp = bnapi->bp;
3051 struct net_device *dev = bp->dev;
3053 prefetch(bnapi->status_blk.msi);
3055 /* Return here if interrupt is disabled. */
3056 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3059 netif_rx_schedule(dev, &bnapi->napi);
3065 bnx2_interrupt(int irq, void *dev_instance)
3067 struct bnx2_napi *bnapi = dev_instance;
3068 struct bnx2 *bp = bnapi->bp;
3069 struct net_device *dev = bp->dev;
3070 struct status_block *sblk = bnapi->status_blk.msi;
3072 /* When using INTx, it is possible for the interrupt to arrive
3073 * at the CPU before the status block posted prior to the
3074 * interrupt. Reading a register will flush the status block.
3075 * When using MSI, the MSI message will always complete after
3076 * the status block write.
3078 if ((sblk->status_idx == bnapi->last_status_idx) &&
3079 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3080 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3083 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3084 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3085 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3087 /* Read back to deassert IRQ immediately to avoid too many
3088 * spurious interrupts.
3090 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3092 /* Return here if interrupt is shared and is disabled. */
3093 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3096 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3097 bnapi->last_status_idx = sblk->status_idx;
3098 __netif_rx_schedule(dev, &bnapi->napi);
3105 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3107 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3108 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3110 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3111 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3116 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3117 STATUS_ATTN_BITS_TIMER_ABORT)
3120 bnx2_has_work(struct bnx2_napi *bnapi)
3122 struct status_block *sblk = bnapi->status_blk.msi;
3124 if (bnx2_has_fast_work(bnapi))
3127 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3128 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3134 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3136 struct status_block *sblk = bnapi->status_blk.msi;
3137 u32 status_attn_bits = sblk->status_attn_bits;
3138 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3140 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3141 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3143 bnx2_phy_int(bp, bnapi);
3145 /* This is needed to take care of transient status
3146 * during link changes.
3148 REG_WR(bp, BNX2_HC_COMMAND,
3149 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3150 REG_RD(bp, BNX2_HC_COMMAND);
3154 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3155 int work_done, int budget)
3157 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3158 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3160 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3161 bnx2_tx_int(bp, bnapi, 0);
3163 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3164 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3169 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3171 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3172 struct bnx2 *bp = bnapi->bp;
3174 struct status_block_msix *sblk = bnapi->status_blk.msix;
3177 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3178 if (unlikely(work_done >= budget))
3181 bnapi->last_status_idx = sblk->status_idx;
3182 /* status idx must be read before checking for more work. */
3184 if (likely(!bnx2_has_fast_work(bnapi))) {
3186 netif_rx_complete(bp->dev, napi);
3187 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3188 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3189 bnapi->last_status_idx);
3196 static int bnx2_poll(struct napi_struct *napi, int budget)
3198 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3199 struct bnx2 *bp = bnapi->bp;
3201 struct status_block *sblk = bnapi->status_blk.msi;
3204 bnx2_poll_link(bp, bnapi);
3206 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3208 if (unlikely(work_done >= budget))
3211 /* bnapi->last_status_idx is used below to tell the hw how
3212 * much work has been processed, so we must read it before
3213 * checking for more work.
3215 bnapi->last_status_idx = sblk->status_idx;
3217 if (likely(!bnx2_has_work(bnapi))) {
3218 netif_rx_complete(bp->dev, napi);
3219 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3220 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3221 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3222 bnapi->last_status_idx);
3225 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3226 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3227 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3228 bnapi->last_status_idx);
3230 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3231 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3232 bnapi->last_status_idx);
3240 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3241 * from set_multicast.
3244 bnx2_set_rx_mode(struct net_device *dev)
3246 struct bnx2 *bp = netdev_priv(dev);
3247 u32 rx_mode, sort_mode;
3248 struct dev_addr_list *uc_ptr;
3251 if (!netif_running(dev))
3254 spin_lock_bh(&bp->phy_lock);
3256 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3257 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3258 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3260 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3261 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3263 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3264 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3266 if (dev->flags & IFF_PROMISC) {
3267 /* Promiscuous mode. */
3268 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3269 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3270 BNX2_RPM_SORT_USER0_PROM_VLAN;
3272 else if (dev->flags & IFF_ALLMULTI) {
3273 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3274 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3277 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3280 /* Accept one or more multicast(s). */
3281 struct dev_mc_list *mclist;
3282 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3287 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3289 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3290 i++, mclist = mclist->next) {
3292 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3294 regidx = (bit & 0xe0) >> 5;
3296 mc_filter[regidx] |= (1 << bit);
3299 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3300 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3304 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3308 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3309 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3310 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3311 BNX2_RPM_SORT_USER0_PROM_VLAN;
3312 } else if (!(dev->flags & IFF_PROMISC)) {
3313 uc_ptr = dev->uc_list;
3315 /* Add all entries into to the match filter list */
3316 for (i = 0; i < dev->uc_count; i++) {
3317 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3318 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3320 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3321 uc_ptr = uc_ptr->next;
3326 if (rx_mode != bp->rx_mode) {
3327 bp->rx_mode = rx_mode;
3328 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3331 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3332 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3333 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3335 spin_unlock_bh(&bp->phy_lock);
3339 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3345 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3346 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3347 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3348 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3349 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3352 for (i = 0; i < rv2p_code_len; i += 8) {
3353 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3355 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3358 if (rv2p_proc == RV2P_PROC1) {
3359 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3360 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3363 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3364 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3368 /* Reset the processor, un-stall is done later. */
3369 if (rv2p_proc == RV2P_PROC1) {
3370 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3373 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3378 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3385 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3386 val |= cpu_reg->mode_value_halt;
3387 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3388 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3390 /* Load the Text area. */
3391 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3395 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3400 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3401 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3405 /* Load the Data area. */
3406 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3410 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3411 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3415 /* Load the SBSS area. */
3416 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3420 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3421 bnx2_reg_wr_ind(bp, offset, 0);
3425 /* Load the BSS area. */
3426 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3430 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3431 bnx2_reg_wr_ind(bp, offset, 0);
3435 /* Load the Read-Only area. */
3436 offset = cpu_reg->spad_base +
3437 (fw->rodata_addr - cpu_reg->mips_view_base);
3441 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3442 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3446 /* Clear the pre-fetch instruction. */
3447 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3448 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3450 /* Start the CPU. */
3451 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3452 val &= ~cpu_reg->mode_value_halt;
3453 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3454 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3460 bnx2_init_cpus(struct bnx2 *bp)
3466 /* Initialize the RV2P processor. */
3467 text = vmalloc(FW_BUF_SIZE);
3470 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3471 rv2p = bnx2_xi_rv2p_proc1;
3472 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3474 rv2p = bnx2_rv2p_proc1;
3475 rv2p_len = sizeof(bnx2_rv2p_proc1);
3477 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3481 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3483 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3484 rv2p = bnx2_xi_rv2p_proc2;
3485 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3487 rv2p = bnx2_rv2p_proc2;
3488 rv2p_len = sizeof(bnx2_rv2p_proc2);
3490 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3494 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3496 /* Initialize the RX Processor. */
3497 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3498 fw = &bnx2_rxp_fw_09;
3500 fw = &bnx2_rxp_fw_06;
3503 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3507 /* Initialize the TX Processor. */
3508 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3509 fw = &bnx2_txp_fw_09;
3511 fw = &bnx2_txp_fw_06;
3514 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3518 /* Initialize the TX Patch-up Processor. */
3519 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3520 fw = &bnx2_tpat_fw_09;
3522 fw = &bnx2_tpat_fw_06;
3525 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3529 /* Initialize the Completion Processor. */
3530 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3531 fw = &bnx2_com_fw_09;
3533 fw = &bnx2_com_fw_06;
3536 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3540 /* Initialize the Command Processor. */
3541 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3542 fw = &bnx2_cp_fw_09;
3544 fw = &bnx2_cp_fw_06;
3547 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3555 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3559 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3565 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3566 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3567 PCI_PM_CTRL_PME_STATUS);
3569 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3570 /* delay required during transition out of D3hot */
3573 val = REG_RD(bp, BNX2_EMAC_MODE);
3574 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3575 val &= ~BNX2_EMAC_MODE_MPKT;
3576 REG_WR(bp, BNX2_EMAC_MODE, val);
3578 val = REG_RD(bp, BNX2_RPM_CONFIG);
3579 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3580 REG_WR(bp, BNX2_RPM_CONFIG, val);
3591 autoneg = bp->autoneg;
3592 advertising = bp->advertising;
3594 if (bp->phy_port == PORT_TP) {
3595 bp->autoneg = AUTONEG_SPEED;
3596 bp->advertising = ADVERTISED_10baseT_Half |
3597 ADVERTISED_10baseT_Full |
3598 ADVERTISED_100baseT_Half |
3599 ADVERTISED_100baseT_Full |
3603 spin_lock_bh(&bp->phy_lock);
3604 bnx2_setup_phy(bp, bp->phy_port);
3605 spin_unlock_bh(&bp->phy_lock);
3607 bp->autoneg = autoneg;
3608 bp->advertising = advertising;
3610 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3612 val = REG_RD(bp, BNX2_EMAC_MODE);
3614 /* Enable port mode. */
3615 val &= ~BNX2_EMAC_MODE_PORT;
3616 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3617 BNX2_EMAC_MODE_ACPI_RCVD |
3618 BNX2_EMAC_MODE_MPKT;
3619 if (bp->phy_port == PORT_TP)
3620 val |= BNX2_EMAC_MODE_PORT_MII;
3622 val |= BNX2_EMAC_MODE_PORT_GMII;
3623 if (bp->line_speed == SPEED_2500)
3624 val |= BNX2_EMAC_MODE_25G_MODE;
3627 REG_WR(bp, BNX2_EMAC_MODE, val);
3629 /* receive all multicast */
3630 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3631 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3634 REG_WR(bp, BNX2_EMAC_RX_MODE,
3635 BNX2_EMAC_RX_MODE_SORT_MODE);
3637 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3638 BNX2_RPM_SORT_USER0_MC_EN;
3639 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3640 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3641 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3642 BNX2_RPM_SORT_USER0_ENA);
3644 /* Need to enable EMAC and RPM for WOL. */
3645 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3646 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3647 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3648 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3650 val = REG_RD(bp, BNX2_RPM_CONFIG);
3651 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3652 REG_WR(bp, BNX2_RPM_CONFIG, val);
3654 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3657 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3660 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3661 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3664 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3665 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3666 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3675 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3677 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3680 /* No more memory access after this point until
3681 * device is brought back to D0.
3693 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3698 /* Request access to the flash interface. */
3699 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3700 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3701 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3702 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3708 if (j >= NVRAM_TIMEOUT_COUNT)
3715 bnx2_release_nvram_lock(struct bnx2 *bp)
3720 /* Relinquish nvram interface. */
3721 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3723 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3724 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3725 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3731 if (j >= NVRAM_TIMEOUT_COUNT)
3739 bnx2_enable_nvram_write(struct bnx2 *bp)
3743 val = REG_RD(bp, BNX2_MISC_CFG);
3744 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3746 if (bp->flash_info->flags & BNX2_NV_WREN) {
3749 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3750 REG_WR(bp, BNX2_NVM_COMMAND,
3751 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3753 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3756 val = REG_RD(bp, BNX2_NVM_COMMAND);
3757 if (val & BNX2_NVM_COMMAND_DONE)
3761 if (j >= NVRAM_TIMEOUT_COUNT)
3768 bnx2_disable_nvram_write(struct bnx2 *bp)
3772 val = REG_RD(bp, BNX2_MISC_CFG);
3773 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3778 bnx2_enable_nvram_access(struct bnx2 *bp)
3782 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3783 /* Enable both bits, even on read. */
3784 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3785 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3789 bnx2_disable_nvram_access(struct bnx2 *bp)
3793 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3794 /* Disable both bits, even after read. */
3795 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3796 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3797 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3801 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3806 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3807 /* Buffered flash, no erase needed */
3810 /* Build an erase command */
3811 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3812 BNX2_NVM_COMMAND_DOIT;
3814 /* Need to clear DONE bit separately. */
3815 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3817 /* Address of the NVRAM to read from. */
3818 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3820 /* Issue an erase command. */
3821 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3823 /* Wait for completion. */
3824 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3829 val = REG_RD(bp, BNX2_NVM_COMMAND);
3830 if (val & BNX2_NVM_COMMAND_DONE)
3834 if (j >= NVRAM_TIMEOUT_COUNT)
3841 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3846 /* Build the command word. */
3847 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3849 /* Calculate an offset of a buffered flash, not needed for 5709. */
3850 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3851 offset = ((offset / bp->flash_info->page_size) <<
3852 bp->flash_info->page_bits) +
3853 (offset % bp->flash_info->page_size);
3856 /* Need to clear DONE bit separately. */
3857 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3859 /* Address of the NVRAM to read from. */
3860 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3862 /* Issue a read command. */
3863 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3865 /* Wait for completion. */
3866 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3871 val = REG_RD(bp, BNX2_NVM_COMMAND);
3872 if (val & BNX2_NVM_COMMAND_DONE) {
3873 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3874 memcpy(ret_val, &v, 4);
3878 if (j >= NVRAM_TIMEOUT_COUNT)
3886 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3892 /* Build the command word. */
3893 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3895 /* Calculate an offset of a buffered flash, not needed for 5709. */
3896 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3897 offset = ((offset / bp->flash_info->page_size) <<
3898 bp->flash_info->page_bits) +
3899 (offset % bp->flash_info->page_size);
3902 /* Need to clear DONE bit separately. */
3903 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3905 memcpy(&val32, val, 4);
3907 /* Write the data. */
3908 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3910 /* Address of the NVRAM to write to. */
3911 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3913 /* Issue the write command. */
3914 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3916 /* Wait for completion. */
3917 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3920 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3923 if (j >= NVRAM_TIMEOUT_COUNT)
3930 bnx2_init_nvram(struct bnx2 *bp)
3933 int j, entry_count, rc = 0;
3934 struct flash_spec *flash;
3936 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3937 bp->flash_info = &flash_5709;
3938 goto get_flash_size;
3941 /* Determine the selected interface. */
3942 val = REG_RD(bp, BNX2_NVM_CFG1);
3944 entry_count = ARRAY_SIZE(flash_table);
3946 if (val & 0x40000000) {
3948 /* Flash interface has been reconfigured */
3949 for (j = 0, flash = &flash_table[0]; j < entry_count;
3951 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3952 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3953 bp->flash_info = flash;
3960 /* Not yet been reconfigured */
3962 if (val & (1 << 23))
3963 mask = FLASH_BACKUP_STRAP_MASK;
3965 mask = FLASH_STRAP_MASK;
3967 for (j = 0, flash = &flash_table[0]; j < entry_count;
3970 if ((val & mask) == (flash->strapping & mask)) {
3971 bp->flash_info = flash;
3973 /* Request access to the flash interface. */
3974 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3977 /* Enable access to flash interface */
3978 bnx2_enable_nvram_access(bp);
3980 /* Reconfigure the flash interface */
3981 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3982 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3983 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3984 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3986 /* Disable access to flash interface */
3987 bnx2_disable_nvram_access(bp);
3988 bnx2_release_nvram_lock(bp);
3993 } /* if (val & 0x40000000) */
3995 if (j == entry_count) {
3996 bp->flash_info = NULL;
3997 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4002 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4003 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4005 bp->flash_size = val;
4007 bp->flash_size = bp->flash_info->total_size;
4013 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4017 u32 cmd_flags, offset32, len32, extra;
4022 /* Request access to the flash interface. */
4023 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4026 /* Enable access to flash interface */
4027 bnx2_enable_nvram_access(bp);
4040 pre_len = 4 - (offset & 3);
4042 if (pre_len >= len32) {
4044 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4045 BNX2_NVM_COMMAND_LAST;
4048 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4051 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4056 memcpy(ret_buf, buf + (offset & 3), pre_len);
4063 extra = 4 - (len32 & 3);
4064 len32 = (len32 + 4) & ~3;
4071 cmd_flags = BNX2_NVM_COMMAND_LAST;
4073 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4074 BNX2_NVM_COMMAND_LAST;
4076 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4078 memcpy(ret_buf, buf, 4 - extra);
4080 else if (len32 > 0) {
4083 /* Read the first word. */
4087 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4089 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4091 /* Advance to the next dword. */
4096 while (len32 > 4 && rc == 0) {
4097 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4099 /* Advance to the next dword. */
4108 cmd_flags = BNX2_NVM_COMMAND_LAST;
4109 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4111 memcpy(ret_buf, buf, 4 - extra);
4114 /* Disable access to flash interface */
4115 bnx2_disable_nvram_access(bp);
4117 bnx2_release_nvram_lock(bp);
4123 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4126 u32 written, offset32, len32;
4127 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4129 int align_start, align_end;
4134 align_start = align_end = 0;
4136 if ((align_start = (offset32 & 3))) {
4138 len32 += align_start;
4141 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4146 align_end = 4 - (len32 & 3);
4148 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4152 if (align_start || align_end) {
4153 align_buf = kmalloc(len32, GFP_KERNEL);
4154 if (align_buf == NULL)
4157 memcpy(align_buf, start, 4);
4160 memcpy(align_buf + len32 - 4, end, 4);
4162 memcpy(align_buf + align_start, data_buf, buf_size);
4166 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4167 flash_buffer = kmalloc(264, GFP_KERNEL);
4168 if (flash_buffer == NULL) {
4170 goto nvram_write_end;
4175 while ((written < len32) && (rc == 0)) {
4176 u32 page_start, page_end, data_start, data_end;
4177 u32 addr, cmd_flags;
4180 /* Find the page_start addr */
4181 page_start = offset32 + written;
4182 page_start -= (page_start % bp->flash_info->page_size);
4183 /* Find the page_end addr */
4184 page_end = page_start + bp->flash_info->page_size;
4185 /* Find the data_start addr */
4186 data_start = (written == 0) ? offset32 : page_start;
4187 /* Find the data_end addr */
4188 data_end = (page_end > offset32 + len32) ?
4189 (offset32 + len32) : page_end;
4191 /* Request access to the flash interface. */
4192 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4193 goto nvram_write_end;
4195 /* Enable access to flash interface */
4196 bnx2_enable_nvram_access(bp);
4198 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4199 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4202 /* Read the whole page into the buffer
4203 * (non-buffer flash only) */
4204 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4205 if (j == (bp->flash_info->page_size - 4)) {
4206 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4208 rc = bnx2_nvram_read_dword(bp,
4214 goto nvram_write_end;
4220 /* Enable writes to flash interface (unlock write-protect) */
4221 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4222 goto nvram_write_end;
4224 /* Loop to write back the buffer data from page_start to
4227 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4228 /* Erase the page */
4229 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4230 goto nvram_write_end;
4232 /* Re-enable the write again for the actual write */
4233 bnx2_enable_nvram_write(bp);
4235 for (addr = page_start; addr < data_start;
4236 addr += 4, i += 4) {
4238 rc = bnx2_nvram_write_dword(bp, addr,
4239 &flash_buffer[i], cmd_flags);
4242 goto nvram_write_end;
4248 /* Loop to write the new data from data_start to data_end */
4249 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4250 if ((addr == page_end - 4) ||
4251 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4252 (addr == data_end - 4))) {
4254 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4256 rc = bnx2_nvram_write_dword(bp, addr, buf,
4260 goto nvram_write_end;
4266 /* Loop to write back the buffer data from data_end
4268 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4269 for (addr = data_end; addr < page_end;
4270 addr += 4, i += 4) {
4272 if (addr == page_end-4) {
4273 cmd_flags = BNX2_NVM_COMMAND_LAST;
4275 rc = bnx2_nvram_write_dword(bp, addr,
4276 &flash_buffer[i], cmd_flags);
4279 goto nvram_write_end;
4285 /* Disable writes to flash interface (lock write-protect) */
4286 bnx2_disable_nvram_write(bp);
4288 /* Disable access to flash interface */
4289 bnx2_disable_nvram_access(bp);
4290 bnx2_release_nvram_lock(bp);
4292 /* Increment written */
4293 written += data_end - data_start;
4297 kfree(flash_buffer);
4303 bnx2_init_fw_cap(struct bnx2 *bp)
4307 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4308 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4310 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4311 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4313 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4314 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4317 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4318 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4319 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4322 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4323 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4326 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4328 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4329 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4330 bp->phy_port = PORT_FIBRE;
4332 bp->phy_port = PORT_TP;
4334 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4335 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4338 if (netif_running(bp->dev) && sig)
4339 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4343 bnx2_setup_msix_tbl(struct bnx2 *bp)
4345 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4347 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4348 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4352 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4358 /* Wait for the current PCI transaction to complete before
4359 * issuing a reset. */
4360 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4361 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4362 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4363 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4364 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4365 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4368 /* Wait for the firmware to tell us it is ok to issue a reset. */
4369 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4371 /* Deposit a driver reset signature so the firmware knows that
4372 * this is a soft reset. */
4373 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4374 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4376 /* Do a dummy read to force the chip to complete all current transaction
4377 * before we issue a reset. */
4378 val = REG_RD(bp, BNX2_MISC_ID);
4380 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4381 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4382 REG_RD(bp, BNX2_MISC_COMMAND);
4385 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4386 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4388 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4391 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4392 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4393 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4396 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4398 /* Reading back any register after chip reset will hang the
4399 * bus on 5706 A0 and A1. The msleep below provides plenty
4400 * of margin for write posting.
4402 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4403 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4406 /* Reset takes approximate 30 usec */
4407 for (i = 0; i < 10; i++) {
4408 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4409 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4410 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4415 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4416 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4417 printk(KERN_ERR PFX "Chip reset did not complete\n");
4422 /* Make sure byte swapping is properly configured. */
4423 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4424 if (val != 0x01020304) {
4425 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4429 /* Wait for the firmware to finish its initialization. */
4430 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4434 spin_lock_bh(&bp->phy_lock);
4435 old_port = bp->phy_port;
4436 bnx2_init_fw_cap(bp);
4437 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4438 old_port != bp->phy_port)
4439 bnx2_set_default_remote_link(bp);
4440 spin_unlock_bh(&bp->phy_lock);
4442 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4443 /* Adjust the voltage regular to two steps lower. The default
4444 * of this register is 0x0000000e. */
4445 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4447 /* Remove bad rbuf memory from the free pool. */
4448 rc = bnx2_alloc_bad_rbuf(bp);
4451 if (bp->flags & BNX2_FLAG_USING_MSIX)
4452 bnx2_setup_msix_tbl(bp);
4458 bnx2_init_chip(struct bnx2 *bp)
4463 /* Make sure the interrupt is not active. */
4464 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4466 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4467 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4469 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4471 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4472 DMA_READ_CHANS << 12 |
4473 DMA_WRITE_CHANS << 16;
4475 val |= (0x2 << 20) | (1 << 11);
4477 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4480 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4481 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4482 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4484 REG_WR(bp, BNX2_DMA_CONFIG, val);
4486 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4487 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4488 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4489 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4492 if (bp->flags & BNX2_FLAG_PCIX) {
4495 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4497 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4498 val16 & ~PCI_X_CMD_ERO);
4501 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4502 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4503 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4504 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4506 /* Initialize context mapping and zero out the quick contexts. The
4507 * context block must have already been enabled. */
4508 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4509 rc = bnx2_init_5709_context(bp);
4513 bnx2_init_context(bp);
4515 if ((rc = bnx2_init_cpus(bp)) != 0)
4518 bnx2_init_nvram(bp);
4520 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4522 val = REG_RD(bp, BNX2_MQ_CONFIG);
4523 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4524 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4525 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4526 val |= BNX2_MQ_CONFIG_HALT_DIS;
4528 REG_WR(bp, BNX2_MQ_CONFIG, val);
4530 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4531 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4532 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4534 val = (BCM_PAGE_BITS - 8) << 24;
4535 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4537 /* Configure page size. */
4538 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4539 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4540 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4541 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4543 val = bp->mac_addr[0] +
4544 (bp->mac_addr[1] << 8) +
4545 (bp->mac_addr[2] << 16) +
4547 (bp->mac_addr[4] << 8) +
4548 (bp->mac_addr[5] << 16);
4549 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4551 /* Program the MTU. Also include 4 bytes for CRC32. */
4552 val = bp->dev->mtu + ETH_HLEN + 4;
4553 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4554 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4555 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4557 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4558 bp->bnx2_napi[i].last_status_idx = 0;
4560 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4562 /* Set up how to generate a link change interrupt. */
4563 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4565 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4566 (u64) bp->status_blk_mapping & 0xffffffff);
4567 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4569 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4570 (u64) bp->stats_blk_mapping & 0xffffffff);
4571 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4572 (u64) bp->stats_blk_mapping >> 32);
4574 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4575 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4577 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4578 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4580 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4581 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4583 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4585 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4587 REG_WR(bp, BNX2_HC_COM_TICKS,
4588 (bp->com_ticks_int << 16) | bp->com_ticks);
4590 REG_WR(bp, BNX2_HC_CMD_TICKS,
4591 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4593 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4594 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4596 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4597 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4599 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4600 val = BNX2_HC_CONFIG_COLLECT_STATS;
4602 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4603 BNX2_HC_CONFIG_COLLECT_STATS;
4606 if (bp->irq_nvecs > 1) {
4607 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4608 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4610 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4613 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4614 val |= BNX2_HC_CONFIG_ONE_SHOT;
4616 REG_WR(bp, BNX2_HC_CONFIG, val);
4618 for (i = 1; i < bp->irq_nvecs; i++) {
4619 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4620 BNX2_HC_SB_CONFIG_1;
4623 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4624 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4625 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4627 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4628 (bp->tx_quick_cons_trip_int << 16) |
4629 bp->tx_quick_cons_trip);
4631 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4632 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4634 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4635 (bp->rx_quick_cons_trip_int << 16) |
4636 bp->rx_quick_cons_trip);
4638 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4639 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4642 /* Clear internal stats counters. */
4643 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4645 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4647 /* Initialize the receive filter. */
4648 bnx2_set_rx_mode(bp->dev);
4650 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4651 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4652 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4653 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4655 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4658 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4659 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4663 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4669 bnx2_clear_ring_states(struct bnx2 *bp)
4671 struct bnx2_napi *bnapi;
4672 struct bnx2_tx_ring_info *txr;
4673 struct bnx2_rx_ring_info *rxr;
4676 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4677 bnapi = &bp->bnx2_napi[i];
4678 txr = &bnapi->tx_ring;
4679 rxr = &bnapi->rx_ring;
4682 txr->hw_tx_cons = 0;
4683 rxr->rx_prod_bseq = 0;
4686 rxr->rx_pg_prod = 0;
4687 rxr->rx_pg_cons = 0;
4692 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4694 u32 val, offset0, offset1, offset2, offset3;
4695 u32 cid_addr = GET_CID_ADDR(cid);
4697 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4698 offset0 = BNX2_L2CTX_TYPE_XI;
4699 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4700 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4701 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4703 offset0 = BNX2_L2CTX_TYPE;
4704 offset1 = BNX2_L2CTX_CMD_TYPE;
4705 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4706 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4708 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4709 bnx2_ctx_wr(bp, cid_addr, offset0, val);
4711 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4712 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4714 val = (u64) txr->tx_desc_mapping >> 32;
4715 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4717 val = (u64) txr->tx_desc_mapping & 0xffffffff;
4718 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4722 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4726 struct bnx2_napi *bnapi;
4727 struct bnx2_tx_ring_info *txr;
4729 bnapi = &bp->bnx2_napi[ring_num];
4730 txr = &bnapi->tx_ring;
4735 cid = TX_TSS_CID + ring_num - 1;
4737 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4739 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4741 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4742 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4745 txr->tx_prod_bseq = 0;
4747 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4748 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4750 bnx2_init_tx_context(bp, cid, txr);
4754 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4760 for (i = 0; i < num_rings; i++) {
4763 rxbd = &rx_ring[i][0];
4764 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4765 rxbd->rx_bd_len = buf_size;
4766 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4768 if (i == (num_rings - 1))
4772 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4773 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4778 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4781 u16 prod, ring_prod;
4782 u32 cid, rx_cid_addr, val;
4783 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4784 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4789 cid = RX_RSS_CID + ring_num - 1;
4791 rx_cid_addr = GET_CID_ADDR(cid);
4793 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4794 bp->rx_buf_use_size, bp->rx_max_ring);
4796 bnx2_init_rx_context(bp, cid);
4798 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4799 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4800 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4803 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4804 if (bp->rx_pg_ring_size) {
4805 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4806 rxr->rx_pg_desc_mapping,
4807 PAGE_SIZE, bp->rx_max_pg_ring);
4808 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4809 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4810 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4811 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4813 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4814 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4816 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4817 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4819 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4820 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4823 val = (u64) rxr->rx_desc_mapping[0] >> 32;
4824 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4826 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4827 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4829 ring_prod = prod = rxr->rx_pg_prod;
4830 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4831 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4833 prod = NEXT_RX_BD(prod);
4834 ring_prod = RX_PG_RING_IDX(prod);
4836 rxr->rx_pg_prod = prod;
4838 ring_prod = prod = rxr->rx_prod;
4839 for (i = 0; i < bp->rx_ring_size; i++) {
4840 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4842 prod = NEXT_RX_BD(prod);
4843 ring_prod = RX_RING_IDX(prod);
4845 rxr->rx_prod = prod;
4847 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4848 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4849 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4851 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4852 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4854 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4858 bnx2_init_all_rings(struct bnx2 *bp)
4863 bnx2_clear_ring_states(bp);
4865 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4866 for (i = 0; i < bp->num_tx_rings; i++)
4867 bnx2_init_tx_ring(bp, i);
4869 if (bp->num_tx_rings > 1)
4870 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4873 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4874 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4876 for (i = 0; i < bp->num_rx_rings; i++)
4877 bnx2_init_rx_ring(bp, i);
4879 if (bp->num_rx_rings > 1) {
4881 u8 *tbl = (u8 *) &tbl_32;
4883 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4884 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4886 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4887 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4890 BNX2_RXP_SCRATCH_RSS_TBL + i,
4891 cpu_to_be32(tbl_32));
4894 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4895 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4897 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4902 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4904 u32 max, num_rings = 1;
4906 while (ring_size > MAX_RX_DESC_CNT) {
4907 ring_size -= MAX_RX_DESC_CNT;
4910 /* round to next power of 2 */
4912 while ((max & num_rings) == 0)
4915 if (num_rings != max)
4922 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4924 u32 rx_size, rx_space, jumbo_size;
4926 /* 8 for CRC and VLAN */
4927 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4929 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4930 sizeof(struct skb_shared_info);
4932 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4933 bp->rx_pg_ring_size = 0;
4934 bp->rx_max_pg_ring = 0;
4935 bp->rx_max_pg_ring_idx = 0;
4936 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4937 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4939 jumbo_size = size * pages;
4940 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4941 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4943 bp->rx_pg_ring_size = jumbo_size;
4944 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4946 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4947 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4948 bp->rx_copy_thresh = 0;
4951 bp->rx_buf_use_size = rx_size;
4953 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4954 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4955 bp->rx_ring_size = size;
4956 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4957 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4961 bnx2_free_tx_skbs(struct bnx2 *bp)
4965 for (i = 0; i < bp->num_tx_rings; i++) {
4966 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4967 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4970 if (txr->tx_buf_ring == NULL)
4973 for (j = 0; j < TX_DESC_CNT; ) {
4974 struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
4975 struct sk_buff *skb = tx_buf->skb;
4983 pci_unmap_single(bp->pdev,
4984 pci_unmap_addr(tx_buf, mapping),
4985 skb_headlen(skb), PCI_DMA_TODEVICE);
4989 last = skb_shinfo(skb)->nr_frags;
4990 for (k = 0; k < last; k++) {
4991 tx_buf = &txr->tx_buf_ring[j + k + 1];
4992 pci_unmap_page(bp->pdev,
4993 pci_unmap_addr(tx_buf, mapping),
4994 skb_shinfo(skb)->frags[j].size,
5004 bnx2_free_rx_skbs(struct bnx2 *bp)
5008 for (i = 0; i < bp->num_rx_rings; i++) {
5009 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5010 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5013 if (rxr->rx_buf_ring == NULL)
5016 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5017 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5018 struct sk_buff *skb = rx_buf->skb;
5023 pci_unmap_single(bp->pdev,
5024 pci_unmap_addr(rx_buf, mapping),
5025 bp->rx_buf_use_size,
5026 PCI_DMA_FROMDEVICE);
5032 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5033 bnx2_free_rx_page(bp, rxr, j);
5038 bnx2_free_skbs(struct bnx2 *bp)
5040 bnx2_free_tx_skbs(bp);
5041 bnx2_free_rx_skbs(bp);
5045 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5049 rc = bnx2_reset_chip(bp, reset_code);
5054 if ((rc = bnx2_init_chip(bp)) != 0)
5057 bnx2_init_all_rings(bp);
5062 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5066 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5069 spin_lock_bh(&bp->phy_lock);
5070 bnx2_init_phy(bp, reset_phy);
5072 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5073 bnx2_remote_phy_event(bp);
5074 spin_unlock_bh(&bp->phy_lock);
5079 bnx2_shutdown_chip(struct bnx2 *bp)
5083 if (bp->flags & BNX2_FLAG_NO_WOL)
5084 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5086 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5088 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5090 return bnx2_reset_chip(bp, reset_code);
5094 bnx2_test_registers(struct bnx2 *bp)
5098 static const struct {
5101 #define BNX2_FL_NOT_5709 1
5105 { 0x006c, 0, 0x00000000, 0x0000003f },
5106 { 0x0090, 0, 0xffffffff, 0x00000000 },
5107 { 0x0094, 0, 0x00000000, 0x00000000 },
5109 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5110 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5111 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5112 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5113 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5114 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5115 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5116 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5117 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5119 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5120 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5121 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5122 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5123 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5124 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5126 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5127 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5128 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5130 { 0x1000, 0, 0x00000000, 0x00000001 },
5131 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5133 { 0x1408, 0, 0x01c00800, 0x00000000 },
5134 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5135 { 0x14a8, 0, 0x00000000, 0x000001ff },
5136 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5137 { 0x14b0, 0, 0x00000002, 0x00000001 },
5138 { 0x14b8, 0, 0x00000000, 0x00000000 },
5139 { 0x14c0, 0, 0x00000000, 0x00000009 },
5140 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5141 { 0x14cc, 0, 0x00000000, 0x00000001 },
5142 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5144 { 0x1800, 0, 0x00000000, 0x00000001 },
5145 { 0x1804, 0, 0x00000000, 0x00000003 },
5147 { 0x2800, 0, 0x00000000, 0x00000001 },
5148 { 0x2804, 0, 0x00000000, 0x00003f01 },
5149 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5150 { 0x2810, 0, 0xffff0000, 0x00000000 },
5151 { 0x2814, 0, 0xffff0000, 0x00000000 },
5152 { 0x2818, 0, 0xffff0000, 0x00000000 },
5153 { 0x281c, 0, 0xffff0000, 0x00000000 },
5154 { 0x2834, 0, 0xffffffff, 0x00000000 },
5155 { 0x2840, 0, 0x00000000, 0xffffffff },
5156 { 0x2844, 0, 0x00000000, 0xffffffff },
5157 { 0x2848, 0, 0xffffffff, 0x00000000 },
5158 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5160 { 0x2c00, 0, 0x00000000, 0x00000011 },
5161 { 0x2c04, 0, 0x00000000, 0x00030007 },
5163 { 0x3c00, 0, 0x00000000, 0x00000001 },
5164 { 0x3c04, 0, 0x00000000, 0x00070000 },
5165 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5166 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5167 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5168 { 0x3c14, 0, 0x00000000, 0xffffffff },
5169 { 0x3c18, 0, 0x00000000, 0xffffffff },
5170 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5171 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5173 { 0x5004, 0, 0x00000000, 0x0000007f },
5174 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5176 { 0x5c00, 0, 0x00000000, 0x00000001 },
5177 { 0x5c04, 0, 0x00000000, 0x0003000f },
5178 { 0x5c08, 0, 0x00000003, 0x00000000 },
5179 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5180 { 0x5c10, 0, 0x00000000, 0xffffffff },
5181 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5182 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5183 { 0x5c88, 0, 0x00000000, 0x00077373 },
5184 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5186 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5187 { 0x680c, 0, 0xffffffff, 0x00000000 },
5188 { 0x6810, 0, 0xffffffff, 0x00000000 },
5189 { 0x6814, 0, 0xffffffff, 0x00000000 },
5190 { 0x6818, 0, 0xffffffff, 0x00000000 },
5191 { 0x681c, 0, 0xffffffff, 0x00000000 },
5192 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5193 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5194 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5195 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5196 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5197 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5198 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5199 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5200 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5201 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5202 { 0x684c, 0, 0xffffffff, 0x00000000 },
5203 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5204 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5205 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5206 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5207 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5208 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5210 { 0xffff, 0, 0x00000000, 0x00000000 },
5215 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5218 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5219 u32 offset, rw_mask, ro_mask, save_val, val;
5220 u16 flags = reg_tbl[i].flags;
5222 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5225 offset = (u32) reg_tbl[i].offset;
5226 rw_mask = reg_tbl[i].rw_mask;
5227 ro_mask = reg_tbl[i].ro_mask;
5229 save_val = readl(bp->regview + offset);
5231 writel(0, bp->regview + offset);
5233 val = readl(bp->regview + offset);
5234 if ((val & rw_mask) != 0) {
5238 if ((val & ro_mask) != (save_val & ro_mask)) {
5242 writel(0xffffffff, bp->regview + offset);
5244 val = readl(bp->regview + offset);
5245 if ((val & rw_mask) != rw_mask) {
5249 if ((val & ro_mask) != (save_val & ro_mask)) {
5253 writel(save_val, bp->regview + offset);
5257 writel(save_val, bp->regview + offset);
5265 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5267 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5268 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5271 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5274 for (offset = 0; offset < size; offset += 4) {
5276 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5278 if (bnx2_reg_rd_ind(bp, start + offset) !=
5288 bnx2_test_memory(struct bnx2 *bp)
5292 static struct mem_entry {
5295 } mem_tbl_5706[] = {
5296 { 0x60000, 0x4000 },
5297 { 0xa0000, 0x3000 },
5298 { 0xe0000, 0x4000 },
5299 { 0x120000, 0x4000 },
5300 { 0x1a0000, 0x4000 },
5301 { 0x160000, 0x4000 },
5305 { 0x60000, 0x4000 },
5306 { 0xa0000, 0x3000 },
5307 { 0xe0000, 0x4000 },
5308 { 0x120000, 0x4000 },
5309 { 0x1a0000, 0x4000 },
5312 struct mem_entry *mem_tbl;
5314 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5315 mem_tbl = mem_tbl_5709;
5317 mem_tbl = mem_tbl_5706;
5319 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5320 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5321 mem_tbl[i].len)) != 0) {
5329 #define BNX2_MAC_LOOPBACK 0
5330 #define BNX2_PHY_LOOPBACK 1
5333 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5335 unsigned int pkt_size, num_pkts, i;
5336 struct sk_buff *skb, *rx_skb;
5337 unsigned char *packet;
5338 u16 rx_start_idx, rx_idx;
5341 struct sw_bd *rx_buf;
5342 struct l2_fhdr *rx_hdr;
5344 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5345 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5346 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5350 txr = &tx_napi->tx_ring;
5351 rxr = &bnapi->rx_ring;
5352 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5353 bp->loopback = MAC_LOOPBACK;
5354 bnx2_set_mac_loopback(bp);
5356 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5357 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5360 bp->loopback = PHY_LOOPBACK;
5361 bnx2_set_phy_loopback(bp);
5366 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5367 skb = netdev_alloc_skb(bp->dev, pkt_size);
5370 packet = skb_put(skb, pkt_size);
5371 memcpy(packet, bp->dev->dev_addr, 6);
5372 memset(packet + 6, 0x0, 8);
5373 for (i = 14; i < pkt_size; i++)
5374 packet[i] = (unsigned char) (i & 0xff);
5376 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5379 REG_WR(bp, BNX2_HC_COMMAND,
5380 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5382 REG_RD(bp, BNX2_HC_COMMAND);
5385 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5389 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5391 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5392 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5393 txbd->tx_bd_mss_nbytes = pkt_size;
5394 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5397 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5398 txr->tx_prod_bseq += pkt_size;
5400 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5401 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5405 REG_WR(bp, BNX2_HC_COMMAND,
5406 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5408 REG_RD(bp, BNX2_HC_COMMAND);
5412 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5415 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5416 goto loopback_test_done;
5418 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5419 if (rx_idx != rx_start_idx + num_pkts) {
5420 goto loopback_test_done;
5423 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5424 rx_skb = rx_buf->skb;
5426 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5427 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5429 pci_dma_sync_single_for_cpu(bp->pdev,
5430 pci_unmap_addr(rx_buf, mapping),
5431 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5433 if (rx_hdr->l2_fhdr_status &
5434 (L2_FHDR_ERRORS_BAD_CRC |
5435 L2_FHDR_ERRORS_PHY_DECODE |
5436 L2_FHDR_ERRORS_ALIGNMENT |
5437 L2_FHDR_ERRORS_TOO_SHORT |
5438 L2_FHDR_ERRORS_GIANT_FRAME)) {
5440 goto loopback_test_done;
5443 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5444 goto loopback_test_done;
5447 for (i = 14; i < pkt_size; i++) {
5448 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5449 goto loopback_test_done;
5460 #define BNX2_MAC_LOOPBACK_FAILED 1
5461 #define BNX2_PHY_LOOPBACK_FAILED 2
5462 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5463 BNX2_PHY_LOOPBACK_FAILED)
5466 bnx2_test_loopback(struct bnx2 *bp)
5470 if (!netif_running(bp->dev))
5471 return BNX2_LOOPBACK_FAILED;
5473 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5474 spin_lock_bh(&bp->phy_lock);
5475 bnx2_init_phy(bp, 1);
5476 spin_unlock_bh(&bp->phy_lock);
5477 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5478 rc |= BNX2_MAC_LOOPBACK_FAILED;
5479 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5480 rc |= BNX2_PHY_LOOPBACK_FAILED;
5484 #define NVRAM_SIZE 0x200
5485 #define CRC32_RESIDUAL 0xdebb20e3
5488 bnx2_test_nvram(struct bnx2 *bp)
5490 __be32 buf[NVRAM_SIZE / 4];
5491 u8 *data = (u8 *) buf;
5495 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5496 goto test_nvram_done;
5498 magic = be32_to_cpu(buf[0]);
5499 if (magic != 0x669955aa) {
5501 goto test_nvram_done;
5504 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5505 goto test_nvram_done;
5507 csum = ether_crc_le(0x100, data);
5508 if (csum != CRC32_RESIDUAL) {
5510 goto test_nvram_done;
5513 csum = ether_crc_le(0x100, data + 0x100);
5514 if (csum != CRC32_RESIDUAL) {
5523 bnx2_test_link(struct bnx2 *bp)
5527 if (!netif_running(bp->dev))
5530 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5535 spin_lock_bh(&bp->phy_lock);
5536 bnx2_enable_bmsr1(bp);
5537 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5538 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5539 bnx2_disable_bmsr1(bp);
5540 spin_unlock_bh(&bp->phy_lock);
5542 if (bmsr & BMSR_LSTATUS) {
5549 bnx2_test_intr(struct bnx2 *bp)
5554 if (!netif_running(bp->dev))
5557 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5559 /* This register is not touched during run-time. */
5560 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5561 REG_RD(bp, BNX2_HC_COMMAND);
5563 for (i = 0; i < 10; i++) {
5564 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5570 msleep_interruptible(10);
5578 /* Determining link for parallel detection. */
5580 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5582 u32 mode_ctl, an_dbg, exp;
5584 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5587 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5588 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5590 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5593 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5594 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5595 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5597 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5600 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5601 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5602 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5604 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5611 bnx2_5706_serdes_timer(struct bnx2 *bp)
5615 spin_lock(&bp->phy_lock);
5616 if (bp->serdes_an_pending) {
5617 bp->serdes_an_pending--;
5619 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5622 bp->current_interval = BNX2_TIMER_INTERVAL;
5624 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5626 if (bmcr & BMCR_ANENABLE) {
5627 if (bnx2_5706_serdes_has_link(bp)) {
5628 bmcr &= ~BMCR_ANENABLE;
5629 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5630 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5631 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5635 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5636 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5639 bnx2_write_phy(bp, 0x17, 0x0f01);
5640 bnx2_read_phy(bp, 0x15, &phy2);
5644 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5645 bmcr |= BMCR_ANENABLE;
5646 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5648 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5651 bp->current_interval = BNX2_TIMER_INTERVAL;
5656 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5657 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5658 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5660 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5661 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5662 bnx2_5706s_force_link_dn(bp, 1);
5663 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5666 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5669 spin_unlock(&bp->phy_lock);
5673 bnx2_5708_serdes_timer(struct bnx2 *bp)
5675 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5678 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5679 bp->serdes_an_pending = 0;
5683 spin_lock(&bp->phy_lock);
5684 if (bp->serdes_an_pending)
5685 bp->serdes_an_pending--;
5686 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5689 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5690 if (bmcr & BMCR_ANENABLE) {
5691 bnx2_enable_forced_2g5(bp);
5692 bp->current_interval = SERDES_FORCED_TIMEOUT;
5694 bnx2_disable_forced_2g5(bp);
5695 bp->serdes_an_pending = 2;
5696 bp->current_interval = BNX2_TIMER_INTERVAL;
5700 bp->current_interval = BNX2_TIMER_INTERVAL;
5702 spin_unlock(&bp->phy_lock);
5706 bnx2_timer(unsigned long data)
5708 struct bnx2 *bp = (struct bnx2 *) data;
5710 if (!netif_running(bp->dev))
5713 if (atomic_read(&bp->intr_sem) != 0)
5714 goto bnx2_restart_timer;
5716 bnx2_send_heart_beat(bp);
5718 bp->stats_blk->stat_FwRxDrop =
5719 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5721 /* workaround occasional corrupted counters */
5722 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5723 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5724 BNX2_HC_COMMAND_STATS_NOW);
5726 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5727 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5728 bnx2_5706_serdes_timer(bp);
5730 bnx2_5708_serdes_timer(bp);
5734 mod_timer(&bp->timer, jiffies + bp->current_interval);
5738 bnx2_request_irq(struct bnx2 *bp)
5740 unsigned long flags;
5741 struct bnx2_irq *irq;
5744 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5747 flags = IRQF_SHARED;
5749 for (i = 0; i < bp->irq_nvecs; i++) {
5750 irq = &bp->irq_tbl[i];
5751 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5761 bnx2_free_irq(struct bnx2 *bp)
5763 struct bnx2_irq *irq;
5766 for (i = 0; i < bp->irq_nvecs; i++) {
5767 irq = &bp->irq_tbl[i];
5769 free_irq(irq->vector, &bp->bnx2_napi[i]);
5772 if (bp->flags & BNX2_FLAG_USING_MSI)
5773 pci_disable_msi(bp->pdev);
5774 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5775 pci_disable_msix(bp->pdev);
5777 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5781 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5784 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5786 bnx2_setup_msix_tbl(bp);
5787 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5788 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5789 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5791 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5792 msix_ent[i].entry = i;
5793 msix_ent[i].vector = 0;
5795 strcpy(bp->irq_tbl[i].name, bp->dev->name);
5796 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5799 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5803 bp->irq_nvecs = msix_vecs;
5804 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5805 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5806 bp->irq_tbl[i].vector = msix_ent[i].vector;
5810 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5812 int cpus = num_online_cpus();
5813 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5815 bp->irq_tbl[0].handler = bnx2_interrupt;
5816 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5818 bp->irq_tbl[0].vector = bp->pdev->irq;
5820 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5821 bnx2_enable_msix(bp, msix_vecs);
5823 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5824 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5825 if (pci_enable_msi(bp->pdev) == 0) {
5826 bp->flags |= BNX2_FLAG_USING_MSI;
5827 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5828 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5829 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5831 bp->irq_tbl[0].handler = bnx2_msi;
5833 bp->irq_tbl[0].vector = bp->pdev->irq;
5837 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5838 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5840 bp->num_rx_rings = bp->irq_nvecs;
5843 /* Called with rtnl_lock */
5845 bnx2_open(struct net_device *dev)
5847 struct bnx2 *bp = netdev_priv(dev);
5850 netif_carrier_off(dev);
5852 bnx2_set_power_state(bp, PCI_D0);
5853 bnx2_disable_int(bp);
5855 bnx2_setup_int_mode(bp, disable_msi);
5856 bnx2_napi_enable(bp);
5857 rc = bnx2_alloc_mem(bp);
5861 rc = bnx2_request_irq(bp);
5865 rc = bnx2_init_nic(bp, 1);
5869 mod_timer(&bp->timer, jiffies + bp->current_interval);
5871 atomic_set(&bp->intr_sem, 0);
5873 bnx2_enable_int(bp);
5875 if (bp->flags & BNX2_FLAG_USING_MSI) {
5876 /* Test MSI to make sure it is working
5877 * If MSI test fails, go back to INTx mode
5879 if (bnx2_test_intr(bp) != 0) {
5880 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5881 " using MSI, switching to INTx mode. Please"
5882 " report this failure to the PCI maintainer"
5883 " and include system chipset information.\n",
5886 bnx2_disable_int(bp);
5889 bnx2_setup_int_mode(bp, 1);
5891 rc = bnx2_init_nic(bp, 0);
5894 rc = bnx2_request_irq(bp);
5897 del_timer_sync(&bp->timer);
5900 bnx2_enable_int(bp);
5903 if (bp->flags & BNX2_FLAG_USING_MSI)
5904 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5905 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5906 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5908 netif_tx_start_all_queues(dev);
5913 bnx2_napi_disable(bp);
5921 bnx2_reset_task(struct work_struct *work)
5923 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5925 if (!netif_running(bp->dev))
5928 bnx2_netif_stop(bp);
5930 bnx2_init_nic(bp, 1);
5932 atomic_set(&bp->intr_sem, 1);
5933 bnx2_netif_start(bp);
5937 bnx2_tx_timeout(struct net_device *dev)
5939 struct bnx2 *bp = netdev_priv(dev);
5941 /* This allows the netif to be shutdown gracefully before resetting */
5942 schedule_work(&bp->reset_task);
5946 /* Called with rtnl_lock */
5948 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5950 struct bnx2 *bp = netdev_priv(dev);
5952 bnx2_netif_stop(bp);
5955 bnx2_set_rx_mode(dev);
5956 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5957 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
5959 bnx2_netif_start(bp);
5963 /* Called with netif_tx_lock.
5964 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5965 * netif_wake_queue().
5968 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5970 struct bnx2 *bp = netdev_priv(dev);
5973 struct sw_bd *tx_buf;
5974 u32 len, vlan_tag_flags, last_frag, mss;
5975 u16 prod, ring_prod;
5977 struct bnx2_napi *bnapi;
5978 struct bnx2_tx_ring_info *txr;
5979 struct netdev_queue *txq;
5981 /* Determine which tx ring we will be placed on */
5982 i = skb_get_queue_mapping(skb);
5983 bnapi = &bp->bnx2_napi[i];
5984 txr = &bnapi->tx_ring;
5985 txq = netdev_get_tx_queue(dev, i);
5987 if (unlikely(bnx2_tx_avail(bp, txr) <
5988 (skb_shinfo(skb)->nr_frags + 1))) {
5989 netif_tx_stop_queue(txq);
5990 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5993 return NETDEV_TX_BUSY;
5995 len = skb_headlen(skb);
5996 prod = txr->tx_prod;
5997 ring_prod = TX_RING_IDX(prod);
6000 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6001 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6005 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6007 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6010 if ((mss = skb_shinfo(skb)->gso_size)) {
6014 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6016 tcp_opt_len = tcp_optlen(skb);
6018 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6019 u32 tcp_off = skb_transport_offset(skb) -
6020 sizeof(struct ipv6hdr) - ETH_HLEN;
6022 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6023 TX_BD_FLAGS_SW_FLAGS;
6024 if (likely(tcp_off == 0))
6025 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6028 vlan_tag_flags |= ((tcp_off & 0x3) <<
6029 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6030 ((tcp_off & 0x10) <<
6031 TX_BD_FLAGS_TCP6_OFF4_SHL);
6032 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6036 if (tcp_opt_len || (iph->ihl > 5)) {
6037 vlan_tag_flags |= ((iph->ihl - 5) +
6038 (tcp_opt_len >> 2)) << 8;
6044 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6046 tx_buf = &txr->tx_buf_ring[ring_prod];
6048 pci_unmap_addr_set(tx_buf, mapping, mapping);
6050 txbd = &txr->tx_desc_ring[ring_prod];
6052 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6053 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6054 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6055 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6057 last_frag = skb_shinfo(skb)->nr_frags;
6059 for (i = 0; i < last_frag; i++) {
6060 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6062 prod = NEXT_TX_BD(prod);
6063 ring_prod = TX_RING_IDX(prod);
6064 txbd = &txr->tx_desc_ring[ring_prod];
6067 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6068 len, PCI_DMA_TODEVICE);
6069 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
6072 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6073 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6074 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6075 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6078 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6080 prod = NEXT_TX_BD(prod);
6081 txr->tx_prod_bseq += skb->len;
6083 REG_WR16(bp, txr->tx_bidx_addr, prod);
6084 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6088 txr->tx_prod = prod;
6089 dev->trans_start = jiffies;
6091 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6092 netif_tx_stop_queue(txq);
6093 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6094 netif_tx_wake_queue(txq);
6097 return NETDEV_TX_OK;
6100 /* Called with rtnl_lock */
6102 bnx2_close(struct net_device *dev)
6104 struct bnx2 *bp = netdev_priv(dev);
6106 cancel_work_sync(&bp->reset_task);
6108 bnx2_disable_int_sync(bp);
6109 bnx2_napi_disable(bp);
6110 del_timer_sync(&bp->timer);
6111 bnx2_shutdown_chip(bp);
6116 netif_carrier_off(bp->dev);
6117 bnx2_set_power_state(bp, PCI_D3hot);
6121 #define GET_NET_STATS64(ctr) \
6122 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6123 (unsigned long) (ctr##_lo)
6125 #define GET_NET_STATS32(ctr) \
6128 #if (BITS_PER_LONG == 64)
6129 #define GET_NET_STATS GET_NET_STATS64
6131 #define GET_NET_STATS GET_NET_STATS32
6134 static struct net_device_stats *
6135 bnx2_get_stats(struct net_device *dev)
6137 struct bnx2 *bp = netdev_priv(dev);
6138 struct statistics_block *stats_blk = bp->stats_blk;
6139 struct net_device_stats *net_stats = &bp->net_stats;
6141 if (bp->stats_blk == NULL) {
6144 net_stats->rx_packets =
6145 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6146 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6147 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6149 net_stats->tx_packets =
6150 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6151 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6152 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6154 net_stats->rx_bytes =
6155 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6157 net_stats->tx_bytes =
6158 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6160 net_stats->multicast =
6161 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6163 net_stats->collisions =
6164 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6166 net_stats->rx_length_errors =
6167 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6168 stats_blk->stat_EtherStatsOverrsizePkts);
6170 net_stats->rx_over_errors =
6171 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6173 net_stats->rx_frame_errors =
6174 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6176 net_stats->rx_crc_errors =
6177 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6179 net_stats->rx_errors = net_stats->rx_length_errors +
6180 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6181 net_stats->rx_crc_errors;
6183 net_stats->tx_aborted_errors =
6184 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6185 stats_blk->stat_Dot3StatsLateCollisions);
6187 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6188 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6189 net_stats->tx_carrier_errors = 0;
6191 net_stats->tx_carrier_errors =
6193 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6196 net_stats->tx_errors =
6198 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6200 net_stats->tx_aborted_errors +
6201 net_stats->tx_carrier_errors;
6203 net_stats->rx_missed_errors =
6204 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6205 stats_blk->stat_FwRxDrop);
6210 /* All ethtool functions called with rtnl_lock */
6213 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6215 struct bnx2 *bp = netdev_priv(dev);
6216 int support_serdes = 0, support_copper = 0;
6218 cmd->supported = SUPPORTED_Autoneg;
6219 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6222 } else if (bp->phy_port == PORT_FIBRE)
6227 if (support_serdes) {
6228 cmd->supported |= SUPPORTED_1000baseT_Full |
6230 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6231 cmd->supported |= SUPPORTED_2500baseX_Full;
6234 if (support_copper) {
6235 cmd->supported |= SUPPORTED_10baseT_Half |
6236 SUPPORTED_10baseT_Full |
6237 SUPPORTED_100baseT_Half |
6238 SUPPORTED_100baseT_Full |
6239 SUPPORTED_1000baseT_Full |
6244 spin_lock_bh(&bp->phy_lock);
6245 cmd->port = bp->phy_port;
6246 cmd->advertising = bp->advertising;
6248 if (bp->autoneg & AUTONEG_SPEED) {
6249 cmd->autoneg = AUTONEG_ENABLE;
6252 cmd->autoneg = AUTONEG_DISABLE;
6255 if (netif_carrier_ok(dev)) {
6256 cmd->speed = bp->line_speed;
6257 cmd->duplex = bp->duplex;
6263 spin_unlock_bh(&bp->phy_lock);
6265 cmd->transceiver = XCVR_INTERNAL;
6266 cmd->phy_address = bp->phy_addr;
6272 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6274 struct bnx2 *bp = netdev_priv(dev);
6275 u8 autoneg = bp->autoneg;
6276 u8 req_duplex = bp->req_duplex;
6277 u16 req_line_speed = bp->req_line_speed;
6278 u32 advertising = bp->advertising;
6281 spin_lock_bh(&bp->phy_lock);
6283 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6284 goto err_out_unlock;
6286 if (cmd->port != bp->phy_port &&
6287 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6288 goto err_out_unlock;
6290 /* If device is down, we can store the settings only if the user
6291 * is setting the currently active port.
6293 if (!netif_running(dev) && cmd->port != bp->phy_port)
6294 goto err_out_unlock;
6296 if (cmd->autoneg == AUTONEG_ENABLE) {
6297 autoneg |= AUTONEG_SPEED;
6299 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6301 /* allow advertising 1 speed */
6302 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6303 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6304 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6305 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6307 if (cmd->port == PORT_FIBRE)
6308 goto err_out_unlock;
6310 advertising = cmd->advertising;
6312 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6313 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6314 (cmd->port == PORT_TP))
6315 goto err_out_unlock;
6316 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6317 advertising = cmd->advertising;
6318 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6319 goto err_out_unlock;
6321 if (cmd->port == PORT_FIBRE)
6322 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6324 advertising = ETHTOOL_ALL_COPPER_SPEED;
6326 advertising |= ADVERTISED_Autoneg;
6329 if (cmd->port == PORT_FIBRE) {
6330 if ((cmd->speed != SPEED_1000 &&
6331 cmd->speed != SPEED_2500) ||
6332 (cmd->duplex != DUPLEX_FULL))
6333 goto err_out_unlock;
6335 if (cmd->speed == SPEED_2500 &&
6336 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6337 goto err_out_unlock;
6339 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6340 goto err_out_unlock;
6342 autoneg &= ~AUTONEG_SPEED;
6343 req_line_speed = cmd->speed;
6344 req_duplex = cmd->duplex;
6348 bp->autoneg = autoneg;
6349 bp->advertising = advertising;
6350 bp->req_line_speed = req_line_speed;
6351 bp->req_duplex = req_duplex;
6354 /* If device is down, the new settings will be picked up when it is
6357 if (netif_running(dev))
6358 err = bnx2_setup_phy(bp, cmd->port);
6361 spin_unlock_bh(&bp->phy_lock);
6367 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6369 struct bnx2 *bp = netdev_priv(dev);
6371 strcpy(info->driver, DRV_MODULE_NAME);
6372 strcpy(info->version, DRV_MODULE_VERSION);
6373 strcpy(info->bus_info, pci_name(bp->pdev));
6374 strcpy(info->fw_version, bp->fw_version);
6377 #define BNX2_REGDUMP_LEN (32 * 1024)
6380 bnx2_get_regs_len(struct net_device *dev)
6382 return BNX2_REGDUMP_LEN;
6386 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6388 u32 *p = _p, i, offset;
6390 struct bnx2 *bp = netdev_priv(dev);
6391 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6392 0x0800, 0x0880, 0x0c00, 0x0c10,
6393 0x0c30, 0x0d08, 0x1000, 0x101c,
6394 0x1040, 0x1048, 0x1080, 0x10a4,
6395 0x1400, 0x1490, 0x1498, 0x14f0,
6396 0x1500, 0x155c, 0x1580, 0x15dc,
6397 0x1600, 0x1658, 0x1680, 0x16d8,
6398 0x1800, 0x1820, 0x1840, 0x1854,
6399 0x1880, 0x1894, 0x1900, 0x1984,
6400 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6401 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6402 0x2000, 0x2030, 0x23c0, 0x2400,
6403 0x2800, 0x2820, 0x2830, 0x2850,
6404 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6405 0x3c00, 0x3c94, 0x4000, 0x4010,
6406 0x4080, 0x4090, 0x43c0, 0x4458,
6407 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6408 0x4fc0, 0x5010, 0x53c0, 0x5444,
6409 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6410 0x5fc0, 0x6000, 0x6400, 0x6428,
6411 0x6800, 0x6848, 0x684c, 0x6860,
6412 0x6888, 0x6910, 0x8000 };
6416 memset(p, 0, BNX2_REGDUMP_LEN);
6418 if (!netif_running(bp->dev))
6422 offset = reg_boundaries[0];
6424 while (offset < BNX2_REGDUMP_LEN) {
6425 *p++ = REG_RD(bp, offset);
6427 if (offset == reg_boundaries[i + 1]) {
6428 offset = reg_boundaries[i + 2];
6429 p = (u32 *) (orig_p + offset);
6436 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6438 struct bnx2 *bp = netdev_priv(dev);
6440 if (bp->flags & BNX2_FLAG_NO_WOL) {
6445 wol->supported = WAKE_MAGIC;
6447 wol->wolopts = WAKE_MAGIC;
6451 memset(&wol->sopass, 0, sizeof(wol->sopass));
6455 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6457 struct bnx2 *bp = netdev_priv(dev);
6459 if (wol->wolopts & ~WAKE_MAGIC)
6462 if (wol->wolopts & WAKE_MAGIC) {
6463 if (bp->flags & BNX2_FLAG_NO_WOL)
6475 bnx2_nway_reset(struct net_device *dev)
6477 struct bnx2 *bp = netdev_priv(dev);
6480 if (!netif_running(dev))
6483 if (!(bp->autoneg & AUTONEG_SPEED)) {
6487 spin_lock_bh(&bp->phy_lock);
6489 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6492 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6493 spin_unlock_bh(&bp->phy_lock);
6497 /* Force a link down visible on the other side */
6498 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6499 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6500 spin_unlock_bh(&bp->phy_lock);
6504 spin_lock_bh(&bp->phy_lock);
6506 bp->current_interval = SERDES_AN_TIMEOUT;
6507 bp->serdes_an_pending = 1;
6508 mod_timer(&bp->timer, jiffies + bp->current_interval);
6511 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6512 bmcr &= ~BMCR_LOOPBACK;
6513 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6515 spin_unlock_bh(&bp->phy_lock);
6521 bnx2_get_eeprom_len(struct net_device *dev)
6523 struct bnx2 *bp = netdev_priv(dev);
6525 if (bp->flash_info == NULL)
6528 return (int) bp->flash_size;
6532 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6535 struct bnx2 *bp = netdev_priv(dev);
6538 if (!netif_running(dev))
6541 /* parameters already validated in ethtool_get_eeprom */
6543 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6549 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6552 struct bnx2 *bp = netdev_priv(dev);
6555 if (!netif_running(dev))
6558 /* parameters already validated in ethtool_set_eeprom */
6560 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6566 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6568 struct bnx2 *bp = netdev_priv(dev);
6570 memset(coal, 0, sizeof(struct ethtool_coalesce));
6572 coal->rx_coalesce_usecs = bp->rx_ticks;
6573 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6574 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6575 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6577 coal->tx_coalesce_usecs = bp->tx_ticks;
6578 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6579 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6580 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6582 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6588 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6590 struct bnx2 *bp = netdev_priv(dev);
6592 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6593 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6595 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6596 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6598 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6599 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6601 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6602 if (bp->rx_quick_cons_trip_int > 0xff)
6603 bp->rx_quick_cons_trip_int = 0xff;
6605 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6606 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6608 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6609 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6611 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6612 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6614 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6615 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6618 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6619 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6620 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6621 bp->stats_ticks = USEC_PER_SEC;
6623 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6624 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6625 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6627 if (netif_running(bp->dev)) {
6628 bnx2_netif_stop(bp);
6629 bnx2_init_nic(bp, 0);
6630 bnx2_netif_start(bp);
6637 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6639 struct bnx2 *bp = netdev_priv(dev);
6641 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6642 ering->rx_mini_max_pending = 0;
6643 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6645 ering->rx_pending = bp->rx_ring_size;
6646 ering->rx_mini_pending = 0;
6647 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6649 ering->tx_max_pending = MAX_TX_DESC_CNT;
6650 ering->tx_pending = bp->tx_ring_size;
6654 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6656 if (netif_running(bp->dev)) {
6657 bnx2_netif_stop(bp);
6658 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6663 bnx2_set_rx_ring_size(bp, rx);
6664 bp->tx_ring_size = tx;
6666 if (netif_running(bp->dev)) {
6669 rc = bnx2_alloc_mem(bp);
6672 bnx2_init_nic(bp, 0);
6673 bnx2_netif_start(bp);
6679 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6681 struct bnx2 *bp = netdev_priv(dev);
6684 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6685 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6686 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6690 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6695 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6697 struct bnx2 *bp = netdev_priv(dev);
6699 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6700 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6701 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6705 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6707 struct bnx2 *bp = netdev_priv(dev);
6709 bp->req_flow_ctrl = 0;
6710 if (epause->rx_pause)
6711 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6712 if (epause->tx_pause)
6713 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6715 if (epause->autoneg) {
6716 bp->autoneg |= AUTONEG_FLOW_CTRL;
6719 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6722 if (netif_running(dev)) {
6723 spin_lock_bh(&bp->phy_lock);
6724 bnx2_setup_phy(bp, bp->phy_port);
6725 spin_unlock_bh(&bp->phy_lock);
6732 bnx2_get_rx_csum(struct net_device *dev)
6734 struct bnx2 *bp = netdev_priv(dev);
6740 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6742 struct bnx2 *bp = netdev_priv(dev);
6749 bnx2_set_tso(struct net_device *dev, u32 data)
6751 struct bnx2 *bp = netdev_priv(dev);
6754 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6755 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6756 dev->features |= NETIF_F_TSO6;
6758 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6763 #define BNX2_NUM_STATS 46
6766 char string[ETH_GSTRING_LEN];
6767 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6769 { "rx_error_bytes" },
6771 { "tx_error_bytes" },
6772 { "rx_ucast_packets" },
6773 { "rx_mcast_packets" },
6774 { "rx_bcast_packets" },
6775 { "tx_ucast_packets" },
6776 { "tx_mcast_packets" },
6777 { "tx_bcast_packets" },
6778 { "tx_mac_errors" },
6779 { "tx_carrier_errors" },
6780 { "rx_crc_errors" },
6781 { "rx_align_errors" },
6782 { "tx_single_collisions" },
6783 { "tx_multi_collisions" },
6785 { "tx_excess_collisions" },
6786 { "tx_late_collisions" },
6787 { "tx_total_collisions" },
6790 { "rx_undersize_packets" },
6791 { "rx_oversize_packets" },
6792 { "rx_64_byte_packets" },
6793 { "rx_65_to_127_byte_packets" },
6794 { "rx_128_to_255_byte_packets" },
6795 { "rx_256_to_511_byte_packets" },
6796 { "rx_512_to_1023_byte_packets" },
6797 { "rx_1024_to_1522_byte_packets" },
6798 { "rx_1523_to_9022_byte_packets" },
6799 { "tx_64_byte_packets" },
6800 { "tx_65_to_127_byte_packets" },
6801 { "tx_128_to_255_byte_packets" },
6802 { "tx_256_to_511_byte_packets" },
6803 { "tx_512_to_1023_byte_packets" },
6804 { "tx_1024_to_1522_byte_packets" },
6805 { "tx_1523_to_9022_byte_packets" },
6806 { "rx_xon_frames" },
6807 { "rx_xoff_frames" },
6808 { "tx_xon_frames" },
6809 { "tx_xoff_frames" },
6810 { "rx_mac_ctrl_frames" },
6811 { "rx_filtered_packets" },
6813 { "rx_fw_discards" },
6816 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6818 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6819 STATS_OFFSET32(stat_IfHCInOctets_hi),
6820 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6821 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6822 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6823 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6824 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6825 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6826 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6827 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6828 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6829 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6830 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6831 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6832 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6833 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6834 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6835 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6836 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6837 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6838 STATS_OFFSET32(stat_EtherStatsCollisions),
6839 STATS_OFFSET32(stat_EtherStatsFragments),
6840 STATS_OFFSET32(stat_EtherStatsJabbers),
6841 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6842 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6843 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6844 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6845 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6846 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6847 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6848 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6849 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6850 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6851 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6852 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6853 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6854 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6855 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6856 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6857 STATS_OFFSET32(stat_XonPauseFramesReceived),
6858 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6859 STATS_OFFSET32(stat_OutXonSent),
6860 STATS_OFFSET32(stat_OutXoffSent),
6861 STATS_OFFSET32(stat_MacControlFramesReceived),
6862 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6863 STATS_OFFSET32(stat_IfInMBUFDiscards),
6864 STATS_OFFSET32(stat_FwRxDrop),
6867 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6868 * skipped because of errata.
6870 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6871 8,0,8,8,8,8,8,8,8,8,
6872 4,0,4,4,4,4,4,4,4,4,
6873 4,4,4,4,4,4,4,4,4,4,
6874 4,4,4,4,4,4,4,4,4,4,
6878 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6879 8,0,8,8,8,8,8,8,8,8,
6880 4,4,4,4,4,4,4,4,4,4,
6881 4,4,4,4,4,4,4,4,4,4,
6882 4,4,4,4,4,4,4,4,4,4,
6886 #define BNX2_NUM_TESTS 6
6889 char string[ETH_GSTRING_LEN];
6890 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6891 { "register_test (offline)" },
6892 { "memory_test (offline)" },
6893 { "loopback_test (offline)" },
6894 { "nvram_test (online)" },
6895 { "interrupt_test (online)" },
6896 { "link_test (online)" },
6900 bnx2_get_sset_count(struct net_device *dev, int sset)
6904 return BNX2_NUM_TESTS;
6906 return BNX2_NUM_STATS;
6913 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6915 struct bnx2 *bp = netdev_priv(dev);
6917 bnx2_set_power_state(bp, PCI_D0);
6919 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6920 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6923 bnx2_netif_stop(bp);
6924 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6927 if (bnx2_test_registers(bp) != 0) {
6929 etest->flags |= ETH_TEST_FL_FAILED;
6931 if (bnx2_test_memory(bp) != 0) {
6933 etest->flags |= ETH_TEST_FL_FAILED;
6935 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6936 etest->flags |= ETH_TEST_FL_FAILED;
6938 if (!netif_running(bp->dev))
6939 bnx2_shutdown_chip(bp);
6941 bnx2_init_nic(bp, 1);
6942 bnx2_netif_start(bp);
6945 /* wait for link up */
6946 for (i = 0; i < 7; i++) {
6949 msleep_interruptible(1000);
6953 if (bnx2_test_nvram(bp) != 0) {
6955 etest->flags |= ETH_TEST_FL_FAILED;
6957 if (bnx2_test_intr(bp) != 0) {
6959 etest->flags |= ETH_TEST_FL_FAILED;
6962 if (bnx2_test_link(bp) != 0) {
6964 etest->flags |= ETH_TEST_FL_FAILED;
6967 if (!netif_running(bp->dev))
6968 bnx2_set_power_state(bp, PCI_D3hot);
6972 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6974 switch (stringset) {
6976 memcpy(buf, bnx2_stats_str_arr,
6977 sizeof(bnx2_stats_str_arr));
6980 memcpy(buf, bnx2_tests_str_arr,
6981 sizeof(bnx2_tests_str_arr));
6987 bnx2_get_ethtool_stats(struct net_device *dev,
6988 struct ethtool_stats *stats, u64 *buf)
6990 struct bnx2 *bp = netdev_priv(dev);
6992 u32 *hw_stats = (u32 *) bp->stats_blk;
6993 u8 *stats_len_arr = NULL;
6995 if (hw_stats == NULL) {
6996 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7000 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7001 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7002 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7003 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7004 stats_len_arr = bnx2_5706_stats_len_arr;
7006 stats_len_arr = bnx2_5708_stats_len_arr;
7008 for (i = 0; i < BNX2_NUM_STATS; i++) {
7009 if (stats_len_arr[i] == 0) {
7010 /* skip this counter */
7014 if (stats_len_arr[i] == 4) {
7015 /* 4-byte counter */
7017 *(hw_stats + bnx2_stats_offset_arr[i]);
7020 /* 8-byte counter */
7021 buf[i] = (((u64) *(hw_stats +
7022 bnx2_stats_offset_arr[i])) << 32) +
7023 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7028 bnx2_phys_id(struct net_device *dev, u32 data)
7030 struct bnx2 *bp = netdev_priv(dev);
7034 bnx2_set_power_state(bp, PCI_D0);
7039 save = REG_RD(bp, BNX2_MISC_CFG);
7040 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7042 for (i = 0; i < (data * 2); i++) {
7044 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7047 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7048 BNX2_EMAC_LED_1000MB_OVERRIDE |
7049 BNX2_EMAC_LED_100MB_OVERRIDE |
7050 BNX2_EMAC_LED_10MB_OVERRIDE |
7051 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7052 BNX2_EMAC_LED_TRAFFIC);
7054 msleep_interruptible(500);
7055 if (signal_pending(current))
7058 REG_WR(bp, BNX2_EMAC_LED, 0);
7059 REG_WR(bp, BNX2_MISC_CFG, save);
7061 if (!netif_running(dev))
7062 bnx2_set_power_state(bp, PCI_D3hot);
7068 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7070 struct bnx2 *bp = netdev_priv(dev);
7072 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7073 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7075 return (ethtool_op_set_tx_csum(dev, data));
7078 static const struct ethtool_ops bnx2_ethtool_ops = {
7079 .get_settings = bnx2_get_settings,
7080 .set_settings = bnx2_set_settings,
7081 .get_drvinfo = bnx2_get_drvinfo,
7082 .get_regs_len = bnx2_get_regs_len,
7083 .get_regs = bnx2_get_regs,
7084 .get_wol = bnx2_get_wol,
7085 .set_wol = bnx2_set_wol,
7086 .nway_reset = bnx2_nway_reset,
7087 .get_link = ethtool_op_get_link,
7088 .get_eeprom_len = bnx2_get_eeprom_len,
7089 .get_eeprom = bnx2_get_eeprom,
7090 .set_eeprom = bnx2_set_eeprom,
7091 .get_coalesce = bnx2_get_coalesce,
7092 .set_coalesce = bnx2_set_coalesce,
7093 .get_ringparam = bnx2_get_ringparam,
7094 .set_ringparam = bnx2_set_ringparam,
7095 .get_pauseparam = bnx2_get_pauseparam,
7096 .set_pauseparam = bnx2_set_pauseparam,
7097 .get_rx_csum = bnx2_get_rx_csum,
7098 .set_rx_csum = bnx2_set_rx_csum,
7099 .set_tx_csum = bnx2_set_tx_csum,
7100 .set_sg = ethtool_op_set_sg,
7101 .set_tso = bnx2_set_tso,
7102 .self_test = bnx2_self_test,
7103 .get_strings = bnx2_get_strings,
7104 .phys_id = bnx2_phys_id,
7105 .get_ethtool_stats = bnx2_get_ethtool_stats,
7106 .get_sset_count = bnx2_get_sset_count,
7109 /* Called with rtnl_lock */
7111 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7113 struct mii_ioctl_data *data = if_mii(ifr);
7114 struct bnx2 *bp = netdev_priv(dev);
7119 data->phy_id = bp->phy_addr;
7125 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7128 if (!netif_running(dev))
7131 spin_lock_bh(&bp->phy_lock);
7132 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7133 spin_unlock_bh(&bp->phy_lock);
7135 data->val_out = mii_regval;
7141 if (!capable(CAP_NET_ADMIN))
7144 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7147 if (!netif_running(dev))
7150 spin_lock_bh(&bp->phy_lock);
7151 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7152 spin_unlock_bh(&bp->phy_lock);
7163 /* Called with rtnl_lock */
7165 bnx2_change_mac_addr(struct net_device *dev, void *p)
7167 struct sockaddr *addr = p;
7168 struct bnx2 *bp = netdev_priv(dev);
7170 if (!is_valid_ether_addr(addr->sa_data))
7173 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7174 if (netif_running(dev))
7175 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7180 /* Called with rtnl_lock */
7182 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7184 struct bnx2 *bp = netdev_priv(dev);
7186 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7187 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7191 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7194 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7196 poll_bnx2(struct net_device *dev)
7198 struct bnx2 *bp = netdev_priv(dev);
7200 disable_irq(bp->pdev->irq);
7201 bnx2_interrupt(bp->pdev->irq, dev);
7202 enable_irq(bp->pdev->irq);
7206 static void __devinit
7207 bnx2_get_5709_media(struct bnx2 *bp)
7209 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7210 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7213 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7215 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7216 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7220 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7221 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7223 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7225 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7230 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7238 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7244 static void __devinit
7245 bnx2_get_pci_speed(struct bnx2 *bp)
7249 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7250 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7253 bp->flags |= BNX2_FLAG_PCIX;
7255 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7257 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7259 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7260 bp->bus_speed_mhz = 133;
7263 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7264 bp->bus_speed_mhz = 100;
7267 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7268 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7269 bp->bus_speed_mhz = 66;
7272 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7273 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7274 bp->bus_speed_mhz = 50;
7277 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7278 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7279 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7280 bp->bus_speed_mhz = 33;
7285 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7286 bp->bus_speed_mhz = 66;
7288 bp->bus_speed_mhz = 33;
7291 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7292 bp->flags |= BNX2_FLAG_PCI_32BIT;
7296 static int __devinit
7297 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7300 unsigned long mem_len;
7303 u64 dma_mask, persist_dma_mask;
7305 SET_NETDEV_DEV(dev, &pdev->dev);
7306 bp = netdev_priv(dev);
7311 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7312 rc = pci_enable_device(pdev);
7314 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7318 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7320 "Cannot find PCI device base address, aborting.\n");
7322 goto err_out_disable;
7325 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7327 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7328 goto err_out_disable;
7331 pci_set_master(pdev);
7332 pci_save_state(pdev);
7334 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7335 if (bp->pm_cap == 0) {
7337 "Cannot find power management capability, aborting.\n");
7339 goto err_out_release;
7345 spin_lock_init(&bp->phy_lock);
7346 spin_lock_init(&bp->indirect_lock);
7347 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7349 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7350 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7351 dev->mem_end = dev->mem_start + mem_len;
7352 dev->irq = pdev->irq;
7354 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7357 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7359 goto err_out_release;
7362 /* Configure byte swap and enable write to the reg_window registers.
7363 * Rely on CPU to do target byte swapping on big endian systems
7364 * The chip's target access swapping will not swap all accesses
7366 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7367 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7368 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7370 bnx2_set_power_state(bp, PCI_D0);
7372 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7374 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7375 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7377 "Cannot find PCIE capability, aborting.\n");
7381 bp->flags |= BNX2_FLAG_PCIE;
7382 if (CHIP_REV(bp) == CHIP_REV_Ax)
7383 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7385 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7386 if (bp->pcix_cap == 0) {
7388 "Cannot find PCIX capability, aborting.\n");
7394 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7395 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7396 bp->flags |= BNX2_FLAG_MSIX_CAP;
7399 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7400 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7401 bp->flags |= BNX2_FLAG_MSI_CAP;
7404 /* 5708 cannot support DMA addresses > 40-bit. */
7405 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7406 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7408 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7410 /* Configure DMA attributes. */
7411 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7412 dev->features |= NETIF_F_HIGHDMA;
7413 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7416 "pci_set_consistent_dma_mask failed, aborting.\n");
7419 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7420 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7424 if (!(bp->flags & BNX2_FLAG_PCIE))
7425 bnx2_get_pci_speed(bp);
7427 /* 5706A0 may falsely detect SERR and PERR. */
7428 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7429 reg = REG_RD(bp, PCI_COMMAND);
7430 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7431 REG_WR(bp, PCI_COMMAND, reg);
7433 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7434 !(bp->flags & BNX2_FLAG_PCIX)) {
7437 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7441 bnx2_init_nvram(bp);
7443 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7445 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7446 BNX2_SHM_HDR_SIGNATURE_SIG) {
7447 u32 off = PCI_FUNC(pdev->devfn) << 2;
7449 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7451 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7453 /* Get the permanent MAC address. First we need to make sure the
7454 * firmware is actually running.
7456 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7458 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7459 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7460 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7465 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7466 for (i = 0, j = 0; i < 3; i++) {
7469 num = (u8) (reg >> (24 - (i * 8)));
7470 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7471 if (num >= k || !skip0 || k == 1) {
7472 bp->fw_version[j++] = (num / k) + '0';
7477 bp->fw_version[j++] = '.';
7479 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7480 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7483 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7484 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7486 for (i = 0; i < 30; i++) {
7487 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7488 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7493 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7494 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7495 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7496 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7497 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7499 bp->fw_version[j++] = ' ';
7500 for (i = 0; i < 3; i++) {
7501 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7503 memcpy(&bp->fw_version[j], ®, 4);
7508 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7509 bp->mac_addr[0] = (u8) (reg >> 8);
7510 bp->mac_addr[1] = (u8) reg;
7512 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7513 bp->mac_addr[2] = (u8) (reg >> 24);
7514 bp->mac_addr[3] = (u8) (reg >> 16);
7515 bp->mac_addr[4] = (u8) (reg >> 8);
7516 bp->mac_addr[5] = (u8) reg;
7518 bp->tx_ring_size = MAX_TX_DESC_CNT;
7519 bnx2_set_rx_ring_size(bp, 255);
7523 bp->tx_quick_cons_trip_int = 20;
7524 bp->tx_quick_cons_trip = 20;
7525 bp->tx_ticks_int = 80;
7528 bp->rx_quick_cons_trip_int = 6;
7529 bp->rx_quick_cons_trip = 6;
7530 bp->rx_ticks_int = 18;
7533 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7535 bp->current_interval = BNX2_TIMER_INTERVAL;
7539 /* Disable WOL support if we are running on a SERDES chip. */
7540 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7541 bnx2_get_5709_media(bp);
7542 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7543 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7545 bp->phy_port = PORT_TP;
7546 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7547 bp->phy_port = PORT_FIBRE;
7548 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7549 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7550 bp->flags |= BNX2_FLAG_NO_WOL;
7553 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7554 /* Don't do parallel detect on this board because of
7555 * some board problems. The link will not go down
7556 * if we do parallel detect.
7558 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7559 pdev->subsystem_device == 0x310c)
7560 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7563 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7564 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7566 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7567 CHIP_NUM(bp) == CHIP_NUM_5708)
7568 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7569 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7570 (CHIP_REV(bp) == CHIP_REV_Ax ||
7571 CHIP_REV(bp) == CHIP_REV_Bx))
7572 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7574 bnx2_init_fw_cap(bp);
7576 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7577 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7578 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7579 bp->flags |= BNX2_FLAG_NO_WOL;
7583 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7584 bp->tx_quick_cons_trip_int =
7585 bp->tx_quick_cons_trip;
7586 bp->tx_ticks_int = bp->tx_ticks;
7587 bp->rx_quick_cons_trip_int =
7588 bp->rx_quick_cons_trip;
7589 bp->rx_ticks_int = bp->rx_ticks;
7590 bp->comp_prod_trip_int = bp->comp_prod_trip;
7591 bp->com_ticks_int = bp->com_ticks;
7592 bp->cmd_ticks_int = bp->cmd_ticks;
7595 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7597 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7598 * with byte enables disabled on the unused 32-bit word. This is legal
7599 * but causes problems on the AMD 8132 which will eventually stop
7600 * responding after a while.
7602 * AMD believes this incompatibility is unique to the 5706, and
7603 * prefers to locally disable MSI rather than globally disabling it.
7605 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7606 struct pci_dev *amd_8132 = NULL;
7608 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7609 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7612 if (amd_8132->revision >= 0x10 &&
7613 amd_8132->revision <= 0x13) {
7615 pci_dev_put(amd_8132);
7621 bnx2_set_default_link(bp);
7622 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7624 init_timer(&bp->timer);
7625 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7626 bp->timer.data = (unsigned long) bp;
7627 bp->timer.function = bnx2_timer;
7633 iounmap(bp->regview);
7638 pci_release_regions(pdev);
7641 pci_disable_device(pdev);
7642 pci_set_drvdata(pdev, NULL);
7648 static char * __devinit
7649 bnx2_bus_string(struct bnx2 *bp, char *str)
7653 if (bp->flags & BNX2_FLAG_PCIE) {
7654 s += sprintf(s, "PCI Express");
7656 s += sprintf(s, "PCI");
7657 if (bp->flags & BNX2_FLAG_PCIX)
7658 s += sprintf(s, "-X");
7659 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7660 s += sprintf(s, " 32-bit");
7662 s += sprintf(s, " 64-bit");
7663 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7668 static void __devinit
7669 bnx2_init_napi(struct bnx2 *bp)
7673 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7674 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7675 int (*poll)(struct napi_struct *, int);
7680 poll = bnx2_poll_msix;
7682 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7687 static int __devinit
7688 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7690 static int version_printed = 0;
7691 struct net_device *dev = NULL;
7695 DECLARE_MAC_BUF(mac);
7697 if (version_printed++ == 0)
7698 printk(KERN_INFO "%s", version);
7700 /* dev zeroed in init_etherdev */
7701 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7706 rc = bnx2_init_board(pdev, dev);
7712 dev->open = bnx2_open;
7713 dev->hard_start_xmit = bnx2_start_xmit;
7714 dev->stop = bnx2_close;
7715 dev->get_stats = bnx2_get_stats;
7716 dev->set_rx_mode = bnx2_set_rx_mode;
7717 dev->do_ioctl = bnx2_ioctl;
7718 dev->set_mac_address = bnx2_change_mac_addr;
7719 dev->change_mtu = bnx2_change_mtu;
7720 dev->tx_timeout = bnx2_tx_timeout;
7721 dev->watchdog_timeo = TX_TIMEOUT;
7723 dev->vlan_rx_register = bnx2_vlan_rx_register;
7725 dev->ethtool_ops = &bnx2_ethtool_ops;
7727 bp = netdev_priv(dev);
7730 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7731 dev->poll_controller = poll_bnx2;
7734 pci_set_drvdata(pdev, dev);
7736 memcpy(dev->dev_addr, bp->mac_addr, 6);
7737 memcpy(dev->perm_addr, bp->mac_addr, 6);
7739 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7740 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7741 dev->features |= NETIF_F_IPV6_CSUM;
7744 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7746 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7747 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7748 dev->features |= NETIF_F_TSO6;
7750 if ((rc = register_netdev(dev))) {
7751 dev_err(&pdev->dev, "Cannot register net device\n");
7753 iounmap(bp->regview);
7754 pci_release_regions(pdev);
7755 pci_disable_device(pdev);
7756 pci_set_drvdata(pdev, NULL);
7761 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7762 "IRQ %d, node addr %s\n",
7764 board_info[ent->driver_data].name,
7765 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7766 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7767 bnx2_bus_string(bp, str),
7769 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7774 static void __devexit
7775 bnx2_remove_one(struct pci_dev *pdev)
7777 struct net_device *dev = pci_get_drvdata(pdev);
7778 struct bnx2 *bp = netdev_priv(dev);
7780 flush_scheduled_work();
7782 unregister_netdev(dev);
7785 iounmap(bp->regview);
7788 pci_release_regions(pdev);
7789 pci_disable_device(pdev);
7790 pci_set_drvdata(pdev, NULL);
7794 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7796 struct net_device *dev = pci_get_drvdata(pdev);
7797 struct bnx2 *bp = netdev_priv(dev);
7799 /* PCI register 4 needs to be saved whether netif_running() or not.
7800 * MSI address and data need to be saved if using MSI and
7803 pci_save_state(pdev);
7804 if (!netif_running(dev))
7807 flush_scheduled_work();
7808 bnx2_netif_stop(bp);
7809 netif_device_detach(dev);
7810 del_timer_sync(&bp->timer);
7811 bnx2_shutdown_chip(bp);
7813 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7818 bnx2_resume(struct pci_dev *pdev)
7820 struct net_device *dev = pci_get_drvdata(pdev);
7821 struct bnx2 *bp = netdev_priv(dev);
7823 pci_restore_state(pdev);
7824 if (!netif_running(dev))
7827 bnx2_set_power_state(bp, PCI_D0);
7828 netif_device_attach(dev);
7829 bnx2_init_nic(bp, 1);
7830 bnx2_netif_start(bp);
7835 * bnx2_io_error_detected - called when PCI error is detected
7836 * @pdev: Pointer to PCI device
7837 * @state: The current pci connection state
7839 * This function is called after a PCI bus error affecting
7840 * this device has been detected.
7842 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7843 pci_channel_state_t state)
7845 struct net_device *dev = pci_get_drvdata(pdev);
7846 struct bnx2 *bp = netdev_priv(dev);
7849 netif_device_detach(dev);
7851 if (netif_running(dev)) {
7852 bnx2_netif_stop(bp);
7853 del_timer_sync(&bp->timer);
7854 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7857 pci_disable_device(pdev);
7860 /* Request a slot slot reset. */
7861 return PCI_ERS_RESULT_NEED_RESET;
7865 * bnx2_io_slot_reset - called after the pci bus has been reset.
7866 * @pdev: Pointer to PCI device
7868 * Restart the card from scratch, as if from a cold-boot.
7870 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7872 struct net_device *dev = pci_get_drvdata(pdev);
7873 struct bnx2 *bp = netdev_priv(dev);
7876 if (pci_enable_device(pdev)) {
7878 "Cannot re-enable PCI device after reset.\n");
7880 return PCI_ERS_RESULT_DISCONNECT;
7882 pci_set_master(pdev);
7883 pci_restore_state(pdev);
7885 if (netif_running(dev)) {
7886 bnx2_set_power_state(bp, PCI_D0);
7887 bnx2_init_nic(bp, 1);
7891 return PCI_ERS_RESULT_RECOVERED;
7895 * bnx2_io_resume - called when traffic can start flowing again.
7896 * @pdev: Pointer to PCI device
7898 * This callback is called when the error recovery driver tells us that
7899 * its OK to resume normal operation.
7901 static void bnx2_io_resume(struct pci_dev *pdev)
7903 struct net_device *dev = pci_get_drvdata(pdev);
7904 struct bnx2 *bp = netdev_priv(dev);
7907 if (netif_running(dev))
7908 bnx2_netif_start(bp);
7910 netif_device_attach(dev);
7914 static struct pci_error_handlers bnx2_err_handler = {
7915 .error_detected = bnx2_io_error_detected,
7916 .slot_reset = bnx2_io_slot_reset,
7917 .resume = bnx2_io_resume,
7920 static struct pci_driver bnx2_pci_driver = {
7921 .name = DRV_MODULE_NAME,
7922 .id_table = bnx2_pci_tbl,
7923 .probe = bnx2_init_one,
7924 .remove = __devexit_p(bnx2_remove_one),
7925 .suspend = bnx2_suspend,
7926 .resume = bnx2_resume,
7927 .err_handler = &bnx2_err_handler,
7930 static int __init bnx2_init(void)
7932 return pci_register_driver(&bnx2_pci_driver);
7935 static void __exit bnx2_cleanup(void)
7937 pci_unregister_driver(&bnx2_pci_driver);
7940 module_init(bnx2_init);
7941 module_exit(bnx2_cleanup);