drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #ifdef NETIF_F_HW_VLAN_TX
  39 #include <linux/if_vlan.h>
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50
  51 #include "bnx2.h"
  52 #include "bnx2_fw.h"
  53 #include "bnx2_fw2.h"
  54
  55 #define FW_BUF_SIZE             0x10000
  56
  57 #define DRV_MODULE_NAME         "bnx2"
  58 #define PFX DRV_MODULE_NAME     ": "
  59 #define DRV_MODULE_VERSION      "1.7.5"
  60 #define DRV_MODULE_RELDATE      "April 29, 2008"
  61
  62 #define RUN_AT(x) (jiffies + (x))
  63
  64 /* Time in jiffies before concluding the transmitter is hung. */
  65 #define TX_TIMEOUT  (5*HZ)
  66
  67 static char version[] __devinitdata =
  68         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  69
  70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  72 MODULE_LICENSE("GPL");
  73 MODULE_VERSION(DRV_MODULE_VERSION);
  74
  75 static int disable_msi = 0;
  76
  77 module_param(disable_msi, int, 0);
  78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  79
  80 typedef enum {
  81         BCM5706 = 0,
  82         NC370T,
  83         NC370I,
  84         BCM5706S,
  85         NC370F,
  86         BCM5708,
  87         BCM5708S,
  88         BCM5709,
  89         BCM5709S,
  90 } board_t;
  91
  92 /* indexed by board_t, above */
  93 static struct {
  94         char *name;
  95 } board_info[] __devinitdata = {
  96         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  97         { "HP NC370T Multifunction Gigabit Server Adapter" },
  98         { "HP NC370i Multifunction Gigabit Server Adapter" },
  99         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 100         { "HP NC370F Multifunction Gigabit Server Adapter" },
 101         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 102         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 103         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 104         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 105         };
 106
 107 static struct pci_device_id bnx2_pci_tbl[] = {
 108         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 109           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 110         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 111           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 112         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 113           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 114         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 115           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 116         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 117           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 118         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 119           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 120         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 121           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 122         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 123           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 124         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 125           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 126         { 0, }
 127 };
 128
 129 static struct flash_spec flash_table[] =
 130 {
 131 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 132 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 133         /* Slow EEPROM */
 134         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 135          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 136          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 137          "EEPROM - slow"},
 138         /* Expansion entry 0001 */
 139         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 140          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 141          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 142          "Entry 0001"},
 143         /* Saifun SA25F010 (non-buffered flash) */
 144         /* strap, cfg1, & write1 need updates */
 145         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 146          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 147          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 148          "Non-buffered flash (128kB)"},
 149         /* Saifun SA25F020 (non-buffered flash) */
 150         /* strap, cfg1, & write1 need updates */
 151         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 152          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 153          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 154          "Non-buffered flash (256kB)"},
 155         /* Expansion entry 0100 */
 156         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 157          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 158          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 159          "Entry 0100"},
 160         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 161         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 162          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 163          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 164          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 165         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 166         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 167          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 168          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 169          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 170         /* Saifun SA25F005 (non-buffered flash) */
 171         /* strap, cfg1, & write1 need updates */
 172         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 173          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 174          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 175          "Non-buffered flash (64kB)"},
 176         /* Fast EEPROM */
 177         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 178          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 179          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 180          "EEPROM - fast"},
 181         /* Expansion entry 1001 */
 182         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 183          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 184          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 185          "Entry 1001"},
 186         /* Expansion entry 1010 */
 187         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 190          "Entry 1010"},
 191         /* ATMEL AT45DB011B (buffered flash) */
 192         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 193          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 194          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 195          "Buffered flash (128kB)"},
 196         /* Expansion entry 1100 */
 197         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 198          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 199          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 200          "Entry 1100"},
 201         /* Expansion entry 1101 */
 202         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1101"},
 206         /* Ateml Expansion entry 1110 */
 207         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 208          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 209          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 210          "Entry 1110 (Atmel)"},
 211         /* ATMEL AT45DB021B (buffered flash) */
 212         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 214          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 215          "Buffered flash (256kB)"},
 216 };
 217
 218 static struct flash_spec flash_5709 = {
 219         .flags          = BNX2_NV_BUFFERED,
 220         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 221         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 222         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 223         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 224         .name           = "5709 Buffered flash (256kB)",
 225 };
 226
 227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 228
 229 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
 230 {
 231         u32 diff;
 232
 233         smp_mb();
 234
 235         /* The ring uses 256 indices for 255 entries, one of them
 236          * needs to be skipped.
 237          */
 238         diff = bp->tx_prod - bnapi->tx_cons;
 239         if (unlikely(diff >= TX_DESC_CNT)) {
 240                 diff &= 0xffff;
 241                 if (diff == TX_DESC_CNT)
 242                         diff = MAX_TX_DESC_CNT;
 243         }
 244         return (bp->tx_ring_size - diff);
 245 }
 246
 247 static u32
 248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 249 {
 250         u32 val;
 251
 252         spin_lock_bh(&bp->indirect_lock);
 253         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 254         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 255         spin_unlock_bh(&bp->indirect_lock);
 256         return val;
 257 }
 258
 259 static void
 260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 261 {
 262         spin_lock_bh(&bp->indirect_lock);
 263         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 264         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 265         spin_unlock_bh(&bp->indirect_lock);
 266 }
 267
 268 static void
 269 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 270 {
 271         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 272 }
 273
 274 static u32
 275 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 276 {
 277         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 278 }
 279
 280 static void
 281 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 282 {
 283         offset += cid_addr;
 284         spin_lock_bh(&bp->indirect_lock);
 285         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 286                 int i;
 287
 288                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 289                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 290                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 291                 for (i = 0; i < 5; i++) {
 292                         u32 val;
 293                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 294                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 295                                 break;
 296                         udelay(5);
 297                 }
 298         } else {
 299                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 300                 REG_WR(bp, BNX2_CTX_DATA, val);
 301         }
 302         spin_unlock_bh(&bp->indirect_lock);
 303 }
 304
 305 static int
 306 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 307 {
 308         u32 val1;
 309         int i, ret;
 310
 311         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 312                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 313                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 314
 315                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 316                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 317
 318                 udelay(40);
 319         }
 320
 321         val1 = (bp->phy_addr << 21) | (reg << 16) |
 322                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 323                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 324         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 325
 326         for (i = 0; i < 50; i++) {
 327                 udelay(10);
 328
 329                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 330                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 331                         udelay(5);
 332
 333                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 334                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 335
 336                         break;
 337                 }
 338         }
 339
 340         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 341                 *val = 0x0;
 342                 ret = -EBUSY;
 343         }
 344         else {
 345                 *val = val1;
 346                 ret = 0;
 347         }
 348
 349         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 350                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 351                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 352
 353                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 354                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 355
 356                 udelay(40);
 357         }
 358
 359         return ret;
 360 }
 361
 362 static int
 363 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 364 {
 365         u32 val1;
 366         int i, ret;
 367
 368         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 369                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 370                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 371
 372                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 373                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 374
 375                 udelay(40);
 376         }
 377
 378         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 379                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 380                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 381         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 382
 383         for (i = 0; i < 50; i++) {
 384                 udelay(10);
 385
 386                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 387                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 388                         udelay(5);
 389                         break;
 390                 }
 391         }
 392
 393         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 394                 ret = -EBUSY;
 395         else
 396                 ret = 0;
 397
 398         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 399                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 400                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 401
 402                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 403                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 404
 405                 udelay(40);
 406         }
 407
 408         return ret;
 409 }
 410
 411 static void
 412 bnx2_disable_int(struct bnx2 *bp)
 413 {
 414         int i;
 415         struct bnx2_napi *bnapi;
 416
 417         for (i = 0; i < bp->irq_nvecs; i++) {
 418                 bnapi = &bp->bnx2_napi[i];
 419                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 420                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 421         }
 422         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 423 }
 424
 425 static void
 426 bnx2_enable_int(struct bnx2 *bp)
 427 {
 428         int i;
 429         struct bnx2_napi *bnapi;
 430
 431         for (i = 0; i < bp->irq_nvecs; i++) {
 432                 bnapi = &bp->bnx2_napi[i];
 433
 434                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 435                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 436                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 437                        bnapi->last_status_idx);
 438
 439                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 440                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 441                        bnapi->last_status_idx);
 442         }
 443         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 444 }
 445
 446 static void
 447 bnx2_disable_int_sync(struct bnx2 *bp)
 448 {
 449         int i;
 450
 451         atomic_inc(&bp->intr_sem);
 452         bnx2_disable_int(bp);
 453         for (i = 0; i < bp->irq_nvecs; i++)
 454                 synchronize_irq(bp->irq_tbl[i].vector);
 455 }
 456
 457 static void
 458 bnx2_napi_disable(struct bnx2 *bp)
 459 {
 460         int i;
 461
 462         for (i = 0; i < bp->irq_nvecs; i++)
 463                 napi_disable(&bp->bnx2_napi[i].napi);
 464 }
 465
 466 static void
 467 bnx2_napi_enable(struct bnx2 *bp)
 468 {
 469         int i;
 470
 471         for (i = 0; i < bp->irq_nvecs; i++)
 472                 napi_enable(&bp->bnx2_napi[i].napi);
 473 }
 474
 475 static void
 476 bnx2_netif_stop(struct bnx2 *bp)
 477 {
 478         bnx2_disable_int_sync(bp);
 479         if (netif_running(bp->dev)) {
 480                 bnx2_napi_disable(bp);
 481                 netif_tx_disable(bp->dev);
 482                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 483         }
 484 }
 485
 486 static void
 487 bnx2_netif_start(struct bnx2 *bp)
 488 {
 489         if (atomic_dec_and_test(&bp->intr_sem)) {
 490                 if (netif_running(bp->dev)) {
 491                         netif_wake_queue(bp->dev);
 492                         bnx2_napi_enable(bp);
 493                         bnx2_enable_int(bp);
 494                 }
 495         }
 496 }
 497
 498 static void
 499 bnx2_free_mem(struct bnx2 *bp)
 500 {
 501         int i;
 502
 503         for (i = 0; i < bp->ctx_pages; i++) {
 504                 if (bp->ctx_blk[i]) {
 505                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 506                                             bp->ctx_blk[i],
 507                                             bp->ctx_blk_mapping[i]);
 508                         bp->ctx_blk[i] = NULL;
 509                 }
 510         }
 511         if (bp->status_blk) {
 512                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 513                                     bp->status_blk, bp->status_blk_mapping);
 514                 bp->status_blk = NULL;
 515                 bp->stats_blk = NULL;
 516         }
 517         if (bp->tx_desc_ring) {
 518                 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 519                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 520                 bp->tx_desc_ring = NULL;
 521         }
 522         kfree(bp->tx_buf_ring);
 523         bp->tx_buf_ring = NULL;
 524         for (i = 0; i < bp->rx_max_ring; i++) {
 525                 if (bp->rx_desc_ring[i])
 526                         pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 527                                             bp->rx_desc_ring[i],
 528                                             bp->rx_desc_mapping[i]);
 529                 bp->rx_desc_ring[i] = NULL;
 530         }
 531         vfree(bp->rx_buf_ring);
 532         bp->rx_buf_ring = NULL;
 533         for (i = 0; i < bp->rx_max_pg_ring; i++) {
 534                 if (bp->rx_pg_desc_ring[i])
 535                         pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 536                                             bp->rx_pg_desc_ring[i],
 537                                             bp->rx_pg_desc_mapping[i]);
 538                 bp->rx_pg_desc_ring[i] = NULL;
 539         }
 540         if (bp->rx_pg_ring)
 541                 vfree(bp->rx_pg_ring);
 542         bp->rx_pg_ring = NULL;
 543 }
 544
 545 static int
 546 bnx2_alloc_mem(struct bnx2 *bp)
 547 {
 548         int i, status_blk_size;
 549
 550         bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 551         if (bp->tx_buf_ring == NULL)
 552                 return -ENOMEM;
 553
 554         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 555                                                 &bp->tx_desc_mapping);
 556         if (bp->tx_desc_ring == NULL)
 557                 goto alloc_mem_err;
 558
 559         bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 560         if (bp->rx_buf_ring == NULL)
 561                 goto alloc_mem_err;
 562
 563         memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
 564
 565         for (i = 0; i < bp->rx_max_ring; i++) {
 566                 bp->rx_desc_ring[i] =
 567                         pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 568                                              &bp->rx_desc_mapping[i]);
 569                 if (bp->rx_desc_ring[i] == NULL)
 570                         goto alloc_mem_err;
 571
 572         }
 573
 574         if (bp->rx_pg_ring_size) {
 575                 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 576                                          bp->rx_max_pg_ring);
 577                 if (bp->rx_pg_ring == NULL)
 578                         goto alloc_mem_err;
 579
 580                 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 581                        bp->rx_max_pg_ring);
 582         }
 583
 584         for (i = 0; i < bp->rx_max_pg_ring; i++) {
 585                 bp->rx_pg_desc_ring[i] =
 586                         pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 587                                              &bp->rx_pg_desc_mapping[i]);
 588                 if (bp->rx_pg_desc_ring[i] == NULL)
 589                         goto alloc_mem_err;
 590
 591         }
 592
 593         /* Combine status and statistics blocks into one allocation. */
 594         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 595         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 596                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 597                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 598         bp->status_stats_size = status_blk_size +
 599                                 sizeof(struct statistics_block);
 600
 601         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 602                                               &bp->status_blk_mapping);
 603         if (bp->status_blk == NULL)
 604                 goto alloc_mem_err;
 605
 606         memset(bp->status_blk, 0, bp->status_stats_size);
 607
 608         bp->bnx2_napi[0].status_blk = bp->status_blk;
 609         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 610                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 611                         struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 612
 613                         bnapi->status_blk_msix = (void *)
 614                                 ((unsigned long) bp->status_blk +
 615                                  BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 616                         bnapi->int_num = i << 24;
 617                 }
 618         }
 619
 620         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
 621                                   status_blk_size);
 622
 623         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 624
 625         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 626                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 627                 if (bp->ctx_pages == 0)
 628                         bp->ctx_pages = 1;
 629                 for (i = 0; i < bp->ctx_pages; i++) {
 630                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 631                                                 BCM_PAGE_SIZE,
 632                                                 &bp->ctx_blk_mapping[i]);
 633                         if (bp->ctx_blk[i] == NULL)
 634                                 goto alloc_mem_err;
 635                 }
 636         }
 637         return 0;
 638
 639 alloc_mem_err:
 640         bnx2_free_mem(bp);
 641         return -ENOMEM;
 642 }
 643
 644 static void
 645 bnx2_report_fw_link(struct bnx2 *bp)
 646 {
 647         u32 fw_link_status = 0;
 648
 649         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 650                 return;
 651
 652         if (bp->link_up) {
 653                 u32 bmsr;
 654
 655                 switch (bp->line_speed) {
 656                 case SPEED_10:
 657                         if (bp->duplex == DUPLEX_HALF)
 658                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 659                         else
 660                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 661                         break;
 662                 case SPEED_100:
 663                         if (bp->duplex == DUPLEX_HALF)
 664                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 665                         else
 666                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 667                         break;
 668                 case SPEED_1000:
 669                         if (bp->duplex == DUPLEX_HALF)
 670                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 671                         else
 672                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 673                         break;
 674                 case SPEED_2500:
 675                         if (bp->duplex == DUPLEX_HALF)
 676                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 677                         else
 678                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 679                         break;
 680                 }
 681
 682                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 683
 684                 if (bp->autoneg) {
 685                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 686
 687                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 688                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 689
 690                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 691                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 692                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 693                         else
 694                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 695                 }
 696         }
 697         else
 698                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 699
 700         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 701 }
 702
 703 static char *
 704 bnx2_xceiver_str(struct bnx2 *bp)
 705 {
 706         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 707                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 708                  "Copper"));
 709 }
 710
 711 static void
 712 bnx2_report_link(struct bnx2 *bp)
 713 {
 714         if (bp->link_up) {
 715                 netif_carrier_on(bp->dev);
 716                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 717                        bnx2_xceiver_str(bp));
 718
 719                 printk("%d Mbps ", bp->line_speed);
 720
 721                 if (bp->duplex == DUPLEX_FULL)
 722                         printk("full duplex");
 723                 else
 724                         printk("half duplex");
 725
 726                 if (bp->flow_ctrl) {
 727                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 728                                 printk(", receive ");
 729                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 730                                         printk("& transmit ");
 731                         }
 732                         else {
 733                                 printk(", transmit ");
 734                         }
 735                         printk("flow control ON");
 736                 }
 737                 printk("\n");
 738         }
 739         else {
 740                 netif_carrier_off(bp->dev);
 741                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 742                        bnx2_xceiver_str(bp));
 743         }
 744
 745         bnx2_report_fw_link(bp);
 746 }
 747
 748 static void
 749 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 750 {
 751         u32 local_adv, remote_adv;
 752
 753         bp->flow_ctrl = 0;
 754         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 755                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 756
 757                 if (bp->duplex == DUPLEX_FULL) {
 758                         bp->flow_ctrl = bp->req_flow_ctrl;
 759                 }
 760                 return;
 761         }
 762
 763         if (bp->duplex != DUPLEX_FULL) {
 764                 return;
 765         }
 766
 767         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
 768             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 769                 u32 val;
 770
 771                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 772                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 773                         bp->flow_ctrl |= FLOW_CTRL_TX;
 774                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 775                         bp->flow_ctrl |= FLOW_CTRL_RX;
 776                 return;
 777         }
 778
 779         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 780         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 781
 782         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
 783                 u32 new_local_adv = 0;
 784                 u32 new_remote_adv = 0;
 785
 786                 if (local_adv & ADVERTISE_1000XPAUSE)
 787                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 788                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 789                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 790                 if (remote_adv & ADVERTISE_1000XPAUSE)
 791                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 792                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 793                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 794
 795                 local_adv = new_local_adv;
 796                 remote_adv = new_remote_adv;
 797         }
 798
 799         /* See Table 28B-3 of 802.3ab-1999 spec. */
 800         if (local_adv & ADVERTISE_PAUSE_CAP) {
 801                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 802                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 803                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 804                         }
 805                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 806                                 bp->flow_ctrl = FLOW_CTRL_RX;
 807                         }
 808                 }
 809                 else {
 810                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 811                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 812                         }
 813                 }
 814         }
 815         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 816                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 817                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 818
 819                         bp->flow_ctrl = FLOW_CTRL_TX;
 820                 }
 821         }
 822 }
 823
 824 static int
 825 bnx2_5709s_linkup(struct bnx2 *bp)
 826 {
 827         u32 val, speed;
 828
 829         bp->link_up = 1;
 830
 831         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 832         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 833         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 834
 835         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 836                 bp->line_speed = bp->req_line_speed;
 837                 bp->duplex = bp->req_duplex;
 838                 return 0;
 839         }
 840         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 841         switch (speed) {
 842                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 843                         bp->line_speed = SPEED_10;
 844                         break;
 845                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 846                         bp->line_speed = SPEED_100;
 847                         break;
 848                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 849                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 850                         bp->line_speed = SPEED_1000;
 851                         break;
 852                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 853                         bp->line_speed = SPEED_2500;
 854                         break;
 855         }
 856         if (val & MII_BNX2_GP_TOP_AN_FD)
 857                 bp->duplex = DUPLEX_FULL;
 858         else
 859                 bp->duplex = DUPLEX_HALF;
 860         return 0;
 861 }
 862
 863 static int
 864 bnx2_5708s_linkup(struct bnx2 *bp)
 865 {
 866         u32 val;
 867
 868         bp->link_up = 1;
 869         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 870         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 871                 case BCM5708S_1000X_STAT1_SPEED_10:
 872                         bp->line_speed = SPEED_10;
 873                         break;
 874                 case BCM5708S_1000X_STAT1_SPEED_100:
 875                         bp->line_speed = SPEED_100;
 876                         break;
 877                 case BCM5708S_1000X_STAT1_SPEED_1G:
 878                         bp->line_speed = SPEED_1000;
 879                         break;
 880                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 881                         bp->line_speed = SPEED_2500;
 882                         break;
 883         }
 884         if (val & BCM5708S_1000X_STAT1_FD)
 885                 bp->duplex = DUPLEX_FULL;
 886         else
 887                 bp->duplex = DUPLEX_HALF;
 888
 889         return 0;
 890 }
 891
 892 static int
 893 bnx2_5706s_linkup(struct bnx2 *bp)
 894 {
 895         u32 bmcr, local_adv, remote_adv, common;
 896
 897         bp->link_up = 1;
 898         bp->line_speed = SPEED_1000;
 899
 900         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 901         if (bmcr & BMCR_FULLDPLX) {
 902                 bp->duplex = DUPLEX_FULL;
 903         }
 904         else {
 905                 bp->duplex = DUPLEX_HALF;
 906         }
 907
 908         if (!(bmcr & BMCR_ANENABLE)) {
 909                 return 0;
 910         }
 911
 912         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 913         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 914
 915         common = local_adv & remote_adv;
 916         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 917
 918                 if (common & ADVERTISE_1000XFULL) {
 919                         bp->duplex = DUPLEX_FULL;
 920                 }
 921                 else {
 922                         bp->duplex = DUPLEX_HALF;
 923                 }
 924         }
 925
 926         return 0;
 927 }
 928
 929 static int
 930 bnx2_copper_linkup(struct bnx2 *bp)
 931 {
 932         u32 bmcr;
 933
 934         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 935         if (bmcr & BMCR_ANENABLE) {
 936                 u32 local_adv, remote_adv, common;
 937
 938                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 939                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 940
 941                 common = local_adv & (remote_adv >> 2);
 942                 if (common & ADVERTISE_1000FULL) {
 943                         bp->line_speed = SPEED_1000;
 944                         bp->duplex = DUPLEX_FULL;
 945                 }
 946                 else if (common & ADVERTISE_1000HALF) {
 947                         bp->line_speed = SPEED_1000;
 948                         bp->duplex = DUPLEX_HALF;
 949                 }
 950                 else {
 951                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 952                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 953
 954                         common = local_adv & remote_adv;
 955                         if (common & ADVERTISE_100FULL) {
 956                                 bp->line_speed = SPEED_100;
 957                                 bp->duplex = DUPLEX_FULL;
 958                         }
 959                         else if (common & ADVERTISE_100HALF) {
 960                                 bp->line_speed = SPEED_100;
 961                                 bp->duplex = DUPLEX_HALF;
 962                         }
 963                         else if (common & ADVERTISE_10FULL) {
 964                                 bp->line_speed = SPEED_10;
 965                                 bp->duplex = DUPLEX_FULL;
 966                         }
 967                         else if (common & ADVERTISE_10HALF) {
 968                                 bp->line_speed = SPEED_10;
 969                                 bp->duplex = DUPLEX_HALF;
 970                         }
 971                         else {
 972                                 bp->line_speed = 0;
 973                                 bp->link_up = 0;
 974                         }
 975                 }
 976         }
 977         else {
 978                 if (bmcr & BMCR_SPEED100) {
 979                         bp->line_speed = SPEED_100;
 980                 }
 981                 else {
 982                         bp->line_speed = SPEED_10;
 983                 }
 984                 if (bmcr & BMCR_FULLDPLX) {
 985                         bp->duplex = DUPLEX_FULL;
 986                 }
 987                 else {
 988                         bp->duplex = DUPLEX_HALF;
 989                 }
 990         }
 991
 992         return 0;
 993 }
 994
 995 static void
 996 bnx2_init_rx_context0(struct bnx2 *bp)
 997 {
 998         u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
 999
1000         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002         val |= 0x02 << 8;
1003
1004         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005                 u32 lo_water, hi_water;
1006
1007                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009                 else
1010                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011                 if (lo_water >= bp->rx_ring_size)
1012                         lo_water = 0;
1013
1014                 hi_water = bp->rx_ring_size / 4;
1015
1016                 if (hi_water <= lo_water)
1017                         lo_water = 0;
1018
1019                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022                 if (hi_water > 0xf)
1023                         hi_water = 0xf;
1024                 else if (hi_water == 0)
1025                         lo_water = 0;
1026                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027         }
1028         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029 }
1030
1031 static int
1032 bnx2_set_mac_link(struct bnx2 *bp)
1033 {
1034         u32 val;
1035
1036         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038                 (bp->duplex == DUPLEX_HALF)) {
1039                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040         }
1041
1042         /* Configure the EMAC mode register. */
1043         val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1046                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1047                 BNX2_EMAC_MODE_25G_MODE);
1048
1049         if (bp->link_up) {
1050                 switch (bp->line_speed) {
1051                         case SPEED_10:
1052                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1054                                         break;
1055                                 }
1056                                 /* fall through */
1057                         case SPEED_100:
1058                                 val |= BNX2_EMAC_MODE_PORT_MII;
1059                                 break;
1060                         case SPEED_2500:
1061                                 val |= BNX2_EMAC_MODE_25G_MODE;
1062                                 /* fall through */
1063                         case SPEED_1000:
1064                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1065                                 break;
1066                 }
1067         }
1068         else {
1069                 val |= BNX2_EMAC_MODE_PORT_GMII;
1070         }
1071
1072         /* Set the MAC to operate in the appropriate duplex mode. */
1073         if (bp->duplex == DUPLEX_HALF)
1074                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075         REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077         /* Enable/disable rx PAUSE. */
1078         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080         if (bp->flow_ctrl & FLOW_CTRL_RX)
1081                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084         /* Enable/disable tx PAUSE. */
1085         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088         if (bp->flow_ctrl & FLOW_CTRL_TX)
1089                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092         /* Acknowledge the interrupt. */
1093         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
1095         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096                 bnx2_init_rx_context0(bp);
1097
1098         return 0;
1099 }
1100
1101 static void
1102 bnx2_enable_bmsr1(struct bnx2 *bp)
1103 {
1104         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1105             (CHIP_NUM(bp) == CHIP_NUM_5709))
1106                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107                                MII_BNX2_BLK_ADDR_GP_STATUS);
1108 }
1109
1110 static void
1111 bnx2_disable_bmsr1(struct bnx2 *bp)
1112 {
1113         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1114             (CHIP_NUM(bp) == CHIP_NUM_5709))
1115                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117 }
1118
1119 static int
1120 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121 {
1122         u32 up1;
1123         int ret = 1;
1124
1125         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1126                 return 0;
1127
1128         if (bp->autoneg & AUTONEG_SPEED)
1129                 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
1131         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
1134         bnx2_read_phy(bp, bp->mii_up1, &up1);
1135         if (!(up1 & BCM5708S_UP1_2G5)) {
1136                 up1 |= BCM5708S_UP1_2G5;
1137                 bnx2_write_phy(bp, bp->mii_up1, up1);
1138                 ret = 0;
1139         }
1140
1141         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
1145         return ret;
1146 }
1147
1148 static int
1149 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150 {
1151         u32 up1;
1152         int ret = 0;
1153
1154         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1155                 return 0;
1156
1157         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
1160         bnx2_read_phy(bp, bp->mii_up1, &up1);
1161         if (up1 & BCM5708S_UP1_2G5) {
1162                 up1 &= ~BCM5708S_UP1_2G5;
1163                 bnx2_write_phy(bp, bp->mii_up1, up1);
1164                 ret = 1;
1165         }
1166
1167         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
1171         return ret;
1172 }
1173
1174 static void
1175 bnx2_enable_forced_2g5(struct bnx2 *bp)
1176 {
1177         u32 bmcr;
1178
1179         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1180                 return;
1181
1182         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183                 u32 val;
1184
1185                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1187                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1197                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199         }
1200
1201         if (bp->autoneg & AUTONEG_SPEED) {
1202                 bmcr &= ~BMCR_ANENABLE;
1203                 if (bp->req_duplex == DUPLEX_FULL)
1204                         bmcr |= BMCR_FULLDPLX;
1205         }
1206         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207 }
1208
1209 static void
1210 bnx2_disable_forced_2g5(struct bnx2 *bp)
1211 {
1212         u32 bmcr;
1213
1214         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1215                 return;
1216
1217         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218                 u32 val;
1219
1220                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1222                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1231                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233         }
1234
1235         if (bp->autoneg & AUTONEG_SPEED)
1236                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238 }
1239
1240 static void
1241 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242 {
1243         u32 val;
1244
1245         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247         if (start)
1248                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249         else
1250                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251 }
1252
1253 static int
1254 bnx2_set_link(struct bnx2 *bp)
1255 {
1256         u32 bmsr;
1257         u8 link_up;
1258
1259         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1260                 bp->link_up = 1;
1261                 return 0;
1262         }
1263
1264         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1265                 return 0;
1266
1267         link_up = bp->link_up;
1268
1269         bnx2_enable_bmsr1(bp);
1270         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272         bnx2_disable_bmsr1(bp);
1273
1274         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1275             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1276                 u32 val, an_dbg;
1277
1278                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1279                         bnx2_5706s_force_link_dn(bp, 0);
1280                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1281                 }
1282                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1283
1284                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
1288                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1290                         bmsr |= BMSR_LSTATUS;
1291                 else
1292                         bmsr &= ~BMSR_LSTATUS;
1293         }
1294
1295         if (bmsr & BMSR_LSTATUS) {
1296                 bp->link_up = 1;
1297
1298                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1299                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300                                 bnx2_5706s_linkup(bp);
1301                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302                                 bnx2_5708s_linkup(bp);
1303                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304                                 bnx2_5709s_linkup(bp);
1305                 }
1306                 else {
1307                         bnx2_copper_linkup(bp);
1308                 }
1309                 bnx2_resolve_flow_ctrl(bp);
1310         }
1311         else {
1312                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1313                     (bp->autoneg & AUTONEG_SPEED))
1314                         bnx2_disable_forced_2g5(bp);
1315
1316                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1317                         u32 bmcr;
1318
1319                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320                         bmcr |= BMCR_ANENABLE;
1321                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1322
1323                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1324                 }
1325                 bp->link_up = 0;
1326         }
1327
1328         if (bp->link_up != link_up) {
1329                 bnx2_report_link(bp);
1330         }
1331
1332         bnx2_set_mac_link(bp);
1333
1334         return 0;
1335 }
1336
1337 static int
1338 bnx2_reset_phy(struct bnx2 *bp)
1339 {
1340         int i;
1341         u32 reg;
1342
1343         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1344
1345 #define PHY_RESET_MAX_WAIT 100
1346         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1347                 udelay(10);
1348
1349                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1350                 if (!(reg & BMCR_RESET)) {
1351                         udelay(20);
1352                         break;
1353                 }
1354         }
1355         if (i == PHY_RESET_MAX_WAIT) {
1356                 return -EBUSY;
1357         }
1358         return 0;
1359 }
1360
1361 static u32
1362 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1363 {
1364         u32 adv = 0;
1365
1366         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1368
1369                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1370                         adv = ADVERTISE_1000XPAUSE;
1371                 }
1372                 else {
1373                         adv = ADVERTISE_PAUSE_CAP;
1374                 }
1375         }
1376         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1377                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1378                         adv = ADVERTISE_1000XPSE_ASYM;
1379                 }
1380                 else {
1381                         adv = ADVERTISE_PAUSE_ASYM;
1382                 }
1383         }
1384         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1385                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1386                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1387                 }
1388                 else {
1389                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1390                 }
1391         }
1392         return adv;
1393 }
1394
1395 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1396
1397 static int
1398 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1399 {
1400         u32 speed_arg = 0, pause_adv;
1401
1402         pause_adv = bnx2_phy_get_pause_adv(bp);
1403
1404         if (bp->autoneg & AUTONEG_SPEED) {
1405                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406                 if (bp->advertising & ADVERTISED_10baseT_Half)
1407                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408                 if (bp->advertising & ADVERTISED_10baseT_Full)
1409                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410                 if (bp->advertising & ADVERTISED_100baseT_Half)
1411                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412                 if (bp->advertising & ADVERTISED_100baseT_Full)
1413                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1418         } else {
1419                 if (bp->req_line_speed == SPEED_2500)
1420                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421                 else if (bp->req_line_speed == SPEED_1000)
1422                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423                 else if (bp->req_line_speed == SPEED_100) {
1424                         if (bp->req_duplex == DUPLEX_FULL)
1425                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1426                         else
1427                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428                 } else if (bp->req_line_speed == SPEED_10) {
1429                         if (bp->req_duplex == DUPLEX_FULL)
1430                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1431                         else
1432                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1433                 }
1434         }
1435
1436         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1438         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1439                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1440
1441         if (port == PORT_TP)
1442                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1444
1445         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1446
1447         spin_unlock_bh(&bp->phy_lock);
1448         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449         spin_lock_bh(&bp->phy_lock);
1450
1451         return 0;
1452 }
1453
1454 static int
1455 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1456 {
1457         u32 adv, bmcr;
1458         u32 new_adv = 0;
1459
1460         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1461                 return (bnx2_setup_remote_phy(bp, port));
1462
1463         if (!(bp->autoneg & AUTONEG_SPEED)) {
1464                 u32 new_bmcr;
1465                 int force_link_down = 0;
1466
1467                 if (bp->req_line_speed == SPEED_2500) {
1468                         if (!bnx2_test_and_enable_2g5(bp))
1469                                 force_link_down = 1;
1470                 } else if (bp->req_line_speed == SPEED_1000) {
1471                         if (bnx2_test_and_disable_2g5(bp))
1472                                 force_link_down = 1;
1473                 }
1474                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1475                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1476
1477                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1478                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1479                 new_bmcr |= BMCR_SPEED1000;
1480
1481                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482                         if (bp->req_line_speed == SPEED_2500)
1483                                 bnx2_enable_forced_2g5(bp);
1484                         else if (bp->req_line_speed == SPEED_1000) {
1485                                 bnx2_disable_forced_2g5(bp);
1486                                 new_bmcr &= ~0x2000;
1487                         }
1488
1489                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1490                         if (bp->req_line_speed == SPEED_2500)
1491                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1492                         else
1493                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1494                 }
1495
1496                 if (bp->req_duplex == DUPLEX_FULL) {
1497                         adv |= ADVERTISE_1000XFULL;
1498                         new_bmcr |= BMCR_FULLDPLX;
1499                 }
1500                 else {
1501                         adv |= ADVERTISE_1000XHALF;
1502                         new_bmcr &= ~BMCR_FULLDPLX;
1503                 }
1504                 if ((new_bmcr != bmcr) || (force_link_down)) {
1505                         /* Force a link down visible on the other side */
1506                         if (bp->link_up) {
1507                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1508                                                ~(ADVERTISE_1000XFULL |
1509                                                  ADVERTISE_1000XHALF));
1510                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1511                                         BMCR_ANRESTART | BMCR_ANENABLE);
1512
1513                                 bp->link_up = 0;
1514                                 netif_carrier_off(bp->dev);
1515                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1516                                 bnx2_report_link(bp);
1517                         }
1518                         bnx2_write_phy(bp, bp->mii_adv, adv);
1519                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1520                 } else {
1521                         bnx2_resolve_flow_ctrl(bp);
1522                         bnx2_set_mac_link(bp);
1523                 }
1524                 return 0;
1525         }
1526
1527         bnx2_test_and_enable_2g5(bp);
1528
1529         if (bp->advertising & ADVERTISED_1000baseT_Full)
1530                 new_adv |= ADVERTISE_1000XFULL;
1531
1532         new_adv |= bnx2_phy_get_pause_adv(bp);
1533
1534         bnx2_read_phy(bp, bp->mii_adv, &adv);
1535         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1536
1537         bp->serdes_an_pending = 0;
1538         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539                 /* Force a link down visible on the other side */
1540                 if (bp->link_up) {
1541                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1542                         spin_unlock_bh(&bp->phy_lock);
1543                         msleep(20);
1544                         spin_lock_bh(&bp->phy_lock);
1545                 }
1546
1547                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1549                         BMCR_ANENABLE);
1550                 /* Speed up link-up time when the link partner
1551                  * does not autonegotiate which is very common
1552                  * in blade servers. Some blade servers use
1553                  * IPMI for kerboard input and it's important
1554                  * to minimize link disruptions. Autoneg. involves
1555                  * exchanging base pages plus 3 next pages and
1556                  * normally completes in about 120 msec.
1557                  */
1558                 bp->current_interval = SERDES_AN_TIMEOUT;
1559                 bp->serdes_an_pending = 1;
1560                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1561         } else {
1562                 bnx2_resolve_flow_ctrl(bp);
1563                 bnx2_set_mac_link(bp);
1564         }
1565
1566         return 0;
1567 }
1568
1569 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1570         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1571                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572                 (ADVERTISED_1000baseT_Full)
1573
1574 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1575         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1576         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1577         ADVERTISED_1000baseT_Full)
1578
1579 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1581
1582 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1583
1584 static void
1585 bnx2_set_default_remote_link(struct bnx2 *bp)
1586 {
1587         u32 link;
1588
1589         if (bp->phy_port == PORT_TP)
1590                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1591         else
1592                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1593
1594         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595                 bp->req_line_speed = 0;
1596                 bp->autoneg |= AUTONEG_SPEED;
1597                 bp->advertising = ADVERTISED_Autoneg;
1598                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599                         bp->advertising |= ADVERTISED_10baseT_Half;
1600                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601                         bp->advertising |= ADVERTISED_10baseT_Full;
1602                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603                         bp->advertising |= ADVERTISED_100baseT_Half;
1604                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605                         bp->advertising |= ADVERTISED_100baseT_Full;
1606                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607                         bp->advertising |= ADVERTISED_1000baseT_Full;
1608                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609                         bp->advertising |= ADVERTISED_2500baseX_Full;
1610         } else {
1611                 bp->autoneg = 0;
1612                 bp->advertising = 0;
1613                 bp->req_duplex = DUPLEX_FULL;
1614                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615                         bp->req_line_speed = SPEED_10;
1616                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617                                 bp->req_duplex = DUPLEX_HALF;
1618                 }
1619                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620                         bp->req_line_speed = SPEED_100;
1621                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622                                 bp->req_duplex = DUPLEX_HALF;
1623                 }
1624                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625                         bp->req_line_speed = SPEED_1000;
1626                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627                         bp->req_line_speed = SPEED_2500;
1628         }
1629 }
1630
1631 static void
1632 bnx2_set_default_link(struct bnx2 *bp)
1633 {
1634         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1635                 bnx2_set_default_remote_link(bp);
1636                 return;
1637         }
1638
1639         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1640         bp->req_line_speed = 0;
1641         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1642                 u32 reg;
1643
1644                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1645
1646                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1647                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1648                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1649                         bp->autoneg = 0;
1650                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1651                         bp->req_duplex = DUPLEX_FULL;
1652                 }
1653         } else
1654                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1655 }
1656
1657 static void
1658 bnx2_send_heart_beat(struct bnx2 *bp)
1659 {
1660         u32 msg;
1661         u32 addr;
1662
1663         spin_lock(&bp->indirect_lock);
1664         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1665         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1666         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1667         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1668         spin_unlock(&bp->indirect_lock);
1669 }
1670
1671 static void
1672 bnx2_remote_phy_event(struct bnx2 *bp)
1673 {
1674         u32 msg;
1675         u8 link_up = bp->link_up;
1676         u8 old_port;
1677
1678         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1679
1680         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1681                 bnx2_send_heart_beat(bp);
1682
1683         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1684
1685         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1686                 bp->link_up = 0;
1687         else {
1688                 u32 speed;
1689
1690                 bp->link_up = 1;
1691                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1692                 bp->duplex = DUPLEX_FULL;
1693                 switch (speed) {
1694                         case BNX2_LINK_STATUS_10HALF:
1695                                 bp->duplex = DUPLEX_HALF;
1696                         case BNX2_LINK_STATUS_10FULL:
1697                                 bp->line_speed = SPEED_10;
1698                                 break;
1699                         case BNX2_LINK_STATUS_100HALF:
1700                                 bp->duplex = DUPLEX_HALF;
1701                         case BNX2_LINK_STATUS_100BASE_T4:
1702                         case BNX2_LINK_STATUS_100FULL:
1703                                 bp->line_speed = SPEED_100;
1704                                 break;
1705                         case BNX2_LINK_STATUS_1000HALF:
1706                                 bp->duplex = DUPLEX_HALF;
1707                         case BNX2_LINK_STATUS_1000FULL:
1708                                 bp->line_speed = SPEED_1000;
1709                                 break;
1710                         case BNX2_LINK_STATUS_2500HALF:
1711                                 bp->duplex = DUPLEX_HALF;
1712                         case BNX2_LINK_STATUS_2500FULL:
1713                                 bp->line_speed = SPEED_2500;
1714                                 break;
1715                         default:
1716                                 bp->line_speed = 0;
1717                                 break;
1718                 }
1719
1720                 bp->flow_ctrl = 0;
1721                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1722                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1723                         if (bp->duplex == DUPLEX_FULL)
1724                                 bp->flow_ctrl = bp->req_flow_ctrl;
1725                 } else {
1726                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1727                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1728                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1729                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1730                 }
1731
1732                 old_port = bp->phy_port;
1733                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1734                         bp->phy_port = PORT_FIBRE;
1735                 else
1736                         bp->phy_port = PORT_TP;
1737
1738                 if (old_port != bp->phy_port)
1739                         bnx2_set_default_link(bp);
1740
1741         }
1742         if (bp->link_up != link_up)
1743                 bnx2_report_link(bp);
1744
1745         bnx2_set_mac_link(bp);
1746 }
1747
1748 static int
1749 bnx2_set_remote_link(struct bnx2 *bp)
1750 {
1751         u32 evt_code;
1752
1753         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1754         switch (evt_code) {
1755                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756                         bnx2_remote_phy_event(bp);
1757                         break;
1758                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1759                 default:
1760                         bnx2_send_heart_beat(bp);
1761                         break;
1762         }
1763         return 0;
1764 }
1765
1766 static int
1767 bnx2_setup_copper_phy(struct bnx2 *bp)
1768 {
1769         u32 bmcr;
1770         u32 new_bmcr;
1771
1772         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1773
1774         if (bp->autoneg & AUTONEG_SPEED) {
1775                 u32 adv_reg, adv1000_reg;
1776                 u32 new_adv_reg = 0;
1777                 u32 new_adv1000_reg = 0;
1778
1779                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1780                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781                         ADVERTISE_PAUSE_ASYM);
1782
1783                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784                 adv1000_reg &= PHY_ALL_1000_SPEED;
1785
1786                 if (bp->advertising & ADVERTISED_10baseT_Half)
1787                         new_adv_reg |= ADVERTISE_10HALF;
1788                 if (bp->advertising & ADVERTISED_10baseT_Full)
1789                         new_adv_reg |= ADVERTISE_10FULL;
1790                 if (bp->advertising & ADVERTISED_100baseT_Half)
1791                         new_adv_reg |= ADVERTISE_100HALF;
1792                 if (bp->advertising & ADVERTISED_100baseT_Full)
1793                         new_adv_reg |= ADVERTISE_100FULL;
1794                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795                         new_adv1000_reg |= ADVERTISE_1000FULL;
1796
1797                 new_adv_reg |= ADVERTISE_CSMA;
1798
1799                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1800
1801                 if ((adv1000_reg != new_adv1000_reg) ||
1802                         (adv_reg != new_adv_reg) ||
1803                         ((bmcr & BMCR_ANENABLE) == 0)) {
1804
1805                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1806                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1807                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1808                                 BMCR_ANENABLE);
1809                 }
1810                 else if (bp->link_up) {
1811                         /* Flow ctrl may have changed from auto to forced */
1812                         /* or vice-versa. */
1813
1814                         bnx2_resolve_flow_ctrl(bp);
1815                         bnx2_set_mac_link(bp);
1816                 }
1817                 return 0;
1818         }
1819
1820         new_bmcr = 0;
1821         if (bp->req_line_speed == SPEED_100) {
1822                 new_bmcr |= BMCR_SPEED100;
1823         }
1824         if (bp->req_duplex == DUPLEX_FULL) {
1825                 new_bmcr |= BMCR_FULLDPLX;
1826         }
1827         if (new_bmcr != bmcr) {
1828                 u32 bmsr;
1829
1830                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1832
1833                 if (bmsr & BMSR_LSTATUS) {
1834                         /* Force link down */
1835                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1836                         spin_unlock_bh(&bp->phy_lock);
1837                         msleep(50);
1838                         spin_lock_bh(&bp->phy_lock);
1839
1840                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1842                 }
1843
1844                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1845
1846                 /* Normally, the new speed is setup after the link has
1847                  * gone down and up again. In some cases, link will not go
1848                  * down so we need to set up the new speed here.
1849                  */
1850                 if (bmsr & BMSR_LSTATUS) {
1851                         bp->line_speed = bp->req_line_speed;
1852                         bp->duplex = bp->req_duplex;
1853                         bnx2_resolve_flow_ctrl(bp);
1854                         bnx2_set_mac_link(bp);
1855                 }
1856         } else {
1857                 bnx2_resolve_flow_ctrl(bp);
1858                 bnx2_set_mac_link(bp);
1859         }
1860         return 0;
1861 }
1862
1863 static int
1864 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1865 {
1866         if (bp->loopback == MAC_LOOPBACK)
1867                 return 0;
1868
1869         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1870                 return (bnx2_setup_serdes_phy(bp, port));
1871         }
1872         else {
1873                 return (bnx2_setup_copper_phy(bp));
1874         }
1875 }
1876
1877 static int
1878 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1879 {
1880         u32 val;
1881
1882         bp->mii_bmcr = MII_BMCR + 0x10;
1883         bp->mii_bmsr = MII_BMSR + 0x10;
1884         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885         bp->mii_adv = MII_ADVERTISE + 0x10;
1886         bp->mii_lpa = MII_LPA + 0x10;
1887         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1888
1889         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891
1892         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1893         if (reset_phy)
1894                 bnx2_reset_phy(bp);
1895
1896         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1897
1898         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1899         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1900         val |= MII_BNX2_SD_1000XCTL1_FIBER;
1901         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1902
1903         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1904         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1905         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
1906                 val |= BCM5708S_UP1_2G5;
1907         else
1908                 val &= ~BCM5708S_UP1_2G5;
1909         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1910
1911         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1912         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1913         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1914         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1915
1916         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1917
1918         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1919               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1920         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1921
1922         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1923
1924         return 0;
1925 }
1926
1927 static int
1928 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
1929 {
1930         u32 val;
1931
1932         if (reset_phy)
1933                 bnx2_reset_phy(bp);
1934
1935         bp->mii_up1 = BCM5708S_UP1;
1936
1937         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1938         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1939         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1940
1941         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1942         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1943         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1944
1945         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1946         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1947         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1948
1949         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
1950                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1951                 val |= BCM5708S_UP1_2G5;
1952                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1953         }
1954
1955         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1956             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1957             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1958                 /* increase tx signal amplitude */
1959                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1960                                BCM5708S_BLK_ADDR_TX_MISC);
1961                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1962                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1963                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1964                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1965         }
1966
1967         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
1968               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1969
1970         if (val) {
1971                 u32 is_backplane;
1972
1973                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
1974                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1975                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1976                                        BCM5708S_BLK_ADDR_TX_MISC);
1977                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1978                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1979                                        BCM5708S_BLK_ADDR_DIG);
1980                 }
1981         }
1982         return 0;
1983 }
1984
1985 static int
1986 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
1987 {
1988         if (reset_phy)
1989                 bnx2_reset_phy(bp);
1990
1991         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1992
1993         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1994                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1995
1996         if (bp->dev->mtu > 1500) {
1997                 u32 val;
1998
1999                 /* Set extended packet length bit */
2000                 bnx2_write_phy(bp, 0x18, 0x7);
2001                 bnx2_read_phy(bp, 0x18, &val);
2002                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2003
2004                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2005                 bnx2_read_phy(bp, 0x1c, &val);
2006                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2007         }
2008         else {
2009                 u32 val;
2010
2011                 bnx2_write_phy(bp, 0x18, 0x7);
2012                 bnx2_read_phy(bp, 0x18, &val);
2013                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2014
2015                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2016                 bnx2_read_phy(bp, 0x1c, &val);
2017                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2018         }
2019
2020         return 0;
2021 }
2022
2023 static int
2024 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2025 {
2026         u32 val;
2027
2028         if (reset_phy)
2029                 bnx2_reset_phy(bp);
2030
2031         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2032                 bnx2_write_phy(bp, 0x18, 0x0c00);
2033                 bnx2_write_phy(bp, 0x17, 0x000a);
2034                 bnx2_write_phy(bp, 0x15, 0x310b);
2035                 bnx2_write_phy(bp, 0x17, 0x201f);
2036                 bnx2_write_phy(bp, 0x15, 0x9506);
2037                 bnx2_write_phy(bp, 0x17, 0x401f);
2038                 bnx2_write_phy(bp, 0x15, 0x14e2);
2039                 bnx2_write_phy(bp, 0x18, 0x0400);
2040         }
2041
2042         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2043                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2044                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2045                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2046                 val &= ~(1 << 8);
2047                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2048         }
2049
2050         if (bp->dev->mtu > 1500) {
2051                 /* Set extended packet length bit */
2052                 bnx2_write_phy(bp, 0x18, 0x7);
2053                 bnx2_read_phy(bp, 0x18, &val);
2054                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2055
2056                 bnx2_read_phy(bp, 0x10, &val);
2057                 bnx2_write_phy(bp, 0x10, val | 0x1);
2058         }
2059         else {
2060                 bnx2_write_phy(bp, 0x18, 0x7);
2061                 bnx2_read_phy(bp, 0x18, &val);
2062                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2063
2064                 bnx2_read_phy(bp, 0x10, &val);
2065                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2066         }
2067
2068         /* ethernet@wirespeed */
2069         bnx2_write_phy(bp, 0x18, 0x7007);
2070         bnx2_read_phy(bp, 0x18, &val);
2071         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2072         return 0;
2073 }
2074
2075
2076 static int
2077 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2078 {
2079         u32 val;
2080         int rc = 0;
2081
2082         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2083         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2084
2085         bp->mii_bmcr = MII_BMCR;
2086         bp->mii_bmsr = MII_BMSR;
2087         bp->mii_bmsr1 = MII_BMSR;
2088         bp->mii_adv = MII_ADVERTISE;
2089         bp->mii_lpa = MII_LPA;
2090
2091         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2092
2093         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2094                 goto setup_phy;
2095
2096         bnx2_read_phy(bp, MII_PHYSID1, &val);
2097         bp->phy_id = val << 16;
2098         bnx2_read_phy(bp, MII_PHYSID2, &val);
2099         bp->phy_id |= val & 0xffff;
2100
2101         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2102                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2103                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2104                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2105                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2106                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2107                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2108         }
2109         else {
2110                 rc = bnx2_init_copper_phy(bp, reset_phy);
2111         }
2112
2113 setup_phy:
2114         if (!rc)
2115                 rc = bnx2_setup_phy(bp, bp->phy_port);
2116
2117         return rc;
2118 }
2119
2120 static int
2121 bnx2_set_mac_loopback(struct bnx2 *bp)
2122 {
2123         u32 mac_mode;
2124
2125         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2126         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2127         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2128         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2129         bp->link_up = 1;
2130         return 0;
2131 }
2132
2133 static int bnx2_test_link(struct bnx2 *);
2134
2135 static int
2136 bnx2_set_phy_loopback(struct bnx2 *bp)
2137 {
2138         u32 mac_mode;
2139         int rc, i;
2140
2141         spin_lock_bh(&bp->phy_lock);
2142         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2143                             BMCR_SPEED1000);
2144         spin_unlock_bh(&bp->phy_lock);
2145         if (rc)
2146                 return rc;
2147
2148         for (i = 0; i < 10; i++) {
2149                 if (bnx2_test_link(bp) == 0)
2150                         break;
2151                 msleep(100);
2152         }
2153
2154         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2155         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2156                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2157                       BNX2_EMAC_MODE_25G_MODE);
2158
2159         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2160         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2161         bp->link_up = 1;
2162         return 0;
2163 }
2164
2165 static int
2166 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2167 {
2168         int i;
2169         u32 val;
2170
2171         bp->fw_wr_seq++;
2172         msg_data |= bp->fw_wr_seq;
2173
2174         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2175
2176         /* wait for an acknowledgement. */
2177         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2178                 msleep(10);
2179
2180                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2181
2182                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2183                         break;
2184         }
2185         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2186                 return 0;
2187
2188         /* If we timed out, inform the firmware that this is the case. */
2189         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2190                 if (!silent)
2191                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2192                                             "%x\n", msg_data);
2193
2194                 msg_data &= ~BNX2_DRV_MSG_CODE;
2195                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2196
2197                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2198
2199                 return -EBUSY;
2200         }
2201
2202         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2203                 return -EIO;
2204
2205         return 0;
2206 }
2207
2208 static int
2209 bnx2_init_5709_context(struct bnx2 *bp)
2210 {
2211         int i, ret = 0;
2212         u32 val;
2213
2214         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2215         val |= (BCM_PAGE_BITS - 8) << 16;
2216         REG_WR(bp, BNX2_CTX_COMMAND, val);
2217         for (i = 0; i < 10; i++) {
2218                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2219                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2220                         break;
2221                 udelay(2);
2222         }
2223         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2224                 return -EBUSY;
2225
2226         for (i = 0; i < bp->ctx_pages; i++) {
2227                 int j;
2228
2229                 if (bp->ctx_blk[i])
2230                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2231                 else
2232                         return -ENOMEM;
2233
2234                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2235                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2236                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2237                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2238                        (u64) bp->ctx_blk_mapping[i] >> 32);
2239                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2240                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2241                 for (j = 0; j < 10; j++) {
2242
2243                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2244                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2245                                 break;
2246                         udelay(5);
2247                 }
2248                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2249                         ret = -EBUSY;
2250                         break;
2251                 }
2252         }
2253         return ret;
2254 }
2255
2256 static void
2257 bnx2_init_context(struct bnx2 *bp)
2258 {
2259         u32 vcid;
2260
2261         vcid = 96;
2262         while (vcid) {
2263                 u32 vcid_addr, pcid_addr, offset;
2264                 int i;
2265
2266                 vcid--;
2267
2268                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2269                         u32 new_vcid;
2270
2271                         vcid_addr = GET_PCID_ADDR(vcid);
2272                         if (vcid & 0x8) {
2273                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2274                         }
2275                         else {
2276                                 new_vcid = vcid;
2277                         }
2278                         pcid_addr = GET_PCID_ADDR(new_vcid);
2279                 }
2280                 else {
2281                         vcid_addr = GET_CID_ADDR(vcid);
2282                         pcid_addr = vcid_addr;
2283                 }
2284
2285                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2286                         vcid_addr += (i << PHY_CTX_SHIFT);
2287                         pcid_addr += (i << PHY_CTX_SHIFT);
2288
2289                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2290                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2291
2292                         /* Zero out the context. */
2293                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2294                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2295                 }
2296         }
2297 }
2298
2299 static int
2300 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2301 {
2302         u16 *good_mbuf;
2303         u32 good_mbuf_cnt;
2304         u32 val;
2305
2306         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2307         if (good_mbuf == NULL) {
2308                 printk(KERN_ERR PFX "Failed to allocate memory in "
2309                                     "bnx2_alloc_bad_rbuf\n");
2310                 return -ENOMEM;
2311         }
2312
2313         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2314                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2315
2316         good_mbuf_cnt = 0;
2317
2318         /* Allocate a bunch of mbufs and save the good ones in an array. */
2319         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2320         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2321                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2322                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2323
2324                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2325
2326                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2327
2328                 /* The addresses with Bit 9 set are bad memory blocks. */
2329                 if (!(val & (1 << 9))) {
2330                         good_mbuf[good_mbuf_cnt] = (u16) val;
2331                         good_mbuf_cnt++;
2332                 }
2333
2334                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2335         }
2336
2337         /* Free the good ones back to the mbuf pool thus discarding
2338          * all the bad ones. */
2339         while (good_mbuf_cnt) {
2340                 good_mbuf_cnt--;
2341
2342                 val = good_mbuf[good_mbuf_cnt];
2343                 val = (val << 9) | val | 1;
2344
2345                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2346         }
2347         kfree(good_mbuf);
2348         return 0;
2349 }
2350
2351 static void
2352 bnx2_set_mac_addr(struct bnx2 *bp)
2353 {
2354         u32 val;
2355         u8 *mac_addr = bp->dev->dev_addr;
2356
2357         val = (mac_addr[0] << 8) | mac_addr[1];
2358
2359         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2360
2361         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2362                 (mac_addr[4] << 8) | mac_addr[5];
2363
2364         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2365 }
2366
2367 static inline int
2368 bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2369 {
2370         dma_addr_t mapping;
2371         struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2372         struct rx_bd *rxbd =
2373                 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2374         struct page *page = alloc_page(GFP_ATOMIC);
2375
2376         if (!page)
2377                 return -ENOMEM;
2378         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2379                                PCI_DMA_FROMDEVICE);
2380         rx_pg->page = page;
2381         pci_unmap_addr_set(rx_pg, mapping, mapping);
2382         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2383         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2384         return 0;
2385 }
2386
2387 static void
2388 bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2389 {
2390         struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2391         struct page *page = rx_pg->page;
2392
2393         if (!page)
2394                 return;
2395
2396         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2397                        PCI_DMA_FROMDEVICE);
2398
2399         __free_page(page);
2400         rx_pg->page = NULL;
2401 }
2402
2403 static inline int
2404 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
2405 {
2406         struct sk_buff *skb;
2407         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2408         dma_addr_t mapping;
2409         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2410         unsigned long align;
2411
2412         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2413         if (skb == NULL) {
2414                 return -ENOMEM;
2415         }
2416
2417         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2418                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2419
2420         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2421                 PCI_DMA_FROMDEVICE);
2422
2423         rx_buf->skb = skb;
2424         pci_unmap_addr_set(rx_buf, mapping, mapping);
2425
2426         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2427         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2428
2429         bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2430
2431         return 0;
2432 }
2433
2434 static int
2435 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2436 {
2437         struct status_block *sblk = bnapi->status_blk;
2438         u32 new_link_state, old_link_state;
2439         int is_set = 1;
2440
2441         new_link_state = sblk->status_attn_bits & event;
2442         old_link_state = sblk->status_attn_bits_ack & event;
2443         if (new_link_state != old_link_state) {
2444                 if (new_link_state)
2445                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2446                 else
2447                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2448         } else
2449                 is_set = 0;
2450
2451         return is_set;
2452 }
2453
2454 static void
2455 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2456 {
2457         spin_lock(&bp->phy_lock);
2458
2459         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2460                 bnx2_set_link(bp);
2461         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2462                 bnx2_set_remote_link(bp);
2463
2464         spin_unlock(&bp->phy_lock);
2465
2466 }
2467
2468 static inline u16
2469 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2470 {
2471         u16 cons;
2472
2473         if (bnapi->int_num == 0)
2474                 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2475         else
2476                 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
2477
2478         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2479                 cons++;
2480         return cons;
2481 }
2482
2483 static int
2484 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2485 {
2486         u16 hw_cons, sw_cons, sw_ring_cons;
2487         int tx_pkt = 0;
2488
2489         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2490         sw_cons = bnapi->tx_cons;
2491
2492         while (sw_cons != hw_cons) {
2493                 struct sw_bd *tx_buf;
2494                 struct sk_buff *skb;
2495                 int i, last;
2496
2497                 sw_ring_cons = TX_RING_IDX(sw_cons);
2498
2499                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2500                 skb = tx_buf->skb;
2501
2502                 /* partial BD completions possible with TSO packets */
2503                 if (skb_is_gso(skb)) {
2504                         u16 last_idx, last_ring_idx;
2505
2506                         last_idx = sw_cons +
2507                                 skb_shinfo(skb)->nr_frags + 1;
2508                         last_ring_idx = sw_ring_cons +
2509                                 skb_shinfo(skb)->nr_frags + 1;
2510                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2511                                 last_idx++;
2512                         }
2513                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2514                                 break;
2515                         }
2516                 }
2517
2518                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2519                         skb_headlen(skb), PCI_DMA_TODEVICE);
2520
2521                 tx_buf->skb = NULL;
2522                 last = skb_shinfo(skb)->nr_frags;
2523
2524                 for (i = 0; i < last; i++) {
2525                         sw_cons = NEXT_TX_BD(sw_cons);
2526
2527                         pci_unmap_page(bp->pdev,
2528                                 pci_unmap_addr(
2529                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2530                                         mapping),
2531                                 skb_shinfo(skb)->frags[i].size,
2532                                 PCI_DMA_TODEVICE);
2533                 }
2534
2535                 sw_cons = NEXT_TX_BD(sw_cons);
2536
2537                 dev_kfree_skb(skb);
2538                 tx_pkt++;
2539                 if (tx_pkt == budget)
2540                         break;
2541
2542                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2543         }
2544
2545         bnapi->hw_tx_cons = hw_cons;
2546         bnapi->tx_cons = sw_cons;
2547         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2548          * before checking for netif_queue_stopped().  Without the
2549          * memory barrier, there is a small possibility that bnx2_start_xmit()
2550          * will miss it and cause the queue to be stopped forever.
2551          */
2552         smp_mb();
2553
2554         if (unlikely(netif_queue_stopped(bp->dev)) &&
2555                      (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2556                 netif_tx_lock(bp->dev);
2557                 if ((netif_queue_stopped(bp->dev)) &&
2558                     (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
2559                         netif_wake_queue(bp->dev);
2560                 netif_tx_unlock(bp->dev);
2561         }
2562         return tx_pkt;
2563 }
2564
2565 static void
2566 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2567                         struct sk_buff *skb, int count)
2568 {
2569         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2570         struct rx_bd *cons_bd, *prod_bd;
2571         dma_addr_t mapping;
2572         int i;
2573         u16 hw_prod = bnapi->rx_pg_prod, prod;
2574         u16 cons = bnapi->rx_pg_cons;
2575
2576         for (i = 0; i < count; i++) {
2577                 prod = RX_PG_RING_IDX(hw_prod);
2578
2579                 prod_rx_pg = &bp->rx_pg_ring[prod];
2580                 cons_rx_pg = &bp->rx_pg_ring[cons];
2581                 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2582                 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2583
2584                 if (i == 0 && skb) {
2585                         struct page *page;
2586                         struct skb_shared_info *shinfo;
2587
2588                         shinfo = skb_shinfo(skb);
2589                         shinfo->nr_frags--;
2590                         page = shinfo->frags[shinfo->nr_frags].page;
2591                         shinfo->frags[shinfo->nr_frags].page = NULL;
2592                         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2593                                                PCI_DMA_FROMDEVICE);
2594                         cons_rx_pg->page = page;
2595                         pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2596                         dev_kfree_skb(skb);
2597                 }
2598                 if (prod != cons) {
2599                         prod_rx_pg->page = cons_rx_pg->page;
2600                         cons_rx_pg->page = NULL;
2601                         pci_unmap_addr_set(prod_rx_pg, mapping,
2602                                 pci_unmap_addr(cons_rx_pg, mapping));
2603
2604                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2605                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2606
2607                 }
2608                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2609                 hw_prod = NEXT_RX_BD(hw_prod);
2610         }
2611         bnapi->rx_pg_prod = hw_prod;
2612         bnapi->rx_pg_cons = cons;
2613 }
2614
2615 static inline void
2616 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2617         u16 cons, u16 prod)
2618 {
2619         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2620         struct rx_bd *cons_bd, *prod_bd;
2621
2622         cons_rx_buf = &bp->rx_buf_ring[cons];
2623         prod_rx_buf = &bp->rx_buf_ring[prod];
2624
2625         pci_dma_sync_single_for_device(bp->pdev,
2626                 pci_unmap_addr(cons_rx_buf, mapping),
2627                 BNX2_RX_OFFSET + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2628
2629         bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2630
2631         prod_rx_buf->skb = skb;
2632
2633         if (cons == prod)
2634                 return;
2635
2636         pci_unmap_addr_set(prod_rx_buf, mapping,
2637                         pci_unmap_addr(cons_rx_buf, mapping));
2638
2639         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2640         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2641         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2642         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2643 }
2644
2645 static int
2646 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2647             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2648             u32 ring_idx)
2649 {
2650         int err;
2651         u16 prod = ring_idx & 0xffff;
2652
2653         err = bnx2_alloc_rx_skb(bp, bnapi, prod);
2654         if (unlikely(err)) {
2655                 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
2656                 if (hdr_len) {
2657                         unsigned int raw_len = len + 4;
2658                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2659
2660                         bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
2661                 }
2662                 return err;
2663         }
2664
2665         skb_reserve(skb, BNX2_RX_OFFSET);
2666         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2667                          PCI_DMA_FROMDEVICE);
2668
2669         if (hdr_len == 0) {
2670                 skb_put(skb, len);
2671                 return 0;
2672         } else {
2673                 unsigned int i, frag_len, frag_size, pages;
2674                 struct sw_pg *rx_pg;
2675                 u16 pg_cons = bnapi->rx_pg_cons;
2676                 u16 pg_prod = bnapi->rx_pg_prod;
2677
2678                 frag_size = len + 4 - hdr_len;
2679                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2680                 skb_put(skb, hdr_len);
2681
2682                 for (i = 0; i < pages; i++) {
2683                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2684                         if (unlikely(frag_len <= 4)) {
2685                                 unsigned int tail = 4 - frag_len;
2686
2687                                 bnapi->rx_pg_cons = pg_cons;
2688                                 bnapi->rx_pg_prod = pg_prod;
2689                                 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2690                                                         pages - i);
2691                                 skb->len -= tail;
2692                                 if (i == 0) {
2693                                         skb->tail -= tail;
2694                                 } else {
2695                                         skb_frag_t *frag =
2696                                                 &skb_shinfo(skb)->frags[i - 1];
2697                                         frag->size -= tail;
2698                                         skb->data_len -= tail;
2699                                         skb->truesize -= tail;
2700                                 }
2701                                 return 0;
2702                         }
2703                         rx_pg = &bp->rx_pg_ring[pg_cons];
2704
2705                         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2706                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2707
2708                         if (i == pages - 1)
2709                                 frag_len -= 4;
2710
2711                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2712                         rx_pg->page = NULL;
2713
2714                         err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2715                         if (unlikely(err)) {
2716                                 bnapi->rx_pg_cons = pg_cons;
2717                                 bnapi->rx_pg_prod = pg_prod;
2718                                 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2719                                                         pages - i);
2720                                 return err;
2721                         }
2722
2723                         frag_size -= frag_len;
2724                         skb->data_len += frag_len;
2725                         skb->truesize += frag_len;
2726                         skb->len += frag_len;
2727
2728                         pg_prod = NEXT_RX_BD(pg_prod);
2729                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2730                 }
2731                 bnapi->rx_pg_prod = pg_prod;
2732                 bnapi->rx_pg_cons = pg_cons;
2733         }
2734         return 0;
2735 }
2736
2737 static inline u16
2738 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2739 {
2740         u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
2741
2742         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2743                 cons++;
2744         return cons;
2745 }
2746
2747 static int
2748 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2749 {
2750         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2751         struct l2_fhdr *rx_hdr;
2752         int rx_pkt = 0, pg_ring_used = 0;
2753
2754         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2755         sw_cons = bnapi->rx_cons;
2756         sw_prod = bnapi->rx_prod;
2757
2758         /* Memory barrier necessary as speculative reads of the rx
2759          * buffer can be ahead of the index in the status block
2760          */
2761         rmb();
2762         while (sw_cons != hw_cons) {
2763                 unsigned int len, hdr_len;
2764                 u32 status;
2765                 struct sw_bd *rx_buf;
2766                 struct sk_buff *skb;
2767                 dma_addr_t dma_addr;
2768
2769                 sw_ring_cons = RX_RING_IDX(sw_cons);
2770                 sw_ring_prod = RX_RING_IDX(sw_prod);
2771
2772                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2773                 skb = rx_buf->skb;
2774
2775                 rx_buf->skb = NULL;
2776
2777                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2778
2779                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2780                         BNX2_RX_OFFSET + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2781
2782                 rx_hdr = (struct l2_fhdr *) skb->data;
2783                 len = rx_hdr->l2_fhdr_pkt_len;
2784
2785                 if ((status = rx_hdr->l2_fhdr_status) &
2786                         (L2_FHDR_ERRORS_BAD_CRC |
2787                         L2_FHDR_ERRORS_PHY_DECODE |
2788                         L2_FHDR_ERRORS_ALIGNMENT |
2789                         L2_FHDR_ERRORS_TOO_SHORT |
2790                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2791
2792                         bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2793                                           sw_ring_prod);
2794                         goto next_rx;
2795                 }
2796                 hdr_len = 0;
2797                 if (status & L2_FHDR_STATUS_SPLIT) {
2798                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2799                         pg_ring_used = 1;
2800                 } else if (len > bp->rx_jumbo_thresh) {
2801                         hdr_len = bp->rx_jumbo_thresh;
2802                         pg_ring_used = 1;
2803                 }
2804
2805                 len -= 4;
2806
2807                 if (len <= bp->rx_copy_thresh) {
2808                         struct sk_buff *new_skb;
2809
2810                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
2811                         if (new_skb == NULL) {
2812                                 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2813                                                   sw_ring_prod);
2814                                 goto next_rx;
2815                         }
2816
2817                         /* aligned copy */
2818                         skb_copy_from_linear_data_offset(skb,
2819                                                          BNX2_RX_OFFSET - 2,
2820                                       new_skb->data, len + 2);
2821                         skb_reserve(new_skb, 2);
2822                         skb_put(new_skb, len);
2823
2824                         bnx2_reuse_rx_skb(bp, bnapi, skb,
2825                                 sw_ring_cons, sw_ring_prod);
2826
2827                         skb = new_skb;
2828                 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2829                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2830                         goto next_rx;
2831
2832                 skb->protocol = eth_type_trans(skb, bp->dev);
2833
2834                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2835                         (ntohs(skb->protocol) != 0x8100)) {
2836
2837                         dev_kfree_skb(skb);
2838                         goto next_rx;
2839
2840                 }
2841
2842                 skb->ip_summed = CHECKSUM_NONE;
2843                 if (bp->rx_csum &&
2844                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2845                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2846
2847                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2848                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2849                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2850                 }
2851
2852 #ifdef BCM_VLAN
2853                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
2854                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2855                                 rx_hdr->l2_fhdr_vlan_tag);
2856                 }
2857                 else
2858 #endif
2859                         netif_receive_skb(skb);
2860
2861                 bp->dev->last_rx = jiffies;
2862                 rx_pkt++;
2863
2864 next_rx:
2865                 sw_cons = NEXT_RX_BD(sw_cons);
2866                 sw_prod = NEXT_RX_BD(sw_prod);
2867
2868                 if ((rx_pkt == budget))
2869                         break;
2870
2871                 /* Refresh hw_cons to see if there is new work */
2872                 if (sw_cons == hw_cons) {
2873                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2874                         rmb();
2875                 }
2876         }
2877         bnapi->rx_cons = sw_cons;
2878         bnapi->rx_prod = sw_prod;
2879
2880         if (pg_ring_used)
2881                 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
2882                          bnapi->rx_pg_prod);
2883
2884         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2885
2886         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
2887
2888         mmiowb();
2889
2890         return rx_pkt;
2891
2892 }
2893
2894 /* MSI ISR - The only difference between this and the INTx ISR
2895  * is that the MSI interrupt is always serviced.
2896  */
2897 static irqreturn_t
2898 bnx2_msi(int irq, void *dev_instance)
2899 {
2900         struct net_device *dev = dev_instance;
2901         struct bnx2 *bp = netdev_priv(dev);
2902         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2903
2904         prefetch(bnapi->status_blk);
2905         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2906                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2907                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2908
2909         /* Return here if interrupt is disabled. */
2910         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2911                 return IRQ_HANDLED;
2912
2913         netif_rx_schedule(dev, &bnapi->napi);
2914
2915         return IRQ_HANDLED;
2916 }
2917
2918 static irqreturn_t
2919 bnx2_msi_1shot(int irq, void *dev_instance)
2920 {
2921         struct net_device *dev = dev_instance;
2922         struct bnx2 *bp = netdev_priv(dev);
2923         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2924
2925         prefetch(bnapi->status_blk);
2926
2927         /* Return here if interrupt is disabled. */
2928         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2929                 return IRQ_HANDLED;
2930
2931         netif_rx_schedule(dev, &bnapi->napi);
2932
2933         return IRQ_HANDLED;
2934 }
2935
2936 static irqreturn_t
2937 bnx2_interrupt(int irq, void *dev_instance)
2938 {
2939         struct net_device *dev = dev_instance;
2940         struct bnx2 *bp = netdev_priv(dev);
2941         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2942         struct status_block *sblk = bnapi->status_blk;
2943
2944         /* When using INTx, it is possible for the interrupt to arrive
2945          * at the CPU before the status block posted prior to the
2946          * interrupt. Reading a register will flush the status block.
2947          * When using MSI, the MSI message will always complete after
2948          * the status block write.
2949          */
2950         if ((sblk->status_idx == bnapi->last_status_idx) &&
2951             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2952              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2953                 return IRQ_NONE;
2954
2955         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2956                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2957                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2958
2959         /* Read back to deassert IRQ immediately to avoid too many
2960          * spurious interrupts.
2961          */
2962         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2963
2964         /* Return here if interrupt is shared and is disabled. */
2965         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2966                 return IRQ_HANDLED;
2967
2968         if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2969                 bnapi->last_status_idx = sblk->status_idx;
2970                 __netif_rx_schedule(dev, &bnapi->napi);
2971         }
2972
2973         return IRQ_HANDLED;
2974 }
2975
2976 static irqreturn_t
2977 bnx2_tx_msix(int irq, void *dev_instance)
2978 {
2979         struct net_device *dev = dev_instance;
2980         struct bnx2 *bp = netdev_priv(dev);
2981         struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2982
2983         prefetch(bnapi->status_blk_msix);
2984
2985         /* Return here if interrupt is disabled. */
2986         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2987                 return IRQ_HANDLED;
2988
2989         netif_rx_schedule(dev, &bnapi->napi);
2990         return IRQ_HANDLED;
2991 }
2992
2993 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
2994                                  STATUS_ATTN_BITS_TIMER_ABORT)
2995
2996 static inline int
2997 bnx2_has_work(struct bnx2_napi *bnapi)
2998 {
2999         struct status_block *sblk = bnapi->status_blk;
3000
3001         if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
3002             (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
3003                 return 1;
3004
3005         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3006             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3007                 return 1;
3008
3009         return 0;
3010 }
3011
3012 static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3013 {
3014         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3015         struct bnx2 *bp = bnapi->bp;
3016         int work_done = 0;
3017         struct status_block_msix *sblk = bnapi->status_blk_msix;
3018
3019         do {
3020                 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3021                 if (unlikely(work_done >= budget))
3022                         return work_done;
3023
3024                 bnapi->last_status_idx = sblk->status_idx;
3025                 rmb();
3026         } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3027
3028         netif_rx_complete(bp->dev, napi);
3029         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3030                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3031                bnapi->last_status_idx);
3032         return work_done;
3033 }
3034
3035 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3036                           int work_done, int budget)
3037 {
3038         struct status_block *sblk = bnapi->status_blk;
3039         u32 status_attn_bits = sblk->status_attn_bits;
3040         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3041
3042         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3043             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3044
3045                 bnx2_phy_int(bp, bnapi);
3046
3047                 /* This is needed to take care of transient status
3048                  * during link changes.
3049                  */
3050                 REG_WR(bp, BNX2_HC_COMMAND,
3051                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3052                 REG_RD(bp, BNX2_HC_COMMAND);
3053         }
3054
3055         if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
3056                 bnx2_tx_int(bp, bnapi, 0);
3057
3058         if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
3059                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3060
3061         return work_done;
3062 }
3063
3064 static int bnx2_poll(struct napi_struct *napi, int budget)
3065 {
3066         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3067         struct bnx2 *bp = bnapi->bp;
3068         int work_done = 0;
3069         struct status_block *sblk = bnapi->status_blk;
3070
3071         while (1) {
3072                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3073
3074                 if (unlikely(work_done >= budget))
3075                         break;
3076
3077                 /* bnapi->last_status_idx is used below to tell the hw how
3078                  * much work has been processed, so we must read it before
3079                  * checking for more work.
3080                  */
3081                 bnapi->last_status_idx = sblk->status_idx;
3082                 rmb();
3083                 if (likely(!bnx2_has_work(bnapi))) {
3084                         netif_rx_complete(bp->dev, napi);
3085                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3086                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3087                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3088                                        bnapi->last_status_idx);
3089                                 break;
3090                         }
3091                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3092                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3093                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3094                                bnapi->last_status_idx);
3095
3096                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3097                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3098                                bnapi->last_status_idx);
3099                         break;
3100                 }
3101         }
3102
3103         return work_done;
3104 }
3105
3106 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3107  * from set_multicast.
3108  */
3109 static void
3110 bnx2_set_rx_mode(struct net_device *dev)
3111 {
3112         struct bnx2 *bp = netdev_priv(dev);
3113         u32 rx_mode, sort_mode;
3114         int i;
3115
3116         spin_lock_bh(&bp->phy_lock);
3117
3118         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3119                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3120         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3121 #ifdef BCM_VLAN
3122         if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
3123                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3124 #else
3125         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
3126                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3127 #endif
3128         if (dev->flags & IFF_PROMISC) {
3129                 /* Promiscuous mode. */
3130                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3131                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3132                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3133         }
3134         else if (dev->flags & IFF_ALLMULTI) {
3135                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3136                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3137                                0xffffffff);
3138                 }
3139                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3140         }
3141         else {
3142                 /* Accept one or more multicast(s). */
3143                 struct dev_mc_list *mclist;
3144                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3145                 u32 regidx;
3146                 u32 bit;
3147                 u32 crc;
3148
3149                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3150
3151                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3152                      i++, mclist = mclist->next) {
3153
3154                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3155                         bit = crc & 0xff;
3156                         regidx = (bit & 0xe0) >> 5;
3157                         bit &= 0x1f;
3158                         mc_filter[regidx] |= (1 << bit);
3159                 }
3160
3161                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3162                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3163                                mc_filter[i]);
3164                 }
3165
3166                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3167         }
3168
3169         if (rx_mode != bp->rx_mode) {
3170                 bp->rx_mode = rx_mode;
3171                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3172         }
3173
3174         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3175         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3176         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3177
3178         spin_unlock_bh(&bp->phy_lock);
3179 }
3180
3181 static void
3182 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3183         u32 rv2p_proc)
3184 {
3185         int i;
3186         u32 val;
3187
3188         if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3189                 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3190                 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3191                 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3192                 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3193         }
3194
3195         for (i = 0; i < rv2p_code_len; i += 8) {
3196                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3197                 rv2p_code++;
3198                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3199                 rv2p_code++;
3200
3201                 if (rv2p_proc == RV2P_PROC1) {
3202                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3203                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3204                 }
3205                 else {
3206                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3207                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3208                 }
3209         }
3210
3211         /* Reset the processor, un-stall is done later. */
3212         if (rv2p_proc == RV2P_PROC1) {
3213                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3214         }
3215         else {
3216                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3217         }
3218 }
3219
3220 static int
3221 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3222 {
3223         u32 offset;
3224         u32 val;
3225         int rc;
3226
3227         /* Halt the CPU. */
3228         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3229         val |= cpu_reg->mode_value_halt;
3230         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3231         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3232
3233         /* Load the Text area. */
3234         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3235         if (fw->gz_text) {
3236                 int j;
3237
3238                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3239                                        fw->gz_text_len);
3240                 if (rc < 0)
3241                         return rc;
3242
3243                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3244                         bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3245                 }
3246         }
3247
3248         /* Load the Data area. */
3249         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3250         if (fw->data) {
3251                 int j;
3252
3253                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3254                         bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3255                 }
3256         }
3257
3258         /* Load the SBSS area. */
3259         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3260         if (fw->sbss_len) {
3261                 int j;
3262
3263                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3264                         bnx2_reg_wr_ind(bp, offset, 0);
3265                 }
3266         }
3267
3268         /* Load the BSS area. */
3269         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3270         if (fw->bss_len) {
3271                 int j;
3272
3273                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3274                         bnx2_reg_wr_ind(bp, offset, 0);
3275                 }
3276         }
3277
3278         /* Load the Read-Only area. */
3279         offset = cpu_reg->spad_base +
3280                 (fw->rodata_addr - cpu_reg->mips_view_base);
3281         if (fw->rodata) {
3282                 int j;
3283
3284                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3285                         bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3286                 }
3287         }
3288
3289         /* Clear the pre-fetch instruction. */
3290         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3291         bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3292
3293         /* Start the CPU. */
3294         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3295         val &= ~cpu_reg->mode_value_halt;
3296         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3297         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3298
3299         return 0;
3300 }
3301
3302 static int
3303 bnx2_init_cpus(struct bnx2 *bp)
3304 {
3305         struct cpu_reg cpu_reg;
3306         struct fw_info *fw;
3307         int rc, rv2p_len;
3308         void *text, *rv2p;
3309
3310         /* Initialize the RV2P processor. */
3311         text = vmalloc(FW_BUF_SIZE);
3312         if (!text)
3313                 return -ENOMEM;
3314         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3315                 rv2p = bnx2_xi_rv2p_proc1;
3316                 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3317         } else {
3318                 rv2p = bnx2_rv2p_proc1;
3319                 rv2p_len = sizeof(bnx2_rv2p_proc1);
3320         }
3321         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3322         if (rc < 0)
3323                 goto init_cpu_err;
3324
3325         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3326
3327         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3328                 rv2p = bnx2_xi_rv2p_proc2;
3329                 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3330         } else {
3331                 rv2p = bnx2_rv2p_proc2;
3332                 rv2p_len = sizeof(bnx2_rv2p_proc2);
3333         }
3334         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3335         if (rc < 0)
3336                 goto init_cpu_err;
3337
3338         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3339
3340         /* Initialize the RX Processor. */
3341         cpu_reg.mode = BNX2_RXP_CPU_MODE;
3342         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3343         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3344         cpu_reg.state = BNX2_RXP_CPU_STATE;
3345         cpu_reg.state_value_clear = 0xffffff;
3346         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3347         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3348         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3349         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3350         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3351         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3352         cpu_reg.mips_view_base = 0x8000000;
3353
3354         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3355                 fw = &bnx2_rxp_fw_09;
3356         else
3357                 fw = &bnx2_rxp_fw_06;
3358
3359         fw->text = text;
3360         rc = load_cpu_fw(bp, &cpu_reg, fw);
3361         if (rc)
3362                 goto init_cpu_err;
3363
3364         /* Initialize the TX Processor. */
3365         cpu_reg.mode = BNX2_TXP_CPU_MODE;
3366         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3367         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3368         cpu_reg.state = BNX2_TXP_CPU_STATE;
3369         cpu_reg.state_value_clear = 0xffffff;
3370         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3371         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3372         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3373         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3374         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3375         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3376         cpu_reg.mips_view_base = 0x8000000;
3377
3378         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3379                 fw = &bnx2_txp_fw_09;
3380         else
3381                 fw = &bnx2_txp_fw_06;
3382
3383         fw->text = text;
3384         rc = load_cpu_fw(bp, &cpu_reg, fw);
3385         if (rc)
3386                 goto init_cpu_err;
3387
3388         /* Initialize the TX Patch-up Processor. */
3389         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3390         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3391         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3392         cpu_reg.state = BNX2_TPAT_CPU_STATE;
3393         cpu_reg.state_value_clear = 0xffffff;
3394         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3395         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3396         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3397         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3398         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3399         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3400         cpu_reg.mips_view_base = 0x8000000;
3401
3402         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3403                 fw = &bnx2_tpat_fw_09;
3404         else
3405                 fw = &bnx2_tpat_fw_06;
3406
3407         fw->text = text;
3408         rc = load_cpu_fw(bp, &cpu_reg, fw);
3409         if (rc)
3410                 goto init_cpu_err;
3411
3412         /* Initialize the Completion Processor. */
3413         cpu_reg.mode = BNX2_COM_CPU_MODE;
3414         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3415         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3416         cpu_reg.state = BNX2_COM_CPU_STATE;
3417         cpu_reg.state_value_clear = 0xffffff;
3418         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3419         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3420         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3421         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3422         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3423         cpu_reg.spad_base = BNX2_COM_SCRATCH;
3424         cpu_reg.mips_view_base = 0x8000000;
3425
3426         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3427                 fw = &bnx2_com_fw_09;
3428         else
3429                 fw = &bnx2_com_fw_06;
3430
3431         fw->text = text;
3432         rc = load_cpu_fw(bp, &cpu_reg, fw);
3433         if (rc)
3434                 goto init_cpu_err;
3435
3436         /* Initialize the Command Processor. */
3437         cpu_reg.mode = BNX2_CP_CPU_MODE;
3438         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3439         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3440         cpu_reg.state = BNX2_CP_CPU_STATE;
3441         cpu_reg.state_value_clear = 0xffffff;
3442         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3443         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3444         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3445         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3446         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3447         cpu_reg.spad_base = BNX2_CP_SCRATCH;
3448         cpu_reg.mips_view_base = 0x8000000;
3449
3450         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3451                 fw = &bnx2_cp_fw_09;
3452         else
3453                 fw = &bnx2_cp_fw_06;
3454
3455         fw->text = text;
3456         rc = load_cpu_fw(bp, &cpu_reg, fw);
3457
3458 init_cpu_err:
3459         vfree(text);
3460         return rc;
3461 }
3462
3463 static int
3464 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3465 {
3466         u16 pmcsr;
3467
3468         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3469
3470         switch (state) {
3471         case PCI_D0: {
3472                 u32 val;
3473
3474                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3475                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3476                         PCI_PM_CTRL_PME_STATUS);
3477
3478                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3479                         /* delay required during transition out of D3hot */
3480                         msleep(20);
3481
3482                 val = REG_RD(bp, BNX2_EMAC_MODE);
3483                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3484                 val &= ~BNX2_EMAC_MODE_MPKT;
3485                 REG_WR(bp, BNX2_EMAC_MODE, val);
3486
3487                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3488                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3489                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3490                 break;
3491         }
3492         case PCI_D3hot: {
3493                 int i;
3494                 u32 val, wol_msg;
3495
3496                 if (bp->wol) {
3497                         u32 advertising;
3498                         u8 autoneg;
3499
3500                         autoneg = bp->autoneg;
3501                         advertising = bp->advertising;
3502
3503                         if (bp->phy_port == PORT_TP) {
3504                                 bp->autoneg = AUTONEG_SPEED;
3505                                 bp->advertising = ADVERTISED_10baseT_Half |
3506                                         ADVERTISED_10baseT_Full |
3507                                         ADVERTISED_100baseT_Half |
3508                                         ADVERTISED_100baseT_Full |
3509                                         ADVERTISED_Autoneg;
3510                         }
3511
3512                         spin_lock_bh(&bp->phy_lock);
3513                         bnx2_setup_phy(bp, bp->phy_port);
3514                         spin_unlock_bh(&bp->phy_lock);
3515
3516                         bp->autoneg = autoneg;
3517                         bp->advertising = advertising;
3518
3519                         bnx2_set_mac_addr(bp);
3520
3521                         val = REG_RD(bp, BNX2_EMAC_MODE);
3522
3523                         /* Enable port mode. */
3524                         val &= ~BNX2_EMAC_MODE_PORT;
3525                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3526                                BNX2_EMAC_MODE_ACPI_RCVD |
3527                                BNX2_EMAC_MODE_MPKT;
3528                         if (bp->phy_port == PORT_TP)
3529                                 val |= BNX2_EMAC_MODE_PORT_MII;
3530                         else {
3531                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3532                                 if (bp->line_speed == SPEED_2500)
3533                                         val |= BNX2_EMAC_MODE_25G_MODE;
3534                         }
3535
3536                         REG_WR(bp, BNX2_EMAC_MODE, val);
3537
3538                         /* receive all multicast */
3539                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3540                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3541                                        0xffffffff);
3542                         }
3543                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3544                                BNX2_EMAC_RX_MODE_SORT_MODE);
3545
3546                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3547                               BNX2_RPM_SORT_USER0_MC_EN;
3548                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3549                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3550                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3551                                BNX2_RPM_SORT_USER0_ENA);
3552
3553                         /* Need to enable EMAC and RPM for WOL. */
3554                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3555                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3556                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3557                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3558
3559                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3560                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3561                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3562
3563                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3564                 }
3565                 else {
3566                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3567                 }
3568
3569                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3570                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3571
3572                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3573                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3574                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3575
3576                         if (bp->wol)
3577                                 pmcsr |= 3;
3578                 }
3579                 else {
3580                         pmcsr |= 3;
3581                 }
3582                 if (bp->wol) {
3583                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3584                 }
3585                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3586                                       pmcsr);
3587
3588                 /* No more memory access after this point until
3589                  * device is brought back to D0.
3590                  */
3591                 udelay(50);
3592                 break;
3593         }
3594         default:
3595                 return -EINVAL;
3596         }
3597         return 0;
3598 }
3599
3600 static int
3601 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3602 {
3603         u32 val;
3604         int j;
3605
3606         /* Request access to the flash interface. */
3607         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3608         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3609                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3610                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3611                         break;
3612
3613                 udelay(5);
3614         }
3615
3616         if (j >= NVRAM_TIMEOUT_COUNT)
3617                 return -EBUSY;
3618
3619         return 0;
3620 }
3621
3622 static int
3623 bnx2_release_nvram_lock(struct bnx2 *bp)
3624 {
3625         int j;
3626         u32 val;
3627
3628         /* Relinquish nvram interface. */
3629         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3630
3631         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3632                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3633                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3634                         break;
3635
3636                 udelay(5);
3637         }
3638
3639         if (j >= NVRAM_TIMEOUT_COUNT)
3640                 return -EBUSY;
3641
3642         return 0;
3643 }
3644
3645
3646 static int
3647 bnx2_enable_nvram_write(struct bnx2 *bp)
3648 {
3649         u32 val;
3650
3651         val = REG_RD(bp, BNX2_MISC_CFG);
3652         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3653
3654         if (bp->flash_info->flags & BNX2_NV_WREN) {
3655                 int j;
3656
3657                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3658                 REG_WR(bp, BNX2_NVM_COMMAND,
3659                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3660
3661                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3662                         udelay(5);
3663
3664                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3665                         if (val & BNX2_NVM_COMMAND_DONE)
3666                                 break;
3667                 }
3668
3669                 if (j >= NVRAM_TIMEOUT_COUNT)
3670                         return -EBUSY;
3671         }
3672         return 0;
3673 }
3674
3675 static void
3676 bnx2_disable_nvram_write(struct bnx2 *bp)
3677 {
3678         u32 val;
3679
3680         val = REG_RD(bp, BNX2_MISC_CFG);
3681         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3682 }
3683
3684
3685 static void
3686 bnx2_enable_nvram_access(struct bnx2 *bp)
3687 {
3688         u32 val;
3689
3690         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3691         /* Enable both bits, even on read. */
3692         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3693                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3694 }
3695
3696 static void
3697 bnx2_disable_nvram_access(struct bnx2 *bp)
3698 {
3699         u32 val;
3700
3701         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3702         /* Disable both bits, even after read. */
3703         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3704                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3705                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3706 }
3707
3708 static int
3709 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3710 {
3711         u32 cmd;
3712         int j;
3713
3714         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3715                 /* Buffered flash, no erase needed */
3716                 return 0;
3717
3718         /* Build an erase command */
3719         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3720               BNX2_NVM_COMMAND_DOIT;
3721
3722         /* Need to clear DONE bit separately. */
3723         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3724
3725         /* Address of the NVRAM to read from. */
3726         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3727
3728         /* Issue an erase command. */
3729         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3730
3731         /* Wait for completion. */
3732         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3733                 u32 val;
3734
3735                 udelay(5);
3736
3737                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3738                 if (val & BNX2_NVM_COMMAND_DONE)
3739                         break;
3740         }
3741
3742         if (j >= NVRAM_TIMEOUT_COUNT)
3743                 return -EBUSY;
3744
3745         return 0;
3746 }
3747
3748 static int
3749 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3750 {
3751         u32 cmd;
3752         int j;
3753
3754         /* Build the command word. */
3755         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3756
3757         /* Calculate an offset of a buffered flash, not needed for 5709. */
3758         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3759                 offset = ((offset / bp->flash_info->page_size) <<
3760                            bp->flash_info->page_bits) +
3761                           (offset % bp->flash_info->page_size);
3762         }
3763
3764         /* Need to clear DONE bit separately. */
3765         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3766
3767         /* Address of the NVRAM to read from. */
3768         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3769
3770         /* Issue a read command. */
3771         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3772
3773         /* Wait for completion. */
3774         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3775                 u32 val;
3776
3777                 udelay(5);
3778
3779                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3780                 if (val & BNX2_NVM_COMMAND_DONE) {
3781                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3782                         memcpy(ret_val, &v, 4);
3783                         break;
3784                 }
3785         }
3786         if (j >= NVRAM_TIMEOUT_COUNT)
3787                 return -EBUSY;
3788
3789         return 0;
3790 }
3791
3792
3793 static int
3794 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3795 {
3796         u32 cmd;
3797         __be32 val32;
3798         int j;
3799
3800         /* Build the command word. */
3801         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3802
3803         /* Calculate an offset of a buffered flash, not needed for 5709. */
3804         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3805                 offset = ((offset / bp->flash_info->page_size) <<
3806                           bp->flash_info->page_bits) +
3807                          (offset % bp->flash_info->page_size);
3808         }
3809
3810         /* Need to clear DONE bit separately. */
3811         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3812
3813         memcpy(&val32, val, 4);
3814
3815         /* Write the data. */
3816         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3817
3818         /* Address of the NVRAM to write to. */
3819         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3820
3821         /* Issue the write command. */
3822         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3823
3824         /* Wait for completion. */
3825         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3826                 udelay(5);
3827
3828                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3829                         break;
3830         }
3831         if (j >= NVRAM_TIMEOUT_COUNT)
3832                 return -EBUSY;
3833
3834         return 0;
3835 }
3836
3837 static int
3838 bnx2_init_nvram(struct bnx2 *bp)
3839 {
3840         u32 val;
3841         int j, entry_count, rc = 0;
3842         struct flash_spec *flash;
3843
3844         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3845                 bp->flash_info = &flash_5709;
3846                 goto get_flash_size;
3847         }
3848
3849         /* Determine the selected interface. */
3850         val = REG_RD(bp, BNX2_NVM_CFG1);
3851
3852         entry_count = ARRAY_SIZE(flash_table);
3853
3854         if (val & 0x40000000) {
3855
3856                 /* Flash interface has been reconfigured */
3857                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3858                      j++, flash++) {
3859                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3860                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3861                                 bp->flash_info = flash;
3862                                 break;
3863                         }
3864                 }
3865         }
3866         else {
3867                 u32 mask;
3868                 /* Not yet been reconfigured */
3869
3870                 if (val & (1 << 23))
3871                         mask = FLASH_BACKUP_STRAP_MASK;
3872                 else
3873                         mask = FLASH_STRAP_MASK;
3874
3875                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3876                         j++, flash++) {
3877
3878                         if ((val & mask) == (flash->strapping & mask)) {
3879                                 bp->flash_info = flash;
3880
3881                                 /* Request access to the flash interface. */
3882                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3883                                         return rc;
3884
3885                                 /* Enable access to flash interface */
3886                                 bnx2_enable_nvram_access(bp);
3887
3888                                 /* Reconfigure the flash interface */
3889                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3890                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3891                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3892                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3893
3894                                 /* Disable access to flash interface */
3895                                 bnx2_disable_nvram_access(bp);
3896                                 bnx2_release_nvram_lock(bp);
3897
3898                                 break;
3899                         }
3900                 }
3901         } /* if (val & 0x40000000) */
3902
3903         if (j == entry_count) {
3904                 bp->flash_info = NULL;
3905                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3906                 return -ENODEV;
3907         }
3908
3909 get_flash_size:
3910         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
3911         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3912         if (val)
3913                 bp->flash_size = val;
3914         else
3915                 bp->flash_size = bp->flash_info->total_size;
3916
3917         return rc;
3918 }
3919
3920 static int
3921 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3922                 int buf_size)
3923 {
3924         int rc = 0;
3925         u32 cmd_flags, offset32, len32, extra;
3926
3927         if (buf_size == 0)
3928                 return 0;
3929
3930         /* Request access to the flash interface. */
3931         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3932                 return rc;
3933
3934         /* Enable access to flash interface */
3935         bnx2_enable_nvram_access(bp);
3936
3937         len32 = buf_size;
3938         offset32 = offset;
3939         extra = 0;
3940
3941         cmd_flags = 0;
3942
3943         if (offset32 & 3) {
3944                 u8 buf[4];
3945                 u32 pre_len;
3946
3947                 offset32 &= ~3;
3948                 pre_len = 4 - (offset & 3);
3949
3950                 if (pre_len >= len32) {
3951                         pre_len = len32;
3952                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3953                                     BNX2_NVM_COMMAND_LAST;
3954                 }
3955                 else {
3956                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3957                 }
3958
3959                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3960
3961                 if (rc)
3962                         return rc;
3963
3964                 memcpy(ret_buf, buf + (offset & 3), pre_len);
3965
3966                 offset32 += 4;
3967                 ret_buf += pre_len;
3968                 len32 -= pre_len;
3969         }
3970         if (len32 & 3) {
3971                 extra = 4 - (len32 & 3);
3972                 len32 = (len32 + 4) & ~3;
3973         }
3974
3975         if (len32 == 4) {
3976                 u8 buf[4];
3977
3978                 if (cmd_flags)
3979                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3980                 else
3981                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3982                                     BNX2_NVM_COMMAND_LAST;
3983
3984                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3985
3986                 memcpy(ret_buf, buf, 4 - extra);
3987         }
3988         else if (len32 > 0) {
3989                 u8 buf[4];
3990
3991                 /* Read the first word. */
3992                 if (cmd_flags)
3993                         cmd_flags = 0;
3994                 else
3995                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3996
3997                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3998
3999                 /* Advance to the next dword. */
4000                 offset32 += 4;
4001                 ret_buf += 4;
4002                 len32 -= 4;
4003
4004                 while (len32 > 4 && rc == 0) {
4005                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4006
4007                         /* Advance to the next dword. */
4008                         offset32 += 4;
4009                         ret_buf += 4;
4010                         len32 -= 4;
4011                 }
4012
4013                 if (rc)
4014                         return rc;
4015
4016                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4017                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4018
4019                 memcpy(ret_buf, buf, 4 - extra);
4020         }
4021
4022         /* Disable access to flash interface */
4023         bnx2_disable_nvram_access(bp);
4024
4025         bnx2_release_nvram_lock(bp);
4026
4027         return rc;
4028 }
4029
4030 static int
4031 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4032                 int buf_size)
4033 {
4034         u32 written, offset32, len32;
4035         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4036         int rc = 0;
4037         int align_start, align_end;
4038
4039         buf = data_buf;
4040         offset32 = offset;
4041         len32 = buf_size;
4042         align_start = align_end = 0;
4043
4044         if ((align_start = (offset32 & 3))) {
4045                 offset32 &= ~3;
4046                 len32 += align_start;
4047                 if (len32 < 4)
4048                         len32 = 4;
4049                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4050                         return rc;
4051         }
4052
4053         if (len32 & 3) {
4054                 align_end = 4 - (len32 & 3);
4055                 len32 += align_end;
4056                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4057                         return rc;
4058         }
4059
4060         if (align_start || align_end) {
4061                 align_buf = kmalloc(len32, GFP_KERNEL);
4062                 if (align_buf == NULL)
4063                         return -ENOMEM;
4064                 if (align_start) {
4065                         memcpy(align_buf, start, 4);
4066                 }
4067                 if (align_end) {
4068                         memcpy(align_buf + len32 - 4, end, 4);
4069                 }
4070                 memcpy(align_buf + align_start, data_buf, buf_size);
4071                 buf = align_buf;
4072         }
4073
4074         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4075                 flash_buffer = kmalloc(264, GFP_KERNEL);
4076                 if (flash_buffer == NULL) {
4077                         rc = -ENOMEM;
4078                         goto nvram_write_end;
4079                 }
4080         }
4081
4082         written = 0;
4083         while ((written < len32) && (rc == 0)) {
4084                 u32 page_start, page_end, data_start, data_end;
4085                 u32 addr, cmd_flags;
4086                 int i;
4087
4088                 /* Find the page_start addr */
4089                 page_start = offset32 + written;
4090                 page_start -= (page_start % bp->flash_info->page_size);
4091                 /* Find the page_end addr */
4092                 page_end = page_start + bp->flash_info->page_size;
4093                 /* Find the data_start addr */
4094                 data_start = (written == 0) ? offset32 : page_start;
4095                 /* Find the data_end addr */
4096                 data_end = (page_end > offset32 + len32) ?
4097                         (offset32 + len32) : page_end;
4098
4099                 /* Request access to the flash interface. */
4100                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4101                         goto nvram_write_end;
4102
4103                 /* Enable access to flash interface */
4104                 bnx2_enable_nvram_access(bp);
4105
4106                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4107                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4108                         int j;
4109
4110                         /* Read the whole page into the buffer
4111                          * (non-buffer flash only) */
4112                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4113                                 if (j == (bp->flash_info->page_size - 4)) {
4114                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4115                                 }
4116                                 rc = bnx2_nvram_read_dword(bp,
4117                                         page_start + j,
4118                                         &flash_buffer[j],
4119                                         cmd_flags);
4120
4121                                 if (rc)
4122                                         goto nvram_write_end;
4123
4124                                 cmd_flags = 0;
4125                         }
4126                 }
4127
4128                 /* Enable writes to flash interface (unlock write-protect) */
4129                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4130                         goto nvram_write_end;
4131
4132                 /* Loop to write back the buffer data from page_start to
4133                  * data_start */
4134                 i = 0;
4135                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4136                         /* Erase the page */
4137                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4138                                 goto nvram_write_end;
4139
4140                         /* Re-enable the write again for the actual write */
4141                         bnx2_enable_nvram_write(bp);
4142
4143                         for (addr = page_start; addr < data_start;
4144                                 addr += 4, i += 4) {
4145
4146                                 rc = bnx2_nvram_write_dword(bp, addr,
4147                                         &flash_buffer[i], cmd_flags);
4148
4149                                 if (rc != 0)
4150                                         goto nvram_write_end;
4151
4152                                 cmd_flags = 0;
4153                         }
4154                 }
4155
4156                 /* Loop to write the new data from data_start to data_end */
4157                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4158                         if ((addr == page_end - 4) ||
4159                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4160                                  (addr == data_end - 4))) {
4161
4162                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4163                         }
4164                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4165                                 cmd_flags);
4166
4167                         if (rc != 0)
4168                                 goto nvram_write_end;
4169
4170                         cmd_flags = 0;
4171                         buf += 4;
4172                 }
4173
4174                 /* Loop to write back the buffer data from data_end
4175                  * to page_end */
4176                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4177                         for (addr = data_end; addr < page_end;
4178                                 addr += 4, i += 4) {
4179
4180                                 if (addr == page_end-4) {
4181                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4182                                 }
4183                                 rc = bnx2_nvram_write_dword(bp, addr,
4184                                         &flash_buffer[i], cmd_flags);
4185
4186                                 if (rc != 0)
4187                                         goto nvram_write_end;
4188
4189                                 cmd_flags = 0;
4190                         }
4191                 }
4192
4193                 /* Disable writes to flash interface (lock write-protect) */
4194                 bnx2_disable_nvram_write(bp);
4195
4196                 /* Disable access to flash interface */
4197                 bnx2_disable_nvram_access(bp);
4198                 bnx2_release_nvram_lock(bp);
4199
4200                 /* Increment written */
4201                 written += data_end - data_start;
4202         }
4203
4204 nvram_write_end:
4205         kfree(flash_buffer);
4206         kfree(align_buf);
4207         return rc;
4208 }
4209
4210 static void
4211 bnx2_init_remote_phy(struct bnx2 *bp)
4212 {
4213         u32 val;
4214
4215         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4216         if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
4217                 return;
4218
4219         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4220         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4221                 return;
4222
4223         if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
4224                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4225
4226                 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4227                 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4228                         bp->phy_port = PORT_FIBRE;
4229                 else
4230                         bp->phy_port = PORT_TP;
4231
4232                 if (netif_running(bp->dev)) {
4233                         u32 sig;
4234
4235                         sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4236                               BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4237                         bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4238                 }
4239         }
4240 }
4241
4242 static void
4243 bnx2_setup_msix_tbl(struct bnx2 *bp)
4244 {
4245         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4246
4247         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4248         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4249 }
4250
4251 static int
4252 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4253 {
4254         u32 val;
4255         int i, rc = 0;
4256         u8 old_port;
4257
4258         /* Wait for the current PCI transaction to complete before
4259          * issuing a reset. */
4260         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4261                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4262                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4263                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4264                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4265         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4266         udelay(5);
4267
4268         /* Wait for the firmware to tell us it is ok to issue a reset. */
4269         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4270
4271         /* Deposit a driver reset signature so the firmware knows that
4272          * this is a soft reset. */
4273         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4274                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4275
4276         /* Do a dummy read to force the chip to complete all current transaction
4277          * before we issue a reset. */
4278         val = REG_RD(bp, BNX2_MISC_ID);
4279
4280         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4281                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4282                 REG_RD(bp, BNX2_MISC_COMMAND);
4283                 udelay(5);
4284
4285                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4286                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4287
4288                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4289
4290         } else {
4291                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4292                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4293                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4294
4295                 /* Chip reset. */
4296                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4297
4298                 /* Reading back any register after chip reset will hang the
4299                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4300                  * of margin for write posting.
4301                  */
4302                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4303                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4304                         msleep(20);
4305
4306                 /* Reset takes approximate 30 usec */
4307                 for (i = 0; i < 10; i++) {
4308                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4309                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4310                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4311                                 break;
4312                         udelay(10);
4313                 }
4314
4315                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4316                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4317                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4318                         return -EBUSY;
4319                 }
4320         }
4321
4322         /* Make sure byte swapping is properly configured. */
4323         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4324         if (val != 0x01020304) {
4325                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4326                 return -ENODEV;
4327         }
4328
4329         /* Wait for the firmware to finish its initialization. */
4330         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4331         if (rc)
4332                 return rc;
4333
4334         spin_lock_bh(&bp->phy_lock);
4335         old_port = bp->phy_port;
4336         bnx2_init_remote_phy(bp);
4337         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4338             old_port != bp->phy_port)
4339                 bnx2_set_default_remote_link(bp);
4340         spin_unlock_bh(&bp->phy_lock);
4341
4342         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4343                 /* Adjust the voltage regular to two steps lower.  The default
4344                  * of this register is 0x0000000e. */
4345                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4346
4347                 /* Remove bad rbuf memory from the free pool. */
4348                 rc = bnx2_alloc_bad_rbuf(bp);
4349         }
4350
4351         if (bp->flags & BNX2_FLAG_USING_MSIX)
4352                 bnx2_setup_msix_tbl(bp);
4353
4354         return rc;
4355 }
4356
4357 static int
4358 bnx2_init_chip(struct bnx2 *bp)
4359 {
4360         u32 val;
4361         int rc, i;
4362
4363         /* Make sure the interrupt is not active. */
4364         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4365
4366         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4367               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4368 #ifdef __BIG_ENDIAN
4369               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4370 #endif
4371               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4372               DMA_READ_CHANS << 12 |
4373               DMA_WRITE_CHANS << 16;
4374
4375         val |= (0x2 << 20) | (1 << 11);
4376
4377         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4378                 val |= (1 << 23);
4379
4380         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4381             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4382                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4383
4384         REG_WR(bp, BNX2_DMA_CONFIG, val);
4385
4386         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4387                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4388                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4389                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4390         }
4391
4392         if (bp->flags & BNX2_FLAG_PCIX) {
4393                 u16 val16;
4394
4395                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4396                                      &val16);
4397                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4398                                       val16 & ~PCI_X_CMD_ERO);
4399         }
4400
4401         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4402                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4403                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4404                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4405
4406         /* Initialize context mapping and zero out the quick contexts.  The
4407          * context block must have already been enabled. */
4408         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4409                 rc = bnx2_init_5709_context(bp);
4410                 if (rc)
4411                         return rc;
4412         } else
4413                 bnx2_init_context(bp);
4414
4415         if ((rc = bnx2_init_cpus(bp)) != 0)
4416                 return rc;
4417
4418         bnx2_init_nvram(bp);
4419
4420         bnx2_set_mac_addr(bp);
4421
4422         val = REG_RD(bp, BNX2_MQ_CONFIG);
4423         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4424         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4425         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4426                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4427
4428         REG_WR(bp, BNX2_MQ_CONFIG, val);
4429
4430         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4431         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4432         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4433
4434         val = (BCM_PAGE_BITS - 8) << 24;
4435         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4436
4437         /* Configure page size. */
4438         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4439         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4440         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4441         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4442
4443         val = bp->mac_addr[0] +
4444               (bp->mac_addr[1] << 8) +
4445               (bp->mac_addr[2] << 16) +
4446               bp->mac_addr[3] +
4447               (bp->mac_addr[4] << 8) +
4448               (bp->mac_addr[5] << 16);
4449         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4450
4451         /* Program the MTU.  Also include 4 bytes for CRC32. */
4452         val = bp->dev->mtu + ETH_HLEN + 4;
4453         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4454                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4455         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4456
4457         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4458                 bp->bnx2_napi[i].last_status_idx = 0;
4459
4460         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4461
4462         /* Set up how to generate a link change interrupt. */
4463         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4464
4465         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4466                (u64) bp->status_blk_mapping & 0xffffffff);
4467         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4468
4469         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4470                (u64) bp->stats_blk_mapping & 0xffffffff);
4471         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4472                (u64) bp->stats_blk_mapping >> 32);
4473
4474         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4475                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4476
4477         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4478                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4479
4480         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4481                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4482
4483         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4484
4485         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4486
4487         REG_WR(bp, BNX2_HC_COM_TICKS,
4488                (bp->com_ticks_int << 16) | bp->com_ticks);
4489
4490         REG_WR(bp, BNX2_HC_CMD_TICKS,
4491                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4492
4493         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4494                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4495         else
4496                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4497         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4498
4499         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4500                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4501         else {
4502                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4503                       BNX2_HC_CONFIG_COLLECT_STATS;
4504         }
4505
4506         if (bp->flags & BNX2_FLAG_USING_MSIX) {
4507                 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4508                            BNX2_HC_SB_CONFIG_1;
4509
4510                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4511                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4512
4513                 REG_WR(bp, base,
4514                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4515                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4516
4517                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4518                         (bp->tx_quick_cons_trip_int << 16) |
4519                          bp->tx_quick_cons_trip);
4520
4521                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4522                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4523
4524                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4525         }
4526
4527         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4528                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4529
4530         REG_WR(bp, BNX2_HC_CONFIG, val);
4531
4532         /* Clear internal stats counters. */
4533         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4534
4535         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4536
4537         /* Initialize the receive filter. */
4538         bnx2_set_rx_mode(bp->dev);
4539
4540         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4541                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4542                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4543                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4544         }
4545         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4546                           0);
4547
4548         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4549         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4550
4551         udelay(20);
4552
4553         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4554
4555         return rc;
4556 }
4557
4558 static void
4559 bnx2_clear_ring_states(struct bnx2 *bp)
4560 {
4561         struct bnx2_napi *bnapi;
4562         int i;
4563
4564         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4565                 bnapi = &bp->bnx2_napi[i];
4566
4567                 bnapi->tx_cons = 0;
4568                 bnapi->hw_tx_cons = 0;
4569                 bnapi->rx_prod_bseq = 0;
4570                 bnapi->rx_prod = 0;
4571                 bnapi->rx_cons = 0;
4572                 bnapi->rx_pg_prod = 0;
4573                 bnapi->rx_pg_cons = 0;
4574         }
4575 }
4576
4577 static void
4578 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4579 {
4580         u32 val, offset0, offset1, offset2, offset3;
4581         u32 cid_addr = GET_CID_ADDR(cid);
4582
4583         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4584                 offset0 = BNX2_L2CTX_TYPE_XI;
4585                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4586                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4587                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4588         } else {
4589                 offset0 = BNX2_L2CTX_TYPE;
4590                 offset1 = BNX2_L2CTX_CMD_TYPE;
4591                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4592                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4593         }
4594         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4595         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4596
4597         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4598         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4599
4600         val = (u64) bp->tx_desc_mapping >> 32;
4601         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4602
4603         val = (u64) bp->tx_desc_mapping & 0xffffffff;
4604         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4605 }
4606
4607 static void
4608 bnx2_init_tx_ring(struct bnx2 *bp)
4609 {
4610         struct tx_bd *txbd;
4611         u32 cid = TX_CID;
4612         struct bnx2_napi *bnapi;
4613
4614         bp->tx_vec = 0;
4615         if (bp->flags & BNX2_FLAG_USING_MSIX) {
4616                 cid = TX_TSS_CID;
4617                 bp->tx_vec = BNX2_TX_VEC;
4618                 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4619                        (TX_TSS_CID << 7));
4620         }
4621         bnapi = &bp->bnx2_napi[bp->tx_vec];
4622
4623         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4624
4625         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4626
4627         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4628         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4629
4630         bp->tx_prod = 0;
4631         bp->tx_prod_bseq = 0;
4632
4633         bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4634         bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4635
4636         bnx2_init_tx_context(bp, cid);
4637 }
4638
4639 static void
4640 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4641                      int num_rings)
4642 {
4643         int i;
4644         struct rx_bd *rxbd;
4645
4646         for (i = 0; i < num_rings; i++) {
4647                 int j;
4648
4649                 rxbd = &rx_ring[i][0];
4650                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4651                         rxbd->rx_bd_len = buf_size;
4652                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4653                 }
4654                 if (i == (num_rings - 1))
4655                         j = 0;
4656                 else
4657                         j = i + 1;
4658                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4659                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4660         }
4661 }
4662
4663 static void
4664 bnx2_init_rx_ring(struct bnx2 *bp)
4665 {
4666         int i;
4667         u16 prod, ring_prod;
4668         u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
4669         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
4670
4671         bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4672                              bp->rx_buf_use_size, bp->rx_max_ring);
4673
4674         bnx2_init_rx_context0(bp);
4675
4676         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4677                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4678                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4679         }
4680
4681         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4682         if (bp->rx_pg_ring_size) {
4683                 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4684                                      bp->rx_pg_desc_mapping,
4685                                      PAGE_SIZE, bp->rx_max_pg_ring);
4686                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4687                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4688                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4689                        BNX2_L2CTX_RBDC_JUMBO_KEY);
4690
4691                 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
4692                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4693
4694                 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
4695                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4696
4697                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4698                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4699         }
4700
4701         val = (u64) bp->rx_desc_mapping[0] >> 32;
4702         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4703
4704         val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4705         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4706
4707         ring_prod = prod = bnapi->rx_pg_prod;
4708         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4709                 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4710                         break;
4711                 prod = NEXT_RX_BD(prod);
4712                 ring_prod = RX_PG_RING_IDX(prod);
4713         }
4714         bnapi->rx_pg_prod = prod;
4715
4716         ring_prod = prod = bnapi->rx_prod;
4717         for (i = 0; i < bp->rx_ring_size; i++) {
4718                 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
4719                         break;
4720                 }
4721                 prod = NEXT_RX_BD(prod);
4722                 ring_prod = RX_RING_IDX(prod);
4723         }
4724         bnapi->rx_prod = prod;
4725
4726         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4727                  bnapi->rx_pg_prod);
4728         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4729
4730         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
4731 }
4732
4733 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4734 {
4735         u32 max, num_rings = 1;
4736
4737         while (ring_size > MAX_RX_DESC_CNT) {
4738                 ring_size -= MAX_RX_DESC_CNT;
4739                 num_rings++;
4740         }
4741         /* round to next power of 2 */
4742         max = max_size;
4743         while ((max & num_rings) == 0)
4744                 max >>= 1;
4745
4746         if (num_rings != max)
4747                 max <<= 1;
4748
4749         return max;
4750 }
4751
4752 static void
4753 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4754 {
4755         u32 rx_size, rx_space, jumbo_size;
4756
4757         /* 8 for CRC and VLAN */
4758         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4759
4760         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4761                 sizeof(struct skb_shared_info);
4762
4763         bp->rx_copy_thresh = RX_COPY_THRESH;
4764         bp->rx_pg_ring_size = 0;
4765         bp->rx_max_pg_ring = 0;
4766         bp->rx_max_pg_ring_idx = 0;
4767         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4768                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4769
4770                 jumbo_size = size * pages;
4771                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4772                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4773
4774                 bp->rx_pg_ring_size = jumbo_size;
4775                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4776                                                         MAX_RX_PG_RINGS);
4777                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4778                 rx_size = RX_COPY_THRESH + BNX2_RX_OFFSET;
4779                 bp->rx_copy_thresh = 0;
4780         }
4781
4782         bp->rx_buf_use_size = rx_size;
4783         /* hw alignment */
4784         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4785         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4786         bp->rx_ring_size = size;
4787         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4788         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4789 }
4790
4791 static void
4792 bnx2_free_tx_skbs(struct bnx2 *bp)
4793 {
4794         int i;
4795
4796         if (bp->tx_buf_ring == NULL)
4797                 return;
4798
4799         for (i = 0; i < TX_DESC_CNT; ) {
4800                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4801                 struct sk_buff *skb = tx_buf->skb;
4802                 int j, last;
4803
4804                 if (skb == NULL) {
4805                         i++;
4806                         continue;
4807                 }
4808
4809                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4810                         skb_headlen(skb), PCI_DMA_TODEVICE);
4811
4812                 tx_buf->skb = NULL;
4813
4814                 last = skb_shinfo(skb)->nr_frags;
4815                 for (j = 0; j < last; j++) {
4816                         tx_buf = &bp->tx_buf_ring[i + j + 1];
4817                         pci_unmap_page(bp->pdev,
4818                                 pci_unmap_addr(tx_buf, mapping),
4819                                 skb_shinfo(skb)->frags[j].size,
4820                                 PCI_DMA_TODEVICE);
4821                 }
4822                 dev_kfree_skb(skb);
4823                 i += j + 1;
4824         }
4825
4826 }
4827
4828 static void
4829 bnx2_free_rx_skbs(struct bnx2 *bp)
4830 {
4831         int i;
4832
4833         if (bp->rx_buf_ring == NULL)
4834                 return;
4835
4836         for (i = 0; i < bp->rx_max_ring_idx; i++) {
4837                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4838                 struct sk_buff *skb = rx_buf->skb;
4839
4840                 if (skb == NULL)
4841                         continue;
4842
4843                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4844                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4845
4846                 rx_buf->skb = NULL;
4847
4848                 dev_kfree_skb(skb);
4849         }
4850         for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4851                 bnx2_free_rx_page(bp, i);
4852 }
4853
4854 static void
4855 bnx2_free_skbs(struct bnx2 *bp)
4856 {
4857         bnx2_free_tx_skbs(bp);
4858         bnx2_free_rx_skbs(bp);
4859 }
4860
4861 static int
4862 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4863 {
4864         int rc;
4865
4866         rc = bnx2_reset_chip(bp, reset_code);
4867         bnx2_free_skbs(bp);
4868         if (rc)
4869                 return rc;
4870
4871         if ((rc = bnx2_init_chip(bp)) != 0)
4872                 return rc;
4873
4874         bnx2_clear_ring_states(bp);
4875         bnx2_init_tx_ring(bp);
4876         bnx2_init_rx_ring(bp);
4877         return 0;
4878 }
4879
4880 static int
4881 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
4882 {
4883         int rc;
4884
4885         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4886                 return rc;
4887
4888         spin_lock_bh(&bp->phy_lock);
4889         bnx2_init_phy(bp, reset_phy);
4890         bnx2_set_link(bp);
4891         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4892                 bnx2_remote_phy_event(bp);
4893         spin_unlock_bh(&bp->phy_lock);
4894         return 0;
4895 }
4896
4897 static int
4898 bnx2_test_registers(struct bnx2 *bp)
4899 {
4900         int ret;
4901         int i, is_5709;
4902         static const struct {
4903                 u16   offset;
4904                 u16   flags;
4905 #define BNX2_FL_NOT_5709        1
4906                 u32   rw_mask;
4907                 u32   ro_mask;
4908         } reg_tbl[] = {
4909                 { 0x006c, 0, 0x00000000, 0x0000003f },
4910                 { 0x0090, 0, 0xffffffff, 0x00000000 },
4911                 { 0x0094, 0, 0x00000000, 0x00000000 },
4912
4913                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4914                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4915                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4916                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4917                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4918                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4919                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4920                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4921                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4922
4923                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4924                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4925                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4926                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4927                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4928                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4929
4930                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4931                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4932                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
4933
4934                 { 0x1000, 0, 0x00000000, 0x00000001 },
4935                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
4936
4937                 { 0x1408, 0, 0x01c00800, 0x00000000 },
4938                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4939                 { 0x14a8, 0, 0x00000000, 0x000001ff },
4940                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4941                 { 0x14b0, 0, 0x00000002, 0x00000001 },
4942                 { 0x14b8, 0, 0x00000000, 0x00000000 },
4943                 { 0x14c0, 0, 0x00000000, 0x00000009 },
4944                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4945                 { 0x14cc, 0, 0x00000000, 0x00000001 },
4946                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4947
4948                 { 0x1800, 0, 0x00000000, 0x00000001 },
4949                 { 0x1804, 0, 0x00000000, 0x00000003 },
4950
4951                 { 0x2800, 0, 0x00000000, 0x00000001 },
4952                 { 0x2804, 0, 0x00000000, 0x00003f01 },
4953                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4954                 { 0x2810, 0, 0xffff0000, 0x00000000 },
4955                 { 0x2814, 0, 0xffff0000, 0x00000000 },
4956                 { 0x2818, 0, 0xffff0000, 0x00000000 },
4957                 { 0x281c, 0, 0xffff0000, 0x00000000 },
4958                 { 0x2834, 0, 0xffffffff, 0x00000000 },
4959                 { 0x2840, 0, 0x00000000, 0xffffffff },
4960                 { 0x2844, 0, 0x00000000, 0xffffffff },
4961                 { 0x2848, 0, 0xffffffff, 0x00000000 },
4962                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4963
4964                 { 0x2c00, 0, 0x00000000, 0x00000011 },
4965                 { 0x2c04, 0, 0x00000000, 0x00030007 },
4966
4967                 { 0x3c00, 0, 0x00000000, 0x00000001 },
4968                 { 0x3c04, 0, 0x00000000, 0x00070000 },
4969                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4970                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4971                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4972                 { 0x3c14, 0, 0x00000000, 0xffffffff },
4973                 { 0x3c18, 0, 0x00000000, 0xffffffff },
4974                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4975                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4976
4977                 { 0x5004, 0, 0x00000000, 0x0000007f },
4978                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4979
4980                 { 0x5c00, 0, 0x00000000, 0x00000001 },
4981                 { 0x5c04, 0, 0x00000000, 0x0003000f },
4982                 { 0x5c08, 0, 0x00000003, 0x00000000 },
4983                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4984                 { 0x5c10, 0, 0x00000000, 0xffffffff },
4985                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4986                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4987                 { 0x5c88, 0, 0x00000000, 0x00077373 },
4988                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4989
4990                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4991                 { 0x680c, 0, 0xffffffff, 0x00000000 },
4992                 { 0x6810, 0, 0xffffffff, 0x00000000 },
4993                 { 0x6814, 0, 0xffffffff, 0x00000000 },
4994                 { 0x6818, 0, 0xffffffff, 0x00000000 },
4995                 { 0x681c, 0, 0xffffffff, 0x00000000 },
4996                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4997                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4998                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4999                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5000                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5001                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5002                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5003                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5004                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5005                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5006                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5007                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5008                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5009                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5010                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5011                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5012                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5013
5014                 { 0xffff, 0, 0x00000000, 0x00000000 },
5015         };
5016
5017         ret = 0;
5018         is_5709 = 0;
5019         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5020                 is_5709 = 1;
5021
5022         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5023                 u32 offset, rw_mask, ro_mask, save_val, val;
5024                 u16 flags = reg_tbl[i].flags;
5025
5026                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5027                         continue;
5028
5029                 offset = (u32) reg_tbl[i].offset;
5030                 rw_mask = reg_tbl[i].rw_mask;
5031                 ro_mask = reg_tbl[i].ro_mask;
5032
5033                 save_val = readl(bp->regview + offset);
5034
5035                 writel(0, bp->regview + offset);
5036
5037                 val = readl(bp->regview + offset);
5038                 if ((val & rw_mask) != 0) {
5039                         goto reg_test_err;
5040                 }
5041
5042                 if ((val & ro_mask) != (save_val & ro_mask)) {
5043                         goto reg_test_err;
5044                 }
5045
5046                 writel(0xffffffff, bp->regview + offset);
5047
5048                 val = readl(bp->regview + offset);
5049                 if ((val & rw_mask) != rw_mask) {
5050                         goto reg_test_err;
5051                 }
5052
5053                 if ((val & ro_mask) != (save_val & ro_mask)) {
5054                         goto reg_test_err;
5055                 }
5056
5057                 writel(save_val, bp->regview + offset);
5058                 continue;
5059
5060 reg_test_err:
5061                 writel(save_val, bp->regview + offset);
5062                 ret = -ENODEV;
5063                 break;
5064         }
5065         return ret;
5066 }
5067
5068 static int
5069 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5070 {
5071         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5072                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5073         int i;
5074
5075         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5076                 u32 offset;
5077
5078                 for (offset = 0; offset < size; offset += 4) {
5079
5080                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5081
5082                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5083                                 test_pattern[i]) {
5084                                 return -ENODEV;
5085                         }
5086                 }
5087         }
5088         return 0;
5089 }
5090
5091 static int
5092 bnx2_test_memory(struct bnx2 *bp)
5093 {
5094         int ret = 0;
5095         int i;
5096         static struct mem_entry {
5097                 u32   offset;
5098                 u32   len;
5099         } mem_tbl_5706[] = {
5100                 { 0x60000,  0x4000 },
5101                 { 0xa0000,  0x3000 },
5102                 { 0xe0000,  0x4000 },
5103                 { 0x120000, 0x4000 },
5104                 { 0x1a0000, 0x4000 },
5105                 { 0x160000, 0x4000 },
5106                 { 0xffffffff, 0    },
5107         },
5108         mem_tbl_5709[] = {
5109                 { 0x60000,  0x4000 },
5110                 { 0xa0000,  0x3000 },
5111                 { 0xe0000,  0x4000 },
5112                 { 0x120000, 0x4000 },
5113                 { 0x1a0000, 0x4000 },
5114                 { 0xffffffff, 0    },
5115         };
5116         struct mem_entry *mem_tbl;
5117
5118         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5119                 mem_tbl = mem_tbl_5709;
5120         else
5121                 mem_tbl = mem_tbl_5706;
5122
5123         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5124                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5125                         mem_tbl[i].len)) != 0) {
5126                         return ret;
5127                 }
5128         }
5129
5130         return ret;
5131 }
5132
5133 #define BNX2_MAC_LOOPBACK       0
5134 #define BNX2_PHY_LOOPBACK       1
5135
5136 static int
5137 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5138 {
5139         unsigned int pkt_size, num_pkts, i;
5140         struct sk_buff *skb, *rx_skb;
5141         unsigned char *packet;
5142         u16 rx_start_idx, rx_idx;
5143         dma_addr_t map;
5144         struct tx_bd *txbd;
5145         struct sw_bd *rx_buf;
5146         struct l2_fhdr *rx_hdr;
5147         int ret = -ENODEV;
5148         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5149
5150         tx_napi = bnapi;
5151         if (bp->flags & BNX2_FLAG_USING_MSIX)
5152                 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
5153
5154         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5155                 bp->loopback = MAC_LOOPBACK;
5156                 bnx2_set_mac_loopback(bp);
5157         }
5158         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5159                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5160                         return 0;
5161
5162                 bp->loopback = PHY_LOOPBACK;
5163                 bnx2_set_phy_loopback(bp);
5164         }
5165         else
5166                 return -EINVAL;
5167
5168         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5169         skb = netdev_alloc_skb(bp->dev, pkt_size);
5170         if (!skb)
5171                 return -ENOMEM;
5172         packet = skb_put(skb, pkt_size);
5173         memcpy(packet, bp->dev->dev_addr, 6);
5174         memset(packet + 6, 0x0, 8);
5175         for (i = 14; i < pkt_size; i++)
5176                 packet[i] = (unsigned char) (i & 0xff);
5177
5178         map = pci_map_single(bp->pdev, skb->data, pkt_size,
5179                 PCI_DMA_TODEVICE);
5180
5181         REG_WR(bp, BNX2_HC_COMMAND,
5182                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5183
5184         REG_RD(bp, BNX2_HC_COMMAND);
5185
5186         udelay(5);
5187         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5188
5189         num_pkts = 0;
5190
5191         txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
5192
5193         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5194         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5195         txbd->tx_bd_mss_nbytes = pkt_size;
5196         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5197
5198         num_pkts++;
5199         bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5200         bp->tx_prod_bseq += pkt_size;
5201
5202         REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5203         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5204
5205         udelay(100);
5206
5207         REG_WR(bp, BNX2_HC_COMMAND,
5208                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5209
5210         REG_RD(bp, BNX2_HC_COMMAND);
5211
5212         udelay(5);
5213
5214         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5215         dev_kfree_skb(skb);
5216
5217         if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
5218                 goto loopback_test_done;
5219
5220         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5221         if (rx_idx != rx_start_idx + num_pkts) {
5222                 goto loopback_test_done;
5223         }
5224
5225         rx_buf = &bp->rx_buf_ring[rx_start_idx];
5226         rx_skb = rx_buf->skb;
5227
5228         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5229         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5230
5231         pci_dma_sync_single_for_cpu(bp->pdev,
5232                 pci_unmap_addr(rx_buf, mapping),
5233                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5234
5235         if (rx_hdr->l2_fhdr_status &
5236                 (L2_FHDR_ERRORS_BAD_CRC |
5237                 L2_FHDR_ERRORS_PHY_DECODE |
5238                 L2_FHDR_ERRORS_ALIGNMENT |
5239                 L2_FHDR_ERRORS_TOO_SHORT |
5240                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5241
5242                 goto loopback_test_done;
5243         }
5244
5245         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5246                 goto loopback_test_done;
5247         }
5248
5249         for (i = 14; i < pkt_size; i++) {
5250                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5251                         goto loopback_test_done;
5252                 }
5253         }
5254
5255         ret = 0;
5256
5257 loopback_test_done:
5258         bp->loopback = 0;
5259         return ret;
5260 }
5261
5262 #define BNX2_MAC_LOOPBACK_FAILED        1
5263 #define BNX2_PHY_LOOPBACK_FAILED        2
5264 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5265                                          BNX2_PHY_LOOPBACK_FAILED)
5266
5267 static int
5268 bnx2_test_loopback(struct bnx2 *bp)
5269 {
5270         int rc = 0;
5271
5272         if (!netif_running(bp->dev))
5273                 return BNX2_LOOPBACK_FAILED;
5274
5275         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5276         spin_lock_bh(&bp->phy_lock);
5277         bnx2_init_phy(bp, 1);
5278         spin_unlock_bh(&bp->phy_lock);
5279         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5280                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5281         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5282                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5283         return rc;
5284 }
5285
5286 #define NVRAM_SIZE 0x200
5287 #define CRC32_RESIDUAL 0xdebb20e3
5288
5289 static int
5290 bnx2_test_nvram(struct bnx2 *bp)
5291 {
5292         __be32 buf[NVRAM_SIZE / 4];
5293         u8 *data = (u8 *) buf;
5294         int rc = 0;
5295         u32 magic, csum;
5296
5297         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5298                 goto test_nvram_done;
5299
5300         magic = be32_to_cpu(buf[0]);
5301         if (magic != 0x669955aa) {
5302                 rc = -ENODEV;
5303                 goto test_nvram_done;
5304         }
5305
5306         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5307                 goto test_nvram_done;
5308
5309         csum = ether_crc_le(0x100, data);
5310         if (csum != CRC32_RESIDUAL) {
5311                 rc = -ENODEV;
5312                 goto test_nvram_done;
5313         }
5314
5315         csum = ether_crc_le(0x100, data + 0x100);
5316         if (csum != CRC32_RESIDUAL) {
5317                 rc = -ENODEV;
5318         }
5319
5320 test_nvram_done:
5321         return rc;
5322 }
5323
5324 static int
5325 bnx2_test_link(struct bnx2 *bp)
5326 {
5327         u32 bmsr;
5328
5329         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5330                 if (bp->link_up)
5331                         return 0;
5332                 return -ENODEV;
5333         }
5334         spin_lock_bh(&bp->phy_lock);
5335         bnx2_enable_bmsr1(bp);
5336         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5337         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5338         bnx2_disable_bmsr1(bp);
5339         spin_unlock_bh(&bp->phy_lock);
5340
5341         if (bmsr & BMSR_LSTATUS) {
5342                 return 0;
5343         }
5344         return -ENODEV;
5345 }
5346
5347 static int
5348 bnx2_test_intr(struct bnx2 *bp)
5349 {
5350         int i;
5351         u16 status_idx;
5352
5353         if (!netif_running(bp->dev))
5354                 return -ENODEV;
5355
5356         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5357
5358         /* This register is not touched during run-time. */
5359         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5360         REG_RD(bp, BNX2_HC_COMMAND);
5361
5362         for (i = 0; i < 10; i++) {
5363                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5364                         status_idx) {
5365
5366                         break;
5367                 }
5368
5369                 msleep_interruptible(10);
5370         }
5371         if (i < 10)
5372                 return 0;
5373
5374         return -ENODEV;
5375 }
5376
5377 /* Determining link for parallel detection. */
5378 static int
5379 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5380 {
5381         u32 mode_ctl, an_dbg, exp;
5382
5383         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5384                 return 0;
5385
5386         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5387         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5388
5389         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5390                 return 0;
5391
5392         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5393         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5394         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5395
5396         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5397                 return 0;
5398
5399         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5400         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5401         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5402
5403         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5404                 return 0;
5405
5406         return 1;
5407 }
5408
5409 static void
5410 bnx2_5706_serdes_timer(struct bnx2 *bp)
5411 {
5412         int check_link = 1;
5413
5414         spin_lock(&bp->phy_lock);
5415         if (bp->serdes_an_pending) {
5416                 bp->serdes_an_pending--;
5417                 check_link = 0;
5418         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5419                 u32 bmcr;
5420
5421                 bp->current_interval = bp->timer_interval;
5422
5423                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5424
5425                 if (bmcr & BMCR_ANENABLE) {
5426                         if (bnx2_5706_serdes_has_link(bp)) {
5427                                 bmcr &= ~BMCR_ANENABLE;
5428                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5429                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5430                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5431                         }
5432                 }
5433         }
5434         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5435                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5436                 u32 phy2;
5437
5438                 bnx2_write_phy(bp, 0x17, 0x0f01);
5439                 bnx2_read_phy(bp, 0x15, &phy2);
5440                 if (phy2 & 0x20) {
5441                         u32 bmcr;
5442
5443                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5444                         bmcr |= BMCR_ANENABLE;
5445                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5446
5447                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5448                 }
5449         } else
5450                 bp->current_interval = bp->timer_interval;
5451
5452         if (check_link) {
5453                 u32 val;
5454
5455                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5456                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5457                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5458
5459                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5460                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5461                                 bnx2_5706s_force_link_dn(bp, 1);
5462                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5463                         } else
5464                                 bnx2_set_link(bp);
5465                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5466                         bnx2_set_link(bp);
5467         }
5468         spin_unlock(&bp->phy_lock);
5469 }
5470
5471 static void
5472 bnx2_5708_serdes_timer(struct bnx2 *bp)
5473 {
5474         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5475                 return;
5476
5477         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5478                 bp->serdes_an_pending = 0;
5479                 return;
5480         }
5481
5482         spin_lock(&bp->phy_lock);
5483         if (bp->serdes_an_pending)
5484                 bp->serdes_an_pending--;
5485         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5486                 u32 bmcr;
5487
5488                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5489                 if (bmcr & BMCR_ANENABLE) {
5490                         bnx2_enable_forced_2g5(bp);
5491                         bp->current_interval = SERDES_FORCED_TIMEOUT;
5492                 } else {
5493                         bnx2_disable_forced_2g5(bp);
5494                         bp->serdes_an_pending = 2;
5495                         bp->current_interval = bp->timer_interval;
5496                 }
5497
5498         } else
5499                 bp->current_interval = bp->timer_interval;
5500
5501         spin_unlock(&bp->phy_lock);
5502 }
5503
5504 static void
5505 bnx2_timer(unsigned long data)
5506 {
5507         struct bnx2 *bp = (struct bnx2 *) data;
5508
5509         if (!netif_running(bp->dev))
5510                 return;
5511
5512         if (atomic_read(&bp->intr_sem) != 0)
5513                 goto bnx2_restart_timer;
5514
5515         bnx2_send_heart_beat(bp);
5516
5517         bp->stats_blk->stat_FwRxDrop =
5518                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5519
5520         /* workaround occasional corrupted counters */
5521         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5522                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5523                                             BNX2_HC_COMMAND_STATS_NOW);
5524
5525         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5526                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5527                         bnx2_5706_serdes_timer(bp);
5528                 else
5529                         bnx2_5708_serdes_timer(bp);
5530         }
5531
5532 bnx2_restart_timer:
5533         mod_timer(&bp->timer, jiffies + bp->current_interval);
5534 }
5535
5536 static int
5537 bnx2_request_irq(struct bnx2 *bp)
5538 {
5539         struct net_device *dev = bp->dev;
5540         unsigned long flags;
5541         struct bnx2_irq *irq;
5542         int rc = 0, i;
5543
5544         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5545                 flags = 0;
5546         else
5547                 flags = IRQF_SHARED;
5548
5549         for (i = 0; i < bp->irq_nvecs; i++) {
5550                 irq = &bp->irq_tbl[i];
5551                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5552                                  dev);
5553                 if (rc)
5554                         break;
5555                 irq->requested = 1;
5556         }
5557         return rc;
5558 }
5559
5560 static void
5561 bnx2_free_irq(struct bnx2 *bp)
5562 {
5563         struct net_device *dev = bp->dev;
5564         struct bnx2_irq *irq;
5565         int i;
5566
5567         for (i = 0; i < bp->irq_nvecs; i++) {
5568                 irq = &bp->irq_tbl[i];
5569                 if (irq->requested)
5570                         free_irq(irq->vector, dev);
5571                 irq->requested = 0;
5572         }
5573         if (bp->flags & BNX2_FLAG_USING_MSI)
5574                 pci_disable_msi(bp->pdev);
5575         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5576                 pci_disable_msix(bp->pdev);
5577
5578         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5579 }
5580
5581 static void
5582 bnx2_enable_msix(struct bnx2 *bp)
5583 {
5584         int i, rc;
5585         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5586
5587         bnx2_setup_msix_tbl(bp);
5588         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5589         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5590         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5591
5592         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5593                 msix_ent[i].entry = i;
5594                 msix_ent[i].vector = 0;
5595         }
5596
5597         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5598         if (rc != 0)
5599                 return;
5600
5601         bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5602         bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5603
5604         strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5605         strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5606         strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5607         strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5608
5609         bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
5610         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5611         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5612                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5613 }
5614
5615 static void
5616 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5617 {
5618         bp->irq_tbl[0].handler = bnx2_interrupt;
5619         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5620         bp->irq_nvecs = 1;
5621         bp->irq_tbl[0].vector = bp->pdev->irq;
5622
5623         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5624                 bnx2_enable_msix(bp);
5625
5626         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5627             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5628                 if (pci_enable_msi(bp->pdev) == 0) {
5629                         bp->flags |= BNX2_FLAG_USING_MSI;
5630                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5631                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5632                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5633                         } else
5634                                 bp->irq_tbl[0].handler = bnx2_msi;
5635
5636                         bp->irq_tbl[0].vector = bp->pdev->irq;
5637                 }
5638         }
5639 }
5640
5641 /* Called with rtnl_lock */
5642 static int
5643 bnx2_open(struct net_device *dev)
5644 {
5645         struct bnx2 *bp = netdev_priv(dev);
5646         int rc;
5647
5648         netif_carrier_off(dev);
5649
5650         bnx2_set_power_state(bp, PCI_D0);
5651         bnx2_disable_int(bp);
5652
5653         rc = bnx2_alloc_mem(bp);
5654         if (rc)
5655                 return rc;
5656
5657         bnx2_setup_int_mode(bp, disable_msi);
5658         bnx2_napi_enable(bp);
5659         rc = bnx2_request_irq(bp);
5660
5661         if (rc) {
5662                 bnx2_napi_disable(bp);
5663                 bnx2_free_mem(bp);
5664                 return rc;
5665         }
5666
5667         rc = bnx2_init_nic(bp, 1);
5668
5669         if (rc) {
5670                 bnx2_napi_disable(bp);
5671                 bnx2_free_irq(bp);
5672                 bnx2_free_skbs(bp);
5673                 bnx2_free_mem(bp);
5674                 return rc;
5675         }
5676
5677         mod_timer(&bp->timer, jiffies + bp->current_interval);
5678
5679         atomic_set(&bp->intr_sem, 0);
5680
5681         bnx2_enable_int(bp);
5682
5683         if (bp->flags & BNX2_FLAG_USING_MSI) {
5684                 /* Test MSI to make sure it is working
5685                  * If MSI test fails, go back to INTx mode
5686                  */
5687                 if (bnx2_test_intr(bp) != 0) {
5688                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5689                                " using MSI, switching to INTx mode. Please"
5690                                " report this failure to the PCI maintainer"
5691                                " and include system chipset information.\n",
5692                                bp->dev->name);
5693
5694                         bnx2_disable_int(bp);
5695                         bnx2_free_irq(bp);
5696
5697                         bnx2_setup_int_mode(bp, 1);
5698
5699                         rc = bnx2_init_nic(bp, 0);
5700
5701                         if (!rc)
5702                                 rc = bnx2_request_irq(bp);
5703
5704                         if (rc) {
5705                                 bnx2_napi_disable(bp);
5706                                 bnx2_free_skbs(bp);
5707                                 bnx2_free_mem(bp);
5708                                 del_timer_sync(&bp->timer);
5709                                 return rc;
5710                         }
5711                         bnx2_enable_int(bp);
5712                 }
5713         }
5714         if (bp->flags & BNX2_FLAG_USING_MSI)
5715                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5716         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5717                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5718
5719         netif_start_queue(dev);
5720
5721         return 0;
5722 }
5723
5724 static void
5725 bnx2_reset_task(struct work_struct *work)
5726 {
5727         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5728
5729         if (!netif_running(bp->dev))
5730                 return;
5731
5732         bp->in_reset_task = 1;
5733         bnx2_netif_stop(bp);
5734
5735         bnx2_init_nic(bp, 1);
5736
5737         atomic_set(&bp->intr_sem, 1);
5738         bnx2_netif_start(bp);
5739         bp->in_reset_task = 0;
5740 }
5741
5742 static void
5743 bnx2_tx_timeout(struct net_device *dev)
5744 {
5745         struct bnx2 *bp = netdev_priv(dev);
5746
5747         /* This allows the netif to be shutdown gracefully before resetting */
5748         schedule_work(&bp->reset_task);
5749 }
5750
5751 #ifdef BCM_VLAN
5752 /* Called with rtnl_lock */
5753 static void
5754 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5755 {
5756         struct bnx2 *bp = netdev_priv(dev);
5757
5758         bnx2_netif_stop(bp);
5759
5760         bp->vlgrp = vlgrp;
5761         bnx2_set_rx_mode(dev);
5762
5763         bnx2_netif_start(bp);
5764 }
5765 #endif
5766
5767 /* Called with netif_tx_lock.
5768  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5769  * netif_wake_queue().
5770  */
5771 static int
5772 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5773 {
5774         struct bnx2 *bp = netdev_priv(dev);
5775         dma_addr_t mapping;
5776         struct tx_bd *txbd;
5777         struct sw_bd *tx_buf;
5778         u32 len, vlan_tag_flags, last_frag, mss;
5779         u16 prod, ring_prod;
5780         int i;
5781         struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
5782
5783         if (unlikely(bnx2_tx_avail(bp, bnapi) <
5784             (skb_shinfo(skb)->nr_frags + 1))) {
5785                 netif_stop_queue(dev);
5786                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5787                         dev->name);
5788
5789                 return NETDEV_TX_BUSY;
5790         }
5791         len = skb_headlen(skb);
5792         prod = bp->tx_prod;
5793         ring_prod = TX_RING_IDX(prod);
5794
5795         vlan_tag_flags = 0;
5796         if (skb->ip_summed == CHECKSUM_PARTIAL) {
5797                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5798         }
5799
5800         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5801                 vlan_tag_flags |=
5802                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5803         }
5804         if ((mss = skb_shinfo(skb)->gso_size)) {
5805                 u32 tcp_opt_len, ip_tcp_len;
5806                 struct iphdr *iph;
5807
5808                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5809
5810                 tcp_opt_len = tcp_optlen(skb);
5811
5812                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5813                         u32 tcp_off = skb_transport_offset(skb) -
5814                                       sizeof(struct ipv6hdr) - ETH_HLEN;
5815
5816                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5817                                           TX_BD_FLAGS_SW_FLAGS;
5818                         if (likely(tcp_off == 0))
5819                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5820                         else {
5821                                 tcp_off >>= 3;
5822                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
5823                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
5824                                                   ((tcp_off & 0x10) <<
5825                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
5826                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5827                         }
5828                 } else {
5829                         if (skb_header_cloned(skb) &&
5830                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5831                                 dev_kfree_skb(skb);
5832                                 return NETDEV_TX_OK;
5833                         }
5834
5835                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5836
5837                         iph = ip_hdr(skb);
5838                         iph->check = 0;
5839                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5840                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5841                                                                  iph->daddr, 0,
5842                                                                  IPPROTO_TCP,
5843                                                                  0);
5844                         if (tcp_opt_len || (iph->ihl > 5)) {
5845                                 vlan_tag_flags |= ((iph->ihl - 5) +
5846                                                    (tcp_opt_len >> 2)) << 8;
5847                         }
5848                 }
5849         } else
5850                 mss = 0;
5851
5852         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5853
5854         tx_buf = &bp->tx_buf_ring[ring_prod];
5855         tx_buf->skb = skb;
5856         pci_unmap_addr_set(tx_buf, mapping, mapping);
5857
5858         txbd = &bp->tx_desc_ring[ring_prod];
5859
5860         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5861         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5862         txbd->tx_bd_mss_nbytes = len | (mss << 16);
5863         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5864
5865         last_frag = skb_shinfo(skb)->nr_frags;
5866
5867         for (i = 0; i < last_frag; i++) {
5868                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5869
5870                 prod = NEXT_TX_BD(prod);
5871                 ring_prod = TX_RING_IDX(prod);
5872                 txbd = &bp->tx_desc_ring[ring_prod];
5873
5874                 len = frag->size;
5875                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5876                         len, PCI_DMA_TODEVICE);
5877                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5878                                 mapping, mapping);
5879
5880                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5881                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5882                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5883                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5884
5885         }
5886         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5887
5888         prod = NEXT_TX_BD(prod);
5889         bp->tx_prod_bseq += skb->len;
5890
5891         REG_WR16(bp, bp->tx_bidx_addr, prod);
5892         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5893
5894         mmiowb();
5895
5896         bp->tx_prod = prod;
5897         dev->trans_start = jiffies;
5898
5899         if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
5900                 netif_stop_queue(dev);
5901                 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
5902                         netif_wake_queue(dev);
5903         }
5904
5905         return NETDEV_TX_OK;
5906 }
5907
5908 /* Called with rtnl_lock */
5909 static int
5910 bnx2_close(struct net_device *dev)
5911 {
5912         struct bnx2 *bp = netdev_priv(dev);
5913         u32 reset_code;
5914
5915         /* Calling flush_scheduled_work() may deadlock because
5916          * linkwatch_event() may be on the workqueue and it will try to get
5917          * the rtnl_lock which we are holding.
5918          */
5919         while (bp->in_reset_task)
5920                 msleep(1);
5921
5922         bnx2_disable_int_sync(bp);
5923         bnx2_napi_disable(bp);
5924         del_timer_sync(&bp->timer);
5925         if (bp->flags & BNX2_FLAG_NO_WOL)
5926                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5927         else if (bp->wol)
5928                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5929         else
5930                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5931         bnx2_reset_chip(bp, reset_code);
5932         bnx2_free_irq(bp);
5933         bnx2_free_skbs(bp);
5934         bnx2_free_mem(bp);
5935         bp->link_up = 0;
5936         netif_carrier_off(bp->dev);
5937         bnx2_set_power_state(bp, PCI_D3hot);
5938         return 0;
5939 }
5940
5941 #define GET_NET_STATS64(ctr)                                    \
5942         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
5943         (unsigned long) (ctr##_lo)
5944
5945 #define GET_NET_STATS32(ctr)            \
5946         (ctr##_lo)
5947
5948 #if (BITS_PER_LONG == 64)
5949 #define GET_NET_STATS   GET_NET_STATS64
5950 #else
5951 #define GET_NET_STATS   GET_NET_STATS32
5952 #endif
5953
5954 static struct net_device_stats *
5955 bnx2_get_stats(struct net_device *dev)
5956 {
5957         struct bnx2 *bp = netdev_priv(dev);
5958         struct statistics_block *stats_blk = bp->stats_blk;
5959         struct net_device_stats *net_stats = &bp->net_stats;
5960
5961         if (bp->stats_blk == NULL) {
5962                 return net_stats;
5963         }
5964         net_stats->rx_packets =
5965                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5966                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5967                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5968
5969         net_stats->tx_packets =
5970                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5971                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5972                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5973
5974         net_stats->rx_bytes =
5975                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5976
5977         net_stats->tx_bytes =
5978                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5979
5980         net_stats->multicast =
5981                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5982
5983         net_stats->collisions =
5984                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5985
5986         net_stats->rx_length_errors =
5987                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5988                 stats_blk->stat_EtherStatsOverrsizePkts);
5989
5990         net_stats->rx_over_errors =
5991                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5992
5993         net_stats->rx_frame_errors =
5994                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5995
5996         net_stats->rx_crc_errors =
5997                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5998
5999         net_stats->rx_errors = net_stats->rx_length_errors +
6000                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6001                 net_stats->rx_crc_errors;
6002
6003         net_stats->tx_aborted_errors =
6004                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6005                 stats_blk->stat_Dot3StatsLateCollisions);
6006
6007         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6008             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6009                 net_stats->tx_carrier_errors = 0;
6010         else {
6011                 net_stats->tx_carrier_errors =
6012                         (unsigned long)
6013                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6014         }
6015
6016         net_stats->tx_errors =
6017                 (unsigned long)
6018                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6019                 +
6020                 net_stats->tx_aborted_errors +
6021                 net_stats->tx_carrier_errors;
6022
6023         net_stats->rx_missed_errors =
6024                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6025                 stats_blk->stat_FwRxDrop);
6026
6027         return net_stats;
6028 }
6029
6030 /* All ethtool functions called with rtnl_lock */
6031
6032 static int
6033 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6034 {
6035         struct bnx2 *bp = netdev_priv(dev);
6036         int support_serdes = 0, support_copper = 0;
6037
6038         cmd->supported = SUPPORTED_Autoneg;
6039         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6040                 support_serdes = 1;
6041                 support_copper = 1;
6042         } else if (bp->phy_port == PORT_FIBRE)
6043                 support_serdes = 1;
6044         else
6045                 support_copper = 1;
6046
6047         if (support_serdes) {
6048                 cmd->supported |= SUPPORTED_1000baseT_Full |
6049                         SUPPORTED_FIBRE;
6050                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6051                         cmd->supported |= SUPPORTED_2500baseX_Full;
6052
6053         }
6054         if (support_copper) {
6055                 cmd->supported |= SUPPORTED_10baseT_Half |
6056                         SUPPORTED_10baseT_Full |
6057                         SUPPORTED_100baseT_Half |
6058                         SUPPORTED_100baseT_Full |
6059                         SUPPORTED_1000baseT_Full |
6060                         SUPPORTED_TP;
6061
6062         }
6063
6064         spin_lock_bh(&bp->phy_lock);
6065         cmd->port = bp->phy_port;
6066         cmd->advertising = bp->advertising;
6067
6068         if (bp->autoneg & AUTONEG_SPEED) {
6069                 cmd->autoneg = AUTONEG_ENABLE;
6070         }
6071         else {
6072                 cmd->autoneg = AUTONEG_DISABLE;
6073         }
6074
6075         if (netif_carrier_ok(dev)) {
6076                 cmd->speed = bp->line_speed;
6077                 cmd->duplex = bp->duplex;
6078         }
6079         else {
6080                 cmd->speed = -1;
6081                 cmd->duplex = -1;
6082         }
6083         spin_unlock_bh(&bp->phy_lock);
6084
6085         cmd->transceiver = XCVR_INTERNAL;
6086         cmd->phy_address = bp->phy_addr;
6087
6088         return 0;
6089 }
6090
6091 static int
6092 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6093 {
6094         struct bnx2 *bp = netdev_priv(dev);
6095         u8 autoneg = bp->autoneg;
6096         u8 req_duplex = bp->req_duplex;
6097         u16 req_line_speed = bp->req_line_speed;
6098         u32 advertising = bp->advertising;
6099         int err = -EINVAL;
6100
6101         spin_lock_bh(&bp->phy_lock);
6102
6103         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6104                 goto err_out_unlock;
6105
6106         if (cmd->port != bp->phy_port &&
6107             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6108                 goto err_out_unlock;
6109
6110         if (cmd->autoneg == AUTONEG_ENABLE) {
6111                 autoneg |= AUTONEG_SPEED;
6112
6113                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6114
6115                 /* allow advertising 1 speed */
6116                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6117                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6118                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6119                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6120
6121                         if (cmd->port == PORT_FIBRE)
6122                                 goto err_out_unlock;
6123
6124                         advertising = cmd->advertising;
6125
6126                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6127                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6128                             (cmd->port == PORT_TP))
6129                                 goto err_out_unlock;
6130                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6131                         advertising = cmd->advertising;
6132                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6133                         goto err_out_unlock;
6134                 else {
6135                         if (cmd->port == PORT_FIBRE)
6136                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6137                         else
6138                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6139                 }
6140                 advertising |= ADVERTISED_Autoneg;
6141         }
6142         else {
6143                 if (cmd->port == PORT_FIBRE) {
6144                         if ((cmd->speed != SPEED_1000 &&
6145                              cmd->speed != SPEED_2500) ||
6146                             (cmd->duplex != DUPLEX_FULL))
6147                                 goto err_out_unlock;
6148
6149                         if (cmd->speed == SPEED_2500 &&
6150                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6151                                 goto err_out_unlock;
6152                 }
6153                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6154                         goto err_out_unlock;
6155
6156                 autoneg &= ~AUTONEG_SPEED;
6157                 req_line_speed = cmd->speed;
6158                 req_duplex = cmd->duplex;
6159                 advertising = 0;
6160         }
6161
6162         bp->autoneg = autoneg;
6163         bp->advertising = advertising;
6164         bp->req_line_speed = req_line_speed;
6165         bp->req_duplex = req_duplex;
6166
6167         err = bnx2_setup_phy(bp, cmd->port);
6168
6169 err_out_unlock:
6170         spin_unlock_bh(&bp->phy_lock);
6171
6172         return err;
6173 }
6174
6175 static void
6176 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6177 {
6178         struct bnx2 *bp = netdev_priv(dev);
6179
6180         strcpy(info->driver, DRV_MODULE_NAME);
6181         strcpy(info->version, DRV_MODULE_VERSION);
6182         strcpy(info->bus_info, pci_name(bp->pdev));
6183         strcpy(info->fw_version, bp->fw_version);
6184 }
6185
6186 #define BNX2_REGDUMP_LEN                (32 * 1024)
6187
6188 static int
6189 bnx2_get_regs_len(struct net_device *dev)
6190 {
6191         return BNX2_REGDUMP_LEN;
6192 }
6193
6194 static void
6195 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6196 {
6197         u32 *p = _p, i, offset;
6198         u8 *orig_p = _p;
6199         struct bnx2 *bp = netdev_priv(dev);
6200         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6201                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6202                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6203                                  0x1040, 0x1048, 0x1080, 0x10a4,
6204                                  0x1400, 0x1490, 0x1498, 0x14f0,
6205                                  0x1500, 0x155c, 0x1580, 0x15dc,
6206                                  0x1600, 0x1658, 0x1680, 0x16d8,
6207                                  0x1800, 0x1820, 0x1840, 0x1854,
6208                                  0x1880, 0x1894, 0x1900, 0x1984,
6209                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6210                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6211                                  0x2000, 0x2030, 0x23c0, 0x2400,
6212                                  0x2800, 0x2820, 0x2830, 0x2850,
6213                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6214                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6215                                  0x4080, 0x4090, 0x43c0, 0x4458,
6216                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6217                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6218                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6219                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6220                                  0x6800, 0x6848, 0x684c, 0x6860,
6221                                  0x6888, 0x6910, 0x8000 };
6222
6223         regs->version = 0;
6224
6225         memset(p, 0, BNX2_REGDUMP_LEN);
6226
6227         if (!netif_running(bp->dev))
6228                 return;
6229
6230         i = 0;
6231         offset = reg_boundaries[0];
6232         p += offset;
6233         while (offset < BNX2_REGDUMP_LEN) {
6234                 *p++ = REG_RD(bp, offset);
6235                 offset += 4;
6236                 if (offset == reg_boundaries[i + 1]) {
6237                         offset = reg_boundaries[i + 2];
6238                         p = (u32 *) (orig_p + offset);
6239                         i += 2;
6240                 }
6241         }
6242 }
6243
6244 static void
6245 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6246 {
6247         struct bnx2 *bp = netdev_priv(dev);
6248
6249         if (bp->flags & BNX2_FLAG_NO_WOL) {
6250                 wol->supported = 0;
6251                 wol->wolopts = 0;
6252         }
6253         else {
6254                 wol->supported = WAKE_MAGIC;
6255                 if (bp->wol)
6256                         wol->wolopts = WAKE_MAGIC;
6257                 else
6258                         wol->wolopts = 0;
6259         }
6260         memset(&wol->sopass, 0, sizeof(wol->sopass));
6261 }
6262
6263 static int
6264 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6265 {
6266         struct bnx2 *bp = netdev_priv(dev);
6267
6268         if (wol->wolopts & ~WAKE_MAGIC)
6269                 return -EINVAL;
6270
6271         if (wol->wolopts & WAKE_MAGIC) {
6272                 if (bp->flags & BNX2_FLAG_NO_WOL)
6273                         return -EINVAL;
6274
6275                 bp->wol = 1;
6276         }
6277         else {
6278                 bp->wol = 0;
6279         }
6280         return 0;
6281 }
6282
6283 static int
6284 bnx2_nway_reset(struct net_device *dev)
6285 {
6286         struct bnx2 *bp = netdev_priv(dev);
6287         u32 bmcr;
6288
6289         if (!(bp->autoneg & AUTONEG_SPEED)) {
6290                 return -EINVAL;
6291         }
6292
6293         spin_lock_bh(&bp->phy_lock);
6294
6295         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6296                 int rc;
6297
6298                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6299                 spin_unlock_bh(&bp->phy_lock);
6300                 return rc;
6301         }
6302
6303         /* Force a link down visible on the other side */
6304         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6305                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6306                 spin_unlock_bh(&bp->phy_lock);
6307
6308                 msleep(20);
6309
6310                 spin_lock_bh(&bp->phy_lock);
6311
6312                 bp->current_interval = SERDES_AN_TIMEOUT;
6313                 bp->serdes_an_pending = 1;
6314                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6315         }
6316
6317         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6318         bmcr &= ~BMCR_LOOPBACK;
6319         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6320
6321         spin_unlock_bh(&bp->phy_lock);
6322
6323         return 0;
6324 }
6325
6326 static int
6327 bnx2_get_eeprom_len(struct net_device *dev)
6328 {
6329         struct bnx2 *bp = netdev_priv(dev);
6330
6331         if (bp->flash_info == NULL)
6332                 return 0;
6333
6334         return (int) bp->flash_size;
6335 }
6336
6337 static int
6338 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6339                 u8 *eebuf)
6340 {
6341         struct bnx2 *bp = netdev_priv(dev);
6342         int rc;
6343
6344         /* parameters already validated in ethtool_get_eeprom */
6345
6346         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6347
6348         return rc;
6349 }
6350
6351 static int
6352 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6353                 u8 *eebuf)
6354 {
6355         struct bnx2 *bp = netdev_priv(dev);
6356         int rc;
6357
6358         /* parameters already validated in ethtool_set_eeprom */
6359
6360         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6361
6362         return rc;
6363 }
6364
6365 static int
6366 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6367 {
6368         struct bnx2 *bp = netdev_priv(dev);
6369
6370         memset(coal, 0, sizeof(struct ethtool_coalesce));
6371
6372         coal->rx_coalesce_usecs = bp->rx_ticks;
6373         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6374         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6375         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6376
6377         coal->tx_coalesce_usecs = bp->tx_ticks;
6378         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6379         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6380         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6381
6382         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6383
6384         return 0;
6385 }
6386
6387 static int
6388 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6389 {
6390         struct bnx2 *bp = netdev_priv(dev);
6391
6392         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6393         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6394
6395         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6396         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6397
6398         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6399         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6400
6401         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6402         if (bp->rx_quick_cons_trip_int > 0xff)
6403                 bp->rx_quick_cons_trip_int = 0xff;
6404
6405         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6406         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6407
6408         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6409         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6410
6411         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6412         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6413
6414         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6415         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6416                 0xff;
6417
6418         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6419         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6420                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6421                         bp->stats_ticks = USEC_PER_SEC;
6422         }
6423         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6424                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6425         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6426
6427         if (netif_running(bp->dev)) {
6428                 bnx2_netif_stop(bp);
6429                 bnx2_init_nic(bp, 0);
6430                 bnx2_netif_start(bp);
6431         }
6432
6433         return 0;
6434 }
6435
6436 static void
6437 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6438 {
6439         struct bnx2 *bp = netdev_priv(dev);
6440
6441         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6442         ering->rx_mini_max_pending = 0;
6443         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6444
6445         ering->rx_pending = bp->rx_ring_size;
6446         ering->rx_mini_pending = 0;
6447         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6448
6449         ering->tx_max_pending = MAX_TX_DESC_CNT;
6450         ering->tx_pending = bp->tx_ring_size;
6451 }
6452
6453 static int
6454 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6455 {
6456         if (netif_running(bp->dev)) {
6457                 bnx2_netif_stop(bp);
6458                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6459                 bnx2_free_skbs(bp);
6460                 bnx2_free_mem(bp);
6461         }
6462
6463         bnx2_set_rx_ring_size(bp, rx);
6464         bp->tx_ring_size = tx;
6465
6466         if (netif_running(bp->dev)) {
6467                 int rc;
6468
6469                 rc = bnx2_alloc_mem(bp);
6470                 if (rc)
6471                         return rc;
6472                 bnx2_init_nic(bp, 0);
6473                 bnx2_netif_start(bp);
6474         }
6475         return 0;
6476 }
6477
6478 static int
6479 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6480 {
6481         struct bnx2 *bp = netdev_priv(dev);
6482         int rc;
6483
6484         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6485                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6486                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6487
6488                 return -EINVAL;
6489         }
6490         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6491         return rc;
6492 }
6493
6494 static void
6495 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6496 {
6497         struct bnx2 *bp = netdev_priv(dev);
6498
6499         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6500         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6501         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6502 }
6503
6504 static int
6505 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6506 {
6507         struct bnx2 *bp = netdev_priv(dev);
6508
6509         bp->req_flow_ctrl = 0;
6510         if (epause->rx_pause)
6511                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6512         if (epause->tx_pause)
6513                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6514
6515         if (epause->autoneg) {
6516                 bp->autoneg |= AUTONEG_FLOW_CTRL;
6517         }
6518         else {
6519                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6520         }
6521
6522         spin_lock_bh(&bp->phy_lock);
6523
6524         bnx2_setup_phy(bp, bp->phy_port);
6525
6526         spin_unlock_bh(&bp->phy_lock);
6527
6528         return 0;
6529 }
6530
6531 static u32
6532 bnx2_get_rx_csum(struct net_device *dev)
6533 {
6534         struct bnx2 *bp = netdev_priv(dev);
6535
6536         return bp->rx_csum;
6537 }
6538
6539 static int
6540 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6541 {
6542         struct bnx2 *bp = netdev_priv(dev);
6543
6544         bp->rx_csum = data;
6545         return 0;
6546 }
6547
6548 static int
6549 bnx2_set_tso(struct net_device *dev, u32 data)
6550 {
6551         struct bnx2 *bp = netdev_priv(dev);
6552
6553         if (data) {
6554                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6555                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6556                         dev->features |= NETIF_F_TSO6;
6557         } else
6558                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6559                                    NETIF_F_TSO_ECN);
6560         return 0;
6561 }
6562
6563 #define BNX2_NUM_STATS 46
6564
6565 static struct {
6566         char string[ETH_GSTRING_LEN];
6567 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6568         { "rx_bytes" },
6569         { "rx_error_bytes" },
6570         { "tx_bytes" },
6571         { "tx_error_bytes" },
6572         { "rx_ucast_packets" },
6573         { "rx_mcast_packets" },
6574         { "rx_bcast_packets" },
6575         { "tx_ucast_packets" },
6576         { "tx_mcast_packets" },
6577         { "tx_bcast_packets" },
6578         { "tx_mac_errors" },
6579         { "tx_carrier_errors" },
6580         { "rx_crc_errors" },
6581         { "rx_align_errors" },
6582         { "tx_single_collisions" },
6583         { "tx_multi_collisions" },
6584         { "tx_deferred" },
6585         { "tx_excess_collisions" },
6586         { "tx_late_collisions" },
6587         { "tx_total_collisions" },
6588         { "rx_fragments" },
6589         { "rx_jabbers" },
6590         { "rx_undersize_packets" },
6591         { "rx_oversize_packets" },
6592         { "rx_64_byte_packets" },
6593         { "rx_65_to_127_byte_packets" },
6594         { "rx_128_to_255_byte_packets" },
6595         { "rx_256_to_511_byte_packets" },
6596         { "rx_512_to_1023_byte_packets" },
6597         { "rx_1024_to_1522_byte_packets" },
6598         { "rx_1523_to_9022_byte_packets" },
6599         { "tx_64_byte_packets" },
6600         { "tx_65_to_127_byte_packets" },
6601         { "tx_128_to_255_byte_packets" },
6602         { "tx_256_to_511_byte_packets" },
6603         { "tx_512_to_1023_byte_packets" },
6604         { "tx_1024_to_1522_byte_packets" },
6605         { "tx_1523_to_9022_byte_packets" },
6606         { "rx_xon_frames" },
6607         { "rx_xoff_frames" },
6608         { "tx_xon_frames" },
6609         { "tx_xoff_frames" },
6610         { "rx_mac_ctrl_frames" },
6611         { "rx_filtered_packets" },
6612         { "rx_discards" },
6613         { "rx_fw_discards" },
6614 };
6615
6616 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6617
6618 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6619     STATS_OFFSET32(stat_IfHCInOctets_hi),
6620     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6621     STATS_OFFSET32(stat_IfHCOutOctets_hi),
6622     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6623     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6624     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6625     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6626     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6627     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6628     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6629     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6630     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6631     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6632     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6633     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6634     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6635     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6636     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6637     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6638     STATS_OFFSET32(stat_EtherStatsCollisions),
6639     STATS_OFFSET32(stat_EtherStatsFragments),
6640     STATS_OFFSET32(stat_EtherStatsJabbers),
6641     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6642     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6643     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6644     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6645     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6646     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6647     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6648     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6649     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6650     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6651     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6652     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6653     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6654     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6655     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6656     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6657     STATS_OFFSET32(stat_XonPauseFramesReceived),
6658     STATS_OFFSET32(stat_XoffPauseFramesReceived),
6659     STATS_OFFSET32(stat_OutXonSent),
6660     STATS_OFFSET32(stat_OutXoffSent),
6661     STATS_OFFSET32(stat_MacControlFramesReceived),
6662     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6663     STATS_OFFSET32(stat_IfInMBUFDiscards),
6664     STATS_OFFSET32(stat_FwRxDrop),
6665 };
6666
6667 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6668  * skipped because of errata.
6669  */
6670 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6671         8,0,8,8,8,8,8,8,8,8,
6672         4,0,4,4,4,4,4,4,4,4,
6673         4,4,4,4,4,4,4,4,4,4,
6674         4,4,4,4,4,4,4,4,4,4,
6675         4,4,4,4,4,4,
6676 };
6677
6678 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6679         8,0,8,8,8,8,8,8,8,8,
6680         4,4,4,4,4,4,4,4,4,4,
6681         4,4,4,4,4,4,4,4,4,4,
6682         4,4,4,4,4,4,4,4,4,4,
6683         4,4,4,4,4,4,
6684 };
6685
6686 #define BNX2_NUM_TESTS 6
6687
6688 static struct {
6689         char string[ETH_GSTRING_LEN];
6690 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6691         { "register_test (offline)" },
6692         { "memory_test (offline)" },
6693         { "loopback_test (offline)" },
6694         { "nvram_test (online)" },
6695         { "interrupt_test (online)" },
6696         { "link_test (online)" },
6697 };
6698
6699 static int
6700 bnx2_get_sset_count(struct net_device *dev, int sset)
6701 {
6702         switch (sset) {
6703         case ETH_SS_TEST:
6704                 return BNX2_NUM_TESTS;
6705         case ETH_SS_STATS:
6706                 return BNX2_NUM_STATS;
6707         default:
6708                 return -EOPNOTSUPP;
6709         }
6710 }
6711
6712 static void
6713 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6714 {
6715         struct bnx2 *bp = netdev_priv(dev);
6716
6717         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6718         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6719                 int i;
6720
6721                 bnx2_netif_stop(bp);
6722                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6723                 bnx2_free_skbs(bp);
6724
6725                 if (bnx2_test_registers(bp) != 0) {
6726                         buf[0] = 1;
6727                         etest->flags |= ETH_TEST_FL_FAILED;
6728                 }
6729                 if (bnx2_test_memory(bp) != 0) {
6730                         buf[1] = 1;
6731                         etest->flags |= ETH_TEST_FL_FAILED;
6732                 }
6733                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6734                         etest->flags |= ETH_TEST_FL_FAILED;
6735
6736                 if (!netif_running(bp->dev)) {
6737                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6738                 }
6739                 else {
6740                         bnx2_init_nic(bp, 1);
6741                         bnx2_netif_start(bp);
6742                 }
6743
6744                 /* wait for link up */
6745                 for (i = 0; i < 7; i++) {
6746                         if (bp->link_up)
6747                                 break;
6748                         msleep_interruptible(1000);
6749                 }
6750         }
6751
6752         if (bnx2_test_nvram(bp) != 0) {
6753                 buf[3] = 1;
6754                 etest->flags |= ETH_TEST_FL_FAILED;
6755         }
6756         if (bnx2_test_intr(bp) != 0) {
6757                 buf[4] = 1;
6758                 etest->flags |= ETH_TEST_FL_FAILED;
6759         }
6760
6761         if (bnx2_test_link(bp) != 0) {
6762                 buf[5] = 1;
6763                 etest->flags |= ETH_TEST_FL_FAILED;
6764
6765         }
6766 }
6767
6768 static void
6769 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6770 {
6771         switch (stringset) {
6772         case ETH_SS_STATS:
6773                 memcpy(buf, bnx2_stats_str_arr,
6774                         sizeof(bnx2_stats_str_arr));
6775                 break;
6776         case ETH_SS_TEST:
6777                 memcpy(buf, bnx2_tests_str_arr,
6778                         sizeof(bnx2_tests_str_arr));
6779                 break;
6780         }
6781 }
6782
6783 static void
6784 bnx2_get_ethtool_stats(struct net_device *dev,
6785                 struct ethtool_stats *stats, u64 *buf)
6786 {
6787         struct bnx2 *bp = netdev_priv(dev);
6788         int i;
6789         u32 *hw_stats = (u32 *) bp->stats_blk;
6790         u8 *stats_len_arr = NULL;
6791
6792         if (hw_stats == NULL) {
6793                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6794                 return;
6795         }
6796
6797         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6798             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6799             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6800             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6801                 stats_len_arr = bnx2_5706_stats_len_arr;
6802         else
6803                 stats_len_arr = bnx2_5708_stats_len_arr;
6804
6805         for (i = 0; i < BNX2_NUM_STATS; i++) {
6806                 if (stats_len_arr[i] == 0) {
6807                         /* skip this counter */
6808                         buf[i] = 0;
6809                         continue;
6810                 }
6811                 if (stats_len_arr[i] == 4) {
6812                         /* 4-byte counter */
6813                         buf[i] = (u64)
6814                                 *(hw_stats + bnx2_stats_offset_arr[i]);
6815                         continue;
6816                 }
6817                 /* 8-byte counter */
6818                 buf[i] = (((u64) *(hw_stats +
6819                                         bnx2_stats_offset_arr[i])) << 32) +
6820                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6821         }
6822 }
6823
6824 static int
6825 bnx2_phys_id(struct net_device *dev, u32 data)
6826 {
6827         struct bnx2 *bp = netdev_priv(dev);
6828         int i;
6829         u32 save;
6830
6831         if (data == 0)
6832                 data = 2;
6833
6834         save = REG_RD(bp, BNX2_MISC_CFG);
6835         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6836
6837         for (i = 0; i < (data * 2); i++) {
6838                 if ((i % 2) == 0) {
6839                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6840                 }
6841                 else {
6842                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6843                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
6844                                 BNX2_EMAC_LED_100MB_OVERRIDE |
6845                                 BNX2_EMAC_LED_10MB_OVERRIDE |
6846                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6847                                 BNX2_EMAC_LED_TRAFFIC);
6848                 }
6849                 msleep_interruptible(500);
6850                 if (signal_pending(current))
6851                         break;
6852         }
6853         REG_WR(bp, BNX2_EMAC_LED, 0);
6854         REG_WR(bp, BNX2_MISC_CFG, save);
6855         return 0;
6856 }
6857
6858 static int
6859 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6860 {
6861         struct bnx2 *bp = netdev_priv(dev);
6862
6863         if (CHIP_NUM(bp) == CHIP_NUM_5709)
6864                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6865         else
6866                 return (ethtool_op_set_tx_csum(dev, data));
6867 }
6868
6869 static const struct ethtool_ops bnx2_ethtool_ops = {
6870         .get_settings           = bnx2_get_settings,
6871         .set_settings           = bnx2_set_settings,
6872         .get_drvinfo            = bnx2_get_drvinfo,
6873         .get_regs_len           = bnx2_get_regs_len,
6874         .get_regs               = bnx2_get_regs,
6875         .get_wol                = bnx2_get_wol,
6876         .set_wol                = bnx2_set_wol,
6877         .nway_reset             = bnx2_nway_reset,
6878         .get_link               = ethtool_op_get_link,
6879         .get_eeprom_len         = bnx2_get_eeprom_len,
6880         .get_eeprom             = bnx2_get_eeprom,
6881         .set_eeprom             = bnx2_set_eeprom,
6882         .get_coalesce           = bnx2_get_coalesce,
6883         .set_coalesce           = bnx2_set_coalesce,
6884         .get_ringparam          = bnx2_get_ringparam,
6885         .set_ringparam          = bnx2_set_ringparam,
6886         .get_pauseparam         = bnx2_get_pauseparam,
6887         .set_pauseparam         = bnx2_set_pauseparam,
6888         .get_rx_csum            = bnx2_get_rx_csum,
6889         .set_rx_csum            = bnx2_set_rx_csum,
6890         .set_tx_csum            = bnx2_set_tx_csum,
6891         .set_sg                 = ethtool_op_set_sg,
6892         .set_tso                = bnx2_set_tso,
6893         .self_test              = bnx2_self_test,
6894         .get_strings            = bnx2_get_strings,
6895         .phys_id                = bnx2_phys_id,
6896         .get_ethtool_stats      = bnx2_get_ethtool_stats,
6897         .get_sset_count         = bnx2_get_sset_count,
6898 };
6899
6900 /* Called with rtnl_lock */
6901 static int
6902 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6903 {
6904         struct mii_ioctl_data *data = if_mii(ifr);
6905         struct bnx2 *bp = netdev_priv(dev);
6906         int err;
6907
6908         switch(cmd) {
6909         case SIOCGMIIPHY:
6910                 data->phy_id = bp->phy_addr;
6911
6912                 /* fallthru */
6913         case SIOCGMIIREG: {
6914                 u32 mii_regval;
6915
6916                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6917                         return -EOPNOTSUPP;
6918
6919                 if (!netif_running(dev))
6920                         return -EAGAIN;
6921
6922                 spin_lock_bh(&bp->phy_lock);
6923                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6924                 spin_unlock_bh(&bp->phy_lock);
6925
6926                 data->val_out = mii_regval;
6927
6928                 return err;
6929         }
6930
6931         case SIOCSMIIREG:
6932                 if (!capable(CAP_NET_ADMIN))
6933                         return -EPERM;
6934
6935                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6936                         return -EOPNOTSUPP;
6937
6938                 if (!netif_running(dev))
6939                         return -EAGAIN;
6940
6941                 spin_lock_bh(&bp->phy_lock);
6942                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6943                 spin_unlock_bh(&bp->phy_lock);
6944
6945                 return err;
6946
6947         default:
6948                 /* do nothing */
6949                 break;
6950         }
6951         return -EOPNOTSUPP;
6952 }
6953
6954 /* Called with rtnl_lock */
6955 static int
6956 bnx2_change_mac_addr(struct net_device *dev, void *p)
6957 {
6958         struct sockaddr *addr = p;
6959         struct bnx2 *bp = netdev_priv(dev);
6960
6961         if (!is_valid_ether_addr(addr->sa_data))
6962                 return -EINVAL;
6963
6964         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6965         if (netif_running(dev))
6966                 bnx2_set_mac_addr(bp);
6967
6968         return 0;
6969 }
6970
6971 /* Called with rtnl_lock */
6972 static int
6973 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6974 {
6975         struct bnx2 *bp = netdev_priv(dev);
6976
6977         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6978                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6979                 return -EINVAL;
6980
6981         dev->mtu = new_mtu;
6982         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
6983 }
6984
6985 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6986 static void
6987 poll_bnx2(struct net_device *dev)
6988 {
6989         struct bnx2 *bp = netdev_priv(dev);
6990
6991         disable_irq(bp->pdev->irq);
6992         bnx2_interrupt(bp->pdev->irq, dev);
6993         enable_irq(bp->pdev->irq);
6994 }
6995 #endif
6996
6997 static void __devinit
6998 bnx2_get_5709_media(struct bnx2 *bp)
6999 {
7000         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7001         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7002         u32 strap;
7003
7004         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7005                 return;
7006         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7007                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7008                 return;
7009         }
7010
7011         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7012                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7013         else
7014                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7015
7016         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7017                 switch (strap) {
7018                 case 0x4:
7019                 case 0x5:
7020                 case 0x6:
7021                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7022                         return;
7023                 }
7024         } else {
7025                 switch (strap) {
7026                 case 0x1:
7027                 case 0x2:
7028                 case 0x4:
7029                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7030                         return;
7031                 }
7032         }
7033 }
7034
7035 static void __devinit
7036 bnx2_get_pci_speed(struct bnx2 *bp)
7037 {
7038         u32 reg;
7039
7040         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7041         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7042                 u32 clkreg;
7043
7044                 bp->flags |= BNX2_FLAG_PCIX;
7045
7046                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7047
7048                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7049                 switch (clkreg) {
7050                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7051                         bp->bus_speed_mhz = 133;
7052                         break;
7053
7054                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7055                         bp->bus_speed_mhz = 100;
7056                         break;
7057
7058                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7059                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7060                         bp->bus_speed_mhz = 66;
7061                         break;
7062
7063                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7064                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7065                         bp->bus_speed_mhz = 50;
7066                         break;
7067
7068                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7069                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7070                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7071                         bp->bus_speed_mhz = 33;
7072                         break;
7073                 }
7074         }
7075         else {
7076                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7077                         bp->bus_speed_mhz = 66;
7078                 else
7079                         bp->bus_speed_mhz = 33;
7080         }
7081
7082         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7083                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7084
7085 }
7086
7087 static int __devinit
7088 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7089 {
7090         struct bnx2 *bp;
7091         unsigned long mem_len;
7092         int rc, i, j;
7093         u32 reg;
7094         u64 dma_mask, persist_dma_mask;
7095
7096         SET_NETDEV_DEV(dev, &pdev->dev);
7097         bp = netdev_priv(dev);
7098
7099         bp->flags = 0;
7100         bp->phy_flags = 0;
7101
7102         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7103         rc = pci_enable_device(pdev);
7104         if (rc) {
7105                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7106                 goto err_out;
7107         }
7108
7109         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7110                 dev_err(&pdev->dev,
7111                         "Cannot find PCI device base address, aborting.\n");
7112                 rc = -ENODEV;
7113                 goto err_out_disable;
7114         }
7115
7116         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7117         if (rc) {
7118                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7119                 goto err_out_disable;
7120         }
7121
7122         pci_set_master(pdev);
7123         pci_save_state(pdev);
7124
7125         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7126         if (bp->pm_cap == 0) {
7127                 dev_err(&pdev->dev,
7128                         "Cannot find power management capability, aborting.\n");
7129                 rc = -EIO;
7130                 goto err_out_release;
7131         }
7132
7133         bp->dev = dev;
7134         bp->pdev = pdev;
7135
7136         spin_lock_init(&bp->phy_lock);
7137         spin_lock_init(&bp->indirect_lock);
7138         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7139
7140         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7141         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
7142         dev->mem_end = dev->mem_start + mem_len;
7143         dev->irq = pdev->irq;
7144
7145         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7146
7147         if (!bp->regview) {
7148                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7149                 rc = -ENOMEM;
7150                 goto err_out_release;
7151         }
7152
7153         /* Configure byte swap and enable write to the reg_window registers.
7154          * Rely on CPU to do target byte swapping on big endian systems
7155          * The chip's target access swapping will not swap all accesses
7156          */
7157         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7158                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7159                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7160
7161         bnx2_set_power_state(bp, PCI_D0);
7162
7163         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7164
7165         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7166                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7167                         dev_err(&pdev->dev,
7168                                 "Cannot find PCIE capability, aborting.\n");
7169                         rc = -EIO;
7170                         goto err_out_unmap;
7171                 }
7172                 bp->flags |= BNX2_FLAG_PCIE;
7173                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7174                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7175         } else {
7176                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7177                 if (bp->pcix_cap == 0) {
7178                         dev_err(&pdev->dev,
7179                                 "Cannot find PCIX capability, aborting.\n");
7180                         rc = -EIO;
7181                         goto err_out_unmap;
7182                 }
7183         }
7184
7185         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7186                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7187                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7188         }
7189
7190         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7191                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7192                         bp->flags |= BNX2_FLAG_MSI_CAP;
7193         }
7194
7195         /* 5708 cannot support DMA addresses > 40-bit.  */
7196         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7197                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7198         else
7199                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7200
7201         /* Configure DMA attributes. */
7202         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7203                 dev->features |= NETIF_F_HIGHDMA;
7204                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7205                 if (rc) {
7206                         dev_err(&pdev->dev,
7207                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7208                         goto err_out_unmap;
7209                 }
7210         } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7211                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7212                 goto err_out_unmap;
7213         }
7214
7215         if (!(bp->flags & BNX2_FLAG_PCIE))
7216                 bnx2_get_pci_speed(bp);
7217
7218         /* 5706A0 may falsely detect SERR and PERR. */
7219         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7220                 reg = REG_RD(bp, PCI_COMMAND);
7221                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7222                 REG_WR(bp, PCI_COMMAND, reg);
7223         }
7224         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7225                 !(bp->flags & BNX2_FLAG_PCIX)) {
7226
7227                 dev_err(&pdev->dev,
7228                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7229                 goto err_out_unmap;
7230         }
7231
7232         bnx2_init_nvram(bp);
7233
7234         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7235
7236         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7237             BNX2_SHM_HDR_SIGNATURE_SIG) {
7238                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7239
7240                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7241         } else
7242                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7243
7244         /* Get the permanent MAC address.  First we need to make sure the
7245          * firmware is actually running.
7246          */
7247         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7248
7249         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7250             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7251                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7252                 rc = -ENODEV;
7253                 goto err_out_unmap;
7254         }
7255
7256         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7257         for (i = 0, j = 0; i < 3; i++) {
7258                 u8 num, k, skip0;
7259
7260                 num = (u8) (reg >> (24 - (i * 8)));
7261                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7262                         if (num >= k || !skip0 || k == 1) {
7263                                 bp->fw_version[j++] = (num / k) + '0';
7264                                 skip0 = 0;
7265                         }
7266                 }
7267                 if (i != 2)
7268                         bp->fw_version[j++] = '.';
7269         }
7270         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7271         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7272                 bp->wol = 1;
7273
7274         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7275                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7276
7277                 for (i = 0; i < 30; i++) {
7278                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7279                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7280                                 break;
7281                         msleep(10);
7282                 }
7283         }
7284         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7285         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7286         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7287             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7288                 int i;
7289                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7290
7291                 bp->fw_version[j++] = ' ';
7292                 for (i = 0; i < 3; i++) {
7293                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7294                         reg = swab32(reg);
7295                         memcpy(&bp->fw_version[j], &reg, 4);
7296                         j += 4;
7297                 }
7298         }
7299
7300         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7301         bp->mac_addr[0] = (u8) (reg >> 8);
7302         bp->mac_addr[1] = (u8) reg;
7303
7304         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7305         bp->mac_addr[2] = (u8) (reg >> 24);
7306         bp->mac_addr[3] = (u8) (reg >> 16);
7307         bp->mac_addr[4] = (u8) (reg >> 8);
7308         bp->mac_addr[5] = (u8) reg;
7309
7310         bp->tx_ring_size = MAX_TX_DESC_CNT;
7311         bnx2_set_rx_ring_size(bp, 255);
7312
7313         bp->rx_csum = 1;
7314
7315         bp->tx_quick_cons_trip_int = 20;
7316         bp->tx_quick_cons_trip = 20;
7317         bp->tx_ticks_int = 80;
7318         bp->tx_ticks = 80;
7319
7320         bp->rx_quick_cons_trip_int = 6;
7321         bp->rx_quick_cons_trip = 6;
7322         bp->rx_ticks_int = 18;
7323         bp->rx_ticks = 18;
7324
7325         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7326
7327         bp->timer_interval =  HZ;
7328         bp->current_interval =  HZ;
7329
7330         bp->phy_addr = 1;
7331
7332         /* Disable WOL support if we are running on a SERDES chip. */
7333         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7334                 bnx2_get_5709_media(bp);
7335         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7336                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7337
7338         bp->phy_port = PORT_TP;
7339         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7340                 bp->phy_port = PORT_FIBRE;
7341                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7342                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7343                         bp->flags |= BNX2_FLAG_NO_WOL;
7344                         bp->wol = 0;
7345                 }
7346                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7347                         /* Don't do parallel detect on this board because of
7348                          * some board problems.  The link will not go down
7349                          * if we do parallel detect.
7350                          */
7351                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7352                             pdev->subsystem_device == 0x310c)
7353                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7354                 } else {
7355                         bp->phy_addr = 2;
7356                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7357                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7358                 }
7359                 bnx2_init_remote_phy(bp);
7360
7361         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7362                    CHIP_NUM(bp) == CHIP_NUM_5708)
7363                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7364         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7365                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7366                   CHIP_REV(bp) == CHIP_REV_Bx))
7367                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7368
7369         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7370             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7371             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7372                 bp->flags |= BNX2_FLAG_NO_WOL;
7373                 bp->wol = 0;
7374         }
7375
7376         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7377                 bp->tx_quick_cons_trip_int =
7378                         bp->tx_quick_cons_trip;
7379                 bp->tx_ticks_int = bp->tx_ticks;
7380                 bp->rx_quick_cons_trip_int =
7381                         bp->rx_quick_cons_trip;
7382                 bp->rx_ticks_int = bp->rx_ticks;
7383                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7384                 bp->com_ticks_int = bp->com_ticks;
7385                 bp->cmd_ticks_int = bp->cmd_ticks;
7386         }
7387
7388         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7389          *
7390          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7391          * with byte enables disabled on the unused 32-bit word.  This is legal
7392          * but causes problems on the AMD 8132 which will eventually stop
7393          * responding after a while.
7394          *
7395          * AMD believes this incompatibility is unique to the 5706, and
7396          * prefers to locally disable MSI rather than globally disabling it.
7397          */
7398         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7399                 struct pci_dev *amd_8132 = NULL;
7400
7401                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7402                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7403                                                   amd_8132))) {
7404
7405                         if (amd_8132->revision >= 0x10 &&
7406                             amd_8132->revision <= 0x13) {
7407                                 disable_msi = 1;
7408                                 pci_dev_put(amd_8132);
7409                                 break;
7410                         }
7411                 }
7412         }
7413
7414         bnx2_set_default_link(bp);
7415         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7416
7417         init_timer(&bp->timer);
7418         bp->timer.expires = RUN_AT(bp->timer_interval);
7419         bp->timer.data = (unsigned long) bp;
7420         bp->timer.function = bnx2_timer;
7421
7422         return 0;
7423
7424 err_out_unmap:
7425         if (bp->regview) {
7426                 iounmap(bp->regview);
7427                 bp->regview = NULL;
7428         }
7429
7430 err_out_release:
7431         pci_release_regions(pdev);
7432
7433 err_out_disable:
7434         pci_disable_device(pdev);
7435         pci_set_drvdata(pdev, NULL);
7436
7437 err_out:
7438         return rc;
7439 }
7440
7441 static char * __devinit
7442 bnx2_bus_string(struct bnx2 *bp, char *str)
7443 {
7444         char *s = str;
7445
7446         if (bp->flags & BNX2_FLAG_PCIE) {
7447                 s += sprintf(s, "PCI Express");
7448         } else {
7449                 s += sprintf(s, "PCI");
7450                 if (bp->flags & BNX2_FLAG_PCIX)
7451                         s += sprintf(s, "-X");
7452                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7453                         s += sprintf(s, " 32-bit");
7454                 else
7455                         s += sprintf(s, " 64-bit");
7456                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7457         }
7458         return str;
7459 }
7460
7461 static void __devinit
7462 bnx2_init_napi(struct bnx2 *bp)
7463 {
7464         int i;
7465         struct bnx2_napi *bnapi;
7466
7467         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7468                 bnapi = &bp->bnx2_napi[i];
7469                 bnapi->bp = bp;
7470         }
7471         netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
7472         netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7473                        64);
7474 }
7475
7476 static int __devinit
7477 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7478 {
7479         static int version_printed = 0;
7480         struct net_device *dev = NULL;
7481         struct bnx2 *bp;
7482         int rc;
7483         char str[40];
7484         DECLARE_MAC_BUF(mac);
7485
7486         if (version_printed++ == 0)
7487                 printk(KERN_INFO "%s", version);
7488
7489         /* dev zeroed in init_etherdev */
7490         dev = alloc_etherdev(sizeof(*bp));
7491
7492         if (!dev)
7493                 return -ENOMEM;
7494
7495         rc = bnx2_init_board(pdev, dev);
7496         if (rc < 0) {
7497                 free_netdev(dev);
7498                 return rc;
7499         }
7500
7501         dev->open = bnx2_open;
7502         dev->hard_start_xmit = bnx2_start_xmit;
7503         dev->stop = bnx2_close;
7504         dev->get_stats = bnx2_get_stats;
7505         dev->set_multicast_list = bnx2_set_rx_mode;
7506         dev->do_ioctl = bnx2_ioctl;
7507         dev->set_mac_address = bnx2_change_mac_addr;
7508         dev->change_mtu = bnx2_change_mtu;
7509         dev->tx_timeout = bnx2_tx_timeout;
7510         dev->watchdog_timeo = TX_TIMEOUT;
7511 #ifdef BCM_VLAN
7512         dev->vlan_rx_register = bnx2_vlan_rx_register;
7513 #endif
7514         dev->ethtool_ops = &bnx2_ethtool_ops;
7515
7516         bp = netdev_priv(dev);
7517         bnx2_init_napi(bp);
7518
7519 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7520         dev->poll_controller = poll_bnx2;
7521 #endif
7522
7523         pci_set_drvdata(pdev, dev);
7524
7525         memcpy(dev->dev_addr, bp->mac_addr, 6);
7526         memcpy(dev->perm_addr, bp->mac_addr, 6);
7527         bp->name = board_info[ent->driver_data].name;
7528
7529         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7530         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7531                 dev->features |= NETIF_F_IPV6_CSUM;
7532
7533 #ifdef BCM_VLAN
7534         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7535 #endif
7536         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7537         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7538                 dev->features |= NETIF_F_TSO6;
7539
7540         if ((rc = register_netdev(dev))) {
7541                 dev_err(&pdev->dev, "Cannot register net device\n");
7542                 if (bp->regview)
7543                         iounmap(bp->regview);
7544                 pci_release_regions(pdev);
7545                 pci_disable_device(pdev);
7546                 pci_set_drvdata(pdev, NULL);
7547                 free_netdev(dev);
7548                 return rc;
7549         }
7550
7551         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7552                 "IRQ %d, node addr %s\n",
7553                 dev->name,
7554                 bp->name,
7555                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7556                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7557                 bnx2_bus_string(bp, str),
7558                 dev->base_addr,
7559                 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7560
7561         return 0;
7562 }
7563
7564 static void __devexit
7565 bnx2_remove_one(struct pci_dev *pdev)
7566 {
7567         struct net_device *dev = pci_get_drvdata(pdev);
7568         struct bnx2 *bp = netdev_priv(dev);
7569
7570         flush_scheduled_work();
7571
7572         unregister_netdev(dev);
7573
7574         if (bp->regview)
7575                 iounmap(bp->regview);
7576
7577         free_netdev(dev);
7578         pci_release_regions(pdev);
7579         pci_disable_device(pdev);
7580         pci_set_drvdata(pdev, NULL);
7581 }
7582
7583 static int
7584 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7585 {
7586         struct net_device *dev = pci_get_drvdata(pdev);
7587         struct bnx2 *bp = netdev_priv(dev);
7588         u32 reset_code;
7589
7590         /* PCI register 4 needs to be saved whether netif_running() or not.
7591          * MSI address and data need to be saved if using MSI and
7592          * netif_running().
7593          */
7594         pci_save_state(pdev);
7595         if (!netif_running(dev))
7596                 return 0;
7597
7598         flush_scheduled_work();
7599         bnx2_netif_stop(bp);
7600         netif_device_detach(dev);
7601         del_timer_sync(&bp->timer);
7602         if (bp->flags & BNX2_FLAG_NO_WOL)
7603                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7604         else if (bp->wol)
7605                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7606         else
7607                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7608         bnx2_reset_chip(bp, reset_code);
7609         bnx2_free_skbs(bp);
7610         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7611         return 0;
7612 }
7613
7614 static int
7615 bnx2_resume(struct pci_dev *pdev)
7616 {
7617         struct net_device *dev = pci_get_drvdata(pdev);
7618         struct bnx2 *bp = netdev_priv(dev);
7619
7620         pci_restore_state(pdev);
7621         if (!netif_running(dev))
7622                 return 0;
7623
7624         bnx2_set_power_state(bp, PCI_D0);
7625         netif_device_attach(dev);
7626         bnx2_init_nic(bp, 1);
7627         bnx2_netif_start(bp);
7628         return 0;
7629 }
7630
7631 /**
7632  * bnx2_io_error_detected - called when PCI error is detected
7633  * @pdev: Pointer to PCI device
7634  * @state: The current pci connection state
7635  *
7636  * This function is called after a PCI bus error affecting
7637  * this device has been detected.
7638  */
7639 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7640                                                pci_channel_state_t state)
7641 {
7642         struct net_device *dev = pci_get_drvdata(pdev);
7643         struct bnx2 *bp = netdev_priv(dev);
7644
7645         rtnl_lock();
7646         netif_device_detach(dev);
7647
7648         if (netif_running(dev)) {
7649                 bnx2_netif_stop(bp);
7650                 del_timer_sync(&bp->timer);
7651                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7652         }
7653
7654         pci_disable_device(pdev);
7655         rtnl_unlock();
7656
7657         /* Request a slot slot reset. */
7658         return PCI_ERS_RESULT_NEED_RESET;
7659 }
7660
7661 /**
7662  * bnx2_io_slot_reset - called after the pci bus has been reset.
7663  * @pdev: Pointer to PCI device
7664  *
7665  * Restart the card from scratch, as if from a cold-boot.
7666  */
7667 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7668 {
7669         struct net_device *dev = pci_get_drvdata(pdev);
7670         struct bnx2 *bp = netdev_priv(dev);
7671
7672         rtnl_lock();
7673         if (pci_enable_device(pdev)) {
7674                 dev_err(&pdev->dev,
7675                         "Cannot re-enable PCI device after reset.\n");
7676                 rtnl_unlock();
7677                 return PCI_ERS_RESULT_DISCONNECT;
7678         }
7679         pci_set_master(pdev);
7680         pci_restore_state(pdev);
7681
7682         if (netif_running(dev)) {
7683                 bnx2_set_power_state(bp, PCI_D0);
7684                 bnx2_init_nic(bp, 1);
7685         }
7686
7687         rtnl_unlock();
7688         return PCI_ERS_RESULT_RECOVERED;
7689 }
7690
7691 /**
7692  * bnx2_io_resume - called when traffic can start flowing again.
7693  * @pdev: Pointer to PCI device
7694  *
7695  * This callback is called when the error recovery driver tells us that
7696  * its OK to resume normal operation.
7697  */
7698 static void bnx2_io_resume(struct pci_dev *pdev)
7699 {
7700         struct net_device *dev = pci_get_drvdata(pdev);
7701         struct bnx2 *bp = netdev_priv(dev);
7702
7703         rtnl_lock();
7704         if (netif_running(dev))
7705                 bnx2_netif_start(bp);
7706
7707         netif_device_attach(dev);
7708         rtnl_unlock();
7709 }
7710
7711 static struct pci_error_handlers bnx2_err_handler = {
7712         .error_detected = bnx2_io_error_detected,
7713         .slot_reset     = bnx2_io_slot_reset,
7714         .resume         = bnx2_io_resume,
7715 };
7716
7717 static struct pci_driver bnx2_pci_driver = {
7718         .name           = DRV_MODULE_NAME,
7719         .id_table       = bnx2_pci_tbl,
7720         .probe          = bnx2_init_one,
7721         .remove         = __devexit_p(bnx2_remove_one),
7722         .suspend        = bnx2_suspend,
7723         .resume         = bnx2_resume,
7724         .err_handler    = &bnx2_err_handler,
7725 };
7726
7727 static int __init bnx2_init(void)
7728 {
7729         return pci_register_driver(&bnx2_pci_driver);
7730 }
7731
7732 static void __exit bnx2_cleanup(void)
7733 {
7734         pci_unregister_driver(&bnx2_pci_driver);
7735 }
7736
7737 module_init(bnx2_init);
7738 module_exit(bnx2_cleanup);
7739
7740
7741