1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
15 /****************************************************************************
16 * Shared HW configuration *
17 ****************************************************************************/
18 struct shared_hw_cfg { /* NVRAM Offset */
19 /* Up to 16 bytes of NULL-terminated string */
20 u8 part_num[16]; /* 0x104 */
22 u32 config; /* 0x114 */
23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
29 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
31 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
33 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
35 /* Whatever MFW found in NVM
36 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
39 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
40 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
41 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
44 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
47 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
51 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
52 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
53 #define SHARED_HW_CFG_LED_MAC1 0x00000000
54 #define SHARED_HW_CFG_LED_PHY1 0x00010000
55 #define SHARED_HW_CFG_LED_PHY2 0x00020000
56 #define SHARED_HW_CFG_LED_PHY3 0x00030000
57 #define SHARED_HW_CFG_LED_MAC2 0x00040000
58 #define SHARED_HW_CFG_LED_PHY4 0x00050000
59 #define SHARED_HW_CFG_LED_PHY5 0x00060000
60 #define SHARED_HW_CFG_LED_PHY6 0x00070000
61 #define SHARED_HW_CFG_LED_MAC3 0x00080000
62 #define SHARED_HW_CFG_LED_PHY7 0x00090000
63 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
64 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
65 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
66 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
68 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
70 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
71 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
72 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
77 u32 config2; /* 0x118 */
78 /* one time auto detect grace period (in sec) */
79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
84 /* The default value for the core clock is 250MHz and it is
85 achieved by setting the clock change to 4 */
86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
92 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
94 u32 power_dissipated; /* 0x11c */
95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
105 u32 ump_nc_si_config; /* 0x120 */
106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
121 u32 board; /* 0x124 */
122 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
123 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
125 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
126 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
128 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
129 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
131 u32 reserved; /* 0x128 */
136 /****************************************************************************
137 * Port HW configuration *
138 ****************************************************************************/
139 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
142 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
143 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
146 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
147 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
149 u32 power_dissipated;
150 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
151 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
152 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
153 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
154 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
155 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
156 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
157 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
160 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
161 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
162 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
163 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
164 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
165 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
166 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
167 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
170 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
171 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
174 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
177 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
181 /* for external PHY, or forced mode or during AN */
182 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
183 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
185 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
186 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
188 u16 serdes_tx_driver_pre_emphasis[16];
189 u16 serdes_rx_driver_equalizer[16];
191 u32 xgxs_config_lane0;
192 u32 xgxs_config_lane1;
193 u32 xgxs_config_lane2;
194 u32 xgxs_config_lane3;
195 /* for external PHY, or forced mode or during AN */
196 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
197 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
199 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
200 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
202 u16 xgxs_tx_driver_pre_emphasis_lane0[16];
203 u16 xgxs_tx_driver_pre_emphasis_lane1[16];
204 u16 xgxs_tx_driver_pre_emphasis_lane2[16];
205 u16 xgxs_tx_driver_pre_emphasis_lane3[16];
207 u16 xgxs_rx_driver_equalizer_lane0[16];
208 u16 xgxs_rx_driver_equalizer_lane1[16];
209 u16 xgxs_rx_driver_equalizer_lane2[16];
210 u16 xgxs_rx_driver_equalizer_lane3[16];
213 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
214 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
215 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
216 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
217 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
218 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
219 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
220 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
222 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
224 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
226 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
228 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
230 u32 external_phy_config;
231 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
232 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
233 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
234 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
235 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
237 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
238 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
240 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
241 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
242 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
243 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
244 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
245 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
246 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
247 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
248 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
249 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
250 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
251 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
252 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
254 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
255 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
257 u32 speed_capability_mask;
258 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
259 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
260 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
261 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
262 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
263 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
264 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
265 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
266 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
267 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
268 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
269 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
270 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
271 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
272 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
274 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
275 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
276 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
277 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
278 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
279 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
280 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
281 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
282 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
283 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
284 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
285 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
286 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
287 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
288 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
295 /****************************************************************************
296 * Shared Feature configuration *
297 ****************************************************************************/
298 struct shared_feat_cfg { /* NVRAM Offset */
300 u32 config; /* 0x450 */
301 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
302 #define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
307 /****************************************************************************
308 * Port Feature configuration *
309 ****************************************************************************/
310 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
313 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
314 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
315 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
316 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
317 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
318 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
319 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
320 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
321 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
322 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
323 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
324 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
325 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
326 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
327 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
328 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
329 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
330 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
331 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
332 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
333 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
334 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
335 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
336 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
337 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
338 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
339 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
340 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
341 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
342 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
343 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
344 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
345 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
346 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
347 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
348 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
349 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
350 #define PORT_FEATURE_EN_SIZE_SHIFT 24
351 #define PORT_FEATURE_WOL_ENABLED 0x01000000
352 #define PORT_FEATURE_MBA_ENABLED 0x02000000
353 #define PORT_FEATURE_MFW_ENABLED 0x04000000
356 /* Default is used when driver sets to "auto" mode */
357 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
358 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
359 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
360 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
361 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
362 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
363 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
364 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
365 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
368 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
369 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
370 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
371 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
372 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
373 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
374 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
375 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
376 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
377 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
378 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
379 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
380 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
381 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
382 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
383 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
384 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
385 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
386 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
387 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
388 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
389 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
390 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
391 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
392 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
393 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
394 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
395 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
396 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
397 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
398 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
399 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
400 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
401 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
402 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
403 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
404 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
405 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
406 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
407 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
408 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
409 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
410 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
411 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
412 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
413 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
414 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
415 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
416 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
417 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
418 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
419 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
420 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
421 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
424 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
425 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
428 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
429 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
430 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
433 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
434 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
435 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
436 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
437 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
441 #define PORT_FEATURE_SMBUS_EN 0x00000001
442 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
443 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
447 u32 link_config; /* Used as HW defaults for the driver */
448 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
449 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
450 /* (forced) low speed switch (< 10G) */
451 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
452 /* (forced) high speed switch (>= 10G) */
453 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
454 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
455 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
457 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
458 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
459 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
460 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
461 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
462 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
463 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
464 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
465 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
466 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
467 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
468 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
469 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
470 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
471 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
472 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
473 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
475 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
476 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
477 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
478 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
479 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
480 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
481 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
483 /* The default for MCP link configuration,
484 uses the same defines as link_config */
485 u32 mfw_wol_link_cfg;
492 /****************************************************************************
493 * Device Information *
494 ****************************************************************************/
495 struct dev_info { /* size */
497 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
499 struct shared_hw_cfg shared_hw_config; /* 40 */
501 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
503 struct shared_feat_cfg shared_feature_config; /* 4 */
505 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
518 #define E1_FUNC_MAX 2
519 #define E1H_FUNC_MAX 8
529 /* This value (in milliseconds) determines the frequency of the driver
530 * issuing the PULSE message code. The firmware monitors this periodic
531 * pulse to determine when to switch to an OS-absent mode. */
532 #define DRV_PULSE_PERIOD_MS 250
534 /* This value (in milliseconds) determines how long the driver should
535 * wait for an acknowledgement from the firmware before timing out. Once
536 * the firmware has timed out, the driver will assume there is no firmware
537 * running and there won't be any firmware-driver synchronization during a
539 #define FW_ACK_TIME_OUT_MS 5000
541 #define FW_ACK_POLL_TIME_MS 1
543 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
545 /* LED Blink rate that will achieve ~15.9Hz */
546 #define LED_BLINK_RATE_VAL 480
548 /****************************************************************************
549 * Driver <-> FW Mailbox *
550 ****************************************************************************/
554 /* Driver should update this field on any link change event */
556 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
557 #define LINK_STATUS_LINK_UP 0x00000001
558 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
559 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
560 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
561 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
562 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
563 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
564 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
565 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
566 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
567 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
568 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
569 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
570 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
571 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
572 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
573 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
574 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
575 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
576 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
577 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
578 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
579 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
580 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
581 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
582 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
584 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
585 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
587 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
588 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
589 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
591 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
592 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
593 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
594 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
595 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
596 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
597 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
599 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
600 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
602 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
603 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
605 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
606 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
607 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
608 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
609 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
611 #define LINK_STATUS_SERDES_LINK 0x00100000
613 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
614 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
615 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
616 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
617 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
618 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
619 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
620 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
633 #define DRV_MSG_CODE_MASK 0xffff0000
634 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
635 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
636 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
637 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
638 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
639 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
640 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
641 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
642 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
643 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
644 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
645 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
646 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
648 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
649 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
650 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
651 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
653 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
658 #define FW_MSG_CODE_MASK 0xffff0000
659 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
660 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
661 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
662 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
663 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
664 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
665 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
666 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
667 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
668 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
669 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
670 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
671 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
672 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
673 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
674 #define FW_MSG_CODE_NO_KEY 0x80f00000
675 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
676 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
677 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
678 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
679 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
680 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
682 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
683 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
684 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
685 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
687 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
692 #define DRV_PULSE_SEQ_MASK 0x00007fff
693 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
694 /* The system time is in the format of
695 * (year-2001)*12*32 + month*32 + day. */
696 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
697 /* Indicate to the firmware not to go into the
698 * OS-absent when it is not getting driver pulse.
699 * This is used for debugging as well for PXE(MBA). */
702 #define MCP_PULSE_SEQ_MASK 0x00007fff
703 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
704 /* Indicates to the driver not to assert due to lack
706 #define MCP_EVENT_MASK 0xffff0000
707 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
709 u32 iscsi_boot_signature;
710 u32 iscsi_boot_block_offset;
713 #define DRV_STATUS_PMF 0x00000001
716 #define VIRT_MAC_SIGN_MASK 0xffff0000
717 #define VIRT_MAC_SIGNATURE 0x564d0000
723 /****************************************************************************
724 * Management firmware state *
725 ****************************************************************************/
726 /* Allocate 440 bytes for management firmware */
727 #define MGMTFW_STATE_WORD_SIZE 110
729 struct mgmtfw_state {
730 u32 opaque[MGMTFW_STATE_WORD_SIZE];
734 /****************************************************************************
735 * Multi-Function configuration *
736 ****************************************************************************/
737 struct shared_mf_cfg {
740 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
742 #define SHARED_MF_CLP_EXIT 0x00000001
744 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
750 u32 dynamic_cfg; /* device control channel */
751 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
752 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
753 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
754 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
764 /* function 0 of each port cannot be hidden */
765 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
767 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
768 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
769 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
770 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
771 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
772 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
774 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
777 /* 0 - low priority, 3 - high priority */
778 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
779 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
780 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
783 /* value range - 0..100, increments in 100Mbps */
784 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
785 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
786 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
787 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
788 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
789 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
791 u32 mac_upper; /* MAC */
792 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
793 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
794 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
796 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
798 u32 e1hov_tag; /* VNI */
799 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
800 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
801 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
809 struct shared_mf_cfg shared_mf_config;
810 struct port_mf_cfg port_mf_config[PORT_MAX];
812 struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
814 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
820 /****************************************************************************
821 * Shared Memory Region *
822 ****************************************************************************/
823 struct shmem_region { /* SharedMem Offset (size) */
825 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
826 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
827 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
829 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
830 #define SHR_MEM_VALIDITY_MB 0x00200000
831 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
832 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
833 /* One licensing bit should be set */
834 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
835 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
836 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
837 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
839 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
840 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
841 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
842 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
843 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
844 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
846 struct dev_info dev_info; /* 0x8 (0x438) */
848 u8 reserved[52*PORT_MAX];
850 /* FW information (for internal FW use) */
851 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
852 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
854 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
855 struct drv_func_mb func_mb[E1H_FUNC_MAX];
857 struct mf_cfg mf_cfg;
863 u32 rx_stat_ifhcinoctets;
864 u32 rx_stat_ifhcinbadoctets;
865 u32 rx_stat_etherstatsfragments;
866 u32 rx_stat_ifhcinucastpkts;
867 u32 rx_stat_ifhcinmulticastpkts;
868 u32 rx_stat_ifhcinbroadcastpkts;
869 u32 rx_stat_dot3statsfcserrors;
870 u32 rx_stat_dot3statsalignmenterrors;
871 u32 rx_stat_dot3statscarriersenseerrors;
872 u32 rx_stat_xonpauseframesreceived;
873 u32 rx_stat_xoffpauseframesreceived;
874 u32 rx_stat_maccontrolframesreceived;
875 u32 rx_stat_xoffstateentered;
876 u32 rx_stat_dot3statsframestoolong;
877 u32 rx_stat_etherstatsjabbers;
878 u32 rx_stat_etherstatsundersizepkts;
879 u32 rx_stat_etherstatspkts64octets;
880 u32 rx_stat_etherstatspkts65octetsto127octets;
881 u32 rx_stat_etherstatspkts128octetsto255octets;
882 u32 rx_stat_etherstatspkts256octetsto511octets;
883 u32 rx_stat_etherstatspkts512octetsto1023octets;
884 u32 rx_stat_etherstatspkts1024octetsto1522octets;
885 u32 rx_stat_etherstatspktsover1522octets;
887 u32 rx_stat_falsecarriererrors;
889 u32 tx_stat_ifhcoutoctets;
890 u32 tx_stat_ifhcoutbadoctets;
891 u32 tx_stat_etherstatscollisions;
892 u32 tx_stat_outxonsent;
893 u32 tx_stat_outxoffsent;
894 u32 tx_stat_flowcontroldone;
895 u32 tx_stat_dot3statssinglecollisionframes;
896 u32 tx_stat_dot3statsmultiplecollisionframes;
897 u32 tx_stat_dot3statsdeferredtransmissions;
898 u32 tx_stat_dot3statsexcessivecollisions;
899 u32 tx_stat_dot3statslatecollisions;
900 u32 tx_stat_ifhcoutucastpkts;
901 u32 tx_stat_ifhcoutmulticastpkts;
902 u32 tx_stat_ifhcoutbroadcastpkts;
903 u32 tx_stat_etherstatspkts64octets;
904 u32 tx_stat_etherstatspkts65octetsto127octets;
905 u32 tx_stat_etherstatspkts128octetsto255octets;
906 u32 tx_stat_etherstatspkts256octetsto511octets;
907 u32 tx_stat_etherstatspkts512octetsto1023octets;
908 u32 tx_stat_etherstatspkts1024octetsto1522octets;
909 u32 tx_stat_etherstatspktsover1522octets;
910 u32 tx_stat_dot3statsinternalmactransmiterrors;
915 u32 tx_stat_gtpkt_lo;
916 u32 tx_stat_gtpkt_hi;
917 u32 tx_stat_gtxpf_lo;
918 u32 tx_stat_gtxpf_hi;
919 u32 tx_stat_gtfcs_lo;
920 u32 tx_stat_gtfcs_hi;
921 u32 tx_stat_gtmca_lo;
922 u32 tx_stat_gtmca_hi;
923 u32 tx_stat_gtbca_lo;
924 u32 tx_stat_gtbca_hi;
925 u32 tx_stat_gtfrg_lo;
926 u32 tx_stat_gtfrg_hi;
927 u32 tx_stat_gtovr_lo;
928 u32 tx_stat_gtovr_hi;
931 u32 tx_stat_gt127_lo;
932 u32 tx_stat_gt127_hi;
933 u32 tx_stat_gt255_lo;
934 u32 tx_stat_gt255_hi;
935 u32 tx_stat_gt511_lo;
936 u32 tx_stat_gt511_hi;
937 u32 tx_stat_gt1023_lo;
938 u32 tx_stat_gt1023_hi;
939 u32 tx_stat_gt1518_lo;
940 u32 tx_stat_gt1518_hi;
941 u32 tx_stat_gt2047_lo;
942 u32 tx_stat_gt2047_hi;
943 u32 tx_stat_gt4095_lo;
944 u32 tx_stat_gt4095_hi;
945 u32 tx_stat_gt9216_lo;
946 u32 tx_stat_gt9216_hi;
947 u32 tx_stat_gt16383_lo;
948 u32 tx_stat_gt16383_hi;
949 u32 tx_stat_gtmax_lo;
950 u32 tx_stat_gtmax_hi;
951 u32 tx_stat_gtufl_lo;
952 u32 tx_stat_gtufl_hi;
953 u32 tx_stat_gterr_lo;
954 u32 tx_stat_gterr_hi;
955 u32 tx_stat_gtbyt_lo;
956 u32 tx_stat_gtbyt_hi;
960 u32 rx_stat_gr127_lo;
961 u32 rx_stat_gr127_hi;
962 u32 rx_stat_gr255_lo;
963 u32 rx_stat_gr255_hi;
964 u32 rx_stat_gr511_lo;
965 u32 rx_stat_gr511_hi;
966 u32 rx_stat_gr1023_lo;
967 u32 rx_stat_gr1023_hi;
968 u32 rx_stat_gr1518_lo;
969 u32 rx_stat_gr1518_hi;
970 u32 rx_stat_gr2047_lo;
971 u32 rx_stat_gr2047_hi;
972 u32 rx_stat_gr4095_lo;
973 u32 rx_stat_gr4095_hi;
974 u32 rx_stat_gr9216_lo;
975 u32 rx_stat_gr9216_hi;
976 u32 rx_stat_gr16383_lo;
977 u32 rx_stat_gr16383_hi;
978 u32 rx_stat_grmax_lo;
979 u32 rx_stat_grmax_hi;
980 u32 rx_stat_grpkt_lo;
981 u32 rx_stat_grpkt_hi;
982 u32 rx_stat_grfcs_lo;
983 u32 rx_stat_grfcs_hi;
984 u32 rx_stat_grmca_lo;
985 u32 rx_stat_grmca_hi;
986 u32 rx_stat_grbca_lo;
987 u32 rx_stat_grbca_hi;
988 u32 rx_stat_grxcf_lo;
989 u32 rx_stat_grxcf_hi;
990 u32 rx_stat_grxpf_lo;
991 u32 rx_stat_grxpf_hi;
992 u32 rx_stat_grxuo_lo;
993 u32 rx_stat_grxuo_hi;
994 u32 rx_stat_grjbr_lo;
995 u32 rx_stat_grjbr_hi;
996 u32 rx_stat_grovr_lo;
997 u32 rx_stat_grovr_hi;
998 u32 rx_stat_grflr_lo;
999 u32 rx_stat_grflr_hi;
1000 u32 rx_stat_grmeg_lo;
1001 u32 rx_stat_grmeg_hi;
1002 u32 rx_stat_grmeb_lo;
1003 u32 rx_stat_grmeb_hi;
1004 u32 rx_stat_grbyt_lo;
1005 u32 rx_stat_grbyt_hi;
1006 u32 rx_stat_grund_lo;
1007 u32 rx_stat_grund_hi;
1008 u32 rx_stat_grfrg_lo;
1009 u32 rx_stat_grfrg_hi;
1010 u32 rx_stat_grerb_lo;
1011 u32 rx_stat_grerb_hi;
1012 u32 rx_stat_grfre_lo;
1013 u32 rx_stat_grfre_hi;
1014 u32 rx_stat_gripj_lo;
1015 u32 rx_stat_gripj_hi;
1020 struct emac_stats emac_stats;
1021 struct bmac_stats bmac_stats;
1027 u32 rx_stat_ifhcinbadoctets_hi;
1028 u32 rx_stat_ifhcinbadoctets_lo;
1030 /* out_bad_octets */
1031 u32 tx_stat_ifhcoutbadoctets_hi;
1032 u32 tx_stat_ifhcoutbadoctets_lo;
1034 /* crc_receive_errors */
1035 u32 rx_stat_dot3statsfcserrors_hi;
1036 u32 rx_stat_dot3statsfcserrors_lo;
1037 /* alignment_errors */
1038 u32 rx_stat_dot3statsalignmenterrors_hi;
1039 u32 rx_stat_dot3statsalignmenterrors_lo;
1040 /* carrier_sense_errors */
1041 u32 rx_stat_dot3statscarriersenseerrors_hi;
1042 u32 rx_stat_dot3statscarriersenseerrors_lo;
1043 /* false_carrier_detections */
1044 u32 rx_stat_falsecarriererrors_hi;
1045 u32 rx_stat_falsecarriererrors_lo;
1047 /* runt_packets_received */
1048 u32 rx_stat_etherstatsundersizepkts_hi;
1049 u32 rx_stat_etherstatsundersizepkts_lo;
1050 /* jabber_packets_received */
1051 u32 rx_stat_dot3statsframestoolong_hi;
1052 u32 rx_stat_dot3statsframestoolong_lo;
1054 /* error_runt_packets_received */
1055 u32 rx_stat_etherstatsfragments_hi;
1056 u32 rx_stat_etherstatsfragments_lo;
1057 /* error_jabber_packets_received */
1058 u32 rx_stat_etherstatsjabbers_hi;
1059 u32 rx_stat_etherstatsjabbers_lo;
1061 /* control_frames_received */
1062 u32 rx_stat_maccontrolframesreceived_hi;
1063 u32 rx_stat_maccontrolframesreceived_lo;
1064 u32 rx_stat_bmac_xpf_hi;
1065 u32 rx_stat_bmac_xpf_lo;
1066 u32 rx_stat_bmac_xcf_hi;
1067 u32 rx_stat_bmac_xcf_lo;
1069 /* xoff_state_entered */
1070 u32 rx_stat_xoffstateentered_hi;
1071 u32 rx_stat_xoffstateentered_lo;
1072 /* pause_xon_frames_received */
1073 u32 rx_stat_xonpauseframesreceived_hi;
1074 u32 rx_stat_xonpauseframesreceived_lo;
1075 /* pause_xoff_frames_received */
1076 u32 rx_stat_xoffpauseframesreceived_hi;
1077 u32 rx_stat_xoffpauseframesreceived_lo;
1078 /* pause_xon_frames_transmitted */
1079 u32 tx_stat_outxonsent_hi;
1080 u32 tx_stat_outxonsent_lo;
1081 /* pause_xoff_frames_transmitted */
1082 u32 tx_stat_outxoffsent_hi;
1083 u32 tx_stat_outxoffsent_lo;
1084 /* flow_control_done */
1085 u32 tx_stat_flowcontroldone_hi;
1086 u32 tx_stat_flowcontroldone_lo;
1088 /* ether_stats_collisions */
1089 u32 tx_stat_etherstatscollisions_hi;
1090 u32 tx_stat_etherstatscollisions_lo;
1091 /* single_collision_transmit_frames */
1092 u32 tx_stat_dot3statssinglecollisionframes_hi;
1093 u32 tx_stat_dot3statssinglecollisionframes_lo;
1094 /* multiple_collision_transmit_frames */
1095 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1096 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1097 /* deferred_transmissions */
1098 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1099 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1100 /* excessive_collision_frames */
1101 u32 tx_stat_dot3statsexcessivecollisions_hi;
1102 u32 tx_stat_dot3statsexcessivecollisions_lo;
1103 /* late_collision_frames */
1104 u32 tx_stat_dot3statslatecollisions_hi;
1105 u32 tx_stat_dot3statslatecollisions_lo;
1107 /* frames_transmitted_64_bytes */
1108 u32 tx_stat_etherstatspkts64octets_hi;
1109 u32 tx_stat_etherstatspkts64octets_lo;
1110 /* frames_transmitted_65_127_bytes */
1111 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1112 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1113 /* frames_transmitted_128_255_bytes */
1114 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1115 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1116 /* frames_transmitted_256_511_bytes */
1117 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1118 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1119 /* frames_transmitted_512_1023_bytes */
1120 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1121 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1122 /* frames_transmitted_1024_1522_bytes */
1123 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1124 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1125 /* frames_transmitted_1523_9022_bytes */
1126 u32 tx_stat_etherstatspktsover1522octets_hi;
1127 u32 tx_stat_etherstatspktsover1522octets_lo;
1128 u32 tx_stat_bmac_2047_hi;
1129 u32 tx_stat_bmac_2047_lo;
1130 u32 tx_stat_bmac_4095_hi;
1131 u32 tx_stat_bmac_4095_lo;
1132 u32 tx_stat_bmac_9216_hi;
1133 u32 tx_stat_bmac_9216_lo;
1134 u32 tx_stat_bmac_16383_hi;
1135 u32 tx_stat_bmac_16383_lo;
1137 /* internal_mac_transmit_errors */
1138 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1139 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1141 /* if_out_discards */
1142 u32 tx_stat_bmac_ufl_hi;
1143 u32 tx_stat_bmac_ufl_lo;
1147 #define MAC_STX_IDX_MAX 2
1149 struct host_port_stats {
1150 u32 host_port_stats_start;
1152 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1157 u32 host_port_stats_end;
1161 struct host_func_stats {
1162 u32 host_func_stats_start;
1164 u32 total_bytes_received_hi;
1165 u32 total_bytes_received_lo;
1167 u32 total_bytes_transmitted_hi;
1168 u32 total_bytes_transmitted_lo;
1170 u32 total_unicast_packets_received_hi;
1171 u32 total_unicast_packets_received_lo;
1173 u32 total_multicast_packets_received_hi;
1174 u32 total_multicast_packets_received_lo;
1176 u32 total_broadcast_packets_received_hi;
1177 u32 total_broadcast_packets_received_lo;
1179 u32 total_unicast_packets_transmitted_hi;
1180 u32 total_unicast_packets_transmitted_lo;
1182 u32 total_multicast_packets_transmitted_hi;
1183 u32 total_multicast_packets_transmitted_lo;
1185 u32 total_broadcast_packets_transmitted_hi;
1186 u32 total_broadcast_packets_transmitted_lo;
1188 u32 valid_bytes_received_hi;
1189 u32 valid_bytes_received_lo;
1191 u32 host_func_stats_end;
1195 #define BCM_5710_FW_MAJOR_VERSION 4
1196 #define BCM_5710_FW_MINOR_VERSION 8
1197 #define BCM_5710_FW_REVISION_VERSION 53
1198 #define BCM_5710_FW_ENGINEERING_VERSION 0
1199 #define BCM_5710_FW_COMPILE_FLAGS 1
1205 struct atten_def_status_block {
1210 u16 attn_bits_index;
1216 * common data for all protocols
1218 struct doorbell_hdr {
1220 #define DOORBELL_HDR_RX (0x1<<0)
1221 #define DOORBELL_HDR_RX_SHIFT 0
1222 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1223 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1224 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1225 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1226 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1227 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1231 * doorbell message sent to the chip
1234 #if defined(__BIG_ENDIAN)
1237 struct doorbell_hdr header;
1238 #elif defined(__LITTLE_ENDIAN)
1239 struct doorbell_hdr header;
1247 * IGU driver acknowledgement register
1249 struct igu_ack_register {
1250 #if defined(__BIG_ENDIAN)
1251 u16 sb_id_and_flags;
1252 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1253 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1254 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1255 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1256 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1257 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1258 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1259 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1260 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1261 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1262 u16 status_block_index;
1263 #elif defined(__LITTLE_ENDIAN)
1264 u16 status_block_index;
1265 u16 sb_id_and_flags;
1266 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1267 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1268 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1269 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1270 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1271 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1272 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1273 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1274 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1275 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1281 * Parser parsing flags field
1283 struct parsing_flags {
1285 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1286 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1287 #define PARSING_FLAGS_VLAN (0x1<<1)
1288 #define PARSING_FLAGS_VLAN_SHIFT 1
1289 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1290 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1291 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1292 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1293 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1294 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1295 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1296 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1297 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1298 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1299 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1300 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1301 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1302 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1303 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1304 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1305 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1306 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1307 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1308 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1309 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1310 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1321 * dmae command structure
1323 struct dmae_command {
1325 #define DMAE_COMMAND_SRC (0x1<<0)
1326 #define DMAE_COMMAND_SRC_SHIFT 0
1327 #define DMAE_COMMAND_DST (0x3<<1)
1328 #define DMAE_COMMAND_DST_SHIFT 1
1329 #define DMAE_COMMAND_C_DST (0x1<<3)
1330 #define DMAE_COMMAND_C_DST_SHIFT 3
1331 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1332 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1333 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1334 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1335 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1336 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1337 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1338 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1339 #define DMAE_COMMAND_PORT (0x1<<11)
1340 #define DMAE_COMMAND_PORT_SHIFT 11
1341 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1342 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1343 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1344 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1345 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1346 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1347 #define DMAE_COMMAND_E1HVN (0x3<<15)
1348 #define DMAE_COMMAND_E1HVN_SHIFT 15
1349 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1350 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1355 #if defined(__BIG_ENDIAN)
1358 #elif defined(__LITTLE_ENDIAN)
1367 #if defined(__BIG_ENDIAN)
1370 #elif defined(__LITTLE_ENDIAN)
1374 #if defined(__BIG_ENDIAN)
1377 #elif defined(__LITTLE_ENDIAN)
1381 #if defined(__BIG_ENDIAN)
1384 #elif defined(__LITTLE_ENDIAN)
1391 struct double_regpair {
1400 * The eth storm context of Ustorm (configuration part)
1402 struct ustorm_eth_st_context_config {
1403 #if defined(__BIG_ENDIAN)
1405 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1406 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1407 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1408 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1409 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1410 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1411 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1412 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1413 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1414 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1415 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1416 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1419 u8 sb_index_numbers;
1420 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1421 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1422 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1423 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1424 #elif defined(__LITTLE_ENDIAN)
1425 u8 sb_index_numbers;
1426 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1427 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1428 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1429 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1433 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1434 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1435 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1436 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1437 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1438 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1439 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1440 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1441 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1442 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1443 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1444 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1446 #if defined(__BIG_ENDIAN)
1448 u8 statistics_counter_id;
1449 u8 mc_alignment_log_size;
1450 #elif defined(__LITTLE_ENDIAN)
1451 u8 mc_alignment_log_size;
1452 u8 statistics_counter_id;
1455 #if defined(__BIG_ENDIAN)
1456 u8 __local_sge_prod;
1459 #elif defined(__LITTLE_ENDIAN)
1462 u8 __local_sge_prod;
1465 u32 bd_page_base_lo;
1466 u32 bd_page_base_hi;
1467 u32 sge_page_base_lo;
1468 u32 sge_page_base_hi;
1472 * The eth Rx Buffer Descriptor
1480 * The eth Rx SGE Descriptor
1488 * Local BDs and SGEs rings (in ETH)
1490 struct eth_local_rx_rings {
1491 struct eth_rx_bd __local_bd_ring[16];
1492 struct eth_rx_sge __local_sge_ring[12];
1496 * The eth storm context of Ustorm
1498 struct ustorm_eth_st_context {
1499 struct ustorm_eth_st_context_config common;
1500 struct eth_local_rx_rings __rings;
1504 * The eth storm context of Tstorm
1506 struct tstorm_eth_st_context {
1507 u32 __reserved0[28];
1511 * The eth aggregative context section of Xstorm
1513 struct xstorm_eth_extra_ag_context_section {
1514 #if defined(__BIG_ENDIAN)
1518 #elif defined(__LITTLE_ENDIAN)
1527 #if defined(__BIG_ENDIAN)
1530 u16 __tcp_agg_vars2;
1531 #elif defined(__LITTLE_ENDIAN)
1532 u16 __tcp_agg_vars2;
1540 #if defined(__BIG_ENDIAN)
1543 #elif defined(__LITTLE_ENDIAN)
1547 #if defined(__BIG_ENDIAN)
1552 #elif defined(__LITTLE_ENDIAN)
1558 u32 __tcp_agg_vars6;
1559 #if defined(__BIG_ENDIAN)
1561 u16 __tcp_agg_vars7;
1562 #elif defined(__LITTLE_ENDIAN)
1563 u16 __tcp_agg_vars7;
1568 #if defined(__BIG_ENDIAN)
1572 #elif defined(__LITTLE_ENDIAN)
1580 * The eth aggregative context of Xstorm
1582 struct xstorm_eth_ag_context {
1583 #if defined(__BIG_ENDIAN)
1587 #elif defined(__LITTLE_ENDIAN)
1592 #if defined(__BIG_ENDIAN)
1597 #elif defined(__LITTLE_ENDIAN)
1603 u32 __more_packets_to_send;
1604 #if defined(__BIG_ENDIAN)
1607 #elif defined(__LITTLE_ENDIAN)
1611 struct xstorm_eth_extra_ag_context_section __extra_section;
1612 #if defined(__BIG_ENDIAN)
1616 #elif defined(__LITTLE_ENDIAN)
1621 #if defined(__BIG_ENDIAN)
1624 #elif defined(__LITTLE_ENDIAN)
1628 #if defined(__BIG_ENDIAN)
1632 #elif defined(__LITTLE_ENDIAN)
1637 #if defined(__BIG_ENDIAN)
1640 #elif defined(__LITTLE_ENDIAN)
1645 #if defined(__BIG_ENDIAN)
1648 #elif defined(__LITTLE_ENDIAN)
1652 #if defined(__BIG_ENDIAN)
1657 #elif defined(__LITTLE_ENDIAN)
1663 #if defined(__BIG_ENDIAN)
1665 u16 __bd_ind_max_val;
1666 #elif defined(__LITTLE_ENDIAN)
1667 u16 __bd_ind_max_val;
1676 * The eth aggregative context section of Tstorm
1678 struct tstorm_eth_extra_ag_context_section {
1680 #if defined(__BIG_ENDIAN)
1684 #elif defined(__LITTLE_ENDIAN)
1689 #if defined(__BIG_ENDIAN)
1693 #elif defined(__LITTLE_ENDIAN)
1703 u32 __tcp_agg_vars1;
1710 * The eth aggregative context of Tstorm
1712 struct tstorm_eth_ag_context {
1713 #if defined(__BIG_ENDIAN)
1717 #elif defined(__LITTLE_ENDIAN)
1722 #if defined(__BIG_ENDIAN)
1725 #elif defined(__LITTLE_ENDIAN)
1729 struct tstorm_eth_extra_ag_context_section __extra_section;
1733 * The eth aggregative context of Cstorm
1735 struct cstorm_eth_ag_context {
1737 #if defined(__BIG_ENDIAN)
1741 #elif defined(__LITTLE_ENDIAN)
1746 u32 __num_of_treated_packet;
1747 u32 __last_packet_treated;
1748 #if defined(__BIG_ENDIAN)
1751 #elif defined(__LITTLE_ENDIAN)
1755 #if defined(__BIG_ENDIAN)
1760 #elif defined(__LITTLE_ENDIAN)
1766 #if defined(__BIG_ENDIAN)
1769 #elif defined(__LITTLE_ENDIAN)
1774 #if defined(__BIG_ENDIAN)
1777 #elif defined(__LITTLE_ENDIAN)
1781 #if defined(__BIG_ENDIAN)
1782 u16 __packet_index_th;
1784 #elif defined(__LITTLE_ENDIAN)
1786 u16 __packet_index_th;
1791 * The eth aggregative context of Ustorm
1793 struct ustorm_eth_ag_context {
1794 #if defined(__BIG_ENDIAN)
1795 u8 __aux_counter_flags;
1799 #elif defined(__LITTLE_ENDIAN)
1803 u8 __aux_counter_flags;
1805 #if defined(__BIG_ENDIAN)
1809 #elif defined(__LITTLE_ENDIAN)
1815 #if defined(__BIG_ENDIAN)
1819 #elif defined(__LITTLE_ENDIAN)
1826 #if defined(__BIG_ENDIAN)
1829 #elif defined(__LITTLE_ENDIAN)
1833 #if defined(__BIG_ENDIAN)
1835 u8 __decision_rules;
1836 u8 __decision_rule_enable_bits;
1837 #elif defined(__LITTLE_ENDIAN)
1838 u8 __decision_rule_enable_bits;
1839 u8 __decision_rules;
1845 * Timers connection context
1847 struct timers_block_context {
1852 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1853 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1854 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1855 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1856 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1857 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1861 * structure for easy accessibility to assembler
1863 struct eth_tx_bd_flags {
1865 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1866 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1867 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1868 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1869 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1870 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1871 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1872 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1873 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1874 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1875 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1876 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1877 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1878 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1879 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1880 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1884 * The eth Tx Buffer Descriptor
1892 struct eth_tx_bd_flags bd_flags;
1894 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1895 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1896 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1897 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1901 * Tx parsing BD structure for ETH,Relevant in START
1903 struct eth_tx_parse_bd {
1905 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1906 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1907 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1908 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1909 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1910 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1911 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1912 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1913 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1914 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1916 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1917 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1918 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1919 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1920 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1921 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1922 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1923 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1924 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1925 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1926 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1927 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1928 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1929 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1930 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1931 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1936 u16 tcp_pseudo_csum;
1942 * The last BD in the BD memory will hold a pointer to the next BD memory
1944 struct eth_tx_next_bd {
1951 * union for 3 Bd types
1953 union eth_tx_bd_types {
1954 struct eth_tx_bd reg_bd;
1955 struct eth_tx_parse_bd parse_bd;
1956 struct eth_tx_next_bd next_bd;
1960 * The eth storm context of Xstorm
1962 struct xstorm_eth_st_context {
1963 u32 tx_bd_page_base_lo;
1964 u32 tx_bd_page_base_hi;
1965 #if defined(__BIG_ENDIAN)
1968 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1969 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1970 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1971 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1972 u8 __local_tx_bd_prod;
1973 #elif defined(__LITTLE_ENDIAN)
1974 u8 __local_tx_bd_prod;
1976 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1977 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1978 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1979 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1982 u32 db_data_addr_lo;
1983 u32 db_data_addr_hi;
1987 union eth_tx_bd_types __bds[13];
1991 * The eth storm context of Cstorm
1993 struct cstorm_eth_st_context {
1994 #if defined(__BIG_ENDIAN)
1998 #elif defined(__LITTLE_ENDIAN)
2007 * Ethernet connection context
2009 struct eth_context {
2010 struct ustorm_eth_st_context ustorm_st_context;
2011 struct tstorm_eth_st_context tstorm_st_context;
2012 struct xstorm_eth_ag_context xstorm_ag_context;
2013 struct tstorm_eth_ag_context tstorm_ag_context;
2014 struct cstorm_eth_ag_context cstorm_ag_context;
2015 struct ustorm_eth_ag_context ustorm_ag_context;
2016 struct timers_block_context timers_context;
2017 struct xstorm_eth_st_context xstorm_st_context;
2018 struct cstorm_eth_st_context cstorm_st_context;
2025 struct eth_tx_doorbell {
2026 #if defined(__BIG_ENDIAN)
2029 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2030 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2031 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2032 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2033 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2034 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2035 struct doorbell_hdr hdr;
2036 #elif defined(__LITTLE_ENDIAN)
2037 struct doorbell_hdr hdr;
2039 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2040 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2041 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2042 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2043 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2044 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2051 * ustorm status block
2053 struct ustorm_def_status_block {
2054 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2055 u16 status_block_index;
2062 * cstorm status block
2064 struct cstorm_def_status_block {
2065 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2066 u16 status_block_index;
2073 * xstorm status block
2075 struct xstorm_def_status_block {
2076 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2077 u16 status_block_index;
2084 * tstorm status block
2086 struct tstorm_def_status_block {
2087 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2088 u16 status_block_index;
2097 struct host_def_status_block {
2098 struct atten_def_status_block atten_status_block;
2099 struct ustorm_def_status_block u_def_status_block;
2100 struct cstorm_def_status_block c_def_status_block;
2101 struct xstorm_def_status_block x_def_status_block;
2102 struct tstorm_def_status_block t_def_status_block;
2107 * ustorm status block
2109 struct ustorm_status_block {
2110 u16 index_values[HC_USTORM_SB_NUM_INDICES];
2111 u16 status_block_index;
2118 * cstorm status block
2120 struct cstorm_status_block {
2121 u16 index_values[HC_CSTORM_SB_NUM_INDICES];
2122 u16 status_block_index;
2131 struct host_status_block {
2132 struct ustorm_status_block u_status_block;
2133 struct cstorm_status_block c_status_block;
2138 * The data for RSS setup ramrod
2140 struct eth_client_setup_ramrod_data {
2149 * L2 dynamic host coalescing init parameters
2151 struct eth_dynamic_hc_config {
2158 * regular eth FP CQE parameters struct
2160 struct eth_fast_path_rx_cqe {
2161 u8 type_error_flags;
2162 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2163 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2164 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2165 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2166 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2167 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2168 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2169 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2170 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2171 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2172 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2173 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2174 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2175 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2177 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2178 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2179 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2180 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2181 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2182 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2183 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2184 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2185 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2186 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2187 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2188 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2189 u8 placement_offset;
2191 u32 rss_hash_result;
2195 struct parsing_flags pars_flags;
2201 * The data for RSS setup ramrod
2203 struct eth_halt_ramrod_data {
2210 * The data for statistics query ramrod
2212 struct eth_query_ramrod_data {
2213 #if defined(__BIG_ENDIAN)
2217 #elif defined(__LITTLE_ENDIAN)
2227 * Place holder for ramrods protocol specific data
2229 struct ramrod_data {
2235 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2237 union eth_ramrod_data {
2238 struct ramrod_data general;
2243 * Rx Last BD in page (in ETH)
2245 struct eth_rx_bd_next_page {
2253 * Eth Rx Cqe structure- general structure for ramrods
2255 struct common_ramrod_eth_rx_cqe {
2257 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2258 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2259 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2260 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2263 u32 conn_and_cmd_data;
2264 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2265 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2266 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2267 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2268 struct ramrod_data protocol_data;
2273 * Rx Last CQE in page (in ETH)
2275 struct eth_rx_cqe_next_page {
2282 * union for all eth rx cqe types (fix their sizes)
2285 struct eth_fast_path_rx_cqe fast_path_cqe;
2286 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2287 struct eth_rx_cqe_next_page next_page_cqe;
2292 * common data for all protocols
2295 u32 conn_and_cmd_data;
2296 #define SPE_HDR_CID (0xFFFFFF<<0)
2297 #define SPE_HDR_CID_SHIFT 0
2298 #define SPE_HDR_CMD_ID (0xFF<<24)
2299 #define SPE_HDR_CMD_ID_SHIFT 24
2301 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2302 #define SPE_HDR_CONN_TYPE_SHIFT 0
2303 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2304 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2309 * Ethernet slow path element
2311 union eth_specific_data {
2312 u8 protocol_data[8];
2313 struct regpair mac_config_addr;
2314 struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2315 struct eth_halt_ramrod_data halt_ramrod_data;
2316 struct regpair leading_cqe_addr;
2317 struct regpair update_data_addr;
2318 struct eth_query_ramrod_data query_ramrod_data;
2322 * Ethernet slow path element
2326 union eth_specific_data data;
2331 * doorbell data in host memory
2333 struct eth_tx_db_data {
2341 * Common configuration parameters per function in Tstorm
2343 struct tstorm_eth_function_common_config {
2344 #if defined(__BIG_ENDIAN)
2345 u8 leading_client_id;
2348 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2349 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2350 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2351 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2352 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2353 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2354 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2355 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2356 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2357 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2358 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2359 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2360 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2361 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2362 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2363 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2364 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2365 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2366 #elif defined(__LITTLE_ENDIAN)
2368 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2372 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2373 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2374 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2375 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2377 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2378 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2379 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2380 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2383 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2384 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2385 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2387 u8 leading_client_id;
2393 * parameters for eth update ramrod
2395 struct eth_update_ramrod_data {
2396 struct tstorm_eth_function_common_config func_config;
2397 u8 indirectionTable[128];
2402 * MAC filtering configuration command header
2404 struct mac_configuration_hdr {
2412 * MAC address in list for ramrod
2414 struct tstorm_cam_entry {
2416 u16 middle_mac_addr;
2419 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2420 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2421 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2422 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2423 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2424 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2428 * MAC filtering: CAM target table entry
2430 struct tstorm_cam_target_table_entry {
2432 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2433 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2434 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2435 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2436 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2437 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2438 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2439 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2440 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2441 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2447 * MAC address in list for ramrod
2449 struct mac_configuration_entry {
2450 struct tstorm_cam_entry cam_entry;
2451 struct tstorm_cam_target_table_entry target_table_entry;
2455 * MAC filtering configuration command
2457 struct mac_configuration_cmd {
2458 struct mac_configuration_hdr hdr;
2459 struct mac_configuration_entry config_table[64];
2464 * MAC address in list for ramrod
2466 struct mac_configuration_entry_e1h {
2468 u16 middle_mac_addr;
2474 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2475 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2476 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2477 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2478 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2479 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2480 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2481 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2485 * MAC filtering configuration command
2487 struct mac_configuration_cmd_e1h {
2488 struct mac_configuration_hdr hdr;
2489 struct mac_configuration_entry_e1h config_table[32];
2494 * approximate-match multicast filtering for E1H per function in Tstorm
2496 struct tstorm_eth_approximate_match_multicast_filtering {
2497 u32 mcast_add_hash_bit_array[8];
2502 * Configuration parameters per client in Tstorm
2504 struct tstorm_eth_client_config {
2505 #if defined(__BIG_ENDIAN)
2506 u8 max_sges_for_packet;
2507 u8 statistics_counter_id;
2509 #elif defined(__LITTLE_ENDIAN)
2511 u8 statistics_counter_id;
2512 u8 max_sges_for_packet;
2514 #if defined(__BIG_ENDIAN)
2516 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2517 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2518 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2519 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2520 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2521 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2522 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2523 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2524 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2525 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2527 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2528 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2529 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2530 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2531 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2532 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2533 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2534 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2535 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2536 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2537 #elif defined(__LITTLE_ENDIAN)
2539 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2540 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2541 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2542 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2543 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2544 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2545 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2546 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2547 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2548 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2550 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2551 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2552 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2553 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2554 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2555 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2556 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2557 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2558 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2559 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2565 * MAC filtering configuration parameters per port in Tstorm
2567 struct tstorm_eth_mac_filter_config {
2569 u32 ucast_accept_all;
2571 u32 mcast_accept_all;
2573 u32 bcast_accept_all;
2581 * common flag to indicate existance of TPA.
2583 struct tstorm_eth_tpa_exist {
2584 #if defined(__BIG_ENDIAN)
2588 #elif defined(__LITTLE_ENDIAN)
2598 * rx rings pause data for E1h only
2600 struct ustorm_eth_rx_pause_data_e1h {
2601 #if defined(__BIG_ENDIAN)
2604 #elif defined(__LITTLE_ENDIAN)
2608 #if defined(__BIG_ENDIAN)
2611 #elif defined(__LITTLE_ENDIAN)
2615 #if defined(__BIG_ENDIAN)
2618 #elif defined(__LITTLE_ENDIAN)
2622 #if defined(__BIG_ENDIAN)
2625 #elif defined(__LITTLE_ENDIAN)
2633 * Three RX producers for ETH
2635 struct ustorm_eth_rx_producers {
2636 #if defined(__BIG_ENDIAN)
2639 #elif defined(__LITTLE_ENDIAN)
2643 #if defined(__BIG_ENDIAN)
2646 #elif defined(__LITTLE_ENDIAN)
2654 * per-port SAFC demo variables
2656 struct cmng_flags_per_port {
2657 u8 con_number[NUM_OF_PROTOCOLS];
2659 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2660 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2661 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2662 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2663 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2664 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2665 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2666 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2667 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2668 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2669 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2670 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2675 * per-port rate shaping variables
2677 struct rate_shaping_vars_per_port {
2678 u32 rs_periodic_timeout;
2684 * per-port fairness variables
2686 struct fairness_vars_per_port {
2689 u32 fairness_timeout;
2694 * per-port SAFC variables
2696 struct safc_struct_per_port {
2697 #if defined(__BIG_ENDIAN)
2700 u8 safc_timeout_usec;
2701 #elif defined(__LITTLE_ENDIAN)
2702 u8 safc_timeout_usec;
2706 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2711 * Per-port congestion management variables
2713 struct cmng_struct_per_port {
2714 struct rate_shaping_vars_per_port rs_vars;
2715 struct fairness_vars_per_port fair_vars;
2716 struct safc_struct_per_port safc_vars;
2717 struct cmng_flags_per_port flags;
2722 * Protocol-common statistics collected by the Xstorm (per client)
2724 struct xstorm_per_client_stats {
2725 struct regpair total_sent_bytes;
2726 u32 total_sent_pkts;
2727 u32 unicast_pkts_sent;
2728 struct regpair unicast_bytes_sent;
2729 struct regpair multicast_bytes_sent;
2730 u32 multicast_pkts_sent;
2731 u32 broadcast_pkts_sent;
2732 struct regpair broadcast_bytes_sent;
2740 * Common statistics collected by the Xstorm (per port)
2742 struct xstorm_common_stats {
2743 struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2748 * Protocol-common statistics collected by the Tstorm (per port)
2750 struct tstorm_per_port_stats {
2751 u32 mac_filter_discard;
2752 u32 xxoverflow_discard;
2753 u32 brb_truncate_discard;
2759 * Protocol-common statistics collected by the Tstorm (per client)
2761 struct tstorm_per_client_stats {
2762 struct regpair total_rcv_bytes;
2763 struct regpair rcv_unicast_bytes;
2764 struct regpair rcv_broadcast_bytes;
2765 struct regpair rcv_multicast_bytes;
2766 struct regpair rcv_error_bytes;
2767 u32 checksum_discard;
2768 u32 packets_too_big_discard;
2770 u32 rcv_unicast_pkts;
2771 u32 rcv_broadcast_pkts;
2772 u32 rcv_multicast_pkts;
2773 u32 no_buff_discard;
2781 * Protocol-common statistics collected by the Tstorm
2783 struct tstorm_common_stats {
2784 struct tstorm_per_port_stats port_statistics;
2785 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2789 * Protocol-common statistics collected by the Ustorm (per client)
2791 struct ustorm_per_client_stats {
2792 struct regpair ucast_no_buff_bytes;
2793 struct regpair mcast_no_buff_bytes;
2794 struct regpair bcast_no_buff_bytes;
2795 __le32 ucast_no_buff_pkts;
2796 __le32 mcast_no_buff_pkts;
2797 __le32 bcast_no_buff_pkts;
2798 __le16 stats_counter;
2803 * Protocol-common statistics collected by the Ustorm
2805 struct ustorm_common_stats {
2806 struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
2810 * Eth statistics query structure for the eth_stats_query ramrod
2812 struct eth_stats_query {
2813 struct xstorm_common_stats xstorm_common;
2814 struct tstorm_common_stats tstorm_common;
2815 struct ustorm_common_stats ustorm_common;
2820 * per-vnic fairness variables
2822 struct fairness_vars_per_vn {
2823 u32 cos_credit_delta[MAX_COS_NUMBER];
2824 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2825 u32 vn_credit_delta;
2831 * FW version stored in the Xstorm RAM
2834 #if defined(__BIG_ENDIAN)
2839 #elif defined(__LITTLE_ENDIAN)
2846 #define FW_VERSION_OPTIMIZED (0x1<<0)
2847 #define FW_VERSION_OPTIMIZED_SHIFT 0
2848 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2849 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2850 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2851 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2852 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2853 #define __FW_VERSION_RESERVED_SHIFT 4
2858 * FW version stored in first line of pram
2860 struct pram_fw_version {
2866 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2867 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2868 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2869 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2870 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2871 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2872 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2873 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2874 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2875 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2880 * a single rate shaping counter. can be used as protocol or vnic counter
2882 struct rate_shaping_counter {
2884 #if defined(__BIG_ENDIAN)
2887 #elif defined(__LITTLE_ENDIAN)
2895 * per-vnic rate shaping variables
2897 struct rate_shaping_vars_per_vn {
2898 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2899 struct rate_shaping_counter vn_counter;
2904 * The send queue element
2906 struct slow_path_element {
2908 u8 protocol_data[8];
2913 * eth/toe flags that indicate if to query
2915 struct stats_indication_flags {