drivers/net/bnx2x_hsi.h

   1 /* bnx2x_hsi.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10
  11 #define PORT_0                          0
  12 #define PORT_1                          1
  13 #define PORT_MAX                        2
  14
  15 /****************************************************************************
  16  * Shared HW configuration                                                  *
  17  ****************************************************************************/
  18 struct shared_hw_cfg {                                   /* NVRAM Offset */
  19         /* Up to 16 bytes of NULL-terminated string */
  20         u8  part_num[16];                                       /* 0x104 */
  21
  22         u32 config;                                             /* 0x114 */
  23 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
  24 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
  25 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
  26 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
  27 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
  28
  29 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
  30
  31 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
  32
  33 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
  34 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
  35         /* Whatever MFW found in NVM
  36            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
  37 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
  38 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
  39 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
  40 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
  41         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
  42           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
  43 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
  44         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
  45           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
  46 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
  47         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
  48           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
  49 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
  50
  51 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
  52 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
  53 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
  54 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
  55 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
  56 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
  57 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
  58 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
  59 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
  60 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
  61 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
  62 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
  63 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
  64 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
  65 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
  66 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
  67
  68 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
  69 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
  70 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
  71 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
  72 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
  73 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
  74 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
  75 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
  76
  77         u32 config2;                                            /* 0x118 */
  78         /* one time auto detect grace period (in sec) */
  79 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
  80 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
  81
  82 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
  83
  84         /* The default value for the core clock is 250MHz and it is
  85            achieved by setting the clock change to 4 */
  86 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
  87 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
  88
  89 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
  90 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
  91
  92 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
  93
  94         u32 power_dissipated;                                   /* 0x11c */
  95 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
  96 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
  97
  98 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
  99 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
 100 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
 101 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
 102 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
 103 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
 104
 105         u32 ump_nc_si_config;                                   /* 0x120 */
 106 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
 107 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
 108 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
 109 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
 110 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
 111 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
 112
 113 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
 114 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
 115
 116 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
 117 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
 118 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
 119 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
 120
 121         u32 board;                                              /* 0x124 */
 122 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
 123 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
 124
 125 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
 126 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         24
 127
 128 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
 129 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         28
 130
 131         u32 reserved;                                           /* 0x128 */
 132
 133 };
 134
 135
 136 /****************************************************************************
 137  * Port HW configuration                                                    *
 138  ****************************************************************************/
 139 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
 140
 141         u32 pci_id;
 142 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
 143 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
 144
 145         u32 pci_sub_id;
 146 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
 147 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
 148
 149         u32 power_dissipated;
 150 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
 151 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
 152 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
 153 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
 154 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
 155 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
 156 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
 157 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
 158
 159         u32 power_consumed;
 160 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
 161 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
 162 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
 163 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
 164 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
 165 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
 166 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
 167 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
 168
 169         u32 mac_upper;
 170 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
 171 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
 172         u32 mac_lower;
 173
 174         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
 175         u32 iscsi_mac_lower;
 176
 177         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
 178         u32 rdma_mac_lower;
 179
 180         u32 serdes_config;
 181         /* for external PHY, or forced mode or during AN */
 182 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
 183 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT  16
 184
 185 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0x0000ffff
 186 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT   0
 187
 188         u16 serdes_tx_driver_pre_emphasis[16];
 189         u16 serdes_rx_driver_equalizer[16];
 190
 191         u32 xgxs_config_lane0;
 192         u32 xgxs_config_lane1;
 193         u32 xgxs_config_lane2;
 194         u32 xgxs_config_lane3;
 195         /* for external PHY, or forced mode or during AN */
 196 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK   0xffff0000
 197 #define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT  16
 198
 199 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK      0x0000ffff
 200 #define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT     0
 201
 202         u16 xgxs_tx_driver_pre_emphasis_lane0[16];
 203         u16 xgxs_tx_driver_pre_emphasis_lane1[16];
 204         u16 xgxs_tx_driver_pre_emphasis_lane2[16];
 205         u16 xgxs_tx_driver_pre_emphasis_lane3[16];
 206
 207         u16 xgxs_rx_driver_equalizer_lane0[16];
 208         u16 xgxs_rx_driver_equalizer_lane1[16];
 209         u16 xgxs_rx_driver_equalizer_lane2[16];
 210         u16 xgxs_rx_driver_equalizer_lane3[16];
 211
 212         u32 lane_config;
 213 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
 214 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
 215 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
 216 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
 217 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
 218 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
 219 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
 220 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
 221         /* AN and forced */
 222 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
 223         /* forced only */
 224 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
 225         /* forced only */
 226 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
 227         /* forced only */
 228 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
 229
 230         u32 external_phy_config;
 231 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
 232 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
 233 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
 234 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
 235 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
 236
 237 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
 238 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
 239
 240 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
 241 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
 242 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
 243 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
 244 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
 245 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
 246 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
 247 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
 248 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726       0x00000600
 249 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
 250 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
 251 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
 252 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
 253
 254 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
 255 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
 256
 257         u32 speed_capability_mask;
 258 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
 259 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
 260 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
 261 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
 262 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
 263 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
 264 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
 265 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
 266 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
 267 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
 268 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
 269 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
 270 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
 271 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
 272 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
 273
 274 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
 275 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
 276 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
 277 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
 278 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
 279 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
 280 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
 281 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
 282 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
 283 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
 284 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
 285 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
 286 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
 287 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
 288 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
 289
 290         u32 reserved[2];
 291
 292 };
 293
 294
 295 /****************************************************************************
 296  * Shared Feature configuration                                             *
 297  ****************************************************************************/
 298 struct shared_feat_cfg {                                 /* NVRAM Offset */
 299
 300         u32 config;                                             /* 0x450 */
 301 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
 302
 303         /*  Use the values from options 47 and 48 instead of the HW default
 304           values */
 305 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED     0x00000000
 306 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED      0x00000002
 307
 308 #define SHARED_FEATURE_MF_MODE_DISABLED             0x00000100
 309
 310 };
 311
 312
 313 /****************************************************************************
 314  * Port Feature configuration                                               *
 315  ****************************************************************************/
 316 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
 317
 318         u32 config;
 319 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
 320 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
 321 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
 322 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
 323 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
 324 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
 325 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
 326 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
 327 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
 328 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
 329 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
 330 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
 331 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
 332 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
 333 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
 334 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
 335 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
 336 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
 337 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
 338 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
 339 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
 340 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
 341 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
 342 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
 343 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
 344 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
 345 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
 346 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
 347 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
 348 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
 349 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
 350 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
 351 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
 352 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
 353 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
 354 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
 355 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
 356 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
 357 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
 358 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
 359 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
 360
 361         /*  Check the optic vendor via i2c before allowing it to be used by
 362           SW */
 363 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLED               0x00000000
 364 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED                0x08000000
 365
 366         u32 wol_config;
 367         /* Default is used when driver sets to "auto" mode */
 368 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
 369 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
 370 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
 371 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
 372 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
 373 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
 374 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
 375 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
 376 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
 377
 378         u32 mba_config;
 379 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
 380 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
 381 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
 382 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
 383 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
 384 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
 385 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
 386 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
 387 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
 388 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
 389 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
 390 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
 391 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
 392 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
 393 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
 394 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
 395 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
 396 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
 397 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
 398 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
 399 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
 400 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
 401 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
 402 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
 403 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
 404 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
 405 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
 406 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
 407 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
 408 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
 409 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
 410 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
 411 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
 412 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
 413 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
 414 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
 415 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
 416 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
 417 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
 418 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
 419 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
 420 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
 421 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
 422 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
 423 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
 424 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
 425 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
 426 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
 427 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
 428 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
 429 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
 430 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
 431 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
 432 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
 433
 434         u32 bmc_config;
 435 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
 436 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
 437
 438         u32 mba_vlan_cfg;
 439 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
 440 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
 441 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
 442
 443         u32 resource_cfg;
 444 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
 445 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
 446 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
 447 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
 448 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
 449
 450         u32 smbus_config;
 451         /* Obsolete */
 452 #define PORT_FEATURE_SMBUS_EN                       0x00000001
 453 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
 454 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
 455
 456         u32 reserved1;
 457
 458         u32 link_config;    /* Used as HW defaults for the driver */
 459 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
 460 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
 461         /* (forced) low speed switch (< 10G) */
 462 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
 463         /* (forced) high speed switch (>= 10G) */
 464 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
 465 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
 466 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
 467
 468 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
 469 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
 470 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
 471 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
 472 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
 473 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
 474 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
 475 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
 476 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
 477 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
 478 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
 479 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
 480 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
 481 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
 482 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
 483 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
 484 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
 485
 486 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
 487 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
 488 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
 489 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
 490 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
 491 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
 492 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
 493
 494         /* The default for MCP link configuration,
 495            uses the same defines as link_config */
 496         u32 mfw_wol_link_cfg;
 497
 498         u32 reserved[19];
 499
 500 };
 501
 502
 503 /****************************************************************************
 504  * Device Information                                                       *
 505  ****************************************************************************/
 506 struct dev_info {                                                   /* size */
 507
 508         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
 509
 510         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
 511
 512         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
 513
 514         struct shared_feat_cfg   shared_feature_config;                /* 4 */
 515
 516         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
 517
 518 };
 519
 520
 521 #define FUNC_0                          0
 522 #define FUNC_1                          1
 523 #define FUNC_2                          2
 524 #define FUNC_3                          3
 525 #define FUNC_4                          4
 526 #define FUNC_5                          5
 527 #define FUNC_6                          6
 528 #define FUNC_7                          7
 529 #define E1_FUNC_MAX                     2
 530 #define E1H_FUNC_MAX                    8
 531
 532 #define VN_0                            0
 533 #define VN_1                            1
 534 #define VN_2                            2
 535 #define VN_3                            3
 536 #define E1VN_MAX                        1
 537 #define E1HVN_MAX                       4
 538
 539
 540 /* This value (in milliseconds) determines the frequency of the driver
 541  * issuing the PULSE message code.  The firmware monitors this periodic
 542  * pulse to determine when to switch to an OS-absent mode. */
 543 #define DRV_PULSE_PERIOD_MS             250
 544
 545 /* This value (in milliseconds) determines how long the driver should
 546  * wait for an acknowledgement from the firmware before timing out.  Once
 547  * the firmware has timed out, the driver will assume there is no firmware
 548  * running and there won't be any firmware-driver synchronization during a
 549  * driver reset. */
 550 #define FW_ACK_TIME_OUT_MS              5000
 551
 552 #define FW_ACK_POLL_TIME_MS             1
 553
 554 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
 555
 556 /* LED Blink rate that will achieve ~15.9Hz */
 557 #define LED_BLINK_RATE_VAL              480
 558
 559 /****************************************************************************
 560  * Driver <-> FW Mailbox                                                    *
 561  ****************************************************************************/
 562 struct drv_port_mb {
 563
 564         u32 link_status;
 565         /* Driver should update this field on any link change event */
 566
 567 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
 568 #define LINK_STATUS_LINK_UP                             0x00000001
 569 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
 570 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
 571 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
 572 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
 573 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
 574 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
 575 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
 576 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
 577 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
 578 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
 579 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
 580 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
 581 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
 582 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
 583 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
 584 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
 585 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
 586 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
 587 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
 588 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
 589 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
 590 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
 591 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
 592 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
 593 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
 594
 595 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
 596 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
 597
 598 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
 599 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
 600 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
 601
 602 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
 603 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
 604 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
 605 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
 606 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
 607 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
 608 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
 609
 610 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
 611 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
 612
 613 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
 614 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
 615
 616 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
 617 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
 618 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
 619 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
 620 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
 621
 622 #define LINK_STATUS_SERDES_LINK                         0x00100000
 623
 624 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
 625 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
 626 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
 627 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
 628 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
 629 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
 630 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
 631 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
 632
 633         u32 port_stx;
 634
 635         u32 stat_nig_timer;
 636
 637         /* MCP firmware does not use this field */
 638         u32 ext_phy_fw_version;
 639
 640 };
 641
 642
 643 struct drv_func_mb {
 644
 645         u32 drv_mb_header;
 646 #define DRV_MSG_CODE_MASK                               0xffff0000
 647 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
 648 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
 649 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
 650 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
 651 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
 652 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
 653 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
 654 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
 655 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
 656 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
 657 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
 658 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
 659 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
 660
 661 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
 662 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
 663 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
 664 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI                    0xff040000
 665
 666 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
 667
 668         u32 drv_mb_param;
 669
 670         u32 fw_mb_header;
 671 #define FW_MSG_CODE_MASK                                0xffff0000
 672 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
 673 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
 674 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
 675 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
 676 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
 677 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
 678 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
 679 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
 680 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
 681 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
 682 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
 683 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
 684 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
 685 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
 686 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
 687 #define FW_MSG_CODE_NO_KEY                              0x80f00000
 688 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
 689 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
 690 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
 691 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
 692 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
 693 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
 694
 695 #define FW_MSG_CODE_LIC_CHALLENGE                       0xff010000
 696 #define FW_MSG_CODE_LIC_RESPONSE                        0xff020000
 697 #define FW_MSG_CODE_VIRT_MAC_PRIM                       0xff030000
 698 #define FW_MSG_CODE_VIRT_MAC_ISCSI                      0xff040000
 699
 700 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
 701
 702         u32 fw_mb_param;
 703
 704         u32 drv_pulse_mb;
 705 #define DRV_PULSE_SEQ_MASK                              0x00007fff
 706 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
 707         /* The system time is in the format of
 708          * (year-2001)*12*32 + month*32 + day. */
 709 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
 710         /* Indicate to the firmware not to go into the
 711          * OS-absent when it is not getting driver pulse.
 712          * This is used for debugging as well for PXE(MBA). */
 713
 714         u32 mcp_pulse_mb;
 715 #define MCP_PULSE_SEQ_MASK                              0x00007fff
 716 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
 717         /* Indicates to the driver not to assert due to lack
 718          * of MCP response */
 719 #define MCP_EVENT_MASK                                  0xffff0000
 720 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
 721
 722         u32 iscsi_boot_signature;
 723         u32 iscsi_boot_block_offset;
 724
 725         u32 drv_status;
 726 #define DRV_STATUS_PMF                                  0x00000001
 727
 728         u32 virt_mac_upper;
 729 #define VIRT_MAC_SIGN_MASK                              0xffff0000
 730 #define VIRT_MAC_SIGNATURE                              0x564d0000
 731         u32 virt_mac_lower;
 732
 733 };
 734
 735
 736 /****************************************************************************
 737  * Management firmware state                                                *
 738  ****************************************************************************/
 739 /* Allocate 440 bytes for management firmware */
 740 #define MGMTFW_STATE_WORD_SIZE                              110
 741
 742 struct mgmtfw_state {
 743         u32 opaque[MGMTFW_STATE_WORD_SIZE];
 744 };
 745
 746
 747 /****************************************************************************
 748  * Multi-Function configuration                                             *
 749  ****************************************************************************/
 750 struct shared_mf_cfg {
 751
 752         u32 clp_mb;
 753 #define SHARED_MF_CLP_SET_DEFAULT                   0x00000000
 754         /* set by CLP */
 755 #define SHARED_MF_CLP_EXIT                          0x00000001
 756         /* set by MCP */
 757 #define SHARED_MF_CLP_EXIT_DONE                     0x00010000
 758
 759 };
 760
 761 struct port_mf_cfg {
 762
 763         u32 dynamic_cfg;        /* device control channel */
 764 #define PORT_MF_CFG_OUTER_VLAN_TAG_MASK             0x0000ffff
 765 #define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT            0
 766 #define PORT_MF_CFG_DYNAMIC_CFG_ENABLED             0x00010000
 767 #define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT             0x00000000
 768
 769         u32 reserved[3];
 770
 771 };
 772
 773 struct func_mf_cfg {
 774
 775         u32 config;
 776         /* E/R/I/D */
 777         /* function 0 of each port cannot be hidden */
 778 #define FUNC_MF_CFG_FUNC_HIDE                       0x00000001
 779
 780 #define FUNC_MF_CFG_PROTOCOL_MASK                   0x00000007
 781 #define FUNC_MF_CFG_PROTOCOL_ETHERNET               0x00000002
 782 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
 783 #define FUNC_MF_CFG_PROTOCOL_ISCSI                  0x00000006
 784 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
 785         FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
 786
 787 #define FUNC_MF_CFG_FUNC_DISABLED                   0x00000008
 788
 789         /* PRI */
 790         /* 0 - low priority, 3 - high priority */
 791 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK          0x00000300
 792 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT         8
 793 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT       0x00000000
 794
 795         /* MINBW, MAXBW */
 796         /* value range - 0..100, increments in 100Mbps */
 797 #define FUNC_MF_CFG_MIN_BW_MASK                     0x00ff0000
 798 #define FUNC_MF_CFG_MIN_BW_SHIFT                    16
 799 #define FUNC_MF_CFG_MIN_BW_DEFAULT                  0x00000000
 800 #define FUNC_MF_CFG_MAX_BW_MASK                     0xff000000
 801 #define FUNC_MF_CFG_MAX_BW_SHIFT                    24
 802 #define FUNC_MF_CFG_MAX_BW_DEFAULT                  0x64000000
 803
 804         u32 mac_upper;          /* MAC */
 805 #define FUNC_MF_CFG_UPPERMAC_MASK                   0x0000ffff
 806 #define FUNC_MF_CFG_UPPERMAC_SHIFT                  0
 807 #define FUNC_MF_CFG_UPPERMAC_DEFAULT                FUNC_MF_CFG_UPPERMAC_MASK
 808         u32 mac_lower;
 809 #define FUNC_MF_CFG_LOWERMAC_DEFAULT                0xffffffff
 810
 811         u32 e1hov_tag;  /* VNI */
 812 #define FUNC_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
 813 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT                 0
 814 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT               FUNC_MF_CFG_E1HOV_TAG_MASK
 815
 816         u32 reserved[2];
 817
 818 };
 819
 820 struct mf_cfg {
 821
 822         struct shared_mf_cfg    shared_mf_config;
 823         struct port_mf_cfg      port_mf_config[PORT_MAX];
 824 #if defined(b710)
 825         struct func_mf_cfg      func_mf_config[E1_FUNC_MAX];
 826 #else
 827         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
 828 #endif
 829
 830 };
 831
 832
 833 /****************************************************************************
 834  * Shared Memory Region                                                     *
 835  ****************************************************************************/
 836 struct shmem_region {                          /*   SharedMem Offset (size) */
 837
 838         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
 839 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
 840 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
 841         /* validity bits */
 842 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
 843 #define SHR_MEM_VALIDITY_MB                         0x00200000
 844 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
 845 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
 846         /* One licensing bit should be set */
 847 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
 848 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
 849 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
 850 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
 851         /* Active MFW */
 852 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
 853 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
 854 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
 855 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
 856 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
 857 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
 858
 859         struct dev_info         dev_info;                /* 0x8     (0x438) */
 860
 861         u8                      reserved[52*PORT_MAX];
 862
 863         /* FW information (for internal FW use) */
 864         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
 865         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
 866
 867         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
 868         struct drv_func_mb      func_mb[E1H_FUNC_MAX];
 869
 870         struct mf_cfg           mf_cfg;
 871
 872 };                                                     /* 0x6dc */
 873
 874
 875 struct emac_stats {
 876     u32     rx_stat_ifhcinoctets;
 877     u32     rx_stat_ifhcinbadoctets;
 878     u32     rx_stat_etherstatsfragments;
 879     u32     rx_stat_ifhcinucastpkts;
 880     u32     rx_stat_ifhcinmulticastpkts;
 881     u32     rx_stat_ifhcinbroadcastpkts;
 882     u32     rx_stat_dot3statsfcserrors;
 883     u32     rx_stat_dot3statsalignmenterrors;
 884     u32     rx_stat_dot3statscarriersenseerrors;
 885     u32     rx_stat_xonpauseframesreceived;
 886     u32     rx_stat_xoffpauseframesreceived;
 887     u32     rx_stat_maccontrolframesreceived;
 888     u32     rx_stat_xoffstateentered;
 889     u32     rx_stat_dot3statsframestoolong;
 890     u32     rx_stat_etherstatsjabbers;
 891     u32     rx_stat_etherstatsundersizepkts;
 892     u32     rx_stat_etherstatspkts64octets;
 893     u32     rx_stat_etherstatspkts65octetsto127octets;
 894     u32     rx_stat_etherstatspkts128octetsto255octets;
 895     u32     rx_stat_etherstatspkts256octetsto511octets;
 896     u32     rx_stat_etherstatspkts512octetsto1023octets;
 897     u32     rx_stat_etherstatspkts1024octetsto1522octets;
 898     u32     rx_stat_etherstatspktsover1522octets;
 899
 900     u32     rx_stat_falsecarriererrors;
 901
 902     u32     tx_stat_ifhcoutoctets;
 903     u32     tx_stat_ifhcoutbadoctets;
 904     u32     tx_stat_etherstatscollisions;
 905     u32     tx_stat_outxonsent;
 906     u32     tx_stat_outxoffsent;
 907     u32     tx_stat_flowcontroldone;
 908     u32     tx_stat_dot3statssinglecollisionframes;
 909     u32     tx_stat_dot3statsmultiplecollisionframes;
 910     u32     tx_stat_dot3statsdeferredtransmissions;
 911     u32     tx_stat_dot3statsexcessivecollisions;
 912     u32     tx_stat_dot3statslatecollisions;
 913     u32     tx_stat_ifhcoutucastpkts;
 914     u32     tx_stat_ifhcoutmulticastpkts;
 915     u32     tx_stat_ifhcoutbroadcastpkts;
 916     u32     tx_stat_etherstatspkts64octets;
 917     u32     tx_stat_etherstatspkts65octetsto127octets;
 918     u32     tx_stat_etherstatspkts128octetsto255octets;
 919     u32     tx_stat_etherstatspkts256octetsto511octets;
 920     u32     tx_stat_etherstatspkts512octetsto1023octets;
 921     u32     tx_stat_etherstatspkts1024octetsto1522octets;
 922     u32     tx_stat_etherstatspktsover1522octets;
 923     u32     tx_stat_dot3statsinternalmactransmiterrors;
 924 };
 925
 926
 927 struct bmac_stats {
 928     u32     tx_stat_gtpkt_lo;
 929     u32     tx_stat_gtpkt_hi;
 930     u32     tx_stat_gtxpf_lo;
 931     u32     tx_stat_gtxpf_hi;
 932     u32     tx_stat_gtfcs_lo;
 933     u32     tx_stat_gtfcs_hi;
 934     u32     tx_stat_gtmca_lo;
 935     u32     tx_stat_gtmca_hi;
 936     u32     tx_stat_gtbca_lo;
 937     u32     tx_stat_gtbca_hi;
 938     u32     tx_stat_gtfrg_lo;
 939     u32     tx_stat_gtfrg_hi;
 940     u32     tx_stat_gtovr_lo;
 941     u32     tx_stat_gtovr_hi;
 942     u32     tx_stat_gt64_lo;
 943     u32     tx_stat_gt64_hi;
 944     u32     tx_stat_gt127_lo;
 945     u32     tx_stat_gt127_hi;
 946     u32     tx_stat_gt255_lo;
 947     u32     tx_stat_gt255_hi;
 948     u32     tx_stat_gt511_lo;
 949     u32     tx_stat_gt511_hi;
 950     u32     tx_stat_gt1023_lo;
 951     u32     tx_stat_gt1023_hi;
 952     u32     tx_stat_gt1518_lo;
 953     u32     tx_stat_gt1518_hi;
 954     u32     tx_stat_gt2047_lo;
 955     u32     tx_stat_gt2047_hi;
 956     u32     tx_stat_gt4095_lo;
 957     u32     tx_stat_gt4095_hi;
 958     u32     tx_stat_gt9216_lo;
 959     u32     tx_stat_gt9216_hi;
 960     u32     tx_stat_gt16383_lo;
 961     u32     tx_stat_gt16383_hi;
 962     u32     tx_stat_gtmax_lo;
 963     u32     tx_stat_gtmax_hi;
 964     u32     tx_stat_gtufl_lo;
 965     u32     tx_stat_gtufl_hi;
 966     u32     tx_stat_gterr_lo;
 967     u32     tx_stat_gterr_hi;
 968     u32     tx_stat_gtbyt_lo;
 969     u32     tx_stat_gtbyt_hi;
 970
 971     u32     rx_stat_gr64_lo;
 972     u32     rx_stat_gr64_hi;
 973     u32     rx_stat_gr127_lo;
 974     u32     rx_stat_gr127_hi;
 975     u32     rx_stat_gr255_lo;
 976     u32     rx_stat_gr255_hi;
 977     u32     rx_stat_gr511_lo;
 978     u32     rx_stat_gr511_hi;
 979     u32     rx_stat_gr1023_lo;
 980     u32     rx_stat_gr1023_hi;
 981     u32     rx_stat_gr1518_lo;
 982     u32     rx_stat_gr1518_hi;
 983     u32     rx_stat_gr2047_lo;
 984     u32     rx_stat_gr2047_hi;
 985     u32     rx_stat_gr4095_lo;
 986     u32     rx_stat_gr4095_hi;
 987     u32     rx_stat_gr9216_lo;
 988     u32     rx_stat_gr9216_hi;
 989     u32     rx_stat_gr16383_lo;
 990     u32     rx_stat_gr16383_hi;
 991     u32     rx_stat_grmax_lo;
 992     u32     rx_stat_grmax_hi;
 993     u32     rx_stat_grpkt_lo;
 994     u32     rx_stat_grpkt_hi;
 995     u32     rx_stat_grfcs_lo;
 996     u32     rx_stat_grfcs_hi;
 997     u32     rx_stat_grmca_lo;
 998     u32     rx_stat_grmca_hi;
 999     u32     rx_stat_grbca_lo;
1000     u32     rx_stat_grbca_hi;
1001     u32     rx_stat_grxcf_lo;
1002     u32     rx_stat_grxcf_hi;
1003     u32     rx_stat_grxpf_lo;
1004     u32     rx_stat_grxpf_hi;
1005     u32     rx_stat_grxuo_lo;
1006     u32     rx_stat_grxuo_hi;
1007     u32     rx_stat_grjbr_lo;
1008     u32     rx_stat_grjbr_hi;
1009     u32     rx_stat_grovr_lo;
1010     u32     rx_stat_grovr_hi;
1011     u32     rx_stat_grflr_lo;
1012     u32     rx_stat_grflr_hi;
1013     u32     rx_stat_grmeg_lo;
1014     u32     rx_stat_grmeg_hi;
1015     u32     rx_stat_grmeb_lo;
1016     u32     rx_stat_grmeb_hi;
1017     u32     rx_stat_grbyt_lo;
1018     u32     rx_stat_grbyt_hi;
1019     u32     rx_stat_grund_lo;
1020     u32     rx_stat_grund_hi;
1021     u32     rx_stat_grfrg_lo;
1022     u32     rx_stat_grfrg_hi;
1023     u32     rx_stat_grerb_lo;
1024     u32     rx_stat_grerb_hi;
1025     u32     rx_stat_grfre_lo;
1026     u32     rx_stat_grfre_hi;
1027     u32     rx_stat_gripj_lo;
1028     u32     rx_stat_gripj_hi;
1029 };
1030
1031
1032 union mac_stats {
1033     struct emac_stats   emac_stats;
1034     struct bmac_stats   bmac_stats;
1035 };
1036
1037
1038 struct mac_stx {
1039     /* in_bad_octets */
1040     u32     rx_stat_ifhcinbadoctets_hi;
1041     u32     rx_stat_ifhcinbadoctets_lo;
1042
1043     /* out_bad_octets */
1044     u32     tx_stat_ifhcoutbadoctets_hi;
1045     u32     tx_stat_ifhcoutbadoctets_lo;
1046
1047     /* crc_receive_errors */
1048     u32     rx_stat_dot3statsfcserrors_hi;
1049     u32     rx_stat_dot3statsfcserrors_lo;
1050     /* alignment_errors */
1051     u32     rx_stat_dot3statsalignmenterrors_hi;
1052     u32     rx_stat_dot3statsalignmenterrors_lo;
1053     /* carrier_sense_errors */
1054     u32     rx_stat_dot3statscarriersenseerrors_hi;
1055     u32     rx_stat_dot3statscarriersenseerrors_lo;
1056     /* false_carrier_detections */
1057     u32     rx_stat_falsecarriererrors_hi;
1058     u32     rx_stat_falsecarriererrors_lo;
1059
1060     /* runt_packets_received */
1061     u32     rx_stat_etherstatsundersizepkts_hi;
1062     u32     rx_stat_etherstatsundersizepkts_lo;
1063     /* jabber_packets_received */
1064     u32     rx_stat_dot3statsframestoolong_hi;
1065     u32     rx_stat_dot3statsframestoolong_lo;
1066
1067     /* error_runt_packets_received */
1068     u32     rx_stat_etherstatsfragments_hi;
1069     u32     rx_stat_etherstatsfragments_lo;
1070     /* error_jabber_packets_received */
1071     u32     rx_stat_etherstatsjabbers_hi;
1072     u32     rx_stat_etherstatsjabbers_lo;
1073
1074     /* control_frames_received */
1075     u32     rx_stat_maccontrolframesreceived_hi;
1076     u32     rx_stat_maccontrolframesreceived_lo;
1077     u32     rx_stat_bmac_xpf_hi;
1078     u32     rx_stat_bmac_xpf_lo;
1079     u32     rx_stat_bmac_xcf_hi;
1080     u32     rx_stat_bmac_xcf_lo;
1081
1082     /* xoff_state_entered */
1083     u32     rx_stat_xoffstateentered_hi;
1084     u32     rx_stat_xoffstateentered_lo;
1085     /* pause_xon_frames_received */
1086     u32     rx_stat_xonpauseframesreceived_hi;
1087     u32     rx_stat_xonpauseframesreceived_lo;
1088     /* pause_xoff_frames_received */
1089     u32     rx_stat_xoffpauseframesreceived_hi;
1090     u32     rx_stat_xoffpauseframesreceived_lo;
1091     /* pause_xon_frames_transmitted */
1092     u32     tx_stat_outxonsent_hi;
1093     u32     tx_stat_outxonsent_lo;
1094     /* pause_xoff_frames_transmitted */
1095     u32     tx_stat_outxoffsent_hi;
1096     u32     tx_stat_outxoffsent_lo;
1097     /* flow_control_done */
1098     u32     tx_stat_flowcontroldone_hi;
1099     u32     tx_stat_flowcontroldone_lo;
1100
1101     /* ether_stats_collisions */
1102     u32     tx_stat_etherstatscollisions_hi;
1103     u32     tx_stat_etherstatscollisions_lo;
1104     /* single_collision_transmit_frames */
1105     u32     tx_stat_dot3statssinglecollisionframes_hi;
1106     u32     tx_stat_dot3statssinglecollisionframes_lo;
1107     /* multiple_collision_transmit_frames */
1108     u32     tx_stat_dot3statsmultiplecollisionframes_hi;
1109     u32     tx_stat_dot3statsmultiplecollisionframes_lo;
1110     /* deferred_transmissions */
1111     u32     tx_stat_dot3statsdeferredtransmissions_hi;
1112     u32     tx_stat_dot3statsdeferredtransmissions_lo;
1113     /* excessive_collision_frames */
1114     u32     tx_stat_dot3statsexcessivecollisions_hi;
1115     u32     tx_stat_dot3statsexcessivecollisions_lo;
1116     /* late_collision_frames */
1117     u32     tx_stat_dot3statslatecollisions_hi;
1118     u32     tx_stat_dot3statslatecollisions_lo;
1119
1120     /* frames_transmitted_64_bytes */
1121     u32     tx_stat_etherstatspkts64octets_hi;
1122     u32     tx_stat_etherstatspkts64octets_lo;
1123     /* frames_transmitted_65_127_bytes */
1124     u32     tx_stat_etherstatspkts65octetsto127octets_hi;
1125     u32     tx_stat_etherstatspkts65octetsto127octets_lo;
1126     /* frames_transmitted_128_255_bytes */
1127     u32     tx_stat_etherstatspkts128octetsto255octets_hi;
1128     u32     tx_stat_etherstatspkts128octetsto255octets_lo;
1129     /* frames_transmitted_256_511_bytes */
1130     u32     tx_stat_etherstatspkts256octetsto511octets_hi;
1131     u32     tx_stat_etherstatspkts256octetsto511octets_lo;
1132     /* frames_transmitted_512_1023_bytes */
1133     u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
1134     u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
1135     /* frames_transmitted_1024_1522_bytes */
1136     u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
1137     u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
1138     /* frames_transmitted_1523_9022_bytes */
1139     u32     tx_stat_etherstatspktsover1522octets_hi;
1140     u32     tx_stat_etherstatspktsover1522octets_lo;
1141     u32     tx_stat_bmac_2047_hi;
1142     u32     tx_stat_bmac_2047_lo;
1143     u32     tx_stat_bmac_4095_hi;
1144     u32     tx_stat_bmac_4095_lo;
1145     u32     tx_stat_bmac_9216_hi;
1146     u32     tx_stat_bmac_9216_lo;
1147     u32     tx_stat_bmac_16383_hi;
1148     u32     tx_stat_bmac_16383_lo;
1149
1150     /* internal_mac_transmit_errors */
1151     u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
1152     u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
1153
1154     /* if_out_discards */
1155     u32     tx_stat_bmac_ufl_hi;
1156     u32     tx_stat_bmac_ufl_lo;
1157 };
1158
1159
1160 #define MAC_STX_IDX_MAX                     2
1161
1162 struct host_port_stats {
1163     u32            host_port_stats_start;
1164
1165     struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1166
1167     u32            brb_drop_hi;
1168     u32            brb_drop_lo;
1169
1170     u32            host_port_stats_end;
1171 };
1172
1173
1174 struct host_func_stats {
1175     u32     host_func_stats_start;
1176
1177     u32     total_bytes_received_hi;
1178     u32     total_bytes_received_lo;
1179
1180     u32     total_bytes_transmitted_hi;
1181     u32     total_bytes_transmitted_lo;
1182
1183     u32     total_unicast_packets_received_hi;
1184     u32     total_unicast_packets_received_lo;
1185
1186     u32     total_multicast_packets_received_hi;
1187     u32     total_multicast_packets_received_lo;
1188
1189     u32     total_broadcast_packets_received_hi;
1190     u32     total_broadcast_packets_received_lo;
1191
1192     u32     total_unicast_packets_transmitted_hi;
1193     u32     total_unicast_packets_transmitted_lo;
1194
1195     u32     total_multicast_packets_transmitted_hi;
1196     u32     total_multicast_packets_transmitted_lo;
1197
1198     u32     total_broadcast_packets_transmitted_hi;
1199     u32     total_broadcast_packets_transmitted_lo;
1200
1201     u32     valid_bytes_received_hi;
1202     u32     valid_bytes_received_lo;
1203
1204     u32     host_func_stats_end;
1205 };
1206
1207
1208 #define BCM_5710_FW_MAJOR_VERSION                       4
1209 #define BCM_5710_FW_MINOR_VERSION                       8
1210 #define BCM_5710_FW_REVISION_VERSION                    53
1211 #define BCM_5710_FW_ENGINEERING_VERSION                 0
1212 #define BCM_5710_FW_COMPILE_FLAGS                       1
1213
1214
1215 /*
1216  * attention bits
1217  */
1218 struct atten_def_status_block {
1219         u32 attn_bits;
1220         u32 attn_bits_ack;
1221         u8 status_block_id;
1222         u8 reserved0;
1223         u16 attn_bits_index;
1224         u32 reserved1;
1225 };
1226
1227
1228 /*
1229  * common data for all protocols
1230  */
1231 struct doorbell_hdr {
1232         u8 header;
1233 #define DOORBELL_HDR_RX (0x1<<0)
1234 #define DOORBELL_HDR_RX_SHIFT 0
1235 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1236 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1237 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1238 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1239 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1240 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1241 };
1242
1243 /*
1244  * doorbell message sent to the chip
1245  */
1246 struct doorbell {
1247 #if defined(__BIG_ENDIAN)
1248         u16 zero_fill2;
1249         u8 zero_fill1;
1250         struct doorbell_hdr header;
1251 #elif defined(__LITTLE_ENDIAN)
1252         struct doorbell_hdr header;
1253         u8 zero_fill1;
1254         u16 zero_fill2;
1255 #endif
1256 };
1257
1258
1259 /*
1260  * IGU driver acknowledgement register
1261  */
1262 struct igu_ack_register {
1263 #if defined(__BIG_ENDIAN)
1264         u16 sb_id_and_flags;
1265 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1266 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1267 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1268 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1269 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1270 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1271 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1272 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1273 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1274 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1275         u16 status_block_index;
1276 #elif defined(__LITTLE_ENDIAN)
1277         u16 status_block_index;
1278         u16 sb_id_and_flags;
1279 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1280 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1281 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1282 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1283 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1284 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1285 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1286 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1287 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1288 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1289 #endif
1290 };
1291
1292
1293 /*
1294  * Parser parsing flags field
1295  */
1296 struct parsing_flags {
1297         u16 flags;
1298 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1299 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1300 #define PARSING_FLAGS_VLAN (0x1<<1)
1301 #define PARSING_FLAGS_VLAN_SHIFT 1
1302 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1303 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1304 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1305 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1306 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1307 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1308 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1309 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1310 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1311 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1312 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1313 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1314 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1315 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1316 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1317 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1318 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1319 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1320 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1321 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1322 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1323 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1324 };
1325
1326
1327 struct regpair {
1328         u32 lo;
1329         u32 hi;
1330 };
1331
1332
1333 /*
1334  * dmae command structure
1335  */
1336 struct dmae_command {
1337         u32 opcode;
1338 #define DMAE_COMMAND_SRC (0x1<<0)
1339 #define DMAE_COMMAND_SRC_SHIFT 0
1340 #define DMAE_COMMAND_DST (0x3<<1)
1341 #define DMAE_COMMAND_DST_SHIFT 1
1342 #define DMAE_COMMAND_C_DST (0x1<<3)
1343 #define DMAE_COMMAND_C_DST_SHIFT 3
1344 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1345 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1346 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1347 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1348 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1349 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1350 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1351 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1352 #define DMAE_COMMAND_PORT (0x1<<11)
1353 #define DMAE_COMMAND_PORT_SHIFT 11
1354 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1355 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1356 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1357 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1358 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1359 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1360 #define DMAE_COMMAND_E1HVN (0x3<<15)
1361 #define DMAE_COMMAND_E1HVN_SHIFT 15
1362 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1363 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1364         u32 src_addr_lo;
1365         u32 src_addr_hi;
1366         u32 dst_addr_lo;
1367         u32 dst_addr_hi;
1368 #if defined(__BIG_ENDIAN)
1369         u16 reserved1;
1370         u16 len;
1371 #elif defined(__LITTLE_ENDIAN)
1372         u16 len;
1373         u16 reserved1;
1374 #endif
1375         u32 comp_addr_lo;
1376         u32 comp_addr_hi;
1377         u32 comp_val;
1378         u32 crc32;
1379         u32 crc32_c;
1380 #if defined(__BIG_ENDIAN)
1381         u16 crc16_c;
1382         u16 crc16;
1383 #elif defined(__LITTLE_ENDIAN)
1384         u16 crc16;
1385         u16 crc16_c;
1386 #endif
1387 #if defined(__BIG_ENDIAN)
1388         u16 reserved2;
1389         u16 crc_t10;
1390 #elif defined(__LITTLE_ENDIAN)
1391         u16 crc_t10;
1392         u16 reserved2;
1393 #endif
1394 #if defined(__BIG_ENDIAN)
1395         u16 xsum8;
1396         u16 xsum16;
1397 #elif defined(__LITTLE_ENDIAN)
1398         u16 xsum16;
1399         u16 xsum8;
1400 #endif
1401 };
1402
1403
1404 struct double_regpair {
1405         u32 regpair0_lo;
1406         u32 regpair0_hi;
1407         u32 regpair1_lo;
1408         u32 regpair1_hi;
1409 };
1410
1411
1412 /*
1413  * The eth storm context of Ustorm (configuration part)
1414  */
1415 struct ustorm_eth_st_context_config {
1416 #if defined(__BIG_ENDIAN)
1417         u8 flags;
1418 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1419 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1420 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1421 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1422 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1423 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1424 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1425 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1426 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1427 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1428 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1429 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1430         u8 status_block_id;
1431         u8 clientId;
1432         u8 sb_index_numbers;
1433 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1434 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1435 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1436 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1437 #elif defined(__LITTLE_ENDIAN)
1438         u8 sb_index_numbers;
1439 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1440 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1441 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1442 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1443         u8 clientId;
1444         u8 status_block_id;
1445         u8 flags;
1446 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1447 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1448 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1449 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1450 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1451 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1452 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1453 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1454 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<4)
1455 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 4
1456 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0x7<<5)
1457 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 5
1458 #endif
1459 #if defined(__BIG_ENDIAN)
1460         u16 bd_buff_size;
1461         u8 statistics_counter_id;
1462         u8 mc_alignment_log_size;
1463 #elif defined(__LITTLE_ENDIAN)
1464         u8 mc_alignment_log_size;
1465         u8 statistics_counter_id;
1466         u16 bd_buff_size;
1467 #endif
1468 #if defined(__BIG_ENDIAN)
1469         u8 __local_sge_prod;
1470         u8 __local_bd_prod;
1471         u16 sge_buff_size;
1472 #elif defined(__LITTLE_ENDIAN)
1473         u16 sge_buff_size;
1474         u8 __local_bd_prod;
1475         u8 __local_sge_prod;
1476 #endif
1477         u32 reserved;
1478         u32 bd_page_base_lo;
1479         u32 bd_page_base_hi;
1480         u32 sge_page_base_lo;
1481         u32 sge_page_base_hi;
1482 };
1483
1484 /*
1485  * The eth Rx Buffer Descriptor
1486  */
1487 struct eth_rx_bd {
1488         u32 addr_lo;
1489         u32 addr_hi;
1490 };
1491
1492 /*
1493  * The eth Rx SGE Descriptor
1494  */
1495 struct eth_rx_sge {
1496         u32 addr_lo;
1497         u32 addr_hi;
1498 };
1499
1500 /*
1501  * Local BDs and SGEs rings (in ETH)
1502  */
1503 struct eth_local_rx_rings {
1504         struct eth_rx_bd __local_bd_ring[16];
1505         struct eth_rx_sge __local_sge_ring[12];
1506 };
1507
1508 /*
1509  * The eth storm context of Ustorm
1510  */
1511 struct ustorm_eth_st_context {
1512         struct ustorm_eth_st_context_config common;
1513         struct eth_local_rx_rings __rings;
1514 };
1515
1516 /*
1517  * The eth storm context of Tstorm
1518  */
1519 struct tstorm_eth_st_context {
1520         u32 __reserved0[28];
1521 };
1522
1523 /*
1524  * The eth aggregative context section of Xstorm
1525  */
1526 struct xstorm_eth_extra_ag_context_section {
1527 #if defined(__BIG_ENDIAN)
1528         u8 __tcp_agg_vars1;
1529         u8 __reserved50;
1530         u16 __mss;
1531 #elif defined(__LITTLE_ENDIAN)
1532         u16 __mss;
1533         u8 __reserved50;
1534         u8 __tcp_agg_vars1;
1535 #endif
1536         u32 __snd_nxt;
1537         u32 __tx_wnd;
1538         u32 __snd_una;
1539         u32 __reserved53;
1540 #if defined(__BIG_ENDIAN)
1541         u8 __agg_val8_th;
1542         u8 __agg_val8;
1543         u16 __tcp_agg_vars2;
1544 #elif defined(__LITTLE_ENDIAN)
1545         u16 __tcp_agg_vars2;
1546         u8 __agg_val8;
1547         u8 __agg_val8_th;
1548 #endif
1549         u32 __reserved58;
1550         u32 __reserved59;
1551         u32 __reserved60;
1552         u32 __reserved61;
1553 #if defined(__BIG_ENDIAN)
1554         u16 __agg_val7_th;
1555         u16 __agg_val7;
1556 #elif defined(__LITTLE_ENDIAN)
1557         u16 __agg_val7;
1558         u16 __agg_val7_th;
1559 #endif
1560 #if defined(__BIG_ENDIAN)
1561         u8 __tcp_agg_vars5;
1562         u8 __tcp_agg_vars4;
1563         u8 __tcp_agg_vars3;
1564         u8 __reserved62;
1565 #elif defined(__LITTLE_ENDIAN)
1566         u8 __reserved62;
1567         u8 __tcp_agg_vars3;
1568         u8 __tcp_agg_vars4;
1569         u8 __tcp_agg_vars5;
1570 #endif
1571         u32 __tcp_agg_vars6;
1572 #if defined(__BIG_ENDIAN)
1573         u16 __agg_misc6;
1574         u16 __tcp_agg_vars7;
1575 #elif defined(__LITTLE_ENDIAN)
1576         u16 __tcp_agg_vars7;
1577         u16 __agg_misc6;
1578 #endif
1579         u32 __agg_val10;
1580         u32 __agg_val10_th;
1581 #if defined(__BIG_ENDIAN)
1582         u16 __reserved3;
1583         u8 __reserved2;
1584         u8 __da_only_cnt;
1585 #elif defined(__LITTLE_ENDIAN)
1586         u8 __da_only_cnt;
1587         u8 __reserved2;
1588         u16 __reserved3;
1589 #endif
1590 };
1591
1592 /*
1593  * The eth aggregative context of Xstorm
1594  */
1595 struct xstorm_eth_ag_context {
1596 #if defined(__BIG_ENDIAN)
1597         u16 __bd_prod;
1598         u8 __agg_vars1;
1599         u8 __state;
1600 #elif defined(__LITTLE_ENDIAN)
1601         u8 __state;
1602         u8 __agg_vars1;
1603         u16 __bd_prod;
1604 #endif
1605 #if defined(__BIG_ENDIAN)
1606         u8 cdu_reserved;
1607         u8 __agg_vars4;
1608         u8 __agg_vars3;
1609         u8 __agg_vars2;
1610 #elif defined(__LITTLE_ENDIAN)
1611         u8 __agg_vars2;
1612         u8 __agg_vars3;
1613         u8 __agg_vars4;
1614         u8 cdu_reserved;
1615 #endif
1616         u32 __more_packets_to_send;
1617 #if defined(__BIG_ENDIAN)
1618         u16 __agg_vars5;
1619         u16 __agg_val4_th;
1620 #elif defined(__LITTLE_ENDIAN)
1621         u16 __agg_val4_th;
1622         u16 __agg_vars5;
1623 #endif
1624         struct xstorm_eth_extra_ag_context_section __extra_section;
1625 #if defined(__BIG_ENDIAN)
1626         u16 __agg_vars7;
1627         u8 __agg_val3_th;
1628         u8 __agg_vars6;
1629 #elif defined(__LITTLE_ENDIAN)
1630         u8 __agg_vars6;
1631         u8 __agg_val3_th;
1632         u16 __agg_vars7;
1633 #endif
1634 #if defined(__BIG_ENDIAN)
1635         u16 __agg_val11_th;
1636         u16 __agg_val11;
1637 #elif defined(__LITTLE_ENDIAN)
1638         u16 __agg_val11;
1639         u16 __agg_val11_th;
1640 #endif
1641 #if defined(__BIG_ENDIAN)
1642         u8 __reserved1;
1643         u8 __agg_val6_th;
1644         u16 __agg_val9;
1645 #elif defined(__LITTLE_ENDIAN)
1646         u16 __agg_val9;
1647         u8 __agg_val6_th;
1648         u8 __reserved1;
1649 #endif
1650 #if defined(__BIG_ENDIAN)
1651         u16 __agg_val2_th;
1652         u16 __agg_val2;
1653 #elif defined(__LITTLE_ENDIAN)
1654         u16 __agg_val2;
1655         u16 __agg_val2_th;
1656 #endif
1657         u32 __agg_vars8;
1658 #if defined(__BIG_ENDIAN)
1659         u16 __agg_misc0;
1660         u16 __agg_val4;
1661 #elif defined(__LITTLE_ENDIAN)
1662         u16 __agg_val4;
1663         u16 __agg_misc0;
1664 #endif
1665 #if defined(__BIG_ENDIAN)
1666         u8 __agg_val3;
1667         u8 __agg_val6;
1668         u8 __agg_val5_th;
1669         u8 __agg_val5;
1670 #elif defined(__LITTLE_ENDIAN)
1671         u8 __agg_val5;
1672         u8 __agg_val5_th;
1673         u8 __agg_val6;
1674         u8 __agg_val3;
1675 #endif
1676 #if defined(__BIG_ENDIAN)
1677         u16 __agg_misc1;
1678         u16 __bd_ind_max_val;
1679 #elif defined(__LITTLE_ENDIAN)
1680         u16 __bd_ind_max_val;
1681         u16 __agg_misc1;
1682 #endif
1683         u32 __reserved57;
1684         u32 __agg_misc4;
1685         u32 __agg_misc5;
1686 };
1687
1688 /*
1689  * The eth aggregative context section of Tstorm
1690  */
1691 struct tstorm_eth_extra_ag_context_section {
1692         u32 __agg_val1;
1693 #if defined(__BIG_ENDIAN)
1694         u8 __tcp_agg_vars2;
1695         u8 __agg_val3;
1696         u16 __agg_val2;
1697 #elif defined(__LITTLE_ENDIAN)
1698         u16 __agg_val2;
1699         u8 __agg_val3;
1700         u8 __tcp_agg_vars2;
1701 #endif
1702 #if defined(__BIG_ENDIAN)
1703         u16 __agg_val5;
1704         u8 __agg_val6;
1705         u8 __tcp_agg_vars3;
1706 #elif defined(__LITTLE_ENDIAN)
1707         u8 __tcp_agg_vars3;
1708         u8 __agg_val6;
1709         u16 __agg_val5;
1710 #endif
1711         u32 __reserved63;
1712         u32 __reserved64;
1713         u32 __reserved65;
1714         u32 __reserved66;
1715         u32 __reserved67;
1716         u32 __tcp_agg_vars1;
1717         u32 __reserved61;
1718         u32 __reserved62;
1719         u32 __reserved2;
1720 };
1721
1722 /*
1723  * The eth aggregative context of Tstorm
1724  */
1725 struct tstorm_eth_ag_context {
1726 #if defined(__BIG_ENDIAN)
1727         u16 __reserved54;
1728         u8 __agg_vars1;
1729         u8 __state;
1730 #elif defined(__LITTLE_ENDIAN)
1731         u8 __state;
1732         u8 __agg_vars1;
1733         u16 __reserved54;
1734 #endif
1735 #if defined(__BIG_ENDIAN)
1736         u16 __agg_val4;
1737         u16 __agg_vars2;
1738 #elif defined(__LITTLE_ENDIAN)
1739         u16 __agg_vars2;
1740         u16 __agg_val4;
1741 #endif
1742         struct tstorm_eth_extra_ag_context_section __extra_section;
1743 };
1744
1745 /*
1746  * The eth aggregative context of Cstorm
1747  */
1748 struct cstorm_eth_ag_context {
1749         u32 __agg_vars1;
1750 #if defined(__BIG_ENDIAN)
1751         u8 __aux1_th;
1752         u8 __aux1_val;
1753         u16 __agg_vars2;
1754 #elif defined(__LITTLE_ENDIAN)
1755         u16 __agg_vars2;
1756         u8 __aux1_val;
1757         u8 __aux1_th;
1758 #endif
1759         u32 __num_of_treated_packet;
1760         u32 __last_packet_treated;
1761 #if defined(__BIG_ENDIAN)
1762         u16 __reserved58;
1763         u16 __reserved57;
1764 #elif defined(__LITTLE_ENDIAN)
1765         u16 __reserved57;
1766         u16 __reserved58;
1767 #endif
1768 #if defined(__BIG_ENDIAN)
1769         u8 __reserved62;
1770         u8 __reserved61;
1771         u8 __reserved60;
1772         u8 __reserved59;
1773 #elif defined(__LITTLE_ENDIAN)
1774         u8 __reserved59;
1775         u8 __reserved60;
1776         u8 __reserved61;
1777         u8 __reserved62;
1778 #endif
1779 #if defined(__BIG_ENDIAN)
1780         u16 __reserved64;
1781         u16 __reserved63;
1782 #elif defined(__LITTLE_ENDIAN)
1783         u16 __reserved63;
1784         u16 __reserved64;
1785 #endif
1786         u32 __reserved65;
1787 #if defined(__BIG_ENDIAN)
1788         u16 __agg_vars3;
1789         u16 __rq_inv_cnt;
1790 #elif defined(__LITTLE_ENDIAN)
1791         u16 __rq_inv_cnt;
1792         u16 __agg_vars3;
1793 #endif
1794 #if defined(__BIG_ENDIAN)
1795         u16 __packet_index_th;
1796         u16 __packet_index;
1797 #elif defined(__LITTLE_ENDIAN)
1798         u16 __packet_index;
1799         u16 __packet_index_th;
1800 #endif
1801 };
1802
1803 /*
1804  * The eth aggregative context of Ustorm
1805  */
1806 struct ustorm_eth_ag_context {
1807 #if defined(__BIG_ENDIAN)
1808         u8 __aux_counter_flags;
1809         u8 __agg_vars2;
1810         u8 __agg_vars1;
1811         u8 __state;
1812 #elif defined(__LITTLE_ENDIAN)
1813         u8 __state;
1814         u8 __agg_vars1;
1815         u8 __agg_vars2;
1816         u8 __aux_counter_flags;
1817 #endif
1818 #if defined(__BIG_ENDIAN)
1819         u8 cdu_usage;
1820         u8 __agg_misc2;
1821         u16 __agg_misc1;
1822 #elif defined(__LITTLE_ENDIAN)
1823         u16 __agg_misc1;
1824         u8 __agg_misc2;
1825         u8 cdu_usage;
1826 #endif
1827         u32 __agg_misc4;
1828 #if defined(__BIG_ENDIAN)
1829         u8 __agg_val3_th;
1830         u8 __agg_val3;
1831         u16 __agg_misc3;
1832 #elif defined(__LITTLE_ENDIAN)
1833         u16 __agg_misc3;
1834         u8 __agg_val3;
1835         u8 __agg_val3_th;
1836 #endif
1837         u32 __agg_val1;
1838         u32 __agg_misc4_th;
1839 #if defined(__BIG_ENDIAN)
1840         u16 __agg_val2_th;
1841         u16 __agg_val2;
1842 #elif defined(__LITTLE_ENDIAN)
1843         u16 __agg_val2;
1844         u16 __agg_val2_th;
1845 #endif
1846 #if defined(__BIG_ENDIAN)
1847         u16 __reserved2;
1848         u8 __decision_rules;
1849         u8 __decision_rule_enable_bits;
1850 #elif defined(__LITTLE_ENDIAN)
1851         u8 __decision_rule_enable_bits;
1852         u8 __decision_rules;
1853         u16 __reserved2;
1854 #endif
1855 };
1856
1857 /*
1858  * Timers connection context
1859  */
1860 struct timers_block_context {
1861         u32 __reserved_0;
1862         u32 __reserved_1;
1863         u32 __reserved_2;
1864         u32 flags;
1865 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1866 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1867 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1868 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1869 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1870 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
1871 };
1872
1873 /*
1874  * structure for easy accessibility to assembler
1875  */
1876 struct eth_tx_bd_flags {
1877         u8 as_bitfield;
1878 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1879 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1880 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1881 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1882 #define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1883 #define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1884 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1885 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1886 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1887 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1888 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1889 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1890 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1891 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1892 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1893 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1894 };
1895
1896 /*
1897  * The eth Tx Buffer Descriptor
1898  */
1899 struct eth_tx_bd {
1900         u32 addr_lo;
1901         u32 addr_hi;
1902         u16 nbd;
1903         u16 nbytes;
1904         u16 vlan;
1905         struct eth_tx_bd_flags bd_flags;
1906         u8 general_data;
1907 #define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1908 #define ETH_TX_BD_HDR_NBDS_SHIFT 0
1909 #define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1910 #define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1911 };
1912
1913 /*
1914  * Tx parsing BD structure for ETH,Relevant in START
1915  */
1916 struct eth_tx_parse_bd {
1917         u8 global_data;
1918 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1919 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1920 #define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1921 #define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1922 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1923 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1924 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1925 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1926 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1927 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1928         u8 tcp_flags;
1929 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1930 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1931 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1932 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1933 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1934 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1935 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1936 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1937 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1938 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1939 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1940 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1941 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1942 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1943 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1944 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1945         u8 ip_hlen;
1946         s8 cs_offset;
1947         u16 total_hlen;
1948         u16 lso_mss;
1949         u16 tcp_pseudo_csum;
1950         u16 ip_id;
1951         u32 tcp_send_seq;
1952 };
1953
1954 /*
1955  * The last BD in the BD memory will hold a pointer to the next BD memory
1956  */
1957 struct eth_tx_next_bd {
1958         u32 addr_lo;
1959         u32 addr_hi;
1960         u8 reserved[8];
1961 };
1962
1963 /*
1964  * union for 3 Bd types
1965  */
1966 union eth_tx_bd_types {
1967         struct eth_tx_bd reg_bd;
1968         struct eth_tx_parse_bd parse_bd;
1969         struct eth_tx_next_bd next_bd;
1970 };
1971
1972 /*
1973  * The eth storm context of Xstorm
1974  */
1975 struct xstorm_eth_st_context {
1976         u32 tx_bd_page_base_lo;
1977         u32 tx_bd_page_base_hi;
1978 #if defined(__BIG_ENDIAN)
1979         u16 tx_bd_cons;
1980         u8 statistics_data;
1981 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1982 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1983 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1984 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1985         u8 __local_tx_bd_prod;
1986 #elif defined(__LITTLE_ENDIAN)
1987         u8 __local_tx_bd_prod;
1988         u8 statistics_data;
1989 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1990 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1991 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1992 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
1993         u16 tx_bd_cons;
1994 #endif
1995         u32 db_data_addr_lo;
1996         u32 db_data_addr_hi;
1997         u32 __pkt_cons;
1998         u32 __gso_next;
1999         u32 is_eth_conn_1b;
2000         union eth_tx_bd_types __bds[13];
2001 };
2002
2003 /*
2004  * The eth storm context of Cstorm
2005  */
2006 struct cstorm_eth_st_context {
2007 #if defined(__BIG_ENDIAN)
2008         u16 __reserved0;
2009         u8 sb_index_number;
2010         u8 status_block_id;
2011 #elif defined(__LITTLE_ENDIAN)
2012         u8 status_block_id;
2013         u8 sb_index_number;
2014         u16 __reserved0;
2015 #endif
2016         u32 __reserved1[3];
2017 };
2018
2019 /*
2020  * Ethernet connection context
2021  */
2022 struct eth_context {
2023         struct ustorm_eth_st_context ustorm_st_context;
2024         struct tstorm_eth_st_context tstorm_st_context;
2025         struct xstorm_eth_ag_context xstorm_ag_context;
2026         struct tstorm_eth_ag_context tstorm_ag_context;
2027         struct cstorm_eth_ag_context cstorm_ag_context;
2028         struct ustorm_eth_ag_context ustorm_ag_context;
2029         struct timers_block_context timers_context;
2030         struct xstorm_eth_st_context xstorm_st_context;
2031         struct cstorm_eth_st_context cstorm_st_context;
2032 };
2033
2034
2035 /*
2036  * Ethernet doorbell
2037  */
2038 struct eth_tx_doorbell {
2039 #if defined(__BIG_ENDIAN)
2040         u16 npackets;
2041         u8 params;
2042 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2043 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2044 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2045 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2046 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2047 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2048         struct doorbell_hdr hdr;
2049 #elif defined(__LITTLE_ENDIAN)
2050         struct doorbell_hdr hdr;
2051         u8 params;
2052 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2053 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2054 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2055 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2056 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2057 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2058         u16 npackets;
2059 #endif
2060 };
2061
2062
2063 /*
2064  * ustorm status block
2065  */
2066 struct ustorm_def_status_block {
2067         u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2068         u16 status_block_index;
2069         u8 func;
2070         u8 status_block_id;
2071         u32 __flags;
2072 };
2073
2074 /*
2075  * cstorm status block
2076  */
2077 struct cstorm_def_status_block {
2078         u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2079         u16 status_block_index;
2080         u8 func;
2081         u8 status_block_id;
2082         u32 __flags;
2083 };
2084
2085 /*
2086  * xstorm status block
2087  */
2088 struct xstorm_def_status_block {
2089         u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2090         u16 status_block_index;
2091         u8 func;
2092         u8 status_block_id;
2093         u32 __flags;
2094 };
2095
2096 /*
2097  * tstorm status block
2098  */
2099 struct tstorm_def_status_block {
2100         u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2101         u16 status_block_index;
2102         u8 func;
2103         u8 status_block_id;
2104         u32 __flags;
2105 };
2106
2107 /*
2108  * host status block
2109  */
2110 struct host_def_status_block {
2111         struct atten_def_status_block atten_status_block;
2112         struct ustorm_def_status_block u_def_status_block;
2113         struct cstorm_def_status_block c_def_status_block;
2114         struct xstorm_def_status_block x_def_status_block;
2115         struct tstorm_def_status_block t_def_status_block;
2116 };
2117
2118
2119 /*
2120  * ustorm status block
2121  */
2122 struct ustorm_status_block {
2123         u16 index_values[HC_USTORM_SB_NUM_INDICES];
2124         u16 status_block_index;
2125         u8 func;
2126         u8 status_block_id;
2127         u32 __flags;
2128 };
2129
2130 /*
2131  * cstorm status block
2132  */
2133 struct cstorm_status_block {
2134         u16 index_values[HC_CSTORM_SB_NUM_INDICES];
2135         u16 status_block_index;
2136         u8 func;
2137         u8 status_block_id;
2138         u32 __flags;
2139 };
2140
2141 /*
2142  * host status block
2143  */
2144 struct host_status_block {
2145         struct ustorm_status_block u_status_block;
2146         struct cstorm_status_block c_status_block;
2147 };
2148
2149
2150 /*
2151  * The data for RSS setup ramrod
2152  */
2153 struct eth_client_setup_ramrod_data {
2154         u32 client_id;
2155         u8 is_rdma;
2156         u8 is_fcoe;
2157         u16 reserved1;
2158 };
2159
2160
2161 /*
2162  * L2 dynamic host coalescing init parameters
2163  */
2164 struct eth_dynamic_hc_config {
2165         u32 threshold[3];
2166         u8 hc_timeout[4];
2167 };
2168
2169
2170 /*
2171  * regular eth FP CQE parameters struct
2172  */
2173 struct eth_fast_path_rx_cqe {
2174         u8 type_error_flags;
2175 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2176 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2177 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2178 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2179 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2180 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2181 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2182 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2183 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2184 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2185 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2186 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2187 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2188 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2189         u8 status_flags;
2190 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2191 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2192 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2193 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2194 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2195 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2196 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2197 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2198 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2199 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2200 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2201 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2202         u8 placement_offset;
2203         u8 queue_index;
2204         u32 rss_hash_result;
2205         u16 vlan_tag;
2206         u16 pkt_len;
2207         u16 len_on_bd;
2208         struct parsing_flags pars_flags;
2209         u16 sgl[8];
2210 };
2211
2212
2213 /*
2214  * The data for RSS setup ramrod
2215  */
2216 struct eth_halt_ramrod_data {
2217         u32 client_id;
2218         u32 reserved0;
2219 };
2220
2221
2222 /*
2223  * The data for statistics query ramrod
2224  */
2225 struct eth_query_ramrod_data {
2226 #if defined(__BIG_ENDIAN)
2227         u8 reserved0;
2228         u8 collect_port;
2229         u16 drv_counter;
2230 #elif defined(__LITTLE_ENDIAN)
2231         u16 drv_counter;
2232         u8 collect_port;
2233         u8 reserved0;
2234 #endif
2235         u32 ctr_id_vector;
2236 };
2237
2238
2239 /*
2240  * Place holder for ramrods protocol specific data
2241  */
2242 struct ramrod_data {
2243         u32 data_lo;
2244         u32 data_hi;
2245 };
2246
2247 /*
2248  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2249  */
2250 union eth_ramrod_data {
2251         struct ramrod_data general;
2252 };
2253
2254
2255 /*
2256  * Rx Last BD in page (in ETH)
2257  */
2258 struct eth_rx_bd_next_page {
2259         u32 addr_lo;
2260         u32 addr_hi;
2261         u8 reserved[8];
2262 };
2263
2264
2265 /*
2266  * Eth Rx Cqe structure- general structure for ramrods
2267  */
2268 struct common_ramrod_eth_rx_cqe {
2269         u8 ramrod_type;
2270 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2271 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2272 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
2273 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
2274         u8 conn_type;
2275         u16 reserved1;
2276         u32 conn_and_cmd_data;
2277 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2278 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2279 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2280 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2281         struct ramrod_data protocol_data;
2282         u32 reserved2[4];
2283 };
2284
2285 /*
2286  * Rx Last CQE in page (in ETH)
2287  */
2288 struct eth_rx_cqe_next_page {
2289         u32 addr_lo;
2290         u32 addr_hi;
2291         u32 reserved[6];
2292 };
2293
2294 /*
2295  * union for all eth rx cqe types (fix their sizes)
2296  */
2297 union eth_rx_cqe {
2298         struct eth_fast_path_rx_cqe fast_path_cqe;
2299         struct common_ramrod_eth_rx_cqe ramrod_cqe;
2300         struct eth_rx_cqe_next_page next_page_cqe;
2301 };
2302
2303
2304 /*
2305  * common data for all protocols
2306  */
2307 struct spe_hdr {
2308         u32 conn_and_cmd_data;
2309 #define SPE_HDR_CID (0xFFFFFF<<0)
2310 #define SPE_HDR_CID_SHIFT 0
2311 #define SPE_HDR_CMD_ID (0xFF<<24)
2312 #define SPE_HDR_CMD_ID_SHIFT 24
2313         u16 type;
2314 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2315 #define SPE_HDR_CONN_TYPE_SHIFT 0
2316 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2317 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2318         u16 reserved;
2319 };
2320
2321 /*
2322  * Ethernet slow path element
2323  */
2324 union eth_specific_data {
2325         u8 protocol_data[8];
2326         struct regpair mac_config_addr;
2327         struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2328         struct eth_halt_ramrod_data halt_ramrod_data;
2329         struct regpair leading_cqe_addr;
2330         struct regpair update_data_addr;
2331         struct eth_query_ramrod_data query_ramrod_data;
2332 };
2333
2334 /*
2335  * Ethernet slow path element
2336  */
2337 struct eth_spe {
2338         struct spe_hdr hdr;
2339         union eth_specific_data data;
2340 };
2341
2342
2343 /*
2344  * doorbell data in host memory
2345  */
2346 struct eth_tx_db_data {
2347         u32 packets_prod;
2348         u16 bds_prod;
2349         u16 reserved;
2350 };
2351
2352
2353 /*
2354  * Common configuration parameters per function in Tstorm
2355  */
2356 struct tstorm_eth_function_common_config {
2357 #if defined(__BIG_ENDIAN)
2358         u8 leading_client_id;
2359         u8 rss_result_mask;
2360         u16 config_flags;
2361 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2362 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2363 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2364 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2365 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2366 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2367 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2368 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2372 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2373 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2374 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2375 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2377 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2378 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2379 #elif defined(__LITTLE_ENDIAN)
2380         u16 config_flags;
2381 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2382 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2383 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2384 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2385 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2386 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2387 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2388 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2389 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2390 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2391 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2392 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2393 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2394 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2395 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2396 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2397 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x3F<<10)
2398 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 10
2399         u8 rss_result_mask;
2400         u8 leading_client_id;
2401 #endif
2402         u16 vlan_id[2];
2403 };
2404
2405 /*
2406  * parameters for eth update ramrod
2407  */
2408 struct eth_update_ramrod_data {
2409         struct tstorm_eth_function_common_config func_config;
2410         u8 indirectionTable[128];
2411 };
2412
2413
2414 /*
2415  * MAC filtering configuration command header
2416  */
2417 struct mac_configuration_hdr {
2418         u8 length;
2419         u8 offset;
2420         u16 client_id;
2421         u32 reserved1;
2422 };
2423
2424 /*
2425  * MAC address in list for ramrod
2426  */
2427 struct tstorm_cam_entry {
2428         u16 lsb_mac_addr;
2429         u16 middle_mac_addr;
2430         u16 msb_mac_addr;
2431         u16 flags;
2432 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2433 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2434 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2435 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2436 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2437 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2438 };
2439
2440 /*
2441  * MAC filtering: CAM target table entry
2442  */
2443 struct tstorm_cam_target_table_entry {
2444         u8 flags;
2445 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2446 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2447 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2448 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2449 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2450 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2451 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2452 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2453 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2454 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2455         u8 client_id;
2456         u16 vlan_id;
2457 };
2458
2459 /*
2460  * MAC address in list for ramrod
2461  */
2462 struct mac_configuration_entry {
2463         struct tstorm_cam_entry cam_entry;
2464         struct tstorm_cam_target_table_entry target_table_entry;
2465 };
2466
2467 /*
2468  * MAC filtering configuration command
2469  */
2470 struct mac_configuration_cmd {
2471         struct mac_configuration_hdr hdr;
2472         struct mac_configuration_entry config_table[64];
2473 };
2474
2475
2476 /*
2477  * MAC address in list for ramrod
2478  */
2479 struct mac_configuration_entry_e1h {
2480         u16 lsb_mac_addr;
2481         u16 middle_mac_addr;
2482         u16 msb_mac_addr;
2483         u16 vlan_id;
2484         u16 e1hov_id;
2485         u8 client_id;
2486         u8 flags;
2487 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2488 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2489 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2490 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2491 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2492 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2493 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2494 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2495 };
2496
2497 /*
2498  * MAC filtering configuration command
2499  */
2500 struct mac_configuration_cmd_e1h {
2501         struct mac_configuration_hdr hdr;
2502         struct mac_configuration_entry_e1h config_table[32];
2503 };
2504
2505
2506 /*
2507  * approximate-match multicast filtering for E1H per function in Tstorm
2508  */
2509 struct tstorm_eth_approximate_match_multicast_filtering {
2510         u32 mcast_add_hash_bit_array[8];
2511 };
2512
2513
2514 /*
2515  * Configuration parameters per client in Tstorm
2516  */
2517 struct tstorm_eth_client_config {
2518 #if defined(__BIG_ENDIAN)
2519         u8 max_sges_for_packet;
2520         u8 statistics_counter_id;
2521         u16 mtu;
2522 #elif defined(__LITTLE_ENDIAN)
2523         u16 mtu;
2524         u8 statistics_counter_id;
2525         u8 max_sges_for_packet;
2526 #endif
2527 #if defined(__BIG_ENDIAN)
2528         u16 drop_flags;
2529 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2530 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2531 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2532 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2533 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2534 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2535 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2536 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2537 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2538 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2539         u16 config_flags;
2540 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2541 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2542 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2543 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2544 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2545 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2546 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2547 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2548 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2549 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2550 #elif defined(__LITTLE_ENDIAN)
2551         u16 config_flags;
2552 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2553 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2554 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2555 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2556 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2557 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2558 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<3)
2559 #define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 3
2560 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0xFFF<<4)
2561 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 4
2562         u16 drop_flags;
2563 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2564 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2565 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2566 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2567 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2568 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2569 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2570 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2571 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2572 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
2573 #endif
2574 };
2575
2576
2577 /*
2578  * MAC filtering configuration parameters per port in Tstorm
2579  */
2580 struct tstorm_eth_mac_filter_config {
2581         u32 ucast_drop_all;
2582         u32 ucast_accept_all;
2583         u32 mcast_drop_all;
2584         u32 mcast_accept_all;
2585         u32 bcast_drop_all;
2586         u32 bcast_accept_all;
2587         u32 strict_vlan;
2588         u32 vlan_filter[2];
2589         u32 reserved;
2590 };
2591
2592
2593 /*
2594  * common flag to indicate existance of TPA.
2595  */
2596 struct tstorm_eth_tpa_exist {
2597 #if defined(__BIG_ENDIAN)
2598         u16 reserved1;
2599         u8 reserved0;
2600         u8 tpa_exist;
2601 #elif defined(__LITTLE_ENDIAN)
2602         u8 tpa_exist;
2603         u8 reserved0;
2604         u16 reserved1;
2605 #endif
2606         u32 reserved2;
2607 };
2608
2609
2610 /*
2611  * rx rings pause data for E1h only
2612  */
2613 struct ustorm_eth_rx_pause_data_e1h {
2614 #if defined(__BIG_ENDIAN)
2615         u16 bd_thr_low;
2616         u16 cqe_thr_low;
2617 #elif defined(__LITTLE_ENDIAN)
2618         u16 cqe_thr_low;
2619         u16 bd_thr_low;
2620 #endif
2621 #if defined(__BIG_ENDIAN)
2622         u16 cos;
2623         u16 sge_thr_low;
2624 #elif defined(__LITTLE_ENDIAN)
2625         u16 sge_thr_low;
2626         u16 cos;
2627 #endif
2628 #if defined(__BIG_ENDIAN)
2629         u16 bd_thr_high;
2630         u16 cqe_thr_high;
2631 #elif defined(__LITTLE_ENDIAN)
2632         u16 cqe_thr_high;
2633         u16 bd_thr_high;
2634 #endif
2635 #if defined(__BIG_ENDIAN)
2636         u16 reserved0;
2637         u16 sge_thr_high;
2638 #elif defined(__LITTLE_ENDIAN)
2639         u16 sge_thr_high;
2640         u16 reserved0;
2641 #endif
2642 };
2643
2644
2645 /*
2646  * Three RX producers for ETH
2647  */
2648 struct ustorm_eth_rx_producers {
2649 #if defined(__BIG_ENDIAN)
2650         u16 bd_prod;
2651         u16 cqe_prod;
2652 #elif defined(__LITTLE_ENDIAN)
2653         u16 cqe_prod;
2654         u16 bd_prod;
2655 #endif
2656 #if defined(__BIG_ENDIAN)
2657         u16 reserved;
2658         u16 sge_prod;
2659 #elif defined(__LITTLE_ENDIAN)
2660         u16 sge_prod;
2661         u16 reserved;
2662 #endif
2663 };
2664
2665
2666 /*
2667  * per-port SAFC demo variables
2668  */
2669 struct cmng_flags_per_port {
2670         u8 con_number[NUM_OF_PROTOCOLS];
2671         u32 cmng_enables;
2672 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2673 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2674 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2675 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2676 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2677 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2678 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2679 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2680 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2681 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2682 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2683 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2684 };
2685
2686
2687 /*
2688  * per-port rate shaping variables
2689  */
2690 struct rate_shaping_vars_per_port {
2691         u32 rs_periodic_timeout;
2692         u32 rs_threshold;
2693 };
2694
2695
2696 /*
2697  * per-port fairness variables
2698  */
2699 struct fairness_vars_per_port {
2700         u32 upper_bound;
2701         u32 fair_threshold;
2702         u32 fairness_timeout;
2703 };
2704
2705
2706 /*
2707  * per-port SAFC variables
2708  */
2709 struct safc_struct_per_port {
2710 #if defined(__BIG_ENDIAN)
2711         u16 __reserved1;
2712         u8 __reserved0;
2713         u8 safc_timeout_usec;
2714 #elif defined(__LITTLE_ENDIAN)
2715         u8 safc_timeout_usec;
2716         u8 __reserved0;
2717         u16 __reserved1;
2718 #endif
2719         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2720 };
2721
2722
2723 /*
2724  * Per-port congestion management variables
2725  */
2726 struct cmng_struct_per_port {
2727         struct rate_shaping_vars_per_port rs_vars;
2728         struct fairness_vars_per_port fair_vars;
2729         struct safc_struct_per_port safc_vars;
2730         struct cmng_flags_per_port flags;
2731 };
2732
2733
2734 /*
2735  * Protocol-common statistics collected by the Xstorm (per client)
2736  */
2737 struct xstorm_per_client_stats {
2738         struct regpair total_sent_bytes;
2739         u32 total_sent_pkts;
2740         u32 unicast_pkts_sent;
2741         struct regpair unicast_bytes_sent;
2742         struct regpair multicast_bytes_sent;
2743         u32 multicast_pkts_sent;
2744         u32 broadcast_pkts_sent;
2745         struct regpair broadcast_bytes_sent;
2746         u16 stats_counter;
2747         u16 reserved0;
2748         u32 reserved1;
2749 };
2750
2751
2752 /*
2753  * Common statistics collected by the Xstorm (per port)
2754  */
2755 struct xstorm_common_stats {
2756  struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2757 };
2758
2759
2760 /*
2761  * Protocol-common statistics collected by the Tstorm (per port)
2762  */
2763 struct tstorm_per_port_stats {
2764         u32 mac_filter_discard;
2765         u32 xxoverflow_discard;
2766         u32 brb_truncate_discard;
2767         u32 mac_discard;
2768 };
2769
2770
2771 /*
2772  * Protocol-common statistics collected by the Tstorm (per client)
2773  */
2774 struct tstorm_per_client_stats {
2775         struct regpair total_rcv_bytes;
2776         struct regpair rcv_unicast_bytes;
2777         struct regpair rcv_broadcast_bytes;
2778         struct regpair rcv_multicast_bytes;
2779         struct regpair rcv_error_bytes;
2780         u32 checksum_discard;
2781         u32 packets_too_big_discard;
2782         u32 total_rcv_pkts;
2783         u32 rcv_unicast_pkts;
2784         u32 rcv_broadcast_pkts;
2785         u32 rcv_multicast_pkts;
2786         u32 no_buff_discard;
2787         u32 ttl0_discard;
2788         u16 stats_counter;
2789         u16 reserved0;
2790         u32 reserved1;
2791 };
2792
2793 /*
2794  * Protocol-common statistics collected by the Tstorm
2795  */
2796 struct tstorm_common_stats {
2797         struct tstorm_per_port_stats port_statistics;
2798  struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2799 };
2800
2801 /*
2802  * Protocol-common statistics collected by the Ustorm (per client)
2803  */
2804 struct ustorm_per_client_stats {
2805         struct regpair ucast_no_buff_bytes;
2806         struct regpair mcast_no_buff_bytes;
2807         struct regpair bcast_no_buff_bytes;
2808         __le32 ucast_no_buff_pkts;
2809         __le32 mcast_no_buff_pkts;
2810         __le32 bcast_no_buff_pkts;
2811         __le16 stats_counter;
2812         __le16 reserved0;
2813 };
2814
2815 /*
2816  * Protocol-common statistics collected by the Ustorm
2817  */
2818 struct ustorm_common_stats {
2819  struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
2820 };
2821
2822 /*
2823  * Eth statistics query structure for the eth_stats_query ramrod
2824  */
2825 struct eth_stats_query {
2826         struct xstorm_common_stats xstorm_common;
2827         struct tstorm_common_stats tstorm_common;
2828         struct ustorm_common_stats ustorm_common;
2829 };
2830
2831
2832 /*
2833  * per-vnic fairness variables
2834  */
2835 struct fairness_vars_per_vn {
2836         u32 cos_credit_delta[MAX_COS_NUMBER];
2837         u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2838         u32 vn_credit_delta;
2839         u32 __reserved0;
2840 };
2841
2842
2843 /*
2844  * FW version stored in the Xstorm RAM
2845  */
2846 struct fw_version {
2847 #if defined(__BIG_ENDIAN)
2848         u8 engineering;
2849         u8 revision;
2850         u8 minor;
2851         u8 major;
2852 #elif defined(__LITTLE_ENDIAN)
2853         u8 major;
2854         u8 minor;
2855         u8 revision;
2856         u8 engineering;
2857 #endif
2858         u32 flags;
2859 #define FW_VERSION_OPTIMIZED (0x1<<0)
2860 #define FW_VERSION_OPTIMIZED_SHIFT 0
2861 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
2862 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
2863 #define FW_VERSION_CHIP_VERSION (0x3<<2)
2864 #define FW_VERSION_CHIP_VERSION_SHIFT 2
2865 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2866 #define __FW_VERSION_RESERVED_SHIFT 4
2867 };
2868
2869
2870 /*
2871  * FW version stored in first line of pram
2872  */
2873 struct pram_fw_version {
2874         u8 major;
2875         u8 minor;
2876         u8 revision;
2877         u8 engineering;
2878         u8 flags;
2879 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2880 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2881 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2882 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2883 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2884 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
2885 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2886 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2887 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2888 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2889 };
2890
2891
2892 /*
2893  * a single rate shaping counter. can be used as protocol or vnic counter
2894  */
2895 struct rate_shaping_counter {
2896         u32 quota;
2897 #if defined(__BIG_ENDIAN)
2898         u16 __reserved0;
2899         u16 rate;
2900 #elif defined(__LITTLE_ENDIAN)
2901         u16 rate;
2902         u16 __reserved0;
2903 #endif
2904 };
2905
2906
2907 /*
2908  * per-vnic rate shaping variables
2909  */
2910 struct rate_shaping_vars_per_vn {
2911         struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2912         struct rate_shaping_counter vn_counter;
2913 };
2914
2915
2916 /*
2917  * The send queue element
2918  */
2919 struct slow_path_element {
2920         struct spe_hdr hdr;
2921         u8 protocol_data[8];
2922 };
2923
2924
2925 /*
2926  * eth/toe flags that indicate if to query
2927  */
2928 struct stats_indication_flags {
2929         u32 collect_eth;
2930         u32 collect_toe;
2931 };
2932
2933