1 /*****************************************************************************
5 * $Date: 2005/03/23 07:15:59 $ *
7 * part of the Chelsio 10Gb Ethernet Driver. *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * http://www.chelsio.com *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
26 * Maintainers: maintainers@chelsio.com *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
37 ****************************************************************************/
39 /* Do not edit this file */
42 #define A_SG_CONTROL 0x0
44 #define S_CMDQ0_ENABLE 0
45 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
46 #define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)
48 #define S_CMDQ1_ENABLE 1
49 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
50 #define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)
52 #define S_FL0_ENABLE 2
53 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
54 #define F_FL0_ENABLE V_FL0_ENABLE(1U)
56 #define S_FL1_ENABLE 3
57 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
58 #define F_FL1_ENABLE V_FL1_ENABLE(1U)
60 #define S_CPL_ENABLE 4
61 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
62 #define F_CPL_ENABLE V_CPL_ENABLE(1U)
64 #define S_RESPONSE_QUEUE_ENABLE 5
65 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
66 #define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)
68 #define S_CMDQ_PRIORITY 6
69 #define M_CMDQ_PRIORITY 0x3
70 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
71 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
73 #define S_DISABLE_CMDQ1_GTS 9
74 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
75 #define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
77 #define S_ENABLE_BIG_ENDIAN 12
78 #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
79 #define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
81 #define S_ISCSI_COALESCE 14
82 #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
83 #define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
85 #define S_RX_PKT_OFFSET 15
86 #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
88 #define S_VLAN_XTRACT 18
89 #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
90 #define F_VLAN_XTRACT V_VLAN_XTRACT(1U)
92 #define A_SG_DOORBELL 0x4
93 #define A_SG_CMD0BASELWR 0x8
94 #define A_SG_CMD0BASEUPR 0xc
95 #define A_SG_CMD1BASELWR 0x10
96 #define A_SG_CMD1BASEUPR 0x14
97 #define A_SG_FL0BASELWR 0x18
98 #define A_SG_FL0BASEUPR 0x1c
99 #define A_SG_FL1BASELWR 0x20
100 #define A_SG_FL1BASEUPR 0x24
101 #define A_SG_CMD0SIZE 0x28
102 #define A_SG_FL0SIZE 0x2c
103 #define A_SG_RSPSIZE 0x30
104 #define A_SG_RSPBASELWR 0x34
105 #define A_SG_RSPBASEUPR 0x38
106 #define A_SG_FLTHRESHOLD 0x3c
107 #define A_SG_RSPQUEUECREDIT 0x40
108 #define A_SG_SLEEPING 0x48
109 #define A_SG_INTRTIMER 0x4c
110 #define A_SG_CMD1SIZE 0xb0
111 #define A_SG_FL1SIZE 0xb4
112 #define A_SG_INT_ENABLE 0xb8
114 #define S_RESPQ_EXHAUSTED 0
115 #define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
116 #define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)
118 #define S_RESPQ_OVERFLOW 1
119 #define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
120 #define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)
122 #define S_FL_EXHAUSTED 2
123 #define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
124 #define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)
126 #define S_PACKET_TOO_BIG 3
127 #define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
128 #define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)
130 #define S_PACKET_MISMATCH 4
131 #define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
132 #define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)
134 #define A_SG_INT_CAUSE 0xbc
139 #define V_READY(x) ((x) << S_READY)
140 #define F_READY V_READY(1U)
144 #define A_MC4_CFG 0x180
145 #define S_MC4_SLOW 25
146 #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
147 #define F_MC4_SLOW V_MC4_SLOW(1U)
151 #define A_TPI_ADDR 0x280
152 #define A_TPI_WR_DATA 0x284
153 #define A_TPI_RD_DATA 0x288
154 #define A_TPI_CSR 0x28c
157 #define V_TPIWR(x) ((x) << S_TPIWR)
158 #define F_TPIWR V_TPIWR(1U)
161 #define V_TPIRDY(x) ((x) << S_TPIRDY)
162 #define F_TPIRDY V_TPIRDY(1U)
164 #define A_TPI_PAR 0x29c
167 #define M_TPIPAR 0x7f
168 #define V_TPIPAR(x) ((x) << S_TPIPAR)
169 #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
173 #define A_TP_IN_CONFIG 0x300
175 #define S_TP_IN_CSPI_CPL 3
176 #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
177 #define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
179 #define S_TP_IN_CSPI_CHECK_IP_CSUM 5
180 #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
181 #define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
183 #define S_TP_IN_CSPI_CHECK_TCP_CSUM 6
184 #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
185 #define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
187 #define S_TP_IN_ESPI_ETHERNET 8
188 #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
189 #define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
191 #define S_TP_IN_ESPI_CHECK_IP_CSUM 12
192 #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
193 #define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
195 #define S_TP_IN_ESPI_CHECK_TCP_CSUM 13
196 #define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
197 #define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
199 #define S_OFFLOAD_DISABLE 14
200 #define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
201 #define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)
203 #define A_TP_OUT_CONFIG 0x304
205 #define S_TP_OUT_CSPI_CPL 2
206 #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
207 #define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
209 #define S_TP_OUT_ESPI_ETHERNET 6
210 #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
211 #define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
213 #define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
214 #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
215 #define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
217 #define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11
218 #define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
219 #define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
221 #define A_TP_GLOBAL_CONFIG 0x308
224 #define M_IP_TTL 0xff
225 #define V_IP_TTL(x) ((x) << S_IP_TTL)
227 #define S_TCP_CSUM 11
228 #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
229 #define F_TCP_CSUM V_TCP_CSUM(1U)
231 #define S_UDP_CSUM 12
232 #define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
233 #define F_UDP_CSUM V_UDP_CSUM(1U)
236 #define V_IP_CSUM(x) ((x) << S_IP_CSUM)
237 #define F_IP_CSUM V_IP_CSUM(1U)
239 #define S_PATH_MTU 15
240 #define V_PATH_MTU(x) ((x) << S_PATH_MTU)
241 #define F_PATH_MTU V_PATH_MTU(1U)
243 #define S_5TUPLE_LOOKUP 17
244 #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
246 #define S_SYN_COOKIE_PARAMETER 26
247 #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
249 #define A_TP_PC_CONFIG 0x348
250 #define S_TP_PC_REV 30
251 #define M_TP_PC_REV 0x3
252 #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
253 #define A_TP_RESET 0x44c
255 #define V_TP_RESET(x) ((x) << S_TP_RESET)
256 #define F_TP_RESET V_TP_RESET(1U)
258 #define A_TP_INT_ENABLE 0x470
259 #define A_TP_INT_CAUSE 0x474
260 #define A_TP_TX_DROP_CONFIG 0x4b8
262 #define S_ENABLE_TX_DROP 31
263 #define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
264 #define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U)
266 #define S_ENABLE_TX_ERROR 30
267 #define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
268 #define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
270 #define S_DROP_TICKS_CNT 4
271 #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
273 #define S_NUM_PKTS_DROPPED 0
274 #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
279 #define V_DIP4ERR(x) ((x) << S_DIP4ERR)
280 #define F_DIP4ERR V_DIP4ERR(1U)
283 #define V_RXDROP(x) ((x) << S_RXDROP)
284 #define F_RXDROP V_RXDROP(1U)
287 #define V_TXDROP(x) ((x) << S_TXDROP)
288 #define F_TXDROP V_TXDROP(1U)
290 #define S_RXOVERFLOW 3
291 #define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
292 #define F_RXOVERFLOW V_RXOVERFLOW(1U)
294 #define S_RAMPARITYERR 4
295 #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
296 #define F_RAMPARITYERR V_RAMPARITYERR(1U)
300 #define A_ESPI_SCH_TOKEN0 0x880
301 #define A_ESPI_SCH_TOKEN1 0x884
302 #define A_ESPI_SCH_TOKEN2 0x888
303 #define A_ESPI_SCH_TOKEN3 0x88c
304 #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
305 #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
306 #define A_ESPI_CALENDAR_LENGTH 0x898
307 #define A_PORT_CONFIG 0x89c
309 #define S_RX_NPORTS 0
310 #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
312 #define S_TX_NPORTS 8
313 #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
315 #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
317 #define S_RXSTATUSENABLE 0
318 #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
319 #define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
321 #define S_INTEL1010MODE 4
322 #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
323 #define F_INTEL1010MODE V_INTEL1010MODE(1U)
325 #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
326 #define A_ESPI_TRAIN 0x8ac
327 #define A_ESPI_INTR_STATUS 0x8c8
329 #define S_DIP2PARITYERR 5
330 #define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
331 #define F_DIP2PARITYERR V_DIP2PARITYERR(1U)
333 #define A_ESPI_INTR_ENABLE 0x8cc
334 #define A_RX_DROP_THRESHOLD 0x8d0
335 #define A_ESPI_RX_RESET 0x8ec
336 #define A_ESPI_MISC_CONTROL 0x8f0
338 #define S_OUT_OF_SYNC_COUNT 0
339 #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
341 #define S_DIP2_PARITY_ERR_THRES 5
342 #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
344 #define S_DIP4_THRES 9
345 #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
347 #define S_MONITORED_PORT_NUM 25
348 #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
350 #define S_MONITORED_DIRECTION 27
351 #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
352 #define F_MONITORED_DIRECTION V_MONITORED_DIRECTION(1U)
354 #define S_MONITORED_INTERFACE 28
355 #define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
356 #define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U)
358 #define A_ESPI_DIP2_ERR_COUNT 0x8f4
359 #define A_ESPI_CMD_ADDR 0x8f8
361 #define S_WRITE_DATA 0
362 #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
364 #define S_REGISTER_OFFSET 8
365 #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
367 #define S_CHANNEL_ADDR 12
368 #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
370 #define S_MODULE_ADDR 16
371 #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
373 #define S_BUNDLE_ADDR 20
374 #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
376 #define S_SPI4_COMMAND 24
377 #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
379 #define A_ESPI_GOSTAT 0x8fc
380 #define S_ESPI_CMD_BUSY 8
381 #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
382 #define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U)
386 #define A_PL_ENABLE 0xa00
388 #define S_PL_INTR_SGE_ERR 0
389 #define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
390 #define F_PL_INTR_SGE_ERR V_PL_INTR_SGE_ERR(1U)
392 #define S_PL_INTR_SGE_DATA 1
393 #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
394 #define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U)
396 #define S_PL_INTR_TP 6
397 #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
398 #define F_PL_INTR_TP V_PL_INTR_TP(1U)
400 #define S_PL_INTR_ESPI 8
401 #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
402 #define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U)
404 #define S_PL_INTR_PCIX 10
405 #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
406 #define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U)
408 #define S_PL_INTR_EXT 11
409 #define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
410 #define F_PL_INTR_EXT V_PL_INTR_EXT(1U)
412 #define A_PL_CAUSE 0xa04
416 #define A_MC5_CONFIG 0xc04
418 #define S_TCAM_RESET 1
419 #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
420 #define F_TCAM_RESET V_TCAM_RESET(1U)
422 #define S_M_BUS_ENABLE 5
423 #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
424 #define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U)
426 /* PCICFG registers */
428 #define A_PCICFG_PM_CSR 0x44
429 #define A_PCICFG_VPD_ADDR 0x4a
431 #define S_VPD_OP_FLAG 15
432 #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
433 #define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U)
435 #define A_PCICFG_VPD_DATA 0x4c
437 #define A_PCICFG_INTR_ENABLE 0xf4
438 #define A_PCICFG_INTR_CAUSE 0xf8
440 #define A_PCICFG_MODE 0xfc
442 #define S_PCI_MODE_64BIT 0
443 #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
444 #define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U)
446 #define S_PCI_MODE_PCIX 5
447 #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
448 #define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U)
450 #define S_PCI_MODE_CLK 6
451 #define M_PCI_MODE_CLK 0x3
452 #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)