drivers/net/cpmac.c

   1 /*
   2  * Copyright (C) 2006, 2007 Eugene Konev
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/moduleparam.h>
  22
  23 #include <linux/sched.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/errno.h>
  27 #include <linux/types.h>
  28 #include <linux/delay.h>
  29 #include <linux/version.h>
  30
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/dma-mapping.h>
  39 #include <asm/gpio.h>
  40
  41 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
  42 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  43 MODULE_LICENSE("GPL");
  44
  45 static int debug_level = 8;
  46 static int dumb_switch;
  47
  48 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
  49 module_param(debug_level, int, 0444);
  50 module_param(dumb_switch, int, 0444);
  51
  52 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  53 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
  54
  55 #define CPMAC_VERSION "0.5.0"
  56 /* frame size + 802.1q tag */
  57 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + 4)
  58 #define CPMAC_QUEUES    8
  59
  60 /* Ethernet registers */
  61 #define CPMAC_TX_CONTROL                0x0004
  62 #define CPMAC_TX_TEARDOWN               0x0008
  63 #define CPMAC_RX_CONTROL                0x0014
  64 #define CPMAC_RX_TEARDOWN               0x0018
  65 #define CPMAC_MBP                       0x0100
  66 # define MBP_RXPASSCRC                  0x40000000
  67 # define MBP_RXQOS                      0x20000000
  68 # define MBP_RXNOCHAIN                  0x10000000
  69 # define MBP_RXCMF                      0x01000000
  70 # define MBP_RXSHORT                    0x00800000
  71 # define MBP_RXCEF                      0x00400000
  72 # define MBP_RXPROMISC                  0x00200000
  73 # define MBP_PROMISCCHAN(channel)       (((channel) & 0x7) << 16)
  74 # define MBP_RXBCAST                    0x00002000
  75 # define MBP_BCASTCHAN(channel)         (((channel) & 0x7) << 8)
  76 # define MBP_RXMCAST                    0x00000020
  77 # define MBP_MCASTCHAN(channel)         ((channel) & 0x7)
  78 #define CPMAC_UNICAST_ENABLE            0x0104
  79 #define CPMAC_UNICAST_CLEAR             0x0108
  80 #define CPMAC_MAX_LENGTH                0x010c
  81 #define CPMAC_BUFFER_OFFSET             0x0110
  82 #define CPMAC_MAC_CONTROL               0x0160
  83 # define MAC_TXPTYPE                    0x00000200
  84 # define MAC_TXPACE                     0x00000040
  85 # define MAC_MII                        0x00000020
  86 # define MAC_TXFLOW                     0x00000010
  87 # define MAC_RXFLOW                     0x00000008
  88 # define MAC_MTEST                      0x00000004
  89 # define MAC_LOOPBACK                   0x00000002
  90 # define MAC_FDX                        0x00000001
  91 #define CPMAC_MAC_STATUS                0x0164
  92 # define MAC_STATUS_QOS                 0x00000004
  93 # define MAC_STATUS_RXFLOW              0x00000002
  94 # define MAC_STATUS_TXFLOW              0x00000001
  95 #define CPMAC_TX_INT_ENABLE             0x0178
  96 #define CPMAC_TX_INT_CLEAR              0x017c
  97 #define CPMAC_MAC_INT_VECTOR            0x0180
  98 # define MAC_INT_STATUS                 0x00080000
  99 # define MAC_INT_HOST                   0x00040000
 100 # define MAC_INT_RX                     0x00020000
 101 # define MAC_INT_TX                     0x00010000
 102 #define CPMAC_MAC_EOI_VECTOR            0x0184
 103 #define CPMAC_RX_INT_ENABLE             0x0198
 104 #define CPMAC_RX_INT_CLEAR              0x019c
 105 #define CPMAC_MAC_INT_ENABLE            0x01a8
 106 #define CPMAC_MAC_INT_CLEAR             0x01ac
 107 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
 108 #define CPMAC_MAC_ADDR_MID              0x01d0
 109 #define CPMAC_MAC_ADDR_HI               0x01d4
 110 #define CPMAC_MAC_HASH_LO               0x01d8
 111 #define CPMAC_MAC_HASH_HI               0x01dc
 112 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
 113 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
 114 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
 115 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
 116 #define CPMAC_REG_END                   0x0680
 117 /*
 118  * Rx/Tx statistics
 119  * TODO: use some of them to fill stats in cpmac_stats()
 120  */
 121 #define CPMAC_STATS_RX_GOOD             0x0200
 122 #define CPMAC_STATS_RX_BCAST            0x0204
 123 #define CPMAC_STATS_RX_MCAST            0x0208
 124 #define CPMAC_STATS_RX_PAUSE            0x020c
 125 #define CPMAC_STATS_RX_CRC              0x0210
 126 #define CPMAC_STATS_RX_ALIGN            0x0214
 127 #define CPMAC_STATS_RX_OVER             0x0218
 128 #define CPMAC_STATS_RX_JABBER           0x021c
 129 #define CPMAC_STATS_RX_UNDER            0x0220
 130 #define CPMAC_STATS_RX_FRAG             0x0224
 131 #define CPMAC_STATS_RX_FILTER           0x0228
 132 #define CPMAC_STATS_RX_QOSFILTER        0x022c
 133 #define CPMAC_STATS_RX_OCTETS           0x0230
 134
 135 #define CPMAC_STATS_TX_GOOD             0x0234
 136 #define CPMAC_STATS_TX_BCAST            0x0238
 137 #define CPMAC_STATS_TX_MCAST            0x023c
 138 #define CPMAC_STATS_TX_PAUSE            0x0240
 139 #define CPMAC_STATS_TX_DEFER            0x0244
 140 #define CPMAC_STATS_TX_COLLISION        0x0248
 141 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
 142 #define CPMAC_STATS_TX_MULTICOLL        0x0250
 143 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
 144 #define CPMAC_STATS_TX_LATECOLL         0x0258
 145 #define CPMAC_STATS_TX_UNDERRUN         0x025c
 146 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
 147 #define CPMAC_STATS_TX_OCTETS           0x0264
 148
 149 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
 150 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
 151                                                 (reg)))
 152
 153 /* MDIO bus */
 154 #define CPMAC_MDIO_VERSION              0x0000
 155 #define CPMAC_MDIO_CONTROL              0x0004
 156 # define MDIOC_IDLE                     0x80000000
 157 # define MDIOC_ENABLE                   0x40000000
 158 # define MDIOC_PREAMBLE                 0x00100000
 159 # define MDIOC_FAULT                    0x00080000
 160 # define MDIOC_FAULTDETECT              0x00040000
 161 # define MDIOC_INTTEST                  0x00020000
 162 # define MDIOC_CLKDIV(div)              ((div) & 0xff)
 163 #define CPMAC_MDIO_ALIVE                0x0008
 164 #define CPMAC_MDIO_LINK                 0x000c
 165 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
 166 # define MDIO_BUSY                      0x80000000
 167 # define MDIO_WRITE                     0x40000000
 168 # define MDIO_REG(reg)                  (((reg) & 0x1f) << 21)
 169 # define MDIO_PHY(phy)                  (((phy) & 0x1f) << 16)
 170 # define MDIO_DATA(data)                ((data) & 0xffff)
 171 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
 172 # define PHYSEL_LINKSEL                 0x00000040
 173 # define PHYSEL_LINKINT                 0x00000020
 174
 175 struct cpmac_desc {
 176         u32 hw_next;
 177         u32 hw_data;
 178         u16 buflen;
 179         u16 bufflags;
 180         u16 datalen;
 181         u16 dataflags;
 182 #define CPMAC_SOP                       0x8000
 183 #define CPMAC_EOP                       0x4000
 184 #define CPMAC_OWN                       0x2000
 185 #define CPMAC_EOQ                       0x1000
 186         struct sk_buff *skb;
 187         struct cpmac_desc *next;
 188         dma_addr_t mapping;
 189         dma_addr_t data_mapping;
 190 };
 191
 192 struct cpmac_priv {
 193         spinlock_t lock;
 194         spinlock_t rx_lock;
 195         struct cpmac_desc *rx_head;
 196         int ring_size;
 197         struct cpmac_desc *desc_ring;
 198         dma_addr_t dma_ring;
 199         void __iomem *regs;
 200         struct mii_bus *mii_bus;
 201         struct phy_device *phy;
 202         char phy_name[BUS_ID_SIZE];
 203         int oldlink, oldspeed, oldduplex;
 204         u32 msg_enable;
 205         struct net_device *dev;
 206         struct work_struct reset_work;
 207         struct platform_device *pdev;
 208         struct napi_struct napi;
 209 };
 210
 211 static irqreturn_t cpmac_irq(int, void *);
 212 static void cpmac_hw_start(struct net_device *dev);
 213 static void cpmac_hw_stop(struct net_device *dev);
 214 static int cpmac_stop(struct net_device *dev);
 215 static int cpmac_open(struct net_device *dev);
 216
 217 static void cpmac_dump_regs(struct net_device *dev)
 218 {
 219         int i;
 220         struct cpmac_priv *priv = netdev_priv(dev);
 221         for (i = 0; i < CPMAC_REG_END; i += 4) {
 222                 if (i % 16 == 0) {
 223                         if (i)
 224                                 printk("\n");
 225                         printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
 226                                priv->regs + i);
 227                 }
 228                 printk(" %08x", cpmac_read(priv->regs, i));
 229         }
 230         printk("\n");
 231 }
 232
 233 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
 234 {
 235         int i;
 236         printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
 237         for (i = 0; i < sizeof(*desc) / 4; i++)
 238                 printk(" %08x", ((u32 *)desc)[i]);
 239         printk("\n");
 240 }
 241
 242 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
 243 {
 244         int i;
 245         printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
 246         for (i = 0; i < skb->len; i++) {
 247                 if (i % 16 == 0) {
 248                         if (i)
 249                                 printk("\n");
 250                         printk(KERN_DEBUG "%s: data[%p]:", dev->name,
 251                                skb->data + i);
 252                 }
 253                 printk(" %02x", ((u8 *)skb->data)[i]);
 254         }
 255         printk("\n");
 256 }
 257
 258 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 259 {
 260         u32 val;
 261
 262         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 263                 cpu_relax();
 264         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
 265                     MDIO_PHY(phy_id));
 266         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
 267                 cpu_relax();
 268         return MDIO_DATA(val);
 269 }
 270
 271 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
 272                             int reg, u16 val)
 273 {
 274         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 275                 cpu_relax();
 276         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
 277                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
 278         return 0;
 279 }
 280
 281 static int cpmac_mdio_reset(struct mii_bus *bus)
 282 {
 283         ar7_device_reset(AR7_RESET_BIT_MDIO);
 284         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
 285                     MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
 286         return 0;
 287 }
 288
 289 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
 290
 291 static struct mii_bus cpmac_mii = {
 292         .name = "cpmac-mii",
 293         .read = cpmac_mdio_read,
 294         .write = cpmac_mdio_write,
 295         .reset = cpmac_mdio_reset,
 296         .irq = mii_irqs,
 297 };
 298
 299 static int cpmac_config(struct net_device *dev, struct ifmap *map)
 300 {
 301         if (dev->flags & IFF_UP)
 302                 return -EBUSY;
 303
 304         /* Don't allow changing the I/O address */
 305         if (map->base_addr != dev->base_addr)
 306                 return -EOPNOTSUPP;
 307
 308         /* ignore other fields */
 309         return 0;
 310 }
 311
 312 static void cpmac_set_multicast_list(struct net_device *dev)
 313 {
 314         struct dev_mc_list *iter;
 315         int i;
 316         u8 tmp;
 317         u32 mbp, bit, hash[2] = { 0, };
 318         struct cpmac_priv *priv = netdev_priv(dev);
 319
 320         mbp = cpmac_read(priv->regs, CPMAC_MBP);
 321         if (dev->flags & IFF_PROMISC) {
 322                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
 323                             MBP_RXPROMISC);
 324         } else {
 325                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
 326                 if (dev->flags & IFF_ALLMULTI) {
 327                         /* enable all multicast mode */
 328                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
 329                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
 330                 } else {
 331                         /*
 332                          * cpmac uses some strange mac address hashing
 333                          * (not crc32)
 334                          */
 335                         for (i = 0, iter = dev->mc_list; i < dev->mc_count;
 336                              i++, iter = iter->next) {
 337                                 bit = 0;
 338                                 tmp = iter->dmi_addr[0];
 339                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 340                                 tmp = iter->dmi_addr[1];
 341                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 342                                 tmp = iter->dmi_addr[2];
 343                                 bit  ^= (tmp >> 6) ^ tmp;
 344                                 tmp = iter->dmi_addr[3];
 345                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 346                                 tmp = iter->dmi_addr[4];
 347                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 348                                 tmp = iter->dmi_addr[5];
 349                                 bit  ^= (tmp >> 6) ^ tmp;
 350                                 bit &= 0x3f;
 351                                 hash[bit / 32] |= 1 << (bit % 32);
 352                         }
 353
 354                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
 355                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
 356                 }
 357         }
 358 }
 359
 360 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
 361                                     struct cpmac_desc *desc)
 362 {
 363         struct sk_buff *skb, *result = NULL;
 364
 365         if (unlikely(netif_msg_hw(priv)))
 366                 cpmac_dump_desc(priv->dev, desc);
 367         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
 368         if (unlikely(!desc->datalen)) {
 369                 if (netif_msg_rx_err(priv) && net_ratelimit())
 370                         printk(KERN_WARNING "%s: rx: spurious interrupt\n",
 371                                priv->dev->name);
 372                 return NULL;
 373         }
 374
 375         skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
 376         if (likely(skb)) {
 377                 skb_reserve(skb, 2);
 378                 skb_put(desc->skb, desc->datalen);
 379                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
 380                 desc->skb->ip_summed = CHECKSUM_NONE;
 381                 priv->dev->stats.rx_packets++;
 382                 priv->dev->stats.rx_bytes += desc->datalen;
 383                 result = desc->skb;
 384                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
 385                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
 386                 desc->skb = skb;
 387                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
 388                                                     CPMAC_SKB_SIZE,
 389                                                     DMA_FROM_DEVICE);
 390                 desc->hw_data = (u32)desc->data_mapping;
 391                 if (unlikely(netif_msg_pktdata(priv))) {
 392                         printk(KERN_DEBUG "%s: received packet:\n",
 393                                priv->dev->name);
 394                         cpmac_dump_skb(priv->dev, result);
 395                 }
 396         } else {
 397                 if (netif_msg_rx_err(priv) && net_ratelimit())
 398                         printk(KERN_WARNING
 399                                "%s: low on skbs, dropping packet\n",
 400                                priv->dev->name);
 401                 priv->dev->stats.rx_dropped++;
 402         }
 403
 404         desc->buflen = CPMAC_SKB_SIZE;
 405         desc->dataflags = CPMAC_OWN;
 406
 407         return result;
 408 }
 409
 410 static int cpmac_poll(struct napi_struct *napi, int budget)
 411 {
 412         struct sk_buff *skb;
 413         struct cpmac_desc *desc;
 414         int received = 0;
 415         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
 416
 417         spin_lock(&priv->rx_lock);
 418         if (unlikely(!priv->rx_head)) {
 419                 if (netif_msg_rx_err(priv) && net_ratelimit())
 420                         printk(KERN_WARNING "%s: rx: polling, but no queue\n",
 421                                priv->dev->name);
 422                 netif_rx_complete(priv->dev, napi);
 423                 return 0;
 424         }
 425
 426         desc = priv->rx_head;
 427         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
 428                 skb = cpmac_rx_one(priv, desc);
 429                 if (likely(skb)) {
 430                         netif_receive_skb(skb);
 431                         received++;
 432                 }
 433                 desc = desc->next;
 434         }
 435
 436         priv->rx_head = desc;
 437         spin_unlock(&priv->rx_lock);
 438         if (unlikely(netif_msg_rx_status(priv)))
 439                 printk(KERN_DEBUG "%s: poll processed %d packets\n",
 440                        priv->dev->name, received);
 441         if (desc->dataflags & CPMAC_OWN) {
 442                 netif_rx_complete(priv->dev, napi);
 443                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
 444                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 445                 return 0;
 446         }
 447
 448         return 1;
 449 }
 450
 451 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 452 {
 453         int queue, len;
 454         struct cpmac_desc *desc;
 455         struct cpmac_priv *priv = netdev_priv(dev);
 456
 457         if (unlikely(skb_padto(skb, ETH_ZLEN)))
 458                 return NETDEV_TX_OK;
 459
 460         len = max(skb->len, ETH_ZLEN);
 461         queue = skb->queue_mapping;
 462 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 463         netif_stop_subqueue(dev, queue);
 464 #else
 465         netif_stop_queue(dev);
 466 #endif
 467
 468         desc = &priv->desc_ring[queue];
 469         if (unlikely(desc->dataflags & CPMAC_OWN)) {
 470                 if (netif_msg_tx_err(priv) && net_ratelimit())
 471                         printk(KERN_WARNING "%s: tx dma ring full\n",
 472                                dev->name);
 473                 return NETDEV_TX_BUSY;
 474         }
 475
 476         spin_lock(&priv->lock);
 477         dev->trans_start = jiffies;
 478         spin_unlock(&priv->lock);
 479         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
 480         desc->skb = skb;
 481         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
 482                                             DMA_TO_DEVICE);
 483         desc->hw_data = (u32)desc->data_mapping;
 484         desc->datalen = len;
 485         desc->buflen = len;
 486         if (unlikely(netif_msg_tx_queued(priv)))
 487                 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
 488                        skb->len);
 489         if (unlikely(netif_msg_hw(priv)))
 490                 cpmac_dump_desc(dev, desc);
 491         if (unlikely(netif_msg_pktdata(priv)))
 492                 cpmac_dump_skb(dev, skb);
 493         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
 494
 495         return NETDEV_TX_OK;
 496 }
 497
 498 static void cpmac_end_xmit(struct net_device *dev, int queue)
 499 {
 500         struct cpmac_desc *desc;
 501         struct cpmac_priv *priv = netdev_priv(dev);
 502
 503         desc = &priv->desc_ring[queue];
 504         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
 505         if (likely(desc->skb)) {
 506                 spin_lock(&priv->lock);
 507                 dev->stats.tx_packets++;
 508                 dev->stats.tx_bytes += desc->skb->len;
 509                 spin_unlock(&priv->lock);
 510                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
 511                                  DMA_TO_DEVICE);
 512
 513                 if (unlikely(netif_msg_tx_done(priv)))
 514                         printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
 515                                desc->skb, desc->skb->len);
 516
 517                 dev_kfree_skb_irq(desc->skb);
 518                 desc->skb = NULL;
 519 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 520                 if (netif_subqueue_stopped(dev, queue))
 521                         netif_wake_subqueue(dev, queue);
 522 #else
 523                 if (netif_queue_stopped(dev))
 524                         netif_wake_queue(dev);
 525 #endif
 526         } else {
 527                 if (netif_msg_tx_err(priv) && net_ratelimit())
 528                         printk(KERN_WARNING
 529                                "%s: end_xmit: spurious interrupt\n", dev->name);
 530 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 531                 if (netif_subqueue_stopped(dev, queue))
 532                         netif_wake_subqueue(dev, queue);
 533 #else
 534                 if (netif_queue_stopped(dev))
 535                         netif_wake_queue(dev);
 536 #endif
 537         }
 538 }
 539
 540 static void cpmac_hw_stop(struct net_device *dev)
 541 {
 542         int i;
 543         struct cpmac_priv *priv = netdev_priv(dev);
 544         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 545
 546         ar7_device_reset(pdata->reset_bit);
 547         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 548                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
 549         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 550                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
 551         for (i = 0; i < 8; i++) {
 552                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 553                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 554         }
 555         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 556         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 557         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 558         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 559         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 560                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
 561 }
 562
 563 static void cpmac_hw_start(struct net_device *dev)
 564 {
 565         int i;
 566         struct cpmac_priv *priv = netdev_priv(dev);
 567         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 568
 569         ar7_device_reset(pdata->reset_bit);
 570         for (i = 0; i < 8; i++) {
 571                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 572                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 573         }
 574         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
 575
 576         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
 577                     MBP_RXMCAST);
 578         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
 579         for (i = 0; i < 8; i++)
 580                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
 581         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
 582         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
 583                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
 584                     (dev->dev_addr[3] << 24));
 585         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
 586         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 587         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 588         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 589         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 590         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
 591         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 592         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
 593         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 594
 595         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 596                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
 597         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 598                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
 599         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 600                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
 601                     MAC_FDX);
 602 }
 603
 604 static void cpmac_clear_rx(struct net_device *dev)
 605 {
 606         struct cpmac_priv *priv = netdev_priv(dev);
 607         struct cpmac_desc *desc;
 608         int i;
 609         if (unlikely(!priv->rx_head))
 610                 return;
 611         desc = priv->rx_head;
 612         for (i = 0; i < priv->ring_size; i++) {
 613                 if ((desc->dataflags & CPMAC_OWN) == 0) {
 614                         if (netif_msg_rx_err(priv) && net_ratelimit())
 615                                 printk(KERN_WARNING "%s: packet dropped\n",
 616                                        dev->name);
 617                         if (unlikely(netif_msg_hw(priv)))
 618                                 cpmac_dump_desc(dev, desc);
 619                         desc->dataflags = CPMAC_OWN;
 620                         dev->stats.rx_dropped++;
 621                 }
 622                 desc = desc->next;
 623         }
 624 }
 625
 626 static void cpmac_clear_tx(struct net_device *dev)
 627 {
 628         struct cpmac_priv *priv = netdev_priv(dev);
 629         int i;
 630         if (unlikely(!priv->desc_ring))
 631                 return;
 632         for (i = 0; i < CPMAC_QUEUES; i++) {
 633                 priv->desc_ring[i].dataflags = 0;
 634                 if (priv->desc_ring[i].skb) {
 635                         dev_kfree_skb_any(priv->desc_ring[i].skb);
 636                         if (netif_subqueue_stopped(dev, i))
 637                             netif_wake_subqueue(dev, i);
 638                 }
 639         }
 640 }
 641
 642 static void cpmac_hw_error(struct work_struct *work)
 643 {
 644         struct cpmac_priv *priv =
 645                 container_of(work, struct cpmac_priv, reset_work);
 646
 647         spin_lock(&priv->rx_lock);
 648         cpmac_clear_rx(priv->dev);
 649         spin_unlock(&priv->rx_lock);
 650         cpmac_clear_tx(priv->dev);
 651         cpmac_hw_start(priv->dev);
 652         napi_enable(&priv->napi);
 653         netif_start_queue(priv->dev);
 654 }
 655
 656 static irqreturn_t cpmac_irq(int irq, void *dev_id)
 657 {
 658         struct net_device *dev = dev_id;
 659         struct cpmac_priv *priv;
 660         int queue;
 661         u32 status;
 662
 663         if (!dev)
 664                 return IRQ_NONE;
 665
 666         priv = netdev_priv(dev);
 667
 668         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
 669
 670         if (unlikely(netif_msg_intr(priv)))
 671                 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
 672                        status);
 673
 674         if (status & MAC_INT_TX)
 675                 cpmac_end_xmit(dev, (status & 7));
 676
 677         if (status & MAC_INT_RX) {
 678                 queue = (status >> 8) & 7;
 679                 if (netif_rx_schedule_prep(dev, &priv->napi)) {
 680                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
 681                         __netif_rx_schedule(dev, &priv->napi);
 682                 }
 683         }
 684
 685         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
 686
 687         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
 688                 if (netif_msg_drv(priv) && net_ratelimit())
 689                         printk(KERN_ERR "%s: hw error, resetting...\n",
 690                                dev->name);
 691                 netif_stop_queue(dev);
 692                 napi_disable(&priv->napi);
 693                 cpmac_hw_stop(dev);
 694                 schedule_work(&priv->reset_work);
 695                 if (unlikely(netif_msg_hw(priv)))
 696                         cpmac_dump_regs(dev);
 697         }
 698
 699         return IRQ_HANDLED;
 700 }
 701
 702 static void cpmac_tx_timeout(struct net_device *dev)
 703 {
 704         struct cpmac_priv *priv = netdev_priv(dev);
 705         int i;
 706
 707         spin_lock(&priv->lock);
 708         dev->stats.tx_errors++;
 709         spin_unlock(&priv->lock);
 710         if (netif_msg_tx_err(priv) && net_ratelimit())
 711                 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
 712         /*
 713          * FIXME: waking up random queue is not the best thing to
 714          * do... on the other hand why we got here at all?
 715          */
 716 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 717         for (i = 0; i < CPMAC_QUEUES; i++)
 718                 if (priv->desc_ring[i].skb) {
 719                         priv->desc_ring[i].dataflags = 0;
 720                         dev_kfree_skb_any(priv->desc_ring[i].skb);
 721                         netif_wake_subqueue(dev, i);
 722                         break;
 723                 }
 724 #else
 725         priv->desc_ring[0].dataflags = 0;
 726         if (priv->desc_ring[0].skb)
 727                 dev_kfree_skb_any(priv->desc_ring[0].skb);
 728         netif_wake_queue(dev);
 729 #endif
 730 }
 731
 732 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 733 {
 734         struct cpmac_priv *priv = netdev_priv(dev);
 735         if (!(netif_running(dev)))
 736                 return -EINVAL;
 737         if (!priv->phy)
 738                 return -EINVAL;
 739         if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
 740             (cmd == SIOCSMIIREG))
 741                 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
 742
 743         return -EOPNOTSUPP;
 744 }
 745
 746 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 747 {
 748         struct cpmac_priv *priv = netdev_priv(dev);
 749
 750         if (priv->phy)
 751                 return phy_ethtool_gset(priv->phy, cmd);
 752
 753         return -EINVAL;
 754 }
 755
 756 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 757 {
 758         struct cpmac_priv *priv = netdev_priv(dev);
 759
 760         if (!capable(CAP_NET_ADMIN))
 761                 return -EPERM;
 762
 763         if (priv->phy)
 764                 return phy_ethtool_sset(priv->phy, cmd);
 765
 766         return -EINVAL;
 767 }
 768
 769 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 770 {
 771         struct cpmac_priv *priv = netdev_priv(dev);
 772
 773         ring->rx_max_pending = 1024;
 774         ring->rx_mini_max_pending = 1;
 775         ring->rx_jumbo_max_pending = 1;
 776         ring->tx_max_pending = 1;
 777
 778         ring->rx_pending = priv->ring_size;
 779         ring->rx_mini_pending = 1;
 780         ring->rx_jumbo_pending = 1;
 781         ring->tx_pending = 1;
 782 }
 783
 784 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 785 {
 786         struct cpmac_priv *priv = netdev_priv(dev);
 787
 788         if (netif_running(dev))
 789                 return -EBUSY;
 790         priv->ring_size = ring->rx_pending;
 791         return 0;
 792 }
 793
 794 static void cpmac_get_drvinfo(struct net_device *dev,
 795                               struct ethtool_drvinfo *info)
 796 {
 797         strcpy(info->driver, "cpmac");
 798         strcpy(info->version, CPMAC_VERSION);
 799         info->fw_version[0] = '\0';
 800         sprintf(info->bus_info, "%s", "cpmac");
 801         info->regdump_len = 0;
 802 }
 803
 804 static const struct ethtool_ops cpmac_ethtool_ops = {
 805         .get_settings = cpmac_get_settings,
 806         .set_settings = cpmac_set_settings,
 807         .get_drvinfo = cpmac_get_drvinfo,
 808         .get_link = ethtool_op_get_link,
 809         .get_ringparam = cpmac_get_ringparam,
 810         .set_ringparam = cpmac_set_ringparam,
 811 };
 812
 813 static void cpmac_adjust_link(struct net_device *dev)
 814 {
 815         struct cpmac_priv *priv = netdev_priv(dev);
 816         int new_state = 0;
 817
 818         spin_lock(&priv->lock);
 819         if (priv->phy->link) {
 820                 netif_start_queue(dev);
 821                 if (priv->phy->duplex != priv->oldduplex) {
 822                         new_state = 1;
 823                         priv->oldduplex = priv->phy->duplex;
 824                 }
 825
 826                 if (priv->phy->speed != priv->oldspeed) {
 827                         new_state = 1;
 828                         priv->oldspeed = priv->phy->speed;
 829                 }
 830
 831                 if (!priv->oldlink) {
 832                         new_state = 1;
 833                         priv->oldlink = 1;
 834                         netif_schedule(dev);
 835                 }
 836         } else if (priv->oldlink) {
 837                 netif_stop_queue(dev);
 838                 new_state = 1;
 839                 priv->oldlink = 0;
 840                 priv->oldspeed = 0;
 841                 priv->oldduplex = -1;
 842         }
 843
 844         if (new_state && netif_msg_link(priv) && net_ratelimit())
 845                 phy_print_status(priv->phy);
 846
 847         spin_unlock(&priv->lock);
 848 }
 849
 850 static int cpmac_open(struct net_device *dev)
 851 {
 852         int i, size, res;
 853         struct cpmac_priv *priv = netdev_priv(dev);
 854         struct resource *mem;
 855         struct cpmac_desc *desc;
 856         struct sk_buff *skb;
 857
 858         priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
 859                                 0, PHY_INTERFACE_MODE_MII);
 860         if (IS_ERR(priv->phy)) {
 861                 if (netif_msg_drv(priv))
 862                         printk(KERN_ERR "%s: Could not attach to PHY\n",
 863                                dev->name);
 864                 return PTR_ERR(priv->phy);
 865         }
 866
 867         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
 868         if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
 869                 if (netif_msg_drv(priv))
 870                         printk(KERN_ERR "%s: failed to request registers\n",
 871                                dev->name);
 872                 res = -ENXIO;
 873                 goto fail_reserve;
 874         }
 875
 876         priv->regs = ioremap(mem->start, mem->end - mem->start);
 877         if (!priv->regs) {
 878                 if (netif_msg_drv(priv))
 879                         printk(KERN_ERR "%s: failed to remap registers\n",
 880                                dev->name);
 881                 res = -ENXIO;
 882                 goto fail_remap;
 883         }
 884
 885         size = priv->ring_size + CPMAC_QUEUES;
 886         priv->desc_ring = dma_alloc_coherent(&dev->dev,
 887                                              sizeof(struct cpmac_desc) * size,
 888                                              &priv->dma_ring,
 889                                              GFP_KERNEL);
 890         if (!priv->desc_ring) {
 891                 res = -ENOMEM;
 892                 goto fail_alloc;
 893         }
 894
 895         for (i = 0; i < size; i++)
 896                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
 897
 898         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
 899         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
 900                 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
 901                 if (unlikely(!skb)) {
 902                         res = -ENOMEM;
 903                         goto fail_desc;
 904                 }
 905                 skb_reserve(skb, 2);
 906                 desc->skb = skb;
 907                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
 908                                                     CPMAC_SKB_SIZE,
 909                                                     DMA_FROM_DEVICE);
 910                 desc->hw_data = (u32)desc->data_mapping;
 911                 desc->buflen = CPMAC_SKB_SIZE;
 912                 desc->dataflags = CPMAC_OWN;
 913                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
 914                 desc->hw_next = (u32)desc->next->mapping;
 915         }
 916
 917         if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
 918                                dev->name, dev))) {
 919                 if (netif_msg_drv(priv))
 920                         printk(KERN_ERR "%s: failed to obtain irq\n",
 921                                dev->name);
 922                 goto fail_irq;
 923         }
 924
 925         INIT_WORK(&priv->reset_work, cpmac_hw_error);
 926         cpmac_hw_start(dev);
 927
 928         napi_enable(&priv->napi);
 929         priv->phy->state = PHY_CHANGELINK;
 930         phy_start(priv->phy);
 931
 932         return 0;
 933
 934 fail_irq:
 935 fail_desc:
 936         for (i = 0; i < priv->ring_size; i++) {
 937                 if (priv->rx_head[i].skb) {
 938                         dma_unmap_single(&dev->dev,
 939                                          priv->rx_head[i].data_mapping,
 940                                          CPMAC_SKB_SIZE,
 941                                          DMA_FROM_DEVICE);
 942                         kfree_skb(priv->rx_head[i].skb);
 943                 }
 944         }
 945 fail_alloc:
 946         kfree(priv->desc_ring);
 947         iounmap(priv->regs);
 948
 949 fail_remap:
 950         release_mem_region(mem->start, mem->end - mem->start);
 951
 952 fail_reserve:
 953         phy_disconnect(priv->phy);
 954
 955         return res;
 956 }
 957
 958 static int cpmac_stop(struct net_device *dev)
 959 {
 960         int i;
 961         struct cpmac_priv *priv = netdev_priv(dev);
 962         struct resource *mem;
 963
 964         netif_stop_queue(dev);
 965
 966         cancel_work_sync(&priv->reset_work);
 967         napi_disable(&priv->napi);
 968         phy_stop(priv->phy);
 969         phy_disconnect(priv->phy);
 970         priv->phy = NULL;
 971
 972         cpmac_hw_stop(dev);
 973
 974         for (i = 0; i < 8; i++)
 975                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 976         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
 977         cpmac_write(priv->regs, CPMAC_MBP, 0);
 978
 979         free_irq(dev->irq, dev);
 980         iounmap(priv->regs);
 981         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
 982         release_mem_region(mem->start, mem->end - mem->start);
 983         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
 984         for (i = 0; i < priv->ring_size; i++) {
 985                 if (priv->rx_head[i].skb) {
 986                         dma_unmap_single(&dev->dev,
 987                                          priv->rx_head[i].data_mapping,
 988                                          CPMAC_SKB_SIZE,
 989                                          DMA_FROM_DEVICE);
 990                         kfree_skb(priv->rx_head[i].skb);
 991                 }
 992         }
 993
 994         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
 995                           (CPMAC_QUEUES + priv->ring_size),
 996                           priv->desc_ring, priv->dma_ring);
 997         return 0;
 998 }
 999
1000 static int external_switch;
1001
1002 static int __devinit cpmac_probe(struct platform_device *pdev)
1003 {
1004         int rc, phy_id;
1005         struct resource *mem;
1006         struct cpmac_priv *priv;
1007         struct net_device *dev;
1008         struct plat_cpmac_data *pdata;
1009         DECLARE_MAC_BUF(mac);
1010
1011         pdata = pdev->dev.platform_data;
1012
1013         for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1014                 if (!(pdata->phy_mask & (1 << phy_id)))
1015                         continue;
1016                 if (!cpmac_mii.phy_map[phy_id])
1017                         continue;
1018                 break;
1019         }
1020
1021         if (phy_id == PHY_MAX_ADDR) {
1022                 if (external_switch || dumb_switch)
1023                         phy_id = 0;
1024                 else {
1025                         printk(KERN_ERR "cpmac: no PHY present\n");
1026                         return -ENODEV;
1027                 }
1028         }
1029
1030         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1031
1032         if (!dev) {
1033                 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1034                 return -ENOMEM;
1035         }
1036
1037         platform_set_drvdata(pdev, dev);
1038         priv = netdev_priv(dev);
1039
1040         priv->pdev = pdev;
1041         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1042         if (!mem) {
1043                 rc = -ENODEV;
1044                 goto fail;
1045         }
1046
1047         dev->irq = platform_get_irq_byname(pdev, "irq");
1048
1049         dev->open               = cpmac_open;
1050         dev->stop               = cpmac_stop;
1051         dev->set_config         = cpmac_config;
1052         dev->hard_start_xmit    = cpmac_start_xmit;
1053         dev->do_ioctl           = cpmac_ioctl;
1054         dev->set_multicast_list = cpmac_set_multicast_list;
1055         dev->tx_timeout         = cpmac_tx_timeout;
1056         dev->ethtool_ops        = &cpmac_ethtool_ops;
1057         dev->features |= NETIF_F_MULTI_QUEUE;
1058
1059         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1060
1061         spin_lock_init(&priv->lock);
1062         spin_lock_init(&priv->rx_lock);
1063         priv->dev = dev;
1064         priv->ring_size = 64;
1065         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1066         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1067         if (phy_id == 31) {
1068                 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1069                          cpmac_mii.id, phy_id);
1070         } else
1071                 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1072
1073         if ((rc = register_netdev(dev))) {
1074                 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1075                        dev->name);
1076                 goto fail;
1077         }
1078
1079         if (netif_msg_probe(priv)) {
1080                 printk(KERN_INFO
1081                        "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1082                        "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1083                        priv->phy_name, print_mac(mac, dev->dev_addr));
1084         }
1085         return 0;
1086
1087 fail:
1088         free_netdev(dev);
1089         return rc;
1090 }
1091
1092 static int __devexit cpmac_remove(struct platform_device *pdev)
1093 {
1094         struct net_device *dev = platform_get_drvdata(pdev);
1095         unregister_netdev(dev);
1096         free_netdev(dev);
1097         return 0;
1098 }
1099
1100 static struct platform_driver cpmac_driver = {
1101         .driver.name = "cpmac",
1102         .probe = cpmac_probe,
1103         .remove = __devexit_p(cpmac_remove),
1104 };
1105
1106 int __devinit cpmac_init(void)
1107 {
1108         u32 mask;
1109         int i, res;
1110
1111         cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1112
1113         if (!cpmac_mii.priv) {
1114                 printk(KERN_ERR "Can't ioremap mdio registers\n");
1115                 return -ENXIO;
1116         }
1117
1118 #warning FIXME: unhardcode gpio&reset bits
1119         ar7_gpio_disable(26);
1120         ar7_gpio_disable(27);
1121         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1122         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1123         ar7_device_reset(AR7_RESET_BIT_EPHY);
1124
1125         cpmac_mii.reset(&cpmac_mii);
1126
1127         for (i = 0; i < 300000; i++)
1128                 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1129                         break;
1130                 else
1131                         cpu_relax();
1132
1133         mask &= 0x7fffffff;
1134         if (mask & (mask - 1)) {
1135                 external_switch = 1;
1136                 mask = 0;
1137         }
1138
1139         cpmac_mii.phy_mask = ~(mask | 0x80000000);
1140
1141         res = mdiobus_register(&cpmac_mii);
1142         if (res)
1143                 goto fail_mii;
1144
1145         res = platform_driver_register(&cpmac_driver);
1146         if (res)
1147                 goto fail_cpmac;
1148
1149         return 0;
1150
1151 fail_cpmac:
1152         mdiobus_unregister(&cpmac_mii);
1153
1154 fail_mii:
1155         iounmap(cpmac_mii.priv);
1156
1157         return res;
1158 }
1159
1160 void __devexit cpmac_exit(void)
1161 {
1162         platform_driver_unregister(&cpmac_driver);
1163         mdiobus_unregister(&cpmac_mii);
1164         iounmap(cpmac_mii.priv);
1165 }
1166
1167 module_init(cpmac_init);
1168 module_exit(cpmac_exit);