1 /*******************************************************************************
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36 static void e1000_phy_init_script(struct e1000_hw *hw);
37 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
42 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
43 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
49 uint16_t words, uint16_t *data);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
51 uint16_t offset, uint16_t words,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
54 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
55 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64 static void e1000_release_eeprom(struct e1000_hw *hw);
65 static void e1000_standby_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
68 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
69 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
70 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
71 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
72 static int32_t e1000_check_downshift(struct e1000_hw *hw);
73 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
74 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
75 static void e1000_clear_vfta(struct e1000_hw *hw);
76 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
77 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
79 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
80 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
81 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
82 static int32_t e1000_get_cable_length(struct e1000_hw *hw,
84 uint16_t *max_length);
85 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
86 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
87 static int32_t e1000_id_led_init(struct e1000_hw * hw);
88 static void e1000_init_rx_addrs(struct e1000_hw *hw);
89 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
90 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
91 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
92 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
93 uint16_t words, uint16_t *data);
94 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
95 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
96 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
98 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 #define E1000_WRITE_REG_IO(a, reg, val) \
102 e1000_write_reg_io((a), E1000_##reg, val)
104 /* IGP cable length table */
106 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
107 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
108 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
109 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
110 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
111 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
112 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
113 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
114 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
117 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
118 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
119 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
120 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
121 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
122 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
123 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
124 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
125 104, 109, 114, 118, 121, 124};
128 /******************************************************************************
129 * Set the phy type member in the hw struct.
131 * hw - Struct containing variables accessed by shared code
132 *****************************************************************************/
134 e1000_set_phy_type(struct e1000_hw *hw)
136 DEBUGFUNC("e1000_set_phy_type");
138 if(hw->mac_type == e1000_undefined)
139 return -E1000_ERR_PHY_TYPE;
142 case M88E1000_E_PHY_ID:
143 case M88E1000_I_PHY_ID:
144 case M88E1011_I_PHY_ID:
145 case M88E1111_I_PHY_ID:
146 hw->phy_type = e1000_phy_m88;
148 case IGP01E1000_I_PHY_ID:
149 if(hw->mac_type == e1000_82541 ||
150 hw->mac_type == e1000_82541_rev_2 ||
151 hw->mac_type == e1000_82547 ||
152 hw->mac_type == e1000_82547_rev_2) {
153 hw->phy_type = e1000_phy_igp;
158 /* Should never have loaded on this device */
159 hw->phy_type = e1000_phy_undefined;
160 return -E1000_ERR_PHY_TYPE;
163 return E1000_SUCCESS;
166 /******************************************************************************
167 * IGP phy init script - initializes the GbE PHY
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
172 e1000_phy_init_script(struct e1000_hw *hw)
175 uint16_t phy_saved_data;
177 DEBUGFUNC("e1000_phy_init_script");
179 if(hw->phy_init_script) {
182 /* Save off the current value of register 0x2F5B to be restored at
183 * the end of this routine. */
184 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
186 /* Disabled the PHY transmitter */
187 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
191 e1000_write_phy_reg(hw,0x0000,0x0140);
195 switch(hw->mac_type) {
198 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
200 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
202 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
204 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
206 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
208 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
210 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
212 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
214 e1000_write_phy_reg(hw, 0x2010, 0x0008);
217 case e1000_82541_rev_2:
218 case e1000_82547_rev_2:
219 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
225 e1000_write_phy_reg(hw, 0x0000, 0x3300);
229 /* Now enable the transmitter */
230 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
232 if(hw->mac_type == e1000_82547) {
233 uint16_t fused, fine, coarse;
235 /* Move to analog registers page */
236 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
238 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
239 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
241 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
242 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
244 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
245 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
246 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
247 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
248 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
250 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
251 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
252 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
254 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
255 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
256 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
262 /******************************************************************************
263 * Set the mac type member in the hw struct.
265 * hw - Struct containing variables accessed by shared code
266 *****************************************************************************/
268 e1000_set_mac_type(struct e1000_hw *hw)
270 DEBUGFUNC("e1000_set_mac_type");
272 switch (hw->device_id) {
273 case E1000_DEV_ID_82542:
274 switch (hw->revision_id) {
275 case E1000_82542_2_0_REV_ID:
276 hw->mac_type = e1000_82542_rev2_0;
278 case E1000_82542_2_1_REV_ID:
279 hw->mac_type = e1000_82542_rev2_1;
282 /* Invalid 82542 revision ID */
283 return -E1000_ERR_MAC_TYPE;
286 case E1000_DEV_ID_82543GC_FIBER:
287 case E1000_DEV_ID_82543GC_COPPER:
288 hw->mac_type = e1000_82543;
290 case E1000_DEV_ID_82544EI_COPPER:
291 case E1000_DEV_ID_82544EI_FIBER:
292 case E1000_DEV_ID_82544GC_COPPER:
293 case E1000_DEV_ID_82544GC_LOM:
294 hw->mac_type = e1000_82544;
296 case E1000_DEV_ID_82540EM:
297 case E1000_DEV_ID_82540EM_LOM:
298 case E1000_DEV_ID_82540EP:
299 case E1000_DEV_ID_82540EP_LOM:
300 case E1000_DEV_ID_82540EP_LP:
301 hw->mac_type = e1000_82540;
303 case E1000_DEV_ID_82545EM_COPPER:
304 case E1000_DEV_ID_82545EM_FIBER:
305 hw->mac_type = e1000_82545;
307 case E1000_DEV_ID_82545GM_COPPER:
308 case E1000_DEV_ID_82545GM_FIBER:
309 case E1000_DEV_ID_82545GM_SERDES:
310 hw->mac_type = e1000_82545_rev_3;
312 case E1000_DEV_ID_82546EB_COPPER:
313 case E1000_DEV_ID_82546EB_FIBER:
314 case E1000_DEV_ID_82546EB_QUAD_COPPER:
315 hw->mac_type = e1000_82546;
317 case E1000_DEV_ID_82546GB_COPPER:
318 case E1000_DEV_ID_82546GB_FIBER:
319 case E1000_DEV_ID_82546GB_SERDES:
320 case E1000_DEV_ID_82546GB_PCIE:
321 case E1000_DEV_ID_82546GB_QUAD_COPPER:
322 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
323 hw->mac_type = e1000_82546_rev_3;
325 case E1000_DEV_ID_82541EI:
326 case E1000_DEV_ID_82541EI_MOBILE:
327 hw->mac_type = e1000_82541;
329 case E1000_DEV_ID_82541ER:
330 case E1000_DEV_ID_82541GI:
331 case E1000_DEV_ID_82541GI_LF:
332 case E1000_DEV_ID_82541GI_MOBILE:
333 hw->mac_type = e1000_82541_rev_2;
335 case E1000_DEV_ID_82547EI:
336 hw->mac_type = e1000_82547;
338 case E1000_DEV_ID_82547GI:
339 hw->mac_type = e1000_82547_rev_2;
341 case E1000_DEV_ID_82571EB_COPPER:
342 case E1000_DEV_ID_82571EB_FIBER:
343 case E1000_DEV_ID_82571EB_SERDES:
344 hw->mac_type = e1000_82571;
346 case E1000_DEV_ID_82572EI_COPPER:
347 case E1000_DEV_ID_82572EI_FIBER:
348 case E1000_DEV_ID_82572EI_SERDES:
349 hw->mac_type = e1000_82572;
351 case E1000_DEV_ID_82573E:
352 case E1000_DEV_ID_82573E_IAMT:
353 case E1000_DEV_ID_82573L:
354 hw->mac_type = e1000_82573;
357 /* Should never have loaded on this device */
358 return -E1000_ERR_MAC_TYPE;
361 switch(hw->mac_type) {
365 hw->eeprom_semaphore_present = TRUE;
369 case e1000_82541_rev_2:
370 case e1000_82547_rev_2:
371 hw->asf_firmware_present = TRUE;
377 return E1000_SUCCESS;
380 /*****************************************************************************
381 * Set media type and TBI compatibility.
383 * hw - Struct containing variables accessed by shared code
384 * **************************************************************************/
386 e1000_set_media_type(struct e1000_hw *hw)
390 DEBUGFUNC("e1000_set_media_type");
392 if(hw->mac_type != e1000_82543) {
393 /* tbi_compatibility is only valid on 82543 */
394 hw->tbi_compatibility_en = FALSE;
397 switch (hw->device_id) {
398 case E1000_DEV_ID_82545GM_SERDES:
399 case E1000_DEV_ID_82546GB_SERDES:
400 case E1000_DEV_ID_82571EB_SERDES:
401 case E1000_DEV_ID_82572EI_SERDES:
402 hw->media_type = e1000_media_type_internal_serdes;
405 switch (hw->mac_type) {
406 case e1000_82542_rev2_0:
407 case e1000_82542_rev2_1:
408 hw->media_type = e1000_media_type_fiber;
411 /* The STATUS_TBIMODE bit is reserved or reused for the this
414 hw->media_type = e1000_media_type_copper;
417 status = E1000_READ_REG(hw, STATUS);
418 if (status & E1000_STATUS_TBIMODE) {
419 hw->media_type = e1000_media_type_fiber;
420 /* tbi_compatibility not valid on fiber */
421 hw->tbi_compatibility_en = FALSE;
423 hw->media_type = e1000_media_type_copper;
430 /******************************************************************************
431 * Reset the transmit and receive units; mask and clear all interrupts.
433 * hw - Struct containing variables accessed by shared code
434 *****************************************************************************/
436 e1000_reset_hw(struct e1000_hw *hw)
444 uint32_t extcnf_ctrl;
447 DEBUGFUNC("e1000_reset_hw");
449 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
450 if(hw->mac_type == e1000_82542_rev2_0) {
451 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
452 e1000_pci_clear_mwi(hw);
455 if(hw->bus_type == e1000_bus_type_pci_express) {
456 /* Prevent the PCI-E bus from sticking if there is no TLP connection
457 * on the last TLP read/write transaction when MAC is reset.
459 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
460 DEBUGOUT("PCI-E Master disable polling has failed.\n");
464 /* Clear interrupt mask to stop board from generating interrupts */
465 DEBUGOUT("Masking off all interrupts\n");
466 E1000_WRITE_REG(hw, IMC, 0xffffffff);
468 /* Disable the Transmit and Receive units. Then delay to allow
469 * any pending transactions to complete before we hit the MAC with
472 E1000_WRITE_REG(hw, RCTL, 0);
473 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
474 E1000_WRITE_FLUSH(hw);
476 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
477 hw->tbi_compatibility_on = FALSE;
479 /* Delay to allow any outstanding PCI transactions to complete before
480 * resetting the device
484 ctrl = E1000_READ_REG(hw, CTRL);
486 /* Must reset the PHY before resetting the MAC */
487 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
488 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
492 /* Must acquire the MDIO ownership before MAC reset.
493 * Ownership defaults to firmware after a reset. */
494 if(hw->mac_type == e1000_82573) {
497 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
498 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
501 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
502 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
504 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
507 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
514 /* Issue a global reset to the MAC. This will reset the chip's
515 * transmit, receive, DMA, and link units. It will not effect
516 * the current PCI configuration. The global reset bit is self-
517 * clearing, and should clear within a microsecond.
519 DEBUGOUT("Issuing a global reset to MAC\n");
521 switch(hw->mac_type) {
527 case e1000_82541_rev_2:
528 /* These controllers can't ack the 64-bit write when issuing the
529 * reset, so use IO-mapping as a workaround to issue the reset */
530 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
532 case e1000_82545_rev_3:
533 case e1000_82546_rev_3:
534 /* Reset is performed on a shadow of the control register */
535 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
538 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
542 /* After MAC reset, force reload of EEPROM to restore power-on settings to
543 * device. Later controllers reload the EEPROM automatically, so just wait
544 * for reload to complete.
546 switch(hw->mac_type) {
547 case e1000_82542_rev2_0:
548 case e1000_82542_rev2_1:
551 /* Wait for reset to complete */
553 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
554 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
555 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
556 E1000_WRITE_FLUSH(hw);
557 /* Wait for EEPROM reload */
561 case e1000_82541_rev_2:
563 case e1000_82547_rev_2:
564 /* Wait for EEPROM reload */
568 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
570 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
571 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
572 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
573 E1000_WRITE_FLUSH(hw);
578 ret_val = e1000_get_auto_rd_done(hw);
580 /* We don't want to continue accessing MAC registers. */
584 /* Wait for EEPROM reload (it happens automatically) */
589 /* Disable HW ARPs on ASF enabled adapters */
590 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
591 manc = E1000_READ_REG(hw, MANC);
592 manc &= ~(E1000_MANC_ARP_EN);
593 E1000_WRITE_REG(hw, MANC, manc);
596 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
597 e1000_phy_init_script(hw);
599 /* Configure activity LED after PHY reset */
600 led_ctrl = E1000_READ_REG(hw, LEDCTL);
601 led_ctrl &= IGP_ACTIVITY_LED_MASK;
602 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
603 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
606 /* Clear interrupt mask to stop board from generating interrupts */
607 DEBUGOUT("Masking off all interrupts\n");
608 E1000_WRITE_REG(hw, IMC, 0xffffffff);
610 /* Clear any pending interrupt events. */
611 icr = E1000_READ_REG(hw, ICR);
613 /* If MWI was previously enabled, reenable it. */
614 if(hw->mac_type == e1000_82542_rev2_0) {
615 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
616 e1000_pci_set_mwi(hw);
619 return E1000_SUCCESS;
622 /******************************************************************************
623 * Performs basic configuration of the adapter.
625 * hw - Struct containing variables accessed by shared code
627 * Assumes that the controller has previously been reset and is in a
628 * post-reset uninitialized state. Initializes the receive address registers,
629 * multicast table, and VLAN filter table. Calls routines to setup link
630 * configuration and flow control settings. Clears all on-chip counters. Leaves
631 * the transmit and receive units disabled and uninitialized.
632 *****************************************************************************/
634 e1000_init_hw(struct e1000_hw *hw)
639 uint16_t pcix_cmd_word;
640 uint16_t pcix_stat_hi_word;
646 DEBUGFUNC("e1000_init_hw");
648 /* Initialize Identification LED */
649 ret_val = e1000_id_led_init(hw);
651 DEBUGOUT("Error Initializing Identification LED\n");
655 /* Set the media type and TBI compatibility */
656 e1000_set_media_type(hw);
658 /* Disabling VLAN filtering. */
659 DEBUGOUT("Initializing the IEEE VLAN\n");
660 if (hw->mac_type < e1000_82545_rev_3)
661 E1000_WRITE_REG(hw, VET, 0);
662 e1000_clear_vfta(hw);
664 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
665 if(hw->mac_type == e1000_82542_rev2_0) {
666 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
667 e1000_pci_clear_mwi(hw);
668 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
669 E1000_WRITE_FLUSH(hw);
673 /* Setup the receive address. This involves initializing all of the Receive
674 * Address Registers (RARs 0 - 15).
676 e1000_init_rx_addrs(hw);
678 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
679 if(hw->mac_type == e1000_82542_rev2_0) {
680 E1000_WRITE_REG(hw, RCTL, 0);
681 E1000_WRITE_FLUSH(hw);
683 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
684 e1000_pci_set_mwi(hw);
687 /* Zero out the Multicast HASH table */
688 DEBUGOUT("Zeroing the MTA\n");
689 mta_size = E1000_MC_TBL_SIZE;
690 for(i = 0; i < mta_size; i++)
691 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
693 /* Set the PCI priority bit correctly in the CTRL register. This
694 * determines if the adapter gives priority to receives, or if it
695 * gives equal priority to transmits and receives. Valid only on
696 * 82542 and 82543 silicon.
698 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
699 ctrl = E1000_READ_REG(hw, CTRL);
700 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
703 switch(hw->mac_type) {
704 case e1000_82545_rev_3:
705 case e1000_82546_rev_3:
708 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
709 if(hw->bus_type == e1000_bus_type_pcix) {
710 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
711 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
713 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
714 PCIX_COMMAND_MMRBC_SHIFT;
715 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
716 PCIX_STATUS_HI_MMRBC_SHIFT;
717 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
718 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
719 if(cmd_mmrbc > stat_mmrbc) {
720 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
721 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
722 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
729 /* Call a subroutine to configure the link and setup flow control. */
730 ret_val = e1000_setup_link(hw);
732 /* Set the transmit descriptor write-back policy */
733 if(hw->mac_type > e1000_82544) {
734 ctrl = E1000_READ_REG(hw, TXDCTL);
735 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
736 switch (hw->mac_type) {
742 ctrl |= E1000_TXDCTL_COUNT_DESC;
745 E1000_WRITE_REG(hw, TXDCTL, ctrl);
748 if (hw->mac_type == e1000_82573) {
749 e1000_enable_tx_pkt_filtering(hw);
752 switch (hw->mac_type) {
757 ctrl = E1000_READ_REG(hw, TXDCTL1);
758 ctrl &= ~E1000_TXDCTL_WTHRESH;
759 ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB;
761 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
767 if (hw->mac_type == e1000_82573) {
768 uint32_t gcr = E1000_READ_REG(hw, GCR);
769 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
770 E1000_WRITE_REG(hw, GCR, gcr);
773 /* Clear all of the statistics registers (clear on read). It is
774 * important that we do this after we have tried to establish link
775 * because the symbol error count will increment wildly if there
778 e1000_clear_hw_cntrs(hw);
780 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
781 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
782 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
783 /* Relaxed ordering must be disabled to avoid a parity
784 * error crash in a PCI slot. */
785 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
786 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
792 /******************************************************************************
793 * Adjust SERDES output amplitude based on EEPROM setting.
795 * hw - Struct containing variables accessed by shared code.
796 *****************************************************************************/
798 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
800 uint16_t eeprom_data;
803 DEBUGFUNC("e1000_adjust_serdes_amplitude");
805 if(hw->media_type != e1000_media_type_internal_serdes)
806 return E1000_SUCCESS;
808 switch(hw->mac_type) {
809 case e1000_82545_rev_3:
810 case e1000_82546_rev_3:
813 return E1000_SUCCESS;
816 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
821 if(eeprom_data != EEPROM_RESERVED_WORD) {
822 /* Adjust SERDES output amplitude only. */
823 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
824 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
829 return E1000_SUCCESS;
832 /******************************************************************************
833 * Configures flow control and link settings.
835 * hw - Struct containing variables accessed by shared code
837 * Determines which flow control settings to use. Calls the apropriate media-
838 * specific link configuration function. Configures the flow control settings.
839 * Assuming the adapter has a valid link partner, a valid link should be
840 * established. Assumes the hardware has previously been reset and the
841 * transmitter and receiver are not enabled.
842 *****************************************************************************/
844 e1000_setup_link(struct e1000_hw *hw)
848 uint16_t eeprom_data;
850 DEBUGFUNC("e1000_setup_link");
852 /* In the case of the phy reset being blocked, we already have a link.
853 * We do not have to set it up again. */
854 if (e1000_check_phy_reset_block(hw))
855 return E1000_SUCCESS;
857 /* Read and store word 0x0F of the EEPROM. This word contains bits
858 * that determine the hardware's default PAUSE (flow control) mode,
859 * a bit that determines whether the HW defaults to enabling or
860 * disabling auto-negotiation, and the direction of the
861 * SW defined pins. If there is no SW over-ride of the flow
862 * control setting, then the variable hw->fc will
863 * be initialized based on a value in the EEPROM.
865 if (hw->fc == e1000_fc_default) {
866 switch (hw->mac_type) {
868 hw->fc = e1000_fc_full;
871 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
874 DEBUGOUT("EEPROM Read Error\n");
875 return -E1000_ERR_EEPROM;
877 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
878 hw->fc = e1000_fc_none;
879 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
880 EEPROM_WORD0F_ASM_DIR)
881 hw->fc = e1000_fc_tx_pause;
883 hw->fc = e1000_fc_full;
888 /* We want to save off the original Flow Control configuration just
889 * in case we get disconnected and then reconnected into a different
890 * hub or switch with different Flow Control capabilities.
892 if(hw->mac_type == e1000_82542_rev2_0)
893 hw->fc &= (~e1000_fc_tx_pause);
895 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
896 hw->fc &= (~e1000_fc_rx_pause);
898 hw->original_fc = hw->fc;
900 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
902 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
903 * polarity value for the SW controlled pins, and setup the
904 * Extended Device Control reg with that info.
905 * This is needed because one of the SW controlled pins is used for
906 * signal detection. So this should be done before e1000_setup_pcs_link()
907 * or e1000_phy_setup() is called.
909 if (hw->mac_type == e1000_82543) {
910 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
913 DEBUGOUT("EEPROM Read Error\n");
914 return -E1000_ERR_EEPROM;
916 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
918 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
921 /* Call the necessary subroutine to configure the link. */
922 ret_val = (hw->media_type == e1000_media_type_copper) ?
923 e1000_setup_copper_link(hw) :
924 e1000_setup_fiber_serdes_link(hw);
926 /* Initialize the flow control address, type, and PAUSE timer
927 * registers to their default values. This is done even if flow
928 * control is disabled, because it does not hurt anything to
929 * initialize these registers.
931 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
933 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
934 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
935 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
937 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
939 /* Set the flow control receive threshold registers. Normally,
940 * these registers will be set to a default threshold that may be
941 * adjusted later by the driver's runtime code. However, if the
942 * ability to transmit pause frames in not enabled, then these
943 * registers will be set to 0.
945 if(!(hw->fc & e1000_fc_tx_pause)) {
946 E1000_WRITE_REG(hw, FCRTL, 0);
947 E1000_WRITE_REG(hw, FCRTH, 0);
949 /* We need to set up the Receive Threshold high and low water marks
950 * as well as (optionally) enabling the transmission of XON frames.
952 if(hw->fc_send_xon) {
953 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
954 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
956 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
957 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
963 /******************************************************************************
964 * Sets up link for a fiber based or serdes based adapter
966 * hw - Struct containing variables accessed by shared code
968 * Manipulates Physical Coding Sublayer functions in order to configure
969 * link. Assumes the hardware has been previously reset and the transmitter
970 * and receiver are not enabled.
971 *****************************************************************************/
973 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
982 DEBUGFUNC("e1000_setup_fiber_serdes_link");
984 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
985 * until explicitly turned off or a power cycle is performed. A read to
986 * the register does not indicate its status. Therefore, we ensure
987 * loopback mode is disabled during initialization.
989 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
990 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
992 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
993 * set when the optics detect a signal. On older adapters, it will be
994 * cleared when there is a signal. This applies to fiber media only.
995 * If we're on serdes media, adjust the output amplitude to value set in
998 ctrl = E1000_READ_REG(hw, CTRL);
999 if(hw->media_type == e1000_media_type_fiber)
1000 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1002 ret_val = e1000_adjust_serdes_amplitude(hw);
1006 /* Take the link out of reset */
1007 ctrl &= ~(E1000_CTRL_LRST);
1009 /* Adjust VCO speed to improve BER performance */
1010 ret_val = e1000_set_vco_speed(hw);
1014 e1000_config_collision_dist(hw);
1016 /* Check for a software override of the flow control settings, and setup
1017 * the device accordingly. If auto-negotiation is enabled, then software
1018 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1019 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1020 * auto-negotiation is disabled, then software will have to manually
1021 * configure the two flow control enable bits in the CTRL register.
1023 * The possible values of the "fc" parameter are:
1024 * 0: Flow control is completely disabled
1025 * 1: Rx flow control is enabled (we can receive pause frames, but
1026 * not send pause frames).
1027 * 2: Tx flow control is enabled (we can send pause frames but we do
1028 * not support receiving pause frames).
1029 * 3: Both Rx and TX flow control (symmetric) are enabled.
1033 /* Flow control is completely disabled by a software over-ride. */
1034 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1036 case e1000_fc_rx_pause:
1037 /* RX Flow control is enabled and TX Flow control is disabled by a
1038 * software over-ride. Since there really isn't a way to advertise
1039 * that we are capable of RX Pause ONLY, we will advertise that we
1040 * support both symmetric and asymmetric RX PAUSE. Later, we will
1041 * disable the adapter's ability to send PAUSE frames.
1043 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1045 case e1000_fc_tx_pause:
1046 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1047 * software over-ride.
1049 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1052 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1053 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1056 DEBUGOUT("Flow control param set incorrectly\n");
1057 return -E1000_ERR_CONFIG;
1061 /* Since auto-negotiation is enabled, take the link out of reset (the link
1062 * will be in reset, because we previously reset the chip). This will
1063 * restart auto-negotiation. If auto-neogtiation is successful then the
1064 * link-up status bit will be set and the flow control enable bits (RFCE
1065 * and TFCE) will be set according to their negotiated value.
1067 DEBUGOUT("Auto-negotiation enabled\n");
1069 E1000_WRITE_REG(hw, TXCW, txcw);
1070 E1000_WRITE_REG(hw, CTRL, ctrl);
1071 E1000_WRITE_FLUSH(hw);
1076 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1077 * indication in the Device Status Register. Time-out if a link isn't
1078 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1079 * less than 500 milliseconds even if the other end is doing it in SW).
1080 * For internal serdes, we just assume a signal is present, then poll.
1082 if(hw->media_type == e1000_media_type_internal_serdes ||
1083 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1084 DEBUGOUT("Looking for Link\n");
1085 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1087 status = E1000_READ_REG(hw, STATUS);
1088 if(status & E1000_STATUS_LU) break;
1090 if(i == (LINK_UP_TIMEOUT / 10)) {
1091 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1092 hw->autoneg_failed = 1;
1093 /* AutoNeg failed to achieve a link, so we'll call
1094 * e1000_check_for_link. This routine will force the link up if
1095 * we detect a signal. This will allow us to communicate with
1096 * non-autonegotiating link partners.
1098 ret_val = e1000_check_for_link(hw);
1100 DEBUGOUT("Error while checking for link\n");
1103 hw->autoneg_failed = 0;
1105 hw->autoneg_failed = 0;
1106 DEBUGOUT("Valid Link Found\n");
1109 DEBUGOUT("No Signal Detected\n");
1111 return E1000_SUCCESS;
1114 /******************************************************************************
1115 * Make sure we have a valid PHY and change PHY mode before link setup.
1117 * hw - Struct containing variables accessed by shared code
1118 ******************************************************************************/
1120 e1000_copper_link_preconfig(struct e1000_hw *hw)
1126 DEBUGFUNC("e1000_copper_link_preconfig");
1128 ctrl = E1000_READ_REG(hw, CTRL);
1129 /* With 82543, we need to force speed and duplex on the MAC equal to what
1130 * the PHY speed and duplex configuration is. In addition, we need to
1131 * perform a hardware reset on the PHY to take it out of reset.
1133 if(hw->mac_type > e1000_82543) {
1134 ctrl |= E1000_CTRL_SLU;
1135 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1136 E1000_WRITE_REG(hw, CTRL, ctrl);
1138 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1139 E1000_WRITE_REG(hw, CTRL, ctrl);
1140 ret_val = e1000_phy_hw_reset(hw);
1145 /* Make sure we have a valid PHY */
1146 ret_val = e1000_detect_gig_phy(hw);
1148 DEBUGOUT("Error, did not detect valid phy.\n");
1151 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1153 /* Set PHY to class A mode (if necessary) */
1154 ret_val = e1000_set_phy_mode(hw);
1158 if((hw->mac_type == e1000_82545_rev_3) ||
1159 (hw->mac_type == e1000_82546_rev_3)) {
1160 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1161 phy_data |= 0x00000008;
1162 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1165 if(hw->mac_type <= e1000_82543 ||
1166 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1167 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1168 hw->phy_reset_disable = FALSE;
1170 return E1000_SUCCESS;
1174 /********************************************************************
1175 * Copper link setup for e1000_phy_igp series.
1177 * hw - Struct containing variables accessed by shared code
1178 *********************************************************************/
1180 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1186 DEBUGFUNC("e1000_copper_link_igp_setup");
1188 if (hw->phy_reset_disable)
1189 return E1000_SUCCESS;
1191 ret_val = e1000_phy_reset(hw);
1193 DEBUGOUT("Error Resetting the PHY\n");
1197 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1200 /* Configure activity LED after PHY reset */
1201 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1202 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1203 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1204 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1206 /* disable lplu d3 during driver init */
1207 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1209 DEBUGOUT("Error Disabling LPLU D3\n");
1213 /* disable lplu d0 during driver init */
1214 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1216 DEBUGOUT("Error Disabling LPLU D0\n");
1219 /* Configure mdi-mdix settings */
1220 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1224 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1225 hw->dsp_config_state = e1000_dsp_config_disabled;
1226 /* Force MDI for earlier revs of the IGP PHY */
1227 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1231 hw->dsp_config_state = e1000_dsp_config_enabled;
1232 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1236 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1239 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1243 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1247 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1251 /* set auto-master slave resolution settings */
1253 e1000_ms_type phy_ms_setting = hw->master_slave;
1255 if(hw->ffe_config_state == e1000_ffe_config_active)
1256 hw->ffe_config_state = e1000_ffe_config_enabled;
1258 if(hw->dsp_config_state == e1000_dsp_config_activated)
1259 hw->dsp_config_state = e1000_dsp_config_enabled;
1261 /* when autonegotiation advertisment is only 1000Mbps then we
1262 * should disable SmartSpeed and enable Auto MasterSlave
1263 * resolution as hardware default. */
1264 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1265 /* Disable SmartSpeed */
1266 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1269 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1270 ret_val = e1000_write_phy_reg(hw,
1271 IGP01E1000_PHY_PORT_CONFIG,
1275 /* Set auto Master/Slave resolution process */
1276 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1279 phy_data &= ~CR_1000T_MS_ENABLE;
1280 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1285 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1289 /* load defaults for future use */
1290 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1291 ((phy_data & CR_1000T_MS_VALUE) ?
1292 e1000_ms_force_master :
1293 e1000_ms_force_slave) :
1296 switch (phy_ms_setting) {
1297 case e1000_ms_force_master:
1298 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1300 case e1000_ms_force_slave:
1301 phy_data |= CR_1000T_MS_ENABLE;
1302 phy_data &= ~(CR_1000T_MS_VALUE);
1305 phy_data &= ~CR_1000T_MS_ENABLE;
1309 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1314 return E1000_SUCCESS;
1318 /********************************************************************
1319 * Copper link setup for e1000_phy_m88 series.
1321 * hw - Struct containing variables accessed by shared code
1322 *********************************************************************/
1324 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1329 DEBUGFUNC("e1000_copper_link_mgp_setup");
1331 if(hw->phy_reset_disable)
1332 return E1000_SUCCESS;
1334 /* Enable CRS on TX. This must be set for half-duplex operation. */
1335 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1339 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1342 * MDI/MDI-X = 0 (default)
1343 * 0 - Auto for all speeds
1346 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1348 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1352 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1355 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1358 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1362 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1367 * disable_polarity_correction = 0 (default)
1368 * Automatic Correction for Reversed Cable Polarity
1372 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1373 if(hw->disable_polarity_correction == 1)
1374 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1375 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1379 /* Force TX_CLK in the Extended PHY Specific Control Register
1382 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1386 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1388 if (hw->phy_revision < M88E1011_I_REV_4) {
1389 /* Configure Master and Slave downshift values */
1390 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1391 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1392 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1393 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1394 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1399 /* SW Reset the PHY so all changes take effect */
1400 ret_val = e1000_phy_reset(hw);
1402 DEBUGOUT("Error Resetting the PHY\n");
1406 return E1000_SUCCESS;
1409 /********************************************************************
1410 * Setup auto-negotiation and flow control advertisements,
1411 * and then perform auto-negotiation.
1413 * hw - Struct containing variables accessed by shared code
1414 *********************************************************************/
1416 e1000_copper_link_autoneg(struct e1000_hw *hw)
1421 DEBUGFUNC("e1000_copper_link_autoneg");
1423 /* Perform some bounds checking on the hw->autoneg_advertised
1424 * parameter. If this variable is zero, then set it to the default.
1426 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1428 /* If autoneg_advertised is zero, we assume it was not defaulted
1429 * by the calling code so we set to advertise full capability.
1431 if(hw->autoneg_advertised == 0)
1432 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1434 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1435 ret_val = e1000_phy_setup_autoneg(hw);
1437 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1440 DEBUGOUT("Restarting Auto-Neg\n");
1442 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1443 * the Auto Neg Restart bit in the PHY control register.
1445 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1449 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1450 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1454 /* Does the user want to wait for Auto-Neg to complete here, or
1455 * check at a later time (for example, callback routine).
1457 if(hw->wait_autoneg_complete) {
1458 ret_val = e1000_wait_autoneg(hw);
1460 DEBUGOUT("Error while waiting for autoneg to complete\n");
1465 hw->get_link_status = TRUE;
1467 return E1000_SUCCESS;
1471 /******************************************************************************
1472 * Config the MAC and the PHY after link is up.
1473 * 1) Set up the MAC to the current PHY speed/duplex
1474 * if we are on 82543. If we
1475 * are on newer silicon, we only need to configure
1476 * collision distance in the Transmit Control Register.
1477 * 2) Set up flow control on the MAC to that established with
1479 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1481 * hw - Struct containing variables accessed by shared code
1482 ******************************************************************************/
1484 e1000_copper_link_postconfig(struct e1000_hw *hw)
1487 DEBUGFUNC("e1000_copper_link_postconfig");
1489 if(hw->mac_type >= e1000_82544) {
1490 e1000_config_collision_dist(hw);
1492 ret_val = e1000_config_mac_to_phy(hw);
1494 DEBUGOUT("Error configuring MAC to PHY settings\n");
1498 ret_val = e1000_config_fc_after_link_up(hw);
1500 DEBUGOUT("Error Configuring Flow Control\n");
1504 /* Config DSP to improve Giga link quality */
1505 if(hw->phy_type == e1000_phy_igp) {
1506 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1508 DEBUGOUT("Error Configuring DSP after link up\n");
1513 return E1000_SUCCESS;
1516 /******************************************************************************
1517 * Detects which PHY is present and setup the speed and duplex
1519 * hw - Struct containing variables accessed by shared code
1520 ******************************************************************************/
1522 e1000_setup_copper_link(struct e1000_hw *hw)
1528 DEBUGFUNC("e1000_setup_copper_link");
1530 /* Check if it is a valid PHY and set PHY mode if necessary. */
1531 ret_val = e1000_copper_link_preconfig(hw);
1535 if (hw->phy_type == e1000_phy_igp ||
1536 hw->phy_type == e1000_phy_igp_2) {
1537 ret_val = e1000_copper_link_igp_setup(hw);
1540 } else if (hw->phy_type == e1000_phy_m88) {
1541 ret_val = e1000_copper_link_mgp_setup(hw);
1547 /* Setup autoneg and flow control advertisement
1548 * and perform autonegotiation */
1549 ret_val = e1000_copper_link_autoneg(hw);
1553 /* PHY will be set to 10H, 10F, 100H,or 100F
1554 * depending on value from forced_speed_duplex. */
1555 DEBUGOUT("Forcing speed and duplex\n");
1556 ret_val = e1000_phy_force_speed_duplex(hw);
1558 DEBUGOUT("Error Forcing Speed and Duplex\n");
1563 /* Check link status. Wait up to 100 microseconds for link to become
1566 for(i = 0; i < 10; i++) {
1567 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1570 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1574 if(phy_data & MII_SR_LINK_STATUS) {
1575 /* Config the MAC and PHY after link is up */
1576 ret_val = e1000_copper_link_postconfig(hw);
1580 DEBUGOUT("Valid link established!!!\n");
1581 return E1000_SUCCESS;
1586 DEBUGOUT("Unable to establish link!!!\n");
1587 return E1000_SUCCESS;
1590 /******************************************************************************
1591 * Configures PHY autoneg and flow control advertisement settings
1593 * hw - Struct containing variables accessed by shared code
1594 ******************************************************************************/
1596 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1599 uint16_t mii_autoneg_adv_reg;
1600 uint16_t mii_1000t_ctrl_reg;
1602 DEBUGFUNC("e1000_phy_setup_autoneg");
1604 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1605 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1609 /* Read the MII 1000Base-T Control Register (Address 9). */
1610 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1614 /* Need to parse both autoneg_advertised and fc and set up
1615 * the appropriate PHY registers. First we will parse for
1616 * autoneg_advertised software override. Since we can advertise
1617 * a plethora of combinations, we need to check each bit
1621 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1622 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1623 * the 1000Base-T Control Register (Address 9).
1625 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1626 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1628 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1630 /* Do we want to advertise 10 Mb Half Duplex? */
1631 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1632 DEBUGOUT("Advertise 10mb Half duplex\n");
1633 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1636 /* Do we want to advertise 10 Mb Full Duplex? */
1637 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1638 DEBUGOUT("Advertise 10mb Full duplex\n");
1639 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1642 /* Do we want to advertise 100 Mb Half Duplex? */
1643 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1644 DEBUGOUT("Advertise 100mb Half duplex\n");
1645 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1648 /* Do we want to advertise 100 Mb Full Duplex? */
1649 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1650 DEBUGOUT("Advertise 100mb Full duplex\n");
1651 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1654 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1655 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1656 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1659 /* Do we want to advertise 1000 Mb Full Duplex? */
1660 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1661 DEBUGOUT("Advertise 1000mb Full duplex\n");
1662 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1665 /* Check for a software override of the flow control settings, and
1666 * setup the PHY advertisement registers accordingly. If
1667 * auto-negotiation is enabled, then software will have to set the
1668 * "PAUSE" bits to the correct value in the Auto-Negotiation
1669 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1671 * The possible values of the "fc" parameter are:
1672 * 0: Flow control is completely disabled
1673 * 1: Rx flow control is enabled (we can receive pause frames
1674 * but not send pause frames).
1675 * 2: Tx flow control is enabled (we can send pause frames
1676 * but we do not support receiving pause frames).
1677 * 3: Both Rx and TX flow control (symmetric) are enabled.
1678 * other: No software override. The flow control configuration
1679 * in the EEPROM is used.
1682 case e1000_fc_none: /* 0 */
1683 /* Flow control (RX & TX) is completely disabled by a
1684 * software over-ride.
1686 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1688 case e1000_fc_rx_pause: /* 1 */
1689 /* RX Flow control is enabled, and TX Flow control is
1690 * disabled, by a software over-ride.
1692 /* Since there really isn't a way to advertise that we are
1693 * capable of RX Pause ONLY, we will advertise that we
1694 * support both symmetric and asymmetric RX PAUSE. Later
1695 * (in e1000_config_fc_after_link_up) we will disable the
1696 *hw's ability to send PAUSE frames.
1698 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1700 case e1000_fc_tx_pause: /* 2 */
1701 /* TX Flow control is enabled, and RX Flow control is
1702 * disabled, by a software over-ride.
1704 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1705 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1707 case e1000_fc_full: /* 3 */
1708 /* Flow control (both RX and TX) is enabled by a software
1711 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1714 DEBUGOUT("Flow control param set incorrectly\n");
1715 return -E1000_ERR_CONFIG;
1718 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1722 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1724 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1728 return E1000_SUCCESS;
1731 /******************************************************************************
1732 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1734 * hw - Struct containing variables accessed by shared code
1735 ******************************************************************************/
1737 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1741 uint16_t mii_ctrl_reg;
1742 uint16_t mii_status_reg;
1746 DEBUGFUNC("e1000_phy_force_speed_duplex");
1748 /* Turn off Flow control if we are forcing speed and duplex. */
1749 hw->fc = e1000_fc_none;
1751 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1753 /* Read the Device Control Register. */
1754 ctrl = E1000_READ_REG(hw, CTRL);
1756 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1757 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1758 ctrl &= ~(DEVICE_SPEED_MASK);
1760 /* Clear the Auto Speed Detect Enable bit. */
1761 ctrl &= ~E1000_CTRL_ASDE;
1763 /* Read the MII Control Register. */
1764 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1768 /* We need to disable autoneg in order to force link and duplex. */
1770 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1772 /* Are we forcing Full or Half Duplex? */
1773 if(hw->forced_speed_duplex == e1000_100_full ||
1774 hw->forced_speed_duplex == e1000_10_full) {
1775 /* We want to force full duplex so we SET the full duplex bits in the
1776 * Device and MII Control Registers.
1778 ctrl |= E1000_CTRL_FD;
1779 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1780 DEBUGOUT("Full Duplex\n");
1782 /* We want to force half duplex so we CLEAR the full duplex bits in
1783 * the Device and MII Control Registers.
1785 ctrl &= ~E1000_CTRL_FD;
1786 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1787 DEBUGOUT("Half Duplex\n");
1790 /* Are we forcing 100Mbps??? */
1791 if(hw->forced_speed_duplex == e1000_100_full ||
1792 hw->forced_speed_duplex == e1000_100_half) {
1793 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1794 ctrl |= E1000_CTRL_SPD_100;
1795 mii_ctrl_reg |= MII_CR_SPEED_100;
1796 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1797 DEBUGOUT("Forcing 100mb ");
1799 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1800 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1801 mii_ctrl_reg |= MII_CR_SPEED_10;
1802 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1803 DEBUGOUT("Forcing 10mb ");
1806 e1000_config_collision_dist(hw);
1808 /* Write the configured values back to the Device Control Reg. */
1809 E1000_WRITE_REG(hw, CTRL, ctrl);
1811 if (hw->phy_type == e1000_phy_m88) {
1812 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1816 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1817 * forced whenever speed are duplex are forced.
1819 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1820 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1824 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1826 /* Need to reset the PHY or these changes will be ignored */
1827 mii_ctrl_reg |= MII_CR_RESET;
1829 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1830 * forced whenever speed or duplex are forced.
1832 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1836 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1837 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1839 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1844 /* Write back the modified PHY MII control register. */
1845 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1851 /* The wait_autoneg_complete flag may be a little misleading here.
1852 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1853 * But we do want to delay for a period while forcing only so we
1854 * don't generate false No Link messages. So we will wait here
1855 * only if the user has set wait_autoneg_complete to 1, which is
1858 if(hw->wait_autoneg_complete) {
1859 /* We will wait for autoneg to complete. */
1860 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1863 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1864 for(i = PHY_FORCE_TIME; i > 0; i--) {
1865 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1868 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1872 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1876 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1880 (hw->phy_type == e1000_phy_m88)) {
1881 /* We didn't get link. Reset the DSP and wait again for link. */
1882 ret_val = e1000_phy_reset_dsp(hw);
1884 DEBUGOUT("Error Resetting PHY DSP\n");
1888 /* This loop will early-out if the link condition has been met. */
1889 for(i = PHY_FORCE_TIME; i > 0; i--) {
1890 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1892 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1895 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1899 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1905 if (hw->phy_type == e1000_phy_m88) {
1906 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1907 * Extended PHY Specific Control Register to 25MHz clock. This value
1908 * defaults back to a 2.5MHz clock when the PHY is reset.
1910 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1914 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1915 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1919 /* In addition, because of the s/w reset above, we need to enable CRS on
1920 * TX. This must be set for both full and half duplex operation.
1922 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1926 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1927 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1931 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
1933 (hw->forced_speed_duplex == e1000_10_full ||
1934 hw->forced_speed_duplex == e1000_10_half)) {
1935 ret_val = e1000_polarity_reversal_workaround(hw);
1940 return E1000_SUCCESS;
1943 /******************************************************************************
1944 * Sets the collision distance in the Transmit Control register
1946 * hw - Struct containing variables accessed by shared code
1948 * Link should have been established previously. Reads the speed and duplex
1949 * information from the Device Status register.
1950 ******************************************************************************/
1952 e1000_config_collision_dist(struct e1000_hw *hw)
1954 uint32_t tctl, coll_dist;
1956 DEBUGFUNC("e1000_config_collision_dist");
1958 if (hw->mac_type < e1000_82543)
1959 coll_dist = E1000_COLLISION_DISTANCE_82542;
1961 coll_dist = E1000_COLLISION_DISTANCE;
1963 tctl = E1000_READ_REG(hw, TCTL);
1965 tctl &= ~E1000_TCTL_COLD;
1966 tctl |= coll_dist << E1000_COLD_SHIFT;
1968 E1000_WRITE_REG(hw, TCTL, tctl);
1969 E1000_WRITE_FLUSH(hw);
1972 /******************************************************************************
1973 * Sets MAC speed and duplex settings to reflect the those in the PHY
1975 * hw - Struct containing variables accessed by shared code
1976 * mii_reg - data to write to the MII control register
1978 * The contents of the PHY register containing the needed information need to
1980 ******************************************************************************/
1982 e1000_config_mac_to_phy(struct e1000_hw *hw)
1988 DEBUGFUNC("e1000_config_mac_to_phy");
1990 /* 82544 or newer MAC, Auto Speed Detection takes care of
1991 * MAC speed/duplex configuration.*/
1992 if (hw->mac_type >= e1000_82544)
1993 return E1000_SUCCESS;
1995 /* Read the Device Control Register and set the bits to Force Speed
1998 ctrl = E1000_READ_REG(hw, CTRL);
1999 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2000 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2002 /* Set up duplex in the Device Control and Transmit Control
2003 * registers depending on negotiated values.
2005 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2009 if(phy_data & M88E1000_PSSR_DPLX)
2010 ctrl |= E1000_CTRL_FD;
2012 ctrl &= ~E1000_CTRL_FD;
2014 e1000_config_collision_dist(hw);
2016 /* Set up speed in the Device Control register depending on
2017 * negotiated values.
2019 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2020 ctrl |= E1000_CTRL_SPD_1000;
2021 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2022 ctrl |= E1000_CTRL_SPD_100;
2024 /* Write the configured values back to the Device Control Reg. */
2025 E1000_WRITE_REG(hw, CTRL, ctrl);
2026 return E1000_SUCCESS;
2029 /******************************************************************************
2030 * Forces the MAC's flow control settings.
2032 * hw - Struct containing variables accessed by shared code
2034 * Sets the TFCE and RFCE bits in the device control register to reflect
2035 * the adapter settings. TFCE and RFCE need to be explicitly set by
2036 * software when a Copper PHY is used because autonegotiation is managed
2037 * by the PHY rather than the MAC. Software must also configure these
2038 * bits when link is forced on a fiber connection.
2039 *****************************************************************************/
2041 e1000_force_mac_fc(struct e1000_hw *hw)
2045 DEBUGFUNC("e1000_force_mac_fc");
2047 /* Get the current configuration of the Device Control Register */
2048 ctrl = E1000_READ_REG(hw, CTRL);
2050 /* Because we didn't get link via the internal auto-negotiation
2051 * mechanism (we either forced link or we got link via PHY
2052 * auto-neg), we have to manually enable/disable transmit an
2053 * receive flow control.
2055 * The "Case" statement below enables/disable flow control
2056 * according to the "hw->fc" parameter.
2058 * The possible values of the "fc" parameter are:
2059 * 0: Flow control is completely disabled
2060 * 1: Rx flow control is enabled (we can receive pause
2061 * frames but not send pause frames).
2062 * 2: Tx flow control is enabled (we can send pause frames
2063 * frames but we do not receive pause frames).
2064 * 3: Both Rx and TX flow control (symmetric) is enabled.
2065 * other: No other values should be possible at this point.
2070 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2072 case e1000_fc_rx_pause:
2073 ctrl &= (~E1000_CTRL_TFCE);
2074 ctrl |= E1000_CTRL_RFCE;
2076 case e1000_fc_tx_pause:
2077 ctrl &= (~E1000_CTRL_RFCE);
2078 ctrl |= E1000_CTRL_TFCE;
2081 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2084 DEBUGOUT("Flow control param set incorrectly\n");
2085 return -E1000_ERR_CONFIG;
2088 /* Disable TX Flow Control for 82542 (rev 2.0) */
2089 if(hw->mac_type == e1000_82542_rev2_0)
2090 ctrl &= (~E1000_CTRL_TFCE);
2092 E1000_WRITE_REG(hw, CTRL, ctrl);
2093 return E1000_SUCCESS;
2096 /******************************************************************************
2097 * Configures flow control settings after link is established
2099 * hw - Struct containing variables accessed by shared code
2101 * Should be called immediately after a valid link has been established.
2102 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2103 * and autonegotiation is enabled, the MAC flow control settings will be set
2104 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2105 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2106 *****************************************************************************/
2108 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2111 uint16_t mii_status_reg;
2112 uint16_t mii_nway_adv_reg;
2113 uint16_t mii_nway_lp_ability_reg;
2117 DEBUGFUNC("e1000_config_fc_after_link_up");
2119 /* Check for the case where we have fiber media and auto-neg failed
2120 * so we had to force link. In this case, we need to force the
2121 * configuration of the MAC to match the "fc" parameter.
2123 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2124 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
2125 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2126 ret_val = e1000_force_mac_fc(hw);
2128 DEBUGOUT("Error forcing flow control settings\n");
2133 /* Check for the case where we have copper media and auto-neg is
2134 * enabled. In this case, we need to check and see if Auto-Neg
2135 * has completed, and if so, how the PHY and link partner has
2136 * flow control configured.
2138 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2139 /* Read the MII Status Register and check to see if AutoNeg
2140 * has completed. We read this twice because this reg has
2141 * some "sticky" (latched) bits.
2143 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2146 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2150 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2151 /* The AutoNeg process has completed, so we now need to
2152 * read both the Auto Negotiation Advertisement Register
2153 * (Address 4) and the Auto_Negotiation Base Page Ability
2154 * Register (Address 5) to determine how flow control was
2157 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2161 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2162 &mii_nway_lp_ability_reg);
2166 /* Two bits in the Auto Negotiation Advertisement Register
2167 * (Address 4) and two bits in the Auto Negotiation Base
2168 * Page Ability Register (Address 5) determine flow control
2169 * for both the PHY and the link partner. The following
2170 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2171 * 1999, describes these PAUSE resolution bits and how flow
2172 * control is determined based upon these settings.
2173 * NOTE: DC = Don't Care
2175 * LOCAL DEVICE | LINK PARTNER
2176 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2177 *-------|---------|-------|---------|--------------------
2178 * 0 | 0 | DC | DC | e1000_fc_none
2179 * 0 | 1 | 0 | DC | e1000_fc_none
2180 * 0 | 1 | 1 | 0 | e1000_fc_none
2181 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2182 * 1 | 0 | 0 | DC | e1000_fc_none
2183 * 1 | DC | 1 | DC | e1000_fc_full
2184 * 1 | 1 | 0 | 0 | e1000_fc_none
2185 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2188 /* Are both PAUSE bits set to 1? If so, this implies
2189 * Symmetric Flow Control is enabled at both ends. The
2190 * ASM_DIR bits are irrelevant per the spec.
2192 * For Symmetric Flow Control:
2194 * LOCAL DEVICE | LINK PARTNER
2195 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2196 *-------|---------|-------|---------|--------------------
2197 * 1 | DC | 1 | DC | e1000_fc_full
2200 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2201 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2202 /* Now we need to check if the user selected RX ONLY
2203 * of pause frames. In this case, we had to advertise
2204 * FULL flow control because we could not advertise RX
2205 * ONLY. Hence, we must now check to see if we need to
2206 * turn OFF the TRANSMISSION of PAUSE frames.
2208 if(hw->original_fc == e1000_fc_full) {
2209 hw->fc = e1000_fc_full;
2210 DEBUGOUT("Flow Control = FULL.\r\n");
2212 hw->fc = e1000_fc_rx_pause;
2213 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2216 /* For receiving PAUSE frames ONLY.
2218 * LOCAL DEVICE | LINK PARTNER
2219 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2220 *-------|---------|-------|---------|--------------------
2221 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2224 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2225 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2226 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2227 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2228 hw->fc = e1000_fc_tx_pause;
2229 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2231 /* For transmitting PAUSE frames ONLY.
2233 * LOCAL DEVICE | LINK PARTNER
2234 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2235 *-------|---------|-------|---------|--------------------
2236 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2239 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2240 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2241 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2242 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2243 hw->fc = e1000_fc_rx_pause;
2244 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2246 /* Per the IEEE spec, at this point flow control should be
2247 * disabled. However, we want to consider that we could
2248 * be connected to a legacy switch that doesn't advertise
2249 * desired flow control, but can be forced on the link
2250 * partner. So if we advertised no flow control, that is
2251 * what we will resolve to. If we advertised some kind of
2252 * receive capability (Rx Pause Only or Full Flow Control)
2253 * and the link partner advertised none, we will configure
2254 * ourselves to enable Rx Flow Control only. We can do
2255 * this safely for two reasons: If the link partner really
2256 * didn't want flow control enabled, and we enable Rx, no
2257 * harm done since we won't be receiving any PAUSE frames
2258 * anyway. If the intent on the link partner was to have
2259 * flow control enabled, then by us enabling RX only, we
2260 * can at least receive pause frames and process them.
2261 * This is a good idea because in most cases, since we are
2262 * predominantly a server NIC, more times than not we will
2263 * be asked to delay transmission of packets than asking
2264 * our link partner to pause transmission of frames.
2266 else if((hw->original_fc == e1000_fc_none ||
2267 hw->original_fc == e1000_fc_tx_pause) ||
2268 hw->fc_strict_ieee) {
2269 hw->fc = e1000_fc_none;
2270 DEBUGOUT("Flow Control = NONE.\r\n");
2272 hw->fc = e1000_fc_rx_pause;
2273 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2276 /* Now we need to do one last check... If we auto-
2277 * negotiated to HALF DUPLEX, flow control should not be
2278 * enabled per IEEE 802.3 spec.
2280 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2282 DEBUGOUT("Error getting link speed and duplex\n");
2286 if(duplex == HALF_DUPLEX)
2287 hw->fc = e1000_fc_none;
2289 /* Now we call a subroutine to actually force the MAC
2290 * controller to use the correct flow control settings.
2292 ret_val = e1000_force_mac_fc(hw);
2294 DEBUGOUT("Error forcing flow control settings\n");
2298 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2301 return E1000_SUCCESS;
2304 /******************************************************************************
2305 * Checks to see if the link status of the hardware has changed.
2307 * hw - Struct containing variables accessed by shared code
2309 * Called by any function that needs to check the link status of the adapter.
2310 *****************************************************************************/
2312 e1000_check_for_link(struct e1000_hw *hw)
2319 uint32_t signal = 0;
2323 DEBUGFUNC("e1000_check_for_link");
2325 ctrl = E1000_READ_REG(hw, CTRL);
2326 status = E1000_READ_REG(hw, STATUS);
2328 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2329 * set when the optics detect a signal. On older adapters, it will be
2330 * cleared when there is a signal. This applies to fiber media only.
2332 if((hw->media_type == e1000_media_type_fiber) ||
2333 (hw->media_type == e1000_media_type_internal_serdes)) {
2334 rxcw = E1000_READ_REG(hw, RXCW);
2336 if(hw->media_type == e1000_media_type_fiber) {
2337 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2338 if(status & E1000_STATUS_LU)
2339 hw->get_link_status = FALSE;
2343 /* If we have a copper PHY then we only want to go out to the PHY
2344 * registers to see if Auto-Neg has completed and/or if our link
2345 * status has changed. The get_link_status flag will be set if we
2346 * receive a Link Status Change interrupt or we have Rx Sequence
2349 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2350 /* First we want to see if the MII Status Register reports
2351 * link. If so, then we want to get the current speed/duplex
2353 * Read the register twice since the link bit is sticky.
2355 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2358 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2362 if(phy_data & MII_SR_LINK_STATUS) {
2363 hw->get_link_status = FALSE;
2364 /* Check if there was DownShift, must be checked immediately after
2366 e1000_check_downshift(hw);
2368 /* If we are on 82544 or 82543 silicon and speed/duplex
2369 * are forced to 10H or 10F, then we will implement the polarity
2370 * reversal workaround. We disable interrupts first, and upon
2371 * returning, place the devices interrupt state to its previous
2372 * value except for the link status change interrupt which will
2373 * happen due to the execution of this workaround.
2376 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2378 (hw->forced_speed_duplex == e1000_10_full ||
2379 hw->forced_speed_duplex == e1000_10_half)) {
2380 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2381 ret_val = e1000_polarity_reversal_workaround(hw);
2382 icr = E1000_READ_REG(hw, ICR);
2383 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2384 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2388 /* No link detected */
2389 e1000_config_dsp_after_link_change(hw, FALSE);
2393 /* If we are forcing speed/duplex, then we simply return since
2394 * we have already determined whether we have link or not.
2396 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2398 /* optimize the dsp settings for the igp phy */
2399 e1000_config_dsp_after_link_change(hw, TRUE);
2401 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2402 * have Si on board that is 82544 or newer, Auto
2403 * Speed Detection takes care of MAC speed/duplex
2404 * configuration. So we only need to configure Collision
2405 * Distance in the MAC. Otherwise, we need to force
2406 * speed/duplex on the MAC to the current PHY speed/duplex
2409 if(hw->mac_type >= e1000_82544)
2410 e1000_config_collision_dist(hw);
2412 ret_val = e1000_config_mac_to_phy(hw);
2414 DEBUGOUT("Error configuring MAC to PHY settings\n");
2419 /* Configure Flow Control now that Auto-Neg has completed. First, we
2420 * need to restore the desired flow control settings because we may
2421 * have had to re-autoneg with a different link partner.
2423 ret_val = e1000_config_fc_after_link_up(hw);
2425 DEBUGOUT("Error configuring flow control\n");
2429 /* At this point we know that we are on copper and we have
2430 * auto-negotiated link. These are conditions for checking the link
2431 * partner capability register. We use the link speed to determine if
2432 * TBI compatibility needs to be turned on or off. If the link is not
2433 * at gigabit speed, then TBI compatibility is not needed. If we are
2434 * at gigabit speed, we turn on TBI compatibility.
2436 if(hw->tbi_compatibility_en) {
2437 uint16_t speed, duplex;
2438 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2439 if(speed != SPEED_1000) {
2440 /* If link speed is not set to gigabit speed, we do not need
2441 * to enable TBI compatibility.
2443 if(hw->tbi_compatibility_on) {
2444 /* If we previously were in the mode, turn it off. */
2445 rctl = E1000_READ_REG(hw, RCTL);
2446 rctl &= ~E1000_RCTL_SBP;
2447 E1000_WRITE_REG(hw, RCTL, rctl);
2448 hw->tbi_compatibility_on = FALSE;
2451 /* If TBI compatibility is was previously off, turn it on. For
2452 * compatibility with a TBI link partner, we will store bad
2453 * packets. Some frames have an additional byte on the end and
2454 * will look like CRC errors to to the hardware.
2456 if(!hw->tbi_compatibility_on) {
2457 hw->tbi_compatibility_on = TRUE;
2458 rctl = E1000_READ_REG(hw, RCTL);
2459 rctl |= E1000_RCTL_SBP;
2460 E1000_WRITE_REG(hw, RCTL, rctl);
2465 /* If we don't have link (auto-negotiation failed or link partner cannot
2466 * auto-negotiate), the cable is plugged in (we have signal), and our
2467 * link partner is not trying to auto-negotiate with us (we are receiving
2468 * idles or data), we need to force link up. We also need to give
2469 * auto-negotiation time to complete, in case the cable was just plugged
2470 * in. The autoneg_failed flag does this.
2472 else if((((hw->media_type == e1000_media_type_fiber) &&
2473 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2474 (hw->media_type == e1000_media_type_internal_serdes)) &&
2475 (!(status & E1000_STATUS_LU)) &&
2476 (!(rxcw & E1000_RXCW_C))) {
2477 if(hw->autoneg_failed == 0) {
2478 hw->autoneg_failed = 1;
2481 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2483 /* Disable auto-negotiation in the TXCW register */
2484 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2486 /* Force link-up and also force full-duplex. */
2487 ctrl = E1000_READ_REG(hw, CTRL);
2488 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2489 E1000_WRITE_REG(hw, CTRL, ctrl);
2491 /* Configure Flow Control after forcing link up. */
2492 ret_val = e1000_config_fc_after_link_up(hw);
2494 DEBUGOUT("Error configuring flow control\n");
2498 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2499 * auto-negotiation in the TXCW register and disable forced link in the
2500 * Device Control register in an attempt to auto-negotiate with our link
2503 else if(((hw->media_type == e1000_media_type_fiber) ||
2504 (hw->media_type == e1000_media_type_internal_serdes)) &&
2505 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2506 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2507 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2508 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2510 hw->serdes_link_down = FALSE;
2512 /* If we force link for non-auto-negotiation switch, check link status
2513 * based on MAC synchronization for internal serdes media type.
2515 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2516 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2517 /* SYNCH bit and IV bit are sticky. */
2519 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2520 if(!(rxcw & E1000_RXCW_IV)) {
2521 hw->serdes_link_down = FALSE;
2522 DEBUGOUT("SERDES: Link is up.\n");
2525 hw->serdes_link_down = TRUE;
2526 DEBUGOUT("SERDES: Link is down.\n");
2529 if((hw->media_type == e1000_media_type_internal_serdes) &&
2530 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2531 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2533 return E1000_SUCCESS;
2536 /******************************************************************************
2537 * Detects the current speed and duplex settings of the hardware.
2539 * hw - Struct containing variables accessed by shared code
2540 * speed - Speed of the connection
2541 * duplex - Duplex setting of the connection
2542 *****************************************************************************/
2544 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2552 DEBUGFUNC("e1000_get_speed_and_duplex");
2554 if(hw->mac_type >= e1000_82543) {
2555 status = E1000_READ_REG(hw, STATUS);
2556 if(status & E1000_STATUS_SPEED_1000) {
2557 *speed = SPEED_1000;
2558 DEBUGOUT("1000 Mbs, ");
2559 } else if(status & E1000_STATUS_SPEED_100) {
2561 DEBUGOUT("100 Mbs, ");
2564 DEBUGOUT("10 Mbs, ");
2567 if(status & E1000_STATUS_FD) {
2568 *duplex = FULL_DUPLEX;
2569 DEBUGOUT("Full Duplex\r\n");
2571 *duplex = HALF_DUPLEX;
2572 DEBUGOUT(" Half Duplex\r\n");
2575 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2576 *speed = SPEED_1000;
2577 *duplex = FULL_DUPLEX;
2580 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2581 * if it is operating at half duplex. Here we set the duplex settings to
2582 * match the duplex in the link partner's capabilities.
2584 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2585 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2589 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2590 *duplex = HALF_DUPLEX;
2592 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2595 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2596 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2597 *duplex = HALF_DUPLEX;
2601 return E1000_SUCCESS;
2604 /******************************************************************************
2605 * Blocks until autoneg completes or times out (~4.5 seconds)
2607 * hw - Struct containing variables accessed by shared code
2608 ******************************************************************************/
2610 e1000_wait_autoneg(struct e1000_hw *hw)
2616 DEBUGFUNC("e1000_wait_autoneg");
2617 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2619 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2620 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2621 /* Read the MII Status Register and wait for Auto-Neg
2622 * Complete bit to be set.
2624 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2627 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2630 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2631 return E1000_SUCCESS;
2635 return E1000_SUCCESS;
2638 /******************************************************************************
2639 * Raises the Management Data Clock
2641 * hw - Struct containing variables accessed by shared code
2642 * ctrl - Device control register's current value
2643 ******************************************************************************/
2645 e1000_raise_mdi_clk(struct e1000_hw *hw,
2648 /* Raise the clock input to the Management Data Clock (by setting the MDC
2649 * bit), and then delay 10 microseconds.
2651 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2652 E1000_WRITE_FLUSH(hw);
2656 /******************************************************************************
2657 * Lowers the Management Data Clock
2659 * hw - Struct containing variables accessed by shared code
2660 * ctrl - Device control register's current value
2661 ******************************************************************************/
2663 e1000_lower_mdi_clk(struct e1000_hw *hw,
2666 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2667 * bit), and then delay 10 microseconds.
2669 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2670 E1000_WRITE_FLUSH(hw);
2674 /******************************************************************************
2675 * Shifts data bits out to the PHY
2677 * hw - Struct containing variables accessed by shared code
2678 * data - Data to send out to the PHY
2679 * count - Number of bits to shift out
2681 * Bits are shifted out in MSB to LSB order.
2682 ******************************************************************************/
2684 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2691 /* We need to shift "count" number of bits out to the PHY. So, the value
2692 * in the "data" parameter will be shifted out to the PHY one bit at a
2693 * time. In order to do this, "data" must be broken down into bits.
2696 mask <<= (count - 1);
2698 ctrl = E1000_READ_REG(hw, CTRL);
2700 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2701 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2704 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2705 * then raising and lowering the Management Data Clock. A "0" is
2706 * shifted out to the PHY by setting the MDIO bit to "0" and then
2707 * raising and lowering the clock.
2709 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2710 else ctrl &= ~E1000_CTRL_MDIO;
2712 E1000_WRITE_REG(hw, CTRL, ctrl);
2713 E1000_WRITE_FLUSH(hw);
2717 e1000_raise_mdi_clk(hw, &ctrl);
2718 e1000_lower_mdi_clk(hw, &ctrl);
2724 /******************************************************************************
2725 * Shifts data bits in from the PHY
2727 * hw - Struct containing variables accessed by shared code
2729 * Bits are shifted in in MSB to LSB order.
2730 ******************************************************************************/
2732 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2738 /* In order to read a register from the PHY, we need to shift in a total
2739 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2740 * to avoid contention on the MDIO pin when a read operation is performed.
2741 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2742 * by raising the input to the Management Data Clock (setting the MDC bit),
2743 * and then reading the value of the MDIO bit.
2745 ctrl = E1000_READ_REG(hw, CTRL);
2747 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2748 ctrl &= ~E1000_CTRL_MDIO_DIR;
2749 ctrl &= ~E1000_CTRL_MDIO;
2751 E1000_WRITE_REG(hw, CTRL, ctrl);
2752 E1000_WRITE_FLUSH(hw);
2754 /* Raise and Lower the clock before reading in the data. This accounts for
2755 * the turnaround bits. The first clock occurred when we clocked out the
2756 * last bit of the Register Address.
2758 e1000_raise_mdi_clk(hw, &ctrl);
2759 e1000_lower_mdi_clk(hw, &ctrl);
2761 for(data = 0, i = 0; i < 16; i++) {
2763 e1000_raise_mdi_clk(hw, &ctrl);
2764 ctrl = E1000_READ_REG(hw, CTRL);
2765 /* Check to see if we shifted in a "1". */
2766 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2767 e1000_lower_mdi_clk(hw, &ctrl);
2770 e1000_raise_mdi_clk(hw, &ctrl);
2771 e1000_lower_mdi_clk(hw, &ctrl);
2776 /*****************************************************************************
2777 * Reads the value from a PHY register, if the value is on a specific non zero
2778 * page, sets the page first.
2779 * hw - Struct containing variables accessed by shared code
2780 * reg_addr - address of the PHY register to read
2781 ******************************************************************************/
2783 e1000_read_phy_reg(struct e1000_hw *hw,
2789 DEBUGFUNC("e1000_read_phy_reg");
2791 if((hw->phy_type == e1000_phy_igp ||
2792 hw->phy_type == e1000_phy_igp_2) &&
2793 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2794 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2795 (uint16_t)reg_addr);
2801 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2808 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2814 const uint32_t phy_addr = 1;
2816 DEBUGFUNC("e1000_read_phy_reg_ex");
2818 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2819 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2820 return -E1000_ERR_PARAM;
2823 if(hw->mac_type > e1000_82543) {
2824 /* Set up Op-code, Phy Address, and register address in the MDI
2825 * Control register. The MAC will take care of interfacing with the
2826 * PHY to retrieve the desired data.
2828 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2829 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2830 (E1000_MDIC_OP_READ));
2832 E1000_WRITE_REG(hw, MDIC, mdic);
2834 /* Poll the ready bit to see if the MDI read completed */
2835 for(i = 0; i < 64; i++) {
2837 mdic = E1000_READ_REG(hw, MDIC);
2838 if(mdic & E1000_MDIC_READY) break;
2840 if(!(mdic & E1000_MDIC_READY)) {
2841 DEBUGOUT("MDI Read did not complete\n");
2842 return -E1000_ERR_PHY;
2844 if(mdic & E1000_MDIC_ERROR) {
2845 DEBUGOUT("MDI Error\n");
2846 return -E1000_ERR_PHY;
2848 *phy_data = (uint16_t) mdic;
2850 /* We must first send a preamble through the MDIO pin to signal the
2851 * beginning of an MII instruction. This is done by sending 32
2852 * consecutive "1" bits.
2854 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2856 /* Now combine the next few fields that are required for a read
2857 * operation. We use this method instead of calling the
2858 * e1000_shift_out_mdi_bits routine five different times. The format of
2859 * a MII read instruction consists of a shift out of 14 bits and is
2860 * defined as follows:
2861 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2862 * followed by a shift in of 18 bits. This first two bits shifted in
2863 * are TurnAround bits used to avoid contention on the MDIO pin when a
2864 * READ operation is performed. These two bits are thrown away
2865 * followed by a shift in of 16 bits which contains the desired data.
2867 mdic = ((reg_addr) | (phy_addr << 5) |
2868 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2870 e1000_shift_out_mdi_bits(hw, mdic, 14);
2872 /* Now that we've shifted out the read command to the MII, we need to
2873 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2876 *phy_data = e1000_shift_in_mdi_bits(hw);
2878 return E1000_SUCCESS;
2881 /******************************************************************************
2882 * Writes a value to a PHY register
2884 * hw - Struct containing variables accessed by shared code
2885 * reg_addr - address of the PHY register to write
2886 * data - data to write to the PHY
2887 ******************************************************************************/
2889 e1000_write_phy_reg(struct e1000_hw *hw,
2895 DEBUGFUNC("e1000_write_phy_reg");
2897 if((hw->phy_type == e1000_phy_igp ||
2898 hw->phy_type == e1000_phy_igp_2) &&
2899 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2900 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2901 (uint16_t)reg_addr);
2907 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2914 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2920 const uint32_t phy_addr = 1;
2922 DEBUGFUNC("e1000_write_phy_reg_ex");
2924 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2925 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2926 return -E1000_ERR_PARAM;
2929 if(hw->mac_type > e1000_82543) {
2930 /* Set up Op-code, Phy Address, register address, and data intended
2931 * for the PHY register in the MDI Control register. The MAC will take
2932 * care of interfacing with the PHY to send the desired data.
2934 mdic = (((uint32_t) phy_data) |
2935 (reg_addr << E1000_MDIC_REG_SHIFT) |
2936 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2937 (E1000_MDIC_OP_WRITE));
2939 E1000_WRITE_REG(hw, MDIC, mdic);
2941 /* Poll the ready bit to see if the MDI read completed */
2942 for(i = 0; i < 640; i++) {
2944 mdic = E1000_READ_REG(hw, MDIC);
2945 if(mdic & E1000_MDIC_READY) break;
2947 if(!(mdic & E1000_MDIC_READY)) {
2948 DEBUGOUT("MDI Write did not complete\n");
2949 return -E1000_ERR_PHY;
2952 /* We'll need to use the SW defined pins to shift the write command
2953 * out to the PHY. We first send a preamble to the PHY to signal the
2954 * beginning of the MII instruction. This is done by sending 32
2955 * consecutive "1" bits.
2957 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2959 /* Now combine the remaining required fields that will indicate a
2960 * write operation. We use this method instead of calling the
2961 * e1000_shift_out_mdi_bits routine for each field in the command. The
2962 * format of a MII write instruction is as follows:
2963 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2965 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2966 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2968 mdic |= (uint32_t) phy_data;
2970 e1000_shift_out_mdi_bits(hw, mdic, 32);
2973 return E1000_SUCCESS;
2977 /******************************************************************************
2978 * Returns the PHY to the power-on reset state
2980 * hw - Struct containing variables accessed by shared code
2981 ******************************************************************************/
2983 e1000_phy_hw_reset(struct e1000_hw *hw)
2985 uint32_t ctrl, ctrl_ext;
2989 DEBUGFUNC("e1000_phy_hw_reset");
2991 /* In the case of the phy reset being blocked, it's not an error, we
2992 * simply return success without performing the reset. */
2993 ret_val = e1000_check_phy_reset_block(hw);
2995 return E1000_SUCCESS;
2997 DEBUGOUT("Resetting Phy...\n");
2999 if(hw->mac_type > e1000_82543) {
3000 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3001 * bit. Then, take it out of reset.
3002 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3003 * and deassert. For e1000_82571 hardware and later, we instead delay
3004 * for 10ms after the deassertion.
3006 ctrl = E1000_READ_REG(hw, CTRL);
3007 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3008 E1000_WRITE_FLUSH(hw);
3010 if (hw->mac_type < e1000_82571)
3015 E1000_WRITE_REG(hw, CTRL, ctrl);
3016 E1000_WRITE_FLUSH(hw);
3018 if (hw->mac_type >= e1000_82571)
3021 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3022 * bit to put the PHY into reset. Then, take it out of reset.
3024 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3025 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3026 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3027 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3028 E1000_WRITE_FLUSH(hw);
3030 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3031 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3032 E1000_WRITE_FLUSH(hw);
3036 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3037 /* Configure activity LED after PHY reset */
3038 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3039 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3040 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3041 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3044 /* Wait for FW to finish PHY configuration. */
3045 ret_val = e1000_get_phy_cfg_done(hw);
3050 /******************************************************************************
3053 * hw - Struct containing variables accessed by shared code
3055 * Sets bit 15 of the MII Control regiser
3056 ******************************************************************************/
3058 e1000_phy_reset(struct e1000_hw *hw)
3063 DEBUGFUNC("e1000_phy_reset");
3065 /* In the case of the phy reset being blocked, it's not an error, we
3066 * simply return success without performing the reset. */
3067 ret_val = e1000_check_phy_reset_block(hw);
3069 return E1000_SUCCESS;
3071 switch (hw->mac_type) {
3072 case e1000_82541_rev_2:
3075 ret_val = e1000_phy_hw_reset(hw);
3080 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3084 phy_data |= MII_CR_RESET;
3085 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3093 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3094 e1000_phy_init_script(hw);
3096 return E1000_SUCCESS;
3099 /******************************************************************************
3100 * Probes the expected PHY address for known PHY IDs
3102 * hw - Struct containing variables accessed by shared code
3103 ******************************************************************************/
3105 e1000_detect_gig_phy(struct e1000_hw *hw)
3107 int32_t phy_init_status, ret_val;
3108 uint16_t phy_id_high, phy_id_low;
3109 boolean_t match = FALSE;
3111 DEBUGFUNC("e1000_detect_gig_phy");
3113 /* The 82571 firmware may still be configuring the PHY. In this
3114 * case, we cannot access the PHY until the configuration is done. So
3115 * we explicitly set the PHY values. */
3116 if(hw->mac_type == e1000_82571 ||
3117 hw->mac_type == e1000_82572) {
3118 hw->phy_id = IGP01E1000_I_PHY_ID;
3119 hw->phy_type = e1000_phy_igp_2;
3120 return E1000_SUCCESS;
3123 /* Read the PHY ID Registers to identify which PHY is onboard. */
3124 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3128 hw->phy_id = (uint32_t) (phy_id_high << 16);
3130 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3134 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3135 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3137 switch(hw->mac_type) {
3139 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3142 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3146 case e1000_82545_rev_3:
3148 case e1000_82546_rev_3:
3149 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3152 case e1000_82541_rev_2:
3154 case e1000_82547_rev_2:
3155 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3158 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3161 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3162 return -E1000_ERR_CONFIG;
3164 phy_init_status = e1000_set_phy_type(hw);
3166 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3167 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3168 return E1000_SUCCESS;
3170 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3171 return -E1000_ERR_PHY;
3174 /******************************************************************************
3175 * Resets the PHY's DSP
3177 * hw - Struct containing variables accessed by shared code
3178 ******************************************************************************/
3180 e1000_phy_reset_dsp(struct e1000_hw *hw)
3183 DEBUGFUNC("e1000_phy_reset_dsp");
3186 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3188 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3190 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3192 ret_val = E1000_SUCCESS;
3198 /******************************************************************************
3199 * Get PHY information from various PHY registers for igp PHY only.
3201 * hw - Struct containing variables accessed by shared code
3202 * phy_info - PHY information structure
3203 ******************************************************************************/
3205 e1000_phy_igp_get_info(struct e1000_hw *hw,
3206 struct e1000_phy_info *phy_info)
3209 uint16_t phy_data, polarity, min_length, max_length, average;
3211 DEBUGFUNC("e1000_phy_igp_get_info");
3213 /* The downshift status is checked only once, after link is established,
3214 * and it stored in the hw->speed_downgraded parameter. */
3215 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3217 /* IGP01E1000 does not need to support it. */
3218 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3220 /* IGP01E1000 always correct polarity reversal */
3221 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3223 /* Check polarity status */
3224 ret_val = e1000_check_polarity(hw, &polarity);
3228 phy_info->cable_polarity = polarity;
3230 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3234 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
3235 IGP01E1000_PSSR_MDIX_SHIFT;
3237 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3238 IGP01E1000_PSSR_SPEED_1000MBPS) {
3239 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3240 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3244 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3245 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3246 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3247 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3249 /* Get cable length */
3250 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3254 /* Translate to old method */
3255 average = (max_length + min_length) / 2;
3257 if(average <= e1000_igp_cable_length_50)
3258 phy_info->cable_length = e1000_cable_length_50;
3259 else if(average <= e1000_igp_cable_length_80)
3260 phy_info->cable_length = e1000_cable_length_50_80;
3261 else if(average <= e1000_igp_cable_length_110)
3262 phy_info->cable_length = e1000_cable_length_80_110;
3263 else if(average <= e1000_igp_cable_length_140)
3264 phy_info->cable_length = e1000_cable_length_110_140;
3266 phy_info->cable_length = e1000_cable_length_140;
3269 return E1000_SUCCESS;
3272 /******************************************************************************
3273 * Get PHY information from various PHY registers fot m88 PHY only.
3275 * hw - Struct containing variables accessed by shared code
3276 * phy_info - PHY information structure
3277 ******************************************************************************/
3279 e1000_phy_m88_get_info(struct e1000_hw *hw,
3280 struct e1000_phy_info *phy_info)
3283 uint16_t phy_data, polarity;
3285 DEBUGFUNC("e1000_phy_m88_get_info");
3287 /* The downshift status is checked only once, after link is established,
3288 * and it stored in the hw->speed_downgraded parameter. */
3289 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3291 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3295 phy_info->extended_10bt_distance =
3296 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3297 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
3298 phy_info->polarity_correction =
3299 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3300 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
3302 /* Check polarity status */
3303 ret_val = e1000_check_polarity(hw, &polarity);
3306 phy_info->cable_polarity = polarity;
3308 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3312 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
3313 M88E1000_PSSR_MDIX_SHIFT;
3315 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3316 /* Cable Length Estimation and Local/Remote Receiver Information
3317 * are only valid at 1000 Mbps.
3319 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
3320 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3322 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3326 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3327 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3329 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3330 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3333 return E1000_SUCCESS;
3336 /******************************************************************************
3337 * Get PHY information from various PHY registers
3339 * hw - Struct containing variables accessed by shared code
3340 * phy_info - PHY information structure
3341 ******************************************************************************/
3343 e1000_phy_get_info(struct e1000_hw *hw,
3344 struct e1000_phy_info *phy_info)
3349 DEBUGFUNC("e1000_phy_get_info");
3351 phy_info->cable_length = e1000_cable_length_undefined;
3352 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3353 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3354 phy_info->downshift = e1000_downshift_undefined;
3355 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3356 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3357 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3358 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3360 if(hw->media_type != e1000_media_type_copper) {
3361 DEBUGOUT("PHY info is only valid for copper media\n");
3362 return -E1000_ERR_CONFIG;
3365 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3369 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3373 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3374 DEBUGOUT("PHY info is only valid if link is up\n");
3375 return -E1000_ERR_CONFIG;
3378 if(hw->phy_type == e1000_phy_igp ||
3379 hw->phy_type == e1000_phy_igp_2)
3380 return e1000_phy_igp_get_info(hw, phy_info);
3382 return e1000_phy_m88_get_info(hw, phy_info);
3386 e1000_validate_mdi_setting(struct e1000_hw *hw)
3388 DEBUGFUNC("e1000_validate_mdi_settings");
3390 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3391 DEBUGOUT("Invalid MDI setting detected\n");
3393 return -E1000_ERR_CONFIG;
3395 return E1000_SUCCESS;
3399 /******************************************************************************
3400 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3403 * hw - Struct containing variables accessed by shared code
3404 *****************************************************************************/
3406 e1000_init_eeprom_params(struct e1000_hw *hw)
3408 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3409 uint32_t eecd = E1000_READ_REG(hw, EECD);
3410 int32_t ret_val = E1000_SUCCESS;
3411 uint16_t eeprom_size;
3413 DEBUGFUNC("e1000_init_eeprom_params");
3415 switch (hw->mac_type) {
3416 case e1000_82542_rev2_0:
3417 case e1000_82542_rev2_1:
3420 eeprom->type = e1000_eeprom_microwire;
3421 eeprom->word_size = 64;
3422 eeprom->opcode_bits = 3;
3423 eeprom->address_bits = 6;
3424 eeprom->delay_usec = 50;
3425 eeprom->use_eerd = FALSE;
3426 eeprom->use_eewr = FALSE;
3430 case e1000_82545_rev_3:
3432 case e1000_82546_rev_3:
3433 eeprom->type = e1000_eeprom_microwire;
3434 eeprom->opcode_bits = 3;
3435 eeprom->delay_usec = 50;
3436 if(eecd & E1000_EECD_SIZE) {
3437 eeprom->word_size = 256;
3438 eeprom->address_bits = 8;
3440 eeprom->word_size = 64;
3441 eeprom->address_bits = 6;
3443 eeprom->use_eerd = FALSE;
3444 eeprom->use_eewr = FALSE;
3447 case e1000_82541_rev_2:
3449 case e1000_82547_rev_2:
3450 if (eecd & E1000_EECD_TYPE) {
3451 eeprom->type = e1000_eeprom_spi;
3452 eeprom->opcode_bits = 8;
3453 eeprom->delay_usec = 1;
3454 if (eecd & E1000_EECD_ADDR_BITS) {
3455 eeprom->page_size = 32;
3456 eeprom->address_bits = 16;
3458 eeprom->page_size = 8;
3459 eeprom->address_bits = 8;
3462 eeprom->type = e1000_eeprom_microwire;
3463 eeprom->opcode_bits = 3;
3464 eeprom->delay_usec = 50;
3465 if (eecd & E1000_EECD_ADDR_BITS) {
3466 eeprom->word_size = 256;
3467 eeprom->address_bits = 8;
3469 eeprom->word_size = 64;
3470 eeprom->address_bits = 6;
3473 eeprom->use_eerd = FALSE;
3474 eeprom->use_eewr = FALSE;
3478 eeprom->type = e1000_eeprom_spi;
3479 eeprom->opcode_bits = 8;
3480 eeprom->delay_usec = 1;
3481 if (eecd & E1000_EECD_ADDR_BITS) {
3482 eeprom->page_size = 32;
3483 eeprom->address_bits = 16;
3485 eeprom->page_size = 8;
3486 eeprom->address_bits = 8;
3488 eeprom->use_eerd = FALSE;
3489 eeprom->use_eewr = FALSE;
3492 eeprom->type = e1000_eeprom_spi;
3493 eeprom->opcode_bits = 8;
3494 eeprom->delay_usec = 1;
3495 if (eecd & E1000_EECD_ADDR_BITS) {
3496 eeprom->page_size = 32;
3497 eeprom->address_bits = 16;
3499 eeprom->page_size = 8;
3500 eeprom->address_bits = 8;
3502 eeprom->use_eerd = TRUE;
3503 eeprom->use_eewr = TRUE;
3504 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
3505 eeprom->type = e1000_eeprom_flash;
3506 eeprom->word_size = 2048;
3508 /* Ensure that the Autonomous FLASH update bit is cleared due to
3509 * Flash update issue on parts which use a FLASH for NVM. */
3510 eecd &= ~E1000_EECD_AUPDEN;
3511 E1000_WRITE_REG(hw, EECD, eecd);
3518 if (eeprom->type == e1000_eeprom_spi) {
3519 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3520 * 32KB (incremented by powers of 2).
3522 if(hw->mac_type <= e1000_82547_rev_2) {
3523 /* Set to default value for initial eeprom read. */
3524 eeprom->word_size = 64;
3525 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3528 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3529 /* 256B eeprom size was not supported in earlier hardware, so we
3530 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3531 * is never the result used in the shifting logic below. */
3535 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
3536 E1000_EECD_SIZE_EX_SHIFT);
3539 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3544 /******************************************************************************
3545 * Raises the EEPROM's clock input.
3547 * hw - Struct containing variables accessed by shared code
3548 * eecd - EECD's current value
3549 *****************************************************************************/
3551 e1000_raise_ee_clk(struct e1000_hw *hw,
3554 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3555 * wait <delay> microseconds.
3557 *eecd = *eecd | E1000_EECD_SK;
3558 E1000_WRITE_REG(hw, EECD, *eecd);
3559 E1000_WRITE_FLUSH(hw);
3560 udelay(hw->eeprom.delay_usec);
3563 /******************************************************************************
3564 * Lowers the EEPROM's clock input.
3566 * hw - Struct containing variables accessed by shared code
3567 * eecd - EECD's current value
3568 *****************************************************************************/
3570 e1000_lower_ee_clk(struct e1000_hw *hw,
3573 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3574 * wait 50 microseconds.
3576 *eecd = *eecd & ~E1000_EECD_SK;
3577 E1000_WRITE_REG(hw, EECD, *eecd);
3578 E1000_WRITE_FLUSH(hw);
3579 udelay(hw->eeprom.delay_usec);
3582 /******************************************************************************
3583 * Shift data bits out to the EEPROM.
3585 * hw - Struct containing variables accessed by shared code
3586 * data - data to send to the EEPROM
3587 * count - number of bits to shift out
3588 *****************************************************************************/
3590 e1000_shift_out_ee_bits(struct e1000_hw *hw,
3594 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3598 /* We need to shift "count" bits out to the EEPROM. So, value in the
3599 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3600 * In order to do this, "data" must be broken down into bits.
3602 mask = 0x01 << (count - 1);
3603 eecd = E1000_READ_REG(hw, EECD);
3604 if (eeprom->type == e1000_eeprom_microwire) {
3605 eecd &= ~E1000_EECD_DO;
3606 } else if (eeprom->type == e1000_eeprom_spi) {
3607 eecd |= E1000_EECD_DO;
3610 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3611 * and then raising and then lowering the clock (the SK bit controls
3612 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3613 * by setting "DI" to "0" and then raising and then lowering the clock.
3615 eecd &= ~E1000_EECD_DI;
3618 eecd |= E1000_EECD_DI;
3620 E1000_WRITE_REG(hw, EECD, eecd);
3621 E1000_WRITE_FLUSH(hw);
3623 udelay(eeprom->delay_usec);
3625 e1000_raise_ee_clk(hw, &eecd);
3626 e1000_lower_ee_clk(hw, &eecd);
3632 /* We leave the "DI" bit set to "0" when we leave this routine. */
3633 eecd &= ~E1000_EECD_DI;
3634 E1000_WRITE_REG(hw, EECD, eecd);
3637 /******************************************************************************
3638 * Shift data bits in from the EEPROM
3640 * hw - Struct containing variables accessed by shared code
3641 *****************************************************************************/
3643 e1000_shift_in_ee_bits(struct e1000_hw *hw,
3650 /* In order to read a register from the EEPROM, we need to shift 'count'
3651 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3652 * input to the EEPROM (setting the SK bit), and then reading the value of
3653 * the "DO" bit. During this "shifting in" process the "DI" bit should
3657 eecd = E1000_READ_REG(hw, EECD);
3659 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3662 for(i = 0; i < count; i++) {
3664 e1000_raise_ee_clk(hw, &eecd);
3666 eecd = E1000_READ_REG(hw, EECD);
3668 eecd &= ~(E1000_EECD_DI);
3669 if(eecd & E1000_EECD_DO)
3672 e1000_lower_ee_clk(hw, &eecd);
3678 /******************************************************************************
3679 * Prepares EEPROM for access
3681 * hw - Struct containing variables accessed by shared code
3683 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3684 * function should be called before issuing a command to the EEPROM.
3685 *****************************************************************************/
3687 e1000_acquire_eeprom(struct e1000_hw *hw)
3689 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3692 DEBUGFUNC("e1000_acquire_eeprom");
3694 if(e1000_get_hw_eeprom_semaphore(hw))
3695 return -E1000_ERR_EEPROM;
3697 eecd = E1000_READ_REG(hw, EECD);
3699 if (hw->mac_type != e1000_82573) {
3700 /* Request EEPROM Access */
3701 if(hw->mac_type > e1000_82544) {
3702 eecd |= E1000_EECD_REQ;
3703 E1000_WRITE_REG(hw, EECD, eecd);
3704 eecd = E1000_READ_REG(hw, EECD);
3705 while((!(eecd & E1000_EECD_GNT)) &&
3706 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3709 eecd = E1000_READ_REG(hw, EECD);
3711 if(!(eecd & E1000_EECD_GNT)) {
3712 eecd &= ~E1000_EECD_REQ;
3713 E1000_WRITE_REG(hw, EECD, eecd);
3714 DEBUGOUT("Could not acquire EEPROM grant\n");
3715 e1000_put_hw_eeprom_semaphore(hw);
3716 return -E1000_ERR_EEPROM;
3721 /* Setup EEPROM for Read/Write */
3723 if (eeprom->type == e1000_eeprom_microwire) {
3724 /* Clear SK and DI */
3725 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3726 E1000_WRITE_REG(hw, EECD, eecd);
3729 eecd |= E1000_EECD_CS;
3730 E1000_WRITE_REG(hw, EECD, eecd);
3731 } else if (eeprom->type == e1000_eeprom_spi) {
3732 /* Clear SK and CS */
3733 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3734 E1000_WRITE_REG(hw, EECD, eecd);
3738 return E1000_SUCCESS;
3741 /******************************************************************************
3742 * Returns EEPROM to a "standby" state
3744 * hw - Struct containing variables accessed by shared code
3745 *****************************************************************************/
3747 e1000_standby_eeprom(struct e1000_hw *hw)
3749 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3752 eecd = E1000_READ_REG(hw, EECD);
3754 if(eeprom->type == e1000_eeprom_microwire) {
3755 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3756 E1000_WRITE_REG(hw, EECD, eecd);
3757 E1000_WRITE_FLUSH(hw);
3758 udelay(eeprom->delay_usec);
3761 eecd |= E1000_EECD_SK;
3762 E1000_WRITE_REG(hw, EECD, eecd);
3763 E1000_WRITE_FLUSH(hw);
3764 udelay(eeprom->delay_usec);
3767 eecd |= E1000_EECD_CS;
3768 E1000_WRITE_REG(hw, EECD, eecd);
3769 E1000_WRITE_FLUSH(hw);
3770 udelay(eeprom->delay_usec);
3773 eecd &= ~E1000_EECD_SK;
3774 E1000_WRITE_REG(hw, EECD, eecd);
3775 E1000_WRITE_FLUSH(hw);
3776 udelay(eeprom->delay_usec);
3777 } else if(eeprom->type == e1000_eeprom_spi) {
3778 /* Toggle CS to flush commands */
3779 eecd |= E1000_EECD_CS;
3780 E1000_WRITE_REG(hw, EECD, eecd);
3781 E1000_WRITE_FLUSH(hw);
3782 udelay(eeprom->delay_usec);
3783 eecd &= ~E1000_EECD_CS;
3784 E1000_WRITE_REG(hw, EECD, eecd);
3785 E1000_WRITE_FLUSH(hw);
3786 udelay(eeprom->delay_usec);
3790 /******************************************************************************
3791 * Terminates a command by inverting the EEPROM's chip select pin
3793 * hw - Struct containing variables accessed by shared code
3794 *****************************************************************************/
3796 e1000_release_eeprom(struct e1000_hw *hw)
3800 DEBUGFUNC("e1000_release_eeprom");
3802 eecd = E1000_READ_REG(hw, EECD);
3804 if (hw->eeprom.type == e1000_eeprom_spi) {
3805 eecd |= E1000_EECD_CS; /* Pull CS high */
3806 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3808 E1000_WRITE_REG(hw, EECD, eecd);
3810 udelay(hw->eeprom.delay_usec);
3811 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3812 /* cleanup eeprom */
3814 /* CS on Microwire is active-high */
3815 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3817 E1000_WRITE_REG(hw, EECD, eecd);
3819 /* Rising edge of clock */
3820 eecd |= E1000_EECD_SK;
3821 E1000_WRITE_REG(hw, EECD, eecd);
3822 E1000_WRITE_FLUSH(hw);
3823 udelay(hw->eeprom.delay_usec);
3825 /* Falling edge of clock */
3826 eecd &= ~E1000_EECD_SK;
3827 E1000_WRITE_REG(hw, EECD, eecd);
3828 E1000_WRITE_FLUSH(hw);
3829 udelay(hw->eeprom.delay_usec);
3832 /* Stop requesting EEPROM access */
3833 if(hw->mac_type > e1000_82544) {
3834 eecd &= ~E1000_EECD_REQ;
3835 E1000_WRITE_REG(hw, EECD, eecd);
3838 e1000_put_hw_eeprom_semaphore(hw);
3841 /******************************************************************************
3842 * Reads a 16 bit word from the EEPROM.
3844 * hw - Struct containing variables accessed by shared code
3845 *****************************************************************************/
3847 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3849 uint16_t retry_count = 0;
3850 uint8_t spi_stat_reg;
3852 DEBUGFUNC("e1000_spi_eeprom_ready");
3854 /* Read "Status Register" repeatedly until the LSB is cleared. The
3855 * EEPROM will signal that the command has been completed by clearing
3856 * bit 0 of the internal status register. If it's not cleared within
3857 * 5 milliseconds, then error out.
3861 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3862 hw->eeprom.opcode_bits);
3863 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3864 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3870 e1000_standby_eeprom(hw);
3871 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3873 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3874 * only 0-5mSec on 5V devices)
3876 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3877 DEBUGOUT("SPI EEPROM Status error\n");
3878 return -E1000_ERR_EEPROM;
3881 return E1000_SUCCESS;
3884 /******************************************************************************
3885 * Reads a 16 bit word from the EEPROM.
3887 * hw - Struct containing variables accessed by shared code
3888 * offset - offset of word in the EEPROM to read
3889 * data - word read from the EEPROM
3890 * words - number of words to read
3891 *****************************************************************************/
3893 e1000_read_eeprom(struct e1000_hw *hw,
3898 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3902 DEBUGFUNC("e1000_read_eeprom");
3904 /* A check for invalid values: offset too large, too many words, and not
3907 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
3909 DEBUGOUT("\"words\" parameter out of bounds\n");
3910 return -E1000_ERR_EEPROM;
3913 /* FLASH reads without acquiring the semaphore are safe */
3914 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
3915 hw->eeprom.use_eerd == FALSE) {
3916 switch (hw->mac_type) {
3918 /* Prepare the EEPROM for reading */
3919 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3920 return -E1000_ERR_EEPROM;
3925 if (eeprom->use_eerd == TRUE) {
3926 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
3927 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3928 (hw->mac_type != e1000_82573))
3929 e1000_release_eeprom(hw);
3933 if(eeprom->type == e1000_eeprom_spi) {
3935 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3937 if(e1000_spi_eeprom_ready(hw)) {
3938 e1000_release_eeprom(hw);
3939 return -E1000_ERR_EEPROM;
3942 e1000_standby_eeprom(hw);
3944 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3945 if((eeprom->address_bits == 8) && (offset >= 128))
3946 read_opcode |= EEPROM_A8_OPCODE_SPI;
3948 /* Send the READ command (opcode + addr) */
3949 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3950 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3952 /* Read the data. The address of the eeprom internally increments with
3953 * each byte (spi) being read, saving on the overhead of eeprom setup
3954 * and tear-down. The address counter will roll over if reading beyond
3955 * the size of the eeprom, thus allowing the entire memory to be read
3956 * starting from any offset. */
3957 for (i = 0; i < words; i++) {
3958 word_in = e1000_shift_in_ee_bits(hw, 16);
3959 data[i] = (word_in >> 8) | (word_in << 8);
3961 } else if(eeprom->type == e1000_eeprom_microwire) {
3962 for (i = 0; i < words; i++) {
3963 /* Send the READ command (opcode + addr) */
3964 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3965 eeprom->opcode_bits);
3966 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3967 eeprom->address_bits);
3969 /* Read the data. For microwire, each word requires the overhead
3970 * of eeprom setup and tear-down. */
3971 data[i] = e1000_shift_in_ee_bits(hw, 16);
3972 e1000_standby_eeprom(hw);
3976 /* End this read operation */
3977 e1000_release_eeprom(hw);
3979 return E1000_SUCCESS;
3982 /******************************************************************************
3983 * Reads a 16 bit word from the EEPROM using the EERD register.
3985 * hw - Struct containing variables accessed by shared code
3986 * offset - offset of word in the EEPROM to read
3987 * data - word read from the EEPROM
3988 * words - number of words to read
3989 *****************************************************************************/
3991 e1000_read_eeprom_eerd(struct e1000_hw *hw,
3996 uint32_t i, eerd = 0;
3999 for (i = 0; i < words; i++) {
4000 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4001 E1000_EEPROM_RW_REG_START;
4003 E1000_WRITE_REG(hw, EERD, eerd);
4004 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4009 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
4016 /******************************************************************************
4017 * Writes a 16 bit word from the EEPROM using the EEWR register.
4019 * hw - Struct containing variables accessed by shared code
4020 * offset - offset of word in the EEPROM to read
4021 * data - word read from the EEPROM
4022 * words - number of words to read
4023 *****************************************************************************/
4025 e1000_write_eeprom_eewr(struct e1000_hw *hw,
4030 uint32_t register_value = 0;
4034 for (i = 0; i < words; i++) {
4035 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
4036 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
4037 E1000_EEPROM_RW_REG_START;
4039 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4044 E1000_WRITE_REG(hw, EEWR, register_value);
4046 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4056 /******************************************************************************
4057 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4059 * hw - Struct containing variables accessed by shared code
4060 *****************************************************************************/
4062 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
4064 uint32_t attempts = 100000;
4065 uint32_t i, reg = 0;
4066 int32_t done = E1000_ERR_EEPROM;
4068 for(i = 0; i < attempts; i++) {
4069 if(eerd == E1000_EEPROM_POLL_READ)
4070 reg = E1000_READ_REG(hw, EERD);
4072 reg = E1000_READ_REG(hw, EEWR);
4074 if(reg & E1000_EEPROM_RW_REG_DONE) {
4075 done = E1000_SUCCESS;
4084 /***************************************************************************
4085 * Description: Determines if the onboard NVM is FLASH or EEPROM.
4087 * hw - Struct containing variables accessed by shared code
4088 ****************************************************************************/
4090 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4094 if(hw->mac_type == e1000_82573) {
4095 eecd = E1000_READ_REG(hw, EECD);
4097 /* Isolate bits 15 & 16 */
4098 eecd = ((eecd >> 15) & 0x03);
4100 /* If both bits are set, device is Flash type */
4108 /******************************************************************************
4109 * Verifies that the EEPROM has a valid checksum
4111 * hw - Struct containing variables accessed by shared code
4113 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4114 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4116 *****************************************************************************/
4118 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4120 uint16_t checksum = 0;
4121 uint16_t i, eeprom_data;
4123 DEBUGFUNC("e1000_validate_eeprom_checksum");
4125 if ((hw->mac_type == e1000_82573) &&
4126 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
4127 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
4128 * 10h-12h. Checksum may need to be fixed. */
4129 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
4130 if ((eeprom_data & 0x10) == 0) {
4131 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
4132 * has already been fixed. If the checksum is still wrong and this
4133 * bit is a 1, we need to return bad checksum. Otherwise, we need
4134 * to set this bit to a 1 and update the checksum. */
4135 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
4136 if ((eeprom_data & 0x8000) == 0) {
4137 eeprom_data |= 0x8000;
4138 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
4139 e1000_update_eeprom_checksum(hw);
4144 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4145 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4146 DEBUGOUT("EEPROM Read Error\n");
4147 return -E1000_ERR_EEPROM;
4149 checksum += eeprom_data;
4152 if(checksum == (uint16_t) EEPROM_SUM)
4153 return E1000_SUCCESS;
4155 DEBUGOUT("EEPROM Checksum Invalid\n");
4156 return -E1000_ERR_EEPROM;
4160 /******************************************************************************
4161 * Calculates the EEPROM checksum and writes it to the EEPROM
4163 * hw - Struct containing variables accessed by shared code
4165 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4166 * Writes the difference to word offset 63 of the EEPROM.
4167 *****************************************************************************/
4169 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4171 uint16_t checksum = 0;
4172 uint16_t i, eeprom_data;
4174 DEBUGFUNC("e1000_update_eeprom_checksum");
4176 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4177 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4178 DEBUGOUT("EEPROM Read Error\n");
4179 return -E1000_ERR_EEPROM;
4181 checksum += eeprom_data;
4183 checksum = (uint16_t) EEPROM_SUM - checksum;
4184 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4185 DEBUGOUT("EEPROM Write Error\n");
4186 return -E1000_ERR_EEPROM;
4187 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4188 e1000_commit_shadow_ram(hw);
4190 return E1000_SUCCESS;
4193 /******************************************************************************
4194 * Parent function for writing words to the different EEPROM types.
4196 * hw - Struct containing variables accessed by shared code
4197 * offset - offset within the EEPROM to be written to
4198 * words - number of words to write
4199 * data - 16 bit word to be written to the EEPROM
4201 * If e1000_update_eeprom_checksum is not called after this function, the
4202 * EEPROM will most likely contain an invalid checksum.
4203 *****************************************************************************/
4205 e1000_write_eeprom(struct e1000_hw *hw,
4210 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4213 DEBUGFUNC("e1000_write_eeprom");
4215 /* A check for invalid values: offset too large, too many words, and not
4218 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4220 DEBUGOUT("\"words\" parameter out of bounds\n");
4221 return -E1000_ERR_EEPROM;
4224 /* 82573 writes only through eewr */
4225 if(eeprom->use_eewr == TRUE)
4226 return e1000_write_eeprom_eewr(hw, offset, words, data);
4228 /* Prepare the EEPROM for writing */
4229 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4230 return -E1000_ERR_EEPROM;
4232 if(eeprom->type == e1000_eeprom_microwire) {
4233 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4235 status = e1000_write_eeprom_spi(hw, offset, words, data);
4239 /* Done with writing */
4240 e1000_release_eeprom(hw);
4245 /******************************************************************************
4246 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4248 * hw - Struct containing variables accessed by shared code
4249 * offset - offset within the EEPROM to be written to
4250 * words - number of words to write
4251 * data - pointer to array of 8 bit words to be written to the EEPROM
4253 *****************************************************************************/
4255 e1000_write_eeprom_spi(struct e1000_hw *hw,
4260 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4263 DEBUGFUNC("e1000_write_eeprom_spi");
4265 while (widx < words) {
4266 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
4268 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
4270 e1000_standby_eeprom(hw);
4272 /* Send the WRITE ENABLE command (8 bit opcode ) */
4273 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4274 eeprom->opcode_bits);
4276 e1000_standby_eeprom(hw);
4278 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4279 if((eeprom->address_bits == 8) && (offset >= 128))
4280 write_opcode |= EEPROM_A8_OPCODE_SPI;
4282 /* Send the Write command (8-bit opcode + addr) */
4283 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4285 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
4286 eeprom->address_bits);
4290 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4291 while (widx < words) {
4292 uint16_t word_out = data[widx];
4293 word_out = (word_out >> 8) | (word_out << 8);
4294 e1000_shift_out_ee_bits(hw, word_out, 16);
4297 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4298 * operation, while the smaller eeproms are capable of an 8-byte
4299 * PAGE WRITE operation. Break the inner loop to pass new address
4301 if((((offset + widx)*2) % eeprom->page_size) == 0) {
4302 e1000_standby_eeprom(hw);
4308 return E1000_SUCCESS;
4311 /******************************************************************************
4312 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4314 * hw - Struct containing variables accessed by shared code
4315 * offset - offset within the EEPROM to be written to
4316 * words - number of words to write
4317 * data - pointer to array of 16 bit words to be written to the EEPROM
4319 *****************************************************************************/
4321 e1000_write_eeprom_microwire(struct e1000_hw *hw,
4326 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4328 uint16_t words_written = 0;
4331 DEBUGFUNC("e1000_write_eeprom_microwire");
4333 /* Send the write enable command to the EEPROM (3-bit opcode plus
4334 * 6/8-bit dummy address beginning with 11). It's less work to include
4335 * the 11 of the dummy address as part of the opcode than it is to shift
4336 * it over the correct number of bits for the address. This puts the
4337 * EEPROM into write/erase mode.
4339 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4340 (uint16_t)(eeprom->opcode_bits + 2));
4342 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4344 /* Prepare the EEPROM */
4345 e1000_standby_eeprom(hw);
4347 while (words_written < words) {
4348 /* Send the Write command (3-bit opcode + addr) */
4349 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4350 eeprom->opcode_bits);
4352 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
4353 eeprom->address_bits);
4356 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4358 /* Toggle the CS line. This in effect tells the EEPROM to execute
4359 * the previous command.
4361 e1000_standby_eeprom(hw);
4363 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4364 * signal that the command has been completed by raising the DO signal.
4365 * If DO does not go high in 10 milliseconds, then error out.
4367 for(i = 0; i < 200; i++) {
4368 eecd = E1000_READ_REG(hw, EECD);
4369 if(eecd & E1000_EECD_DO) break;
4373 DEBUGOUT("EEPROM Write did not complete\n");
4374 return -E1000_ERR_EEPROM;
4377 /* Recover from write */
4378 e1000_standby_eeprom(hw);
4383 /* Send the write disable command to the EEPROM (3-bit opcode plus
4384 * 6/8-bit dummy address beginning with 10). It's less work to include
4385 * the 10 of the dummy address as part of the opcode than it is to shift
4386 * it over the correct number of bits for the address. This takes the
4387 * EEPROM out of write/erase mode.
4389 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4390 (uint16_t)(eeprom->opcode_bits + 2));
4392 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4394 return E1000_SUCCESS;
4397 /******************************************************************************
4398 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4399 * in the eeprom cache and the non modified values in the currently active bank
4402 * hw - Struct containing variables accessed by shared code
4403 * offset - offset of word in the EEPROM to read
4404 * data - word read from the EEPROM
4405 * words - number of words to read
4406 *****************************************************************************/
4408 e1000_commit_shadow_ram(struct e1000_hw *hw)
4410 uint32_t attempts = 100000;
4414 int32_t error = E1000_SUCCESS;
4416 /* The flop register will be used to determine if flash type is STM */
4417 flop = E1000_READ_REG(hw, FLOP);
4419 if (hw->mac_type == e1000_82573) {
4420 for (i=0; i < attempts; i++) {
4421 eecd = E1000_READ_REG(hw, EECD);
4422 if ((eecd & E1000_EECD_FLUPD) == 0) {
4428 if (i == attempts) {
4429 return -E1000_ERR_EEPROM;
4432 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4433 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4434 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4437 /* Perform the flash update */
4438 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4440 for (i=0; i < attempts; i++) {
4441 eecd = E1000_READ_REG(hw, EECD);
4442 if ((eecd & E1000_EECD_FLUPD) == 0) {
4448 if (i == attempts) {
4449 return -E1000_ERR_EEPROM;
4456 /******************************************************************************
4457 * Reads the adapter's part number from the EEPROM
4459 * hw - Struct containing variables accessed by shared code
4460 * part_num - Adapter's part number
4461 *****************************************************************************/
4463 e1000_read_part_num(struct e1000_hw *hw,
4466 uint16_t offset = EEPROM_PBA_BYTE_1;
4467 uint16_t eeprom_data;
4469 DEBUGFUNC("e1000_read_part_num");
4471 /* Get word 0 from EEPROM */
4472 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4473 DEBUGOUT("EEPROM Read Error\n");
4474 return -E1000_ERR_EEPROM;
4476 /* Save word 0 in upper half of part_num */
4477 *part_num = (uint32_t) (eeprom_data << 16);
4479 /* Get word 1 from EEPROM */
4480 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
4481 DEBUGOUT("EEPROM Read Error\n");
4482 return -E1000_ERR_EEPROM;
4484 /* Save word 1 in lower half of part_num */
4485 *part_num |= eeprom_data;
4487 return E1000_SUCCESS;
4490 /******************************************************************************
4491 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4492 * second function of dual function devices
4494 * hw - Struct containing variables accessed by shared code
4495 *****************************************************************************/
4497 e1000_read_mac_addr(struct e1000_hw * hw)
4500 uint16_t eeprom_data, i;
4502 DEBUGFUNC("e1000_read_mac_addr");
4504 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4506 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4507 DEBUGOUT("EEPROM Read Error\n");
4508 return -E1000_ERR_EEPROM;
4510 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
4511 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
4514 switch (hw->mac_type) {
4518 case e1000_82546_rev_3:
4520 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4521 hw->perm_mac_addr[5] ^= 0x01;
4525 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
4526 hw->mac_addr[i] = hw->perm_mac_addr[i];
4527 return E1000_SUCCESS;
4530 /******************************************************************************
4531 * Initializes receive address filters.
4533 * hw - Struct containing variables accessed by shared code
4535 * Places the MAC address in receive address register 0 and clears the rest
4536 * of the receive addresss registers. Clears the multicast table. Assumes
4537 * the receiver is in reset when the routine is called.
4538 *****************************************************************************/
4540 e1000_init_rx_addrs(struct e1000_hw *hw)
4545 DEBUGFUNC("e1000_init_rx_addrs");
4547 /* Setup the receive address. */
4548 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4550 e1000_rar_set(hw, hw->mac_addr, 0);
4552 rar_num = E1000_RAR_ENTRIES;
4554 /* Reserve a spot for the Locally Administered Address to work around
4555 * an 82571 issue in which a reset on one port will reload the MAC on
4556 * the other port. */
4557 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
4559 /* Zero out the other 15 receive addresses. */
4560 DEBUGOUT("Clearing RAR[1-15]\n");
4561 for(i = 1; i < rar_num; i++) {
4562 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4563 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4568 /******************************************************************************
4569 * Updates the MAC's list of multicast addresses.
4571 * hw - Struct containing variables accessed by shared code
4572 * mc_addr_list - the list of new multicast addresses
4573 * mc_addr_count - number of addresses
4574 * pad - number of bytes between addresses in the list
4575 * rar_used_count - offset where to start adding mc addresses into the RAR's
4577 * The given list replaces any existing list. Clears the last 15 receive
4578 * address registers and the multicast table. Uses receive address registers
4579 * for the first 15 multicast addresses, and hashes the rest into the
4581 *****************************************************************************/
4583 e1000_mc_addr_list_update(struct e1000_hw *hw,
4584 uint8_t *mc_addr_list,
4585 uint32_t mc_addr_count,
4587 uint32_t rar_used_count)
4589 uint32_t hash_value;
4591 uint32_t num_rar_entry;
4592 uint32_t num_mta_entry;
4594 DEBUGFUNC("e1000_mc_addr_list_update");
4596 /* Set the new number of MC addresses that we are being requested to use. */
4597 hw->num_mc_addrs = mc_addr_count;
4599 /* Clear RAR[1-15] */
4600 DEBUGOUT(" Clearing RAR[1-15]\n");
4601 num_rar_entry = E1000_RAR_ENTRIES;
4602 /* Reserve a spot for the Locally Administered Address to work around
4603 * an 82571 issue in which a reset on one port will reload the MAC on
4604 * the other port. */
4605 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
4608 for(i = rar_used_count; i < num_rar_entry; i++) {
4609 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4610 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4614 DEBUGOUT(" Clearing MTA\n");
4615 num_mta_entry = E1000_NUM_MTA_REGISTERS;
4616 for(i = 0; i < num_mta_entry; i++) {
4617 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4620 /* Add the new addresses */
4621 for(i = 0; i < mc_addr_count; i++) {
4622 DEBUGOUT(" Adding the multicast addresses:\n");
4623 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
4624 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
4625 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
4626 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
4627 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
4628 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
4629 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
4631 hash_value = e1000_hash_mc_addr(hw,
4633 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
4635 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
4637 /* Place this multicast address in the RAR if there is room, *
4638 * else put it in the MTA
4640 if (rar_used_count < num_rar_entry) {
4642 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
4646 e1000_mta_set(hw, hash_value);
4649 DEBUGOUT("MC Update Complete\n");
4653 /******************************************************************************
4654 * Hashes an address to determine its location in the multicast table
4656 * hw - Struct containing variables accessed by shared code
4657 * mc_addr - the multicast address to hash
4658 *****************************************************************************/
4660 e1000_hash_mc_addr(struct e1000_hw *hw,
4663 uint32_t hash_value = 0;
4665 /* The portion of the address that is used for the hash table is
4666 * determined by the mc_filter_type setting.
4668 switch (hw->mc_filter_type) {
4669 /* [0] [1] [2] [3] [4] [5]
4674 /* [47:36] i.e. 0x563 for above example address */
4675 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
4678 /* [46:35] i.e. 0xAC6 for above example address */
4679 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
4682 /* [45:34] i.e. 0x5D8 for above example address */
4683 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
4686 /* [43:32] i.e. 0x634 for above example address */
4687 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
4691 hash_value &= 0xFFF;
4696 /******************************************************************************
4697 * Sets the bit in the multicast table corresponding to the hash value.
4699 * hw - Struct containing variables accessed by shared code
4700 * hash_value - Multicast address hash value
4701 *****************************************************************************/
4703 e1000_mta_set(struct e1000_hw *hw,
4704 uint32_t hash_value)
4706 uint32_t hash_bit, hash_reg;
4710 /* The MTA is a register array of 128 32-bit registers.
4711 * It is treated like an array of 4096 bits. We want to set
4712 * bit BitArray[hash_value]. So we figure out what register
4713 * the bit is in, read it, OR in the new bit, then write
4714 * back the new value. The register is determined by the
4715 * upper 7 bits of the hash value and the bit within that
4716 * register are determined by the lower 5 bits of the value.
4718 hash_reg = (hash_value >> 5) & 0x7F;
4719 hash_bit = hash_value & 0x1F;
4721 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
4723 mta |= (1 << hash_bit);
4725 /* If we are on an 82544 and we are trying to write an odd offset
4726 * in the MTA, save off the previous entry before writing and
4727 * restore the old value after writing.
4729 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
4730 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4731 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4732 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4734 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4738 /******************************************************************************
4739 * Puts an ethernet address into a receive address register.
4741 * hw - Struct containing variables accessed by shared code
4742 * addr - Address to put into receive address register
4743 * index - Receive address register to write
4744 *****************************************************************************/
4746 e1000_rar_set(struct e1000_hw *hw,
4750 uint32_t rar_low, rar_high;
4752 /* HW expects these in little endian so we reverse the byte order
4753 * from network order (big endian) to little endian
4755 rar_low = ((uint32_t) addr[0] |
4756 ((uint32_t) addr[1] << 8) |
4757 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4759 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4761 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4762 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4765 /******************************************************************************
4766 * Writes a value to the specified offset in the VLAN filter table.
4768 * hw - Struct containing variables accessed by shared code
4769 * offset - Offset in VLAN filer table to write
4770 * value - Value to write into VLAN filter table
4771 *****************************************************************************/
4773 e1000_write_vfta(struct e1000_hw *hw,
4779 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4780 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4781 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4782 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4784 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4788 /******************************************************************************
4789 * Clears the VLAN filer table
4791 * hw - Struct containing variables accessed by shared code
4792 *****************************************************************************/
4794 e1000_clear_vfta(struct e1000_hw *hw)
4797 uint32_t vfta_value = 0;
4798 uint32_t vfta_offset = 0;
4799 uint32_t vfta_bit_in_reg = 0;
4801 if (hw->mac_type == e1000_82573) {
4802 if (hw->mng_cookie.vlan_id != 0) {
4803 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4804 * ID. The following operations determine which 32b entry
4805 * (i.e. offset) into the array we want to set the VLAN ID
4806 * (i.e. bit) of the manageability unit. */
4807 vfta_offset = (hw->mng_cookie.vlan_id >>
4808 E1000_VFTA_ENTRY_SHIFT) &
4809 E1000_VFTA_ENTRY_MASK;
4810 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
4811 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
4814 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4815 /* If the offset we want to clear is the same offset of the
4816 * manageability VLAN ID, then clear all bits except that of the
4817 * manageability unit */
4818 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4819 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4824 e1000_id_led_init(struct e1000_hw * hw)
4827 const uint32_t ledctl_mask = 0x000000FF;
4828 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4829 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4830 uint16_t eeprom_data, i, temp;
4831 const uint16_t led_mask = 0x0F;
4833 DEBUGFUNC("e1000_id_led_init");
4835 if(hw->mac_type < e1000_82540) {
4837 return E1000_SUCCESS;
4840 ledctl = E1000_READ_REG(hw, LEDCTL);
4841 hw->ledctl_default = ledctl;
4842 hw->ledctl_mode1 = hw->ledctl_default;
4843 hw->ledctl_mode2 = hw->ledctl_default;
4845 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4846 DEBUGOUT("EEPROM Read Error\n");
4847 return -E1000_ERR_EEPROM;
4849 if((eeprom_data== ID_LED_RESERVED_0000) ||
4850 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4851 for(i = 0; i < 4; i++) {
4852 temp = (eeprom_data >> (i << 2)) & led_mask;
4854 case ID_LED_ON1_DEF2:
4855 case ID_LED_ON1_ON2:
4856 case ID_LED_ON1_OFF2:
4857 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4858 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4860 case ID_LED_OFF1_DEF2:
4861 case ID_LED_OFF1_ON2:
4862 case ID_LED_OFF1_OFF2:
4863 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4864 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4871 case ID_LED_DEF1_ON2:
4872 case ID_LED_ON1_ON2:
4873 case ID_LED_OFF1_ON2:
4874 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4875 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4877 case ID_LED_DEF1_OFF2:
4878 case ID_LED_ON1_OFF2:
4879 case ID_LED_OFF1_OFF2:
4880 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4881 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4888 return E1000_SUCCESS;
4891 /******************************************************************************
4892 * Prepares SW controlable LED for use and saves the current state of the LED.
4894 * hw - Struct containing variables accessed by shared code
4895 *****************************************************************************/
4897 e1000_setup_led(struct e1000_hw *hw)
4900 int32_t ret_val = E1000_SUCCESS;
4902 DEBUGFUNC("e1000_setup_led");
4904 switch(hw->mac_type) {
4905 case e1000_82542_rev2_0:
4906 case e1000_82542_rev2_1:
4909 /* No setup necessary */
4913 case e1000_82541_rev_2:
4914 case e1000_82547_rev_2:
4915 /* Turn off PHY Smart Power Down (if enabled) */
4916 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4917 &hw->phy_spd_default);
4920 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4921 (uint16_t)(hw->phy_spd_default &
4922 ~IGP01E1000_GMII_SPD));
4927 if(hw->media_type == e1000_media_type_fiber) {
4928 ledctl = E1000_READ_REG(hw, LEDCTL);
4929 /* Save current LEDCTL settings */
4930 hw->ledctl_default = ledctl;
4932 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4933 E1000_LEDCTL_LED0_BLINK |
4934 E1000_LEDCTL_LED0_MODE_MASK);
4935 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4936 E1000_LEDCTL_LED0_MODE_SHIFT);
4937 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4938 } else if(hw->media_type == e1000_media_type_copper)
4939 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4943 return E1000_SUCCESS;
4946 /******************************************************************************
4947 * Restores the saved state of the SW controlable LED.
4949 * hw - Struct containing variables accessed by shared code
4950 *****************************************************************************/
4952 e1000_cleanup_led(struct e1000_hw *hw)
4954 int32_t ret_val = E1000_SUCCESS;
4956 DEBUGFUNC("e1000_cleanup_led");
4958 switch(hw->mac_type) {
4959 case e1000_82542_rev2_0:
4960 case e1000_82542_rev2_1:
4963 /* No cleanup necessary */
4967 case e1000_82541_rev_2:
4968 case e1000_82547_rev_2:
4969 /* Turn on PHY Smart Power Down (if previously enabled) */
4970 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4971 hw->phy_spd_default);
4976 /* Restore LEDCTL settings */
4977 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4981 return E1000_SUCCESS;
4984 /******************************************************************************
4985 * Turns on the software controllable LED
4987 * hw - Struct containing variables accessed by shared code
4988 *****************************************************************************/
4990 e1000_led_on(struct e1000_hw *hw)
4992 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4994 DEBUGFUNC("e1000_led_on");
4996 switch(hw->mac_type) {
4997 case e1000_82542_rev2_0:
4998 case e1000_82542_rev2_1:
5000 /* Set SW Defineable Pin 0 to turn on the LED */
5001 ctrl |= E1000_CTRL_SWDPIN0;
5002 ctrl |= E1000_CTRL_SWDPIO0;
5005 if(hw->media_type == e1000_media_type_fiber) {
5006 /* Set SW Defineable Pin 0 to turn on the LED */
5007 ctrl |= E1000_CTRL_SWDPIN0;
5008 ctrl |= E1000_CTRL_SWDPIO0;
5010 /* Clear SW Defineable Pin 0 to turn on the LED */
5011 ctrl &= ~E1000_CTRL_SWDPIN0;
5012 ctrl |= E1000_CTRL_SWDPIO0;
5016 if(hw->media_type == e1000_media_type_fiber) {
5017 /* Clear SW Defineable Pin 0 to turn on the LED */
5018 ctrl &= ~E1000_CTRL_SWDPIN0;
5019 ctrl |= E1000_CTRL_SWDPIO0;
5020 } else if(hw->media_type == e1000_media_type_copper) {
5021 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5022 return E1000_SUCCESS;
5027 E1000_WRITE_REG(hw, CTRL, ctrl);
5029 return E1000_SUCCESS;
5032 /******************************************************************************
5033 * Turns off the software controllable LED
5035 * hw - Struct containing variables accessed by shared code
5036 *****************************************************************************/
5038 e1000_led_off(struct e1000_hw *hw)
5040 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
5042 DEBUGFUNC("e1000_led_off");
5044 switch(hw->mac_type) {
5045 case e1000_82542_rev2_0:
5046 case e1000_82542_rev2_1:
5048 /* Clear SW Defineable Pin 0 to turn off the LED */
5049 ctrl &= ~E1000_CTRL_SWDPIN0;
5050 ctrl |= E1000_CTRL_SWDPIO0;
5053 if(hw->media_type == e1000_media_type_fiber) {
5054 /* Clear SW Defineable Pin 0 to turn off the LED */
5055 ctrl &= ~E1000_CTRL_SWDPIN0;
5056 ctrl |= E1000_CTRL_SWDPIO0;
5058 /* Set SW Defineable Pin 0 to turn off the LED */
5059 ctrl |= E1000_CTRL_SWDPIN0;
5060 ctrl |= E1000_CTRL_SWDPIO0;
5064 if(hw->media_type == e1000_media_type_fiber) {
5065 /* Set SW Defineable Pin 0 to turn off the LED */
5066 ctrl |= E1000_CTRL_SWDPIN0;
5067 ctrl |= E1000_CTRL_SWDPIO0;
5068 } else if(hw->media_type == e1000_media_type_copper) {
5069 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5070 return E1000_SUCCESS;
5075 E1000_WRITE_REG(hw, CTRL, ctrl);
5077 return E1000_SUCCESS;
5080 /******************************************************************************
5081 * Clears all hardware statistics counters.
5083 * hw - Struct containing variables accessed by shared code
5084 *****************************************************************************/
5086 e1000_clear_hw_cntrs(struct e1000_hw *hw)
5088 volatile uint32_t temp;
5090 temp = E1000_READ_REG(hw, CRCERRS);
5091 temp = E1000_READ_REG(hw, SYMERRS);
5092 temp = E1000_READ_REG(hw, MPC);
5093 temp = E1000_READ_REG(hw, SCC);
5094 temp = E1000_READ_REG(hw, ECOL);
5095 temp = E1000_READ_REG(hw, MCC);
5096 temp = E1000_READ_REG(hw, LATECOL);
5097 temp = E1000_READ_REG(hw, COLC);
5098 temp = E1000_READ_REG(hw, DC);
5099 temp = E1000_READ_REG(hw, SEC);
5100 temp = E1000_READ_REG(hw, RLEC);
5101 temp = E1000_READ_REG(hw, XONRXC);
5102 temp = E1000_READ_REG(hw, XONTXC);
5103 temp = E1000_READ_REG(hw, XOFFRXC);
5104 temp = E1000_READ_REG(hw, XOFFTXC);
5105 temp = E1000_READ_REG(hw, FCRUC);
5106 temp = E1000_READ_REG(hw, PRC64);
5107 temp = E1000_READ_REG(hw, PRC127);
5108 temp = E1000_READ_REG(hw, PRC255);
5109 temp = E1000_READ_REG(hw, PRC511);
5110 temp = E1000_READ_REG(hw, PRC1023);
5111 temp = E1000_READ_REG(hw, PRC1522);
5112 temp = E1000_READ_REG(hw, GPRC);
5113 temp = E1000_READ_REG(hw, BPRC);
5114 temp = E1000_READ_REG(hw, MPRC);
5115 temp = E1000_READ_REG(hw, GPTC);
5116 temp = E1000_READ_REG(hw, GORCL);
5117 temp = E1000_READ_REG(hw, GORCH);
5118 temp = E1000_READ_REG(hw, GOTCL);
5119 temp = E1000_READ_REG(hw, GOTCH);
5120 temp = E1000_READ_REG(hw, RNBC);
5121 temp = E1000_READ_REG(hw, RUC);
5122 temp = E1000_READ_REG(hw, RFC);
5123 temp = E1000_READ_REG(hw, ROC);
5124 temp = E1000_READ_REG(hw, RJC);
5125 temp = E1000_READ_REG(hw, TORL);
5126 temp = E1000_READ_REG(hw, TORH);
5127 temp = E1000_READ_REG(hw, TOTL);
5128 temp = E1000_READ_REG(hw, TOTH);
5129 temp = E1000_READ_REG(hw, TPR);
5130 temp = E1000_READ_REG(hw, TPT);
5131 temp = E1000_READ_REG(hw, PTC64);
5132 temp = E1000_READ_REG(hw, PTC127);
5133 temp = E1000_READ_REG(hw, PTC255);
5134 temp = E1000_READ_REG(hw, PTC511);
5135 temp = E1000_READ_REG(hw, PTC1023);
5136 temp = E1000_READ_REG(hw, PTC1522);
5137 temp = E1000_READ_REG(hw, MPTC);
5138 temp = E1000_READ_REG(hw, BPTC);
5140 if(hw->mac_type < e1000_82543) return;
5142 temp = E1000_READ_REG(hw, ALGNERRC);
5143 temp = E1000_READ_REG(hw, RXERRC);
5144 temp = E1000_READ_REG(hw, TNCRS);
5145 temp = E1000_READ_REG(hw, CEXTERR);
5146 temp = E1000_READ_REG(hw, TSCTC);
5147 temp = E1000_READ_REG(hw, TSCTFC);
5149 if(hw->mac_type <= e1000_82544) return;
5151 temp = E1000_READ_REG(hw, MGTPRC);
5152 temp = E1000_READ_REG(hw, MGTPDC);
5153 temp = E1000_READ_REG(hw, MGTPTC);
5155 if(hw->mac_type <= e1000_82547_rev_2) return;
5157 temp = E1000_READ_REG(hw, IAC);
5158 temp = E1000_READ_REG(hw, ICRXOC);
5159 temp = E1000_READ_REG(hw, ICRXPTC);
5160 temp = E1000_READ_REG(hw, ICRXATC);
5161 temp = E1000_READ_REG(hw, ICTXPTC);
5162 temp = E1000_READ_REG(hw, ICTXATC);
5163 temp = E1000_READ_REG(hw, ICTXQEC);
5164 temp = E1000_READ_REG(hw, ICTXQMTC);
5165 temp = E1000_READ_REG(hw, ICRXDMTC);
5168 /******************************************************************************
5169 * Resets Adaptive IFS to its default state.
5171 * hw - Struct containing variables accessed by shared code
5173 * Call this after e1000_init_hw. You may override the IFS defaults by setting
5174 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
5175 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
5176 * before calling this function.
5177 *****************************************************************************/
5179 e1000_reset_adaptive(struct e1000_hw *hw)
5181 DEBUGFUNC("e1000_reset_adaptive");
5183 if(hw->adaptive_ifs) {
5184 if(!hw->ifs_params_forced) {
5185 hw->current_ifs_val = 0;
5186 hw->ifs_min_val = IFS_MIN;
5187 hw->ifs_max_val = IFS_MAX;
5188 hw->ifs_step_size = IFS_STEP;
5189 hw->ifs_ratio = IFS_RATIO;
5191 hw->in_ifs_mode = FALSE;
5192 E1000_WRITE_REG(hw, AIT, 0);
5194 DEBUGOUT("Not in Adaptive IFS mode!\n");
5198 /******************************************************************************
5199 * Called during the callback/watchdog routine to update IFS value based on
5200 * the ratio of transmits to collisions.
5202 * hw - Struct containing variables accessed by shared code
5203 * tx_packets - Number of transmits since last callback
5204 * total_collisions - Number of collisions since last callback
5205 *****************************************************************************/
5207 e1000_update_adaptive(struct e1000_hw *hw)
5209 DEBUGFUNC("e1000_update_adaptive");
5211 if(hw->adaptive_ifs) {
5212 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
5213 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
5214 hw->in_ifs_mode = TRUE;
5215 if(hw->current_ifs_val < hw->ifs_max_val) {
5216 if(hw->current_ifs_val == 0)
5217 hw->current_ifs_val = hw->ifs_min_val;
5219 hw->current_ifs_val += hw->ifs_step_size;
5220 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
5224 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
5225 hw->current_ifs_val = 0;
5226 hw->in_ifs_mode = FALSE;
5227 E1000_WRITE_REG(hw, AIT, 0);
5231 DEBUGOUT("Not in Adaptive IFS mode!\n");
5235 /******************************************************************************
5236 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5238 * hw - Struct containing variables accessed by shared code
5239 * frame_len - The length of the frame in question
5240 * mac_addr - The Ethernet destination address of the frame in question
5241 *****************************************************************************/
5243 e1000_tbi_adjust_stats(struct e1000_hw *hw,
5244 struct e1000_hw_stats *stats,
5250 /* First adjust the frame length. */
5252 /* We need to adjust the statistics counters, since the hardware
5253 * counters overcount this packet as a CRC error and undercount
5254 * the packet as a good packet
5256 /* This packet should not be counted as a CRC error. */
5258 /* This packet does count as a Good Packet Received. */
5261 /* Adjust the Good Octets received counters */
5262 carry_bit = 0x80000000 & stats->gorcl;
5263 stats->gorcl += frame_len;
5264 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5265 * Received Count) was one before the addition,
5266 * AND it is zero after, then we lost the carry out,
5267 * need to add one to Gorch (Good Octets Received Count High).
5268 * This could be simplified if all environments supported
5271 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
5273 /* Is this a broadcast or multicast? Check broadcast first,
5274 * since the test for a multicast frame will test positive on
5275 * a broadcast frame.
5277 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
5278 /* Broadcast packet */
5280 else if(*mac_addr & 0x01)
5281 /* Multicast packet */
5284 if(frame_len == hw->max_frame_size) {
5285 /* In this case, the hardware has overcounted the number of
5292 /* Adjust the bin counters when the extra byte put the frame in the
5293 * wrong bin. Remember that the frame_len was adjusted above.
5295 if(frame_len == 64) {
5298 } else if(frame_len == 127) {
5301 } else if(frame_len == 255) {
5304 } else if(frame_len == 511) {
5307 } else if(frame_len == 1023) {
5310 } else if(frame_len == 1522) {
5315 /******************************************************************************
5316 * Gets the current PCI bus type, speed, and width of the hardware
5318 * hw - Struct containing variables accessed by shared code
5319 *****************************************************************************/
5321 e1000_get_bus_info(struct e1000_hw *hw)
5325 switch (hw->mac_type) {
5326 case e1000_82542_rev2_0:
5327 case e1000_82542_rev2_1:
5328 hw->bus_type = e1000_bus_type_unknown;
5329 hw->bus_speed = e1000_bus_speed_unknown;
5330 hw->bus_width = e1000_bus_width_unknown;
5334 hw->bus_type = e1000_bus_type_pci_express;
5335 hw->bus_speed = e1000_bus_speed_2500;
5336 hw->bus_width = e1000_bus_width_pciex_1;
5339 hw->bus_type = e1000_bus_type_pci_express;
5340 hw->bus_speed = e1000_bus_speed_2500;
5341 hw->bus_width = e1000_bus_width_pciex_4;
5344 status = E1000_READ_REG(hw, STATUS);
5345 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5346 e1000_bus_type_pcix : e1000_bus_type_pci;
5348 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
5349 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
5350 e1000_bus_speed_66 : e1000_bus_speed_120;
5351 } else if(hw->bus_type == e1000_bus_type_pci) {
5352 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
5353 e1000_bus_speed_66 : e1000_bus_speed_33;
5355 switch (status & E1000_STATUS_PCIX_SPEED) {
5356 case E1000_STATUS_PCIX_SPEED_66:
5357 hw->bus_speed = e1000_bus_speed_66;
5359 case E1000_STATUS_PCIX_SPEED_100:
5360 hw->bus_speed = e1000_bus_speed_100;
5362 case E1000_STATUS_PCIX_SPEED_133:
5363 hw->bus_speed = e1000_bus_speed_133;
5366 hw->bus_speed = e1000_bus_speed_reserved;
5370 hw->bus_width = (status & E1000_STATUS_BUS64) ?
5371 e1000_bus_width_64 : e1000_bus_width_32;
5377 /******************************************************************************
5378 * Reads a value from one of the devices registers using port I/O (as opposed
5379 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5381 * hw - Struct containing variables accessed by shared code
5382 * offset - offset to read from
5383 *****************************************************************************/
5385 e1000_read_reg_io(struct e1000_hw *hw,
5388 unsigned long io_addr = hw->io_base;
5389 unsigned long io_data = hw->io_base + 4;
5391 e1000_io_write(hw, io_addr, offset);
5392 return e1000_io_read(hw, io_data);
5396 /******************************************************************************
5397 * Writes a value to one of the devices registers using port I/O (as opposed to
5398 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5400 * hw - Struct containing variables accessed by shared code
5401 * offset - offset to write to
5402 * value - value to write
5403 *****************************************************************************/
5405 e1000_write_reg_io(struct e1000_hw *hw,
5409 unsigned long io_addr = hw->io_base;
5410 unsigned long io_data = hw->io_base + 4;
5412 e1000_io_write(hw, io_addr, offset);
5413 e1000_io_write(hw, io_data, value);
5417 /******************************************************************************
5418 * Estimates the cable length.
5420 * hw - Struct containing variables accessed by shared code
5421 * min_length - The estimated minimum length
5422 * max_length - The estimated maximum length
5424 * returns: - E1000_ERR_XXX
5427 * This function always returns a ranged length (minimum & maximum).
5428 * So for M88 phy's, this function interprets the one value returned from the
5429 * register to the minimum and maximum range.
5430 * For IGP phy's, the function calculates the range by the AGC registers.
5431 *****************************************************************************/
5433 e1000_get_cable_length(struct e1000_hw *hw,
5434 uint16_t *min_length,
5435 uint16_t *max_length)
5438 uint16_t agc_value = 0;
5439 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5440 uint16_t max_agc = 0;
5441 uint16_t i, phy_data;
5442 uint16_t cable_length;
5444 DEBUGFUNC("e1000_get_cable_length");
5446 *min_length = *max_length = 0;
5448 /* Use old method for Phy older than IGP */
5449 if(hw->phy_type == e1000_phy_m88) {
5451 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5455 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5456 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5458 /* Convert the enum value to ranged values */
5459 switch (cable_length) {
5460 case e1000_cable_length_50:
5462 *max_length = e1000_igp_cable_length_50;
5464 case e1000_cable_length_50_80:
5465 *min_length = e1000_igp_cable_length_50;
5466 *max_length = e1000_igp_cable_length_80;
5468 case e1000_cable_length_80_110:
5469 *min_length = e1000_igp_cable_length_80;
5470 *max_length = e1000_igp_cable_length_110;
5472 case e1000_cable_length_110_140:
5473 *min_length = e1000_igp_cable_length_110;
5474 *max_length = e1000_igp_cable_length_140;
5476 case e1000_cable_length_140:
5477 *min_length = e1000_igp_cable_length_140;
5478 *max_length = e1000_igp_cable_length_170;
5481 return -E1000_ERR_PHY;
5484 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
5485 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5486 {IGP01E1000_PHY_AGC_A,
5487 IGP01E1000_PHY_AGC_B,
5488 IGP01E1000_PHY_AGC_C,
5489 IGP01E1000_PHY_AGC_D};
5490 /* Read the AGC registers for all channels */
5491 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5493 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5497 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5499 /* Array bound check. */
5500 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
5502 return -E1000_ERR_PHY;
5504 agc_value += cur_agc;
5506 /* Update minimal AGC value. */
5507 if(min_agc > cur_agc)
5511 /* Remove the minimal AGC result for length < 50m */
5512 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
5513 agc_value -= min_agc;
5515 /* Get the average length of the remaining 3 channels */
5516 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5518 /* Get the average length of all the 4 channels. */
5519 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5522 /* Set the range of the calculated length. */
5523 *min_length = ((e1000_igp_cable_length_table[agc_value] -
5524 IGP01E1000_AGC_RANGE) > 0) ?
5525 (e1000_igp_cable_length_table[agc_value] -
5526 IGP01E1000_AGC_RANGE) : 0;
5527 *max_length = e1000_igp_cable_length_table[agc_value] +
5528 IGP01E1000_AGC_RANGE;
5529 } else if (hw->phy_type == e1000_phy_igp_2) {
5530 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
5531 {IGP02E1000_PHY_AGC_A,
5532 IGP02E1000_PHY_AGC_B,
5533 IGP02E1000_PHY_AGC_C,
5534 IGP02E1000_PHY_AGC_D};
5535 /* Read the AGC registers for all channels */
5536 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
5537 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5541 /* Getting bits 15:9, which represent the combination of course and
5542 * fine gain values. The result is a number that can be put into
5543 * the lookup table to obtain the approximate cable length. */
5544 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
5545 IGP02E1000_AGC_LENGTH_MASK;
5547 /* Remove min & max AGC values from calculation. */
5548 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc])
5550 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc])
5553 agc_value += e1000_igp_2_cable_length_table[cur_agc];
5556 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]);
5557 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
5559 /* Calculate cable length with the error range of +/- 10 meters. */
5560 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
5561 (agc_value - IGP02E1000_AGC_RANGE) : 0;
5562 *max_length = agc_value + IGP02E1000_AGC_RANGE;
5565 return E1000_SUCCESS;
5568 /******************************************************************************
5569 * Check the cable polarity
5571 * hw - Struct containing variables accessed by shared code
5572 * polarity - output parameter : 0 - Polarity is not reversed
5573 * 1 - Polarity is reversed.
5575 * returns: - E1000_ERR_XXX
5578 * For phy's older then IGP, this function simply reads the polarity bit in the
5579 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5580 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5581 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5582 * IGP01E1000_PHY_PCS_INIT_REG.
5583 *****************************************************************************/
5585 e1000_check_polarity(struct e1000_hw *hw,
5591 DEBUGFUNC("e1000_check_polarity");
5593 if(hw->phy_type == e1000_phy_m88) {
5594 /* return the Polarity bit in the Status register. */
5595 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5599 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
5600 M88E1000_PSSR_REV_POLARITY_SHIFT;
5601 } else if(hw->phy_type == e1000_phy_igp ||
5602 hw->phy_type == e1000_phy_igp_2) {
5603 /* Read the Status register to check the speed */
5604 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5609 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5610 * find the polarity status */
5611 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5612 IGP01E1000_PSSR_SPEED_1000MBPS) {
5614 /* Read the GIG initialization PCS register (0x00B4) */
5615 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5620 /* Check the polarity bits */
5621 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
5623 /* For 10 Mbps, read the polarity bit in the status register. (for
5624 * 100 Mbps this bit is always 0) */
5625 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
5628 return E1000_SUCCESS;
5631 /******************************************************************************
5632 * Check if Downshift occured
5634 * hw - Struct containing variables accessed by shared code
5635 * downshift - output parameter : 0 - No Downshift ocured.
5636 * 1 - Downshift ocured.
5638 * returns: - E1000_ERR_XXX
5641 * For phy's older then IGP, this function reads the Downshift bit in the Phy
5642 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5643 * Link Health register. In IGP this bit is latched high, so the driver must
5644 * read it immediately after link is established.
5645 *****************************************************************************/
5647 e1000_check_downshift(struct e1000_hw *hw)
5652 DEBUGFUNC("e1000_check_downshift");
5654 if(hw->phy_type == e1000_phy_igp ||
5655 hw->phy_type == e1000_phy_igp_2) {
5656 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5661 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5662 } else if(hw->phy_type == e1000_phy_m88) {
5663 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5668 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5669 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5672 return E1000_SUCCESS;
5675 /*****************************************************************************
5677 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5678 * gigabit link is achieved to improve link quality.
5680 * hw: Struct containing variables accessed by shared code
5682 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5683 * E1000_SUCCESS at any other case.
5685 ****************************************************************************/
5688 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5692 uint16_t phy_data, phy_saved_data, speed, duplex, i;
5693 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5694 {IGP01E1000_PHY_AGC_PARAM_A,
5695 IGP01E1000_PHY_AGC_PARAM_B,
5696 IGP01E1000_PHY_AGC_PARAM_C,
5697 IGP01E1000_PHY_AGC_PARAM_D};
5698 uint16_t min_length, max_length;
5700 DEBUGFUNC("e1000_config_dsp_after_link_change");
5702 if(hw->phy_type != e1000_phy_igp)
5703 return E1000_SUCCESS;
5706 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5708 DEBUGOUT("Error getting link speed and duplex\n");
5712 if(speed == SPEED_1000) {
5714 e1000_get_cable_length(hw, &min_length, &max_length);
5716 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
5717 min_length >= e1000_igp_cable_length_50) {
5719 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5720 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5725 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5727 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5732 hw->dsp_config_state = e1000_dsp_config_activated;
5735 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
5736 (min_length < e1000_igp_cable_length_50)) {
5738 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5739 uint32_t idle_errs = 0;
5741 /* clear previous idle error counts */
5742 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5747 for(i = 0; i < ffe_idle_err_timeout; i++) {
5749 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5754 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5755 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5756 hw->ffe_config_state = e1000_ffe_config_active;
5758 ret_val = e1000_write_phy_reg(hw,
5759 IGP01E1000_PHY_DSP_FFE,
5760 IGP01E1000_PHY_DSP_FFE_CM_CP);
5767 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5772 if(hw->dsp_config_state == e1000_dsp_config_activated) {
5773 /* Save off the current value of register 0x2F5B to be restored at
5774 * the end of the routines. */
5775 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5780 /* Disable the PHY transmitter */
5781 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5788 ret_val = e1000_write_phy_reg(hw, 0x0000,
5789 IGP01E1000_IEEE_FORCE_GIGA);
5792 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5793 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
5797 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5798 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5800 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
5805 ret_val = e1000_write_phy_reg(hw, 0x0000,
5806 IGP01E1000_IEEE_RESTART_AUTONEG);
5812 /* Now enable the transmitter */
5813 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5818 hw->dsp_config_state = e1000_dsp_config_enabled;
5821 if(hw->ffe_config_state == e1000_ffe_config_active) {
5822 /* Save off the current value of register 0x2F5B to be restored at
5823 * the end of the routines. */
5824 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5829 /* Disable the PHY transmitter */
5830 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5837 ret_val = e1000_write_phy_reg(hw, 0x0000,
5838 IGP01E1000_IEEE_FORCE_GIGA);
5841 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5842 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5846 ret_val = e1000_write_phy_reg(hw, 0x0000,
5847 IGP01E1000_IEEE_RESTART_AUTONEG);
5853 /* Now enable the transmitter */
5854 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5859 hw->ffe_config_state = e1000_ffe_config_enabled;
5862 return E1000_SUCCESS;
5865 /*****************************************************************************
5866 * Set PHY to class A mode
5867 * Assumes the following operations will follow to enable the new class mode.
5868 * 1. Do a PHY soft reset
5869 * 2. Restart auto-negotiation or force link.
5871 * hw - Struct containing variables accessed by shared code
5872 ****************************************************************************/
5874 e1000_set_phy_mode(struct e1000_hw *hw)
5877 uint16_t eeprom_data;
5879 DEBUGFUNC("e1000_set_phy_mode");
5881 if((hw->mac_type == e1000_82545_rev_3) &&
5882 (hw->media_type == e1000_media_type_copper)) {
5883 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
5888 if((eeprom_data != EEPROM_RESERVED_WORD) &&
5889 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5890 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
5893 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
5897 hw->phy_reset_disable = FALSE;
5901 return E1000_SUCCESS;
5904 /*****************************************************************************
5906 * This function sets the lplu state according to the active flag. When
5907 * activating lplu this function also disables smart speed and vise versa.
5908 * lplu will not be activated unless the device autonegotiation advertisment
5909 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5910 * hw: Struct containing variables accessed by shared code
5911 * active - true to enable lplu false to disable lplu.
5913 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5914 * E1000_SUCCESS at any other case.
5916 ****************************************************************************/
5919 e1000_set_d3_lplu_state(struct e1000_hw *hw,
5924 DEBUGFUNC("e1000_set_d3_lplu_state");
5926 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
5927 return E1000_SUCCESS;
5929 /* During driver activity LPLU should not be used or it will attain link
5930 * from the lowest speeds starting from 10Mbps. The capability is used for
5931 * Dx transitions and states */
5932 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
5933 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5937 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5943 if(hw->mac_type == e1000_82541_rev_2 ||
5944 hw->mac_type == e1000_82547_rev_2) {
5945 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5946 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5950 phy_data &= ~IGP02E1000_PM_D3_LPLU;
5951 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5957 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5958 * Dx states where the power conservation is most important. During
5959 * driver activity we should enable SmartSpeed, so performance is
5961 if (hw->smart_speed == e1000_smart_speed_on) {
5962 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5967 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5968 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5972 } else if (hw->smart_speed == e1000_smart_speed_off) {
5973 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5978 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5979 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5985 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5986 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5987 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5989 if(hw->mac_type == e1000_82541_rev_2 ||
5990 hw->mac_type == e1000_82547_rev_2) {
5991 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5992 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5996 phy_data |= IGP02E1000_PM_D3_LPLU;
5997 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6003 /* When LPLU is enabled we should disable SmartSpeed */
6004 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
6008 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6009 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
6014 return E1000_SUCCESS;
6017 /*****************************************************************************
6019 * This function sets the lplu d0 state according to the active flag. When
6020 * activating lplu this function also disables smart speed and vise versa.
6021 * lplu will not be activated unless the device autonegotiation advertisment
6022 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
6023 * hw: Struct containing variables accessed by shared code
6024 * active - true to enable lplu false to disable lplu.
6026 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6027 * E1000_SUCCESS at any other case.
6029 ****************************************************************************/
6032 e1000_set_d0_lplu_state(struct e1000_hw *hw,
6037 DEBUGFUNC("e1000_set_d0_lplu_state");
6039 if(hw->mac_type <= e1000_82547_rev_2)
6040 return E1000_SUCCESS;
6042 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6047 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6048 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6052 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6053 * Dx states where the power conservation is most important. During
6054 * driver activity we should enable SmartSpeed, so performance is
6056 if (hw->smart_speed == e1000_smart_speed_on) {
6057 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6062 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
6063 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6067 } else if (hw->smart_speed == e1000_smart_speed_off) {
6068 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6073 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6074 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6083 phy_data |= IGP02E1000_PM_D0_LPLU;
6084 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6088 /* When LPLU is enabled we should disable SmartSpeed */
6089 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
6093 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6094 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
6099 return E1000_SUCCESS;
6102 /******************************************************************************
6103 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
6105 * hw - Struct containing variables accessed by shared code
6106 *****************************************************************************/
6108 e1000_set_vco_speed(struct e1000_hw *hw)
6111 uint16_t default_page = 0;
6114 DEBUGFUNC("e1000_set_vco_speed");
6116 switch(hw->mac_type) {
6117 case e1000_82545_rev_3:
6118 case e1000_82546_rev_3:
6121 return E1000_SUCCESS;
6124 /* Set PHY register 30, page 5, bit 8 to 0 */
6126 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
6130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
6134 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6138 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
6139 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6143 /* Set PHY register 30, page 4, bit 11 to 1 */
6145 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
6149 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6153 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
6154 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6158 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
6162 return E1000_SUCCESS;
6166 /*****************************************************************************
6167 * This function reads the cookie from ARC ram.
6169 * returns: - E1000_SUCCESS .
6170 ****************************************************************************/
6172 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
6175 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
6176 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
6178 length = (length >> 2);
6179 offset = (offset >> 2);
6181 for (i = 0; i < length; i++) {
6182 *((uint32_t *) buffer + i) =
6183 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
6185 return E1000_SUCCESS;
6189 /*****************************************************************************
6190 * This function checks whether the HOST IF is enabled for command operaton
6191 * and also checks whether the previous command is completed.
6192 * It busy waits in case of previous command is not completed.
6194 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
6196 * - E1000_SUCCESS for success.
6197 ****************************************************************************/
6199 e1000_mng_enable_host_if(struct e1000_hw * hw)
6204 /* Check that the host interface is enabled. */
6205 hicr = E1000_READ_REG(hw, HICR);
6206 if ((hicr & E1000_HICR_EN) == 0) {
6207 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
6208 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6210 /* check the previous command is completed */
6211 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
6212 hicr = E1000_READ_REG(hw, HICR);
6213 if (!(hicr & E1000_HICR_C))
6218 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
6219 DEBUGOUT("Previous command timeout failed .\n");
6220 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6222 return E1000_SUCCESS;
6225 /*****************************************************************************
6226 * This function writes the buffer content at the offset given on the host if.
6227 * It also does alignment considerations to do the writes in most efficient way.
6228 * Also fills up the sum of the buffer in *buffer parameter.
6230 * returns - E1000_SUCCESS for success.
6231 ****************************************************************************/
6233 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6234 uint16_t length, uint16_t offset, uint8_t *sum)
6237 uint8_t *bufptr = buffer;
6239 uint16_t remaining, i, j, prev_bytes;
6241 /* sum = only sum of the data and it is not checksum */
6243 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6244 return -E1000_ERR_PARAM;
6247 tmp = (uint8_t *)&data;
6248 prev_bytes = offset & 0x3;
6253 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6254 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6255 *(tmp + j) = *bufptr++;
6258 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6259 length -= j - prev_bytes;
6263 remaining = length & 0x3;
6264 length -= remaining;
6266 /* Calculate length in DWORDs */
6269 /* The device driver writes the relevant command block into the
6271 for (i = 0; i < length; i++) {
6272 for (j = 0; j < sizeof(uint32_t); j++) {
6273 *(tmp + j) = *bufptr++;
6277 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6280 for (j = 0; j < sizeof(uint32_t); j++) {
6282 *(tmp + j) = *bufptr++;
6288 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6291 return E1000_SUCCESS;
6295 /*****************************************************************************
6296 * This function writes the command header after does the checksum calculation.
6298 * returns - E1000_SUCCESS for success.
6299 ****************************************************************************/
6301 e1000_mng_write_cmd_header(struct e1000_hw * hw,
6302 struct e1000_host_mng_command_header * hdr)
6308 /* Write the whole command header structure which includes sum of
6311 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6313 sum = hdr->checksum;
6316 buffer = (uint8_t *) hdr;
6321 hdr->checksum = 0 - sum;
6324 /* The device driver writes the relevant command block into the ram area. */
6325 for (i = 0; i < length; i++)
6326 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6328 return E1000_SUCCESS;
6332 /*****************************************************************************
6333 * This function indicates to ARC that a new command is pending which completes
6334 * one write operation by the driver.
6336 * returns - E1000_SUCCESS for success.
6337 ****************************************************************************/
6339 e1000_mng_write_commit(
6340 struct e1000_hw * hw)
6344 hicr = E1000_READ_REG(hw, HICR);
6345 /* Setting this bit tells the ARC that a new command is pending. */
6346 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6348 return E1000_SUCCESS;
6352 /*****************************************************************************
6353 * This function checks the mode of the firmware.
6355 * returns - TRUE when the mode is IAMT or FALSE.
6356 ****************************************************************************/
6358 e1000_check_mng_mode(
6359 struct e1000_hw *hw)
6363 fwsm = E1000_READ_REG(hw, FWSM);
6365 if((fwsm & E1000_FWSM_MODE_MASK) ==
6366 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6373 /*****************************************************************************
6374 * This function writes the dhcp info .
6375 ****************************************************************************/
6377 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
6381 struct e1000_host_mng_command_header hdr;
6383 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6384 hdr.command_length = length;
6389 ret_val = e1000_mng_enable_host_if(hw);
6390 if (ret_val == E1000_SUCCESS) {
6391 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6393 if (ret_val == E1000_SUCCESS) {
6394 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
6395 if (ret_val == E1000_SUCCESS)
6396 ret_val = e1000_mng_write_commit(hw);
6403 /*****************************************************************************
6404 * This function calculates the checksum.
6406 * returns - checksum of buffer contents.
6407 ****************************************************************************/
6409 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
6417 for (i=0; i < length; i++)
6420 return (uint8_t) (0 - sum);
6423 /*****************************************************************************
6424 * This function checks whether tx pkt filtering needs to be enabled or not.
6426 * returns - TRUE for packet filtering or FALSE.
6427 ****************************************************************************/
6429 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
6431 /* called in init as well as watchdog timer functions */
6433 int32_t ret_val, checksum;
6434 boolean_t tx_filter = FALSE;
6435 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
6436 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
6438 if (e1000_check_mng_mode(hw)) {
6439 ret_val = e1000_mng_enable_host_if(hw);
6440 if (ret_val == E1000_SUCCESS) {
6441 ret_val = e1000_host_if_read_cookie(hw, buffer);
6442 if (ret_val == E1000_SUCCESS) {
6443 checksum = hdr->checksum;
6445 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
6446 checksum == e1000_calculate_mng_checksum((char *)buffer,
6447 E1000_MNG_DHCP_COOKIE_LENGTH)) {
6449 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
6458 hw->tx_pkt_filtering = tx_filter;
6462 /******************************************************************************
6463 * Verifies the hardware needs to allow ARPs to be processed by the host
6465 * hw - Struct containing variables accessed by shared code
6467 * returns: - TRUE/FALSE
6469 *****************************************************************************/
6471 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
6474 uint32_t fwsm, factps;
6476 if (hw->asf_firmware_present) {
6477 manc = E1000_READ_REG(hw, MANC);
6479 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
6480 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
6482 if (e1000_arc_subsystem_valid(hw) == TRUE) {
6483 fwsm = E1000_READ_REG(hw, FWSM);
6484 factps = E1000_READ_REG(hw, FACTPS);
6486 if (((fwsm & E1000_FWSM_MODE_MASK) ==
6487 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
6488 (factps & E1000_FACTPS_MNGCG))
6491 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
6498 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
6501 uint16_t mii_status_reg;
6504 /* Polarity reversal workaround for forced 10F/10H links. */
6506 /* Disable the transmitter on the PHY */
6508 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
6511 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
6515 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
6519 /* This loop will early-out if the NO link condition has been met. */
6520 for(i = PHY_FORCE_TIME; i > 0; i--) {
6521 /* Read the MII Status Register and wait for Link Status bit
6525 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6529 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6533 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
6534 msec_delay_irq(100);
6537 /* Recommended delay time after link has been lost */
6538 msec_delay_irq(1000);
6540 /* Now we will re-enable th transmitter on the PHY */
6542 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
6546 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
6550 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
6554 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
6558 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
6562 /* This loop will early-out if the link condition has been met. */
6563 for(i = PHY_FORCE_TIME; i > 0; i--) {
6564 /* Read the MII Status Register and wait for Link Status bit
6568 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6572 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6576 if(mii_status_reg & MII_SR_LINK_STATUS) break;
6577 msec_delay_irq(100);
6579 return E1000_SUCCESS;
6582 /***************************************************************************
6584 * Disables PCI-Express master access.
6586 * hw: Struct containing variables accessed by shared code
6590 ***************************************************************************/
6592 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
6596 DEBUGFUNC("e1000_set_pci_express_master_disable");
6598 if (hw->bus_type != e1000_bus_type_pci_express)
6601 ctrl = E1000_READ_REG(hw, CTRL);
6602 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
6603 E1000_WRITE_REG(hw, CTRL, ctrl);
6607 /***************************************************************************
6609 * Enables PCI-Express master access.
6611 * hw: Struct containing variables accessed by shared code
6615 ***************************************************************************/
6617 e1000_enable_pciex_master(struct e1000_hw *hw)
6621 DEBUGFUNC("e1000_enable_pciex_master");
6623 if (hw->bus_type != e1000_bus_type_pci_express)
6626 ctrl = E1000_READ_REG(hw, CTRL);
6627 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
6628 E1000_WRITE_REG(hw, CTRL, ctrl);
6632 /*******************************************************************************
6634 * Disables PCI-Express master access and verifies there are no pending requests
6636 * hw: Struct containing variables accessed by shared code
6638 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6639 * caused the master requests to be disabled.
6640 * E1000_SUCCESS master requests disabled.
6642 ******************************************************************************/
6644 e1000_disable_pciex_master(struct e1000_hw *hw)
6646 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
6648 DEBUGFUNC("e1000_disable_pciex_master");
6650 if (hw->bus_type != e1000_bus_type_pci_express)
6651 return E1000_SUCCESS;
6653 e1000_set_pci_express_master_disable(hw);
6656 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
6664 DEBUGOUT("Master requests are pending.\n");
6665 return -E1000_ERR_MASTER_REQUESTS_PENDING;
6668 return E1000_SUCCESS;
6671 /*******************************************************************************
6673 * Check for EEPROM Auto Read bit done.
6675 * hw: Struct containing variables accessed by shared code
6677 * returns: - E1000_ERR_RESET if fail to reset MAC
6678 * E1000_SUCCESS at any other case.
6680 ******************************************************************************/
6682 e1000_get_auto_rd_done(struct e1000_hw *hw)
6684 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
6686 DEBUGFUNC("e1000_get_auto_rd_done");
6688 switch (hw->mac_type) {
6696 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
6702 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6703 return -E1000_ERR_RESET;
6708 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
6709 * Need to wait for PHY configuration completion before accessing NVM
6711 if (hw->mac_type == e1000_82573)
6714 return E1000_SUCCESS;
6717 /***************************************************************************
6718 * Checks if the PHY configuration is done
6720 * hw: Struct containing variables accessed by shared code
6722 * returns: - E1000_ERR_RESET if fail to reset MAC
6723 * E1000_SUCCESS at any other case.
6725 ***************************************************************************/
6727 e1000_get_phy_cfg_done(struct e1000_hw *hw)
6729 int32_t timeout = PHY_CFG_TIMEOUT;
6730 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
6732 DEBUGFUNC("e1000_get_phy_cfg_done");
6734 switch (hw->mac_type) {
6741 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
6749 DEBUGOUT("MNG configuration cycle has not completed.\n");
6750 return -E1000_ERR_RESET;
6755 return E1000_SUCCESS;
6758 /***************************************************************************
6760 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6761 * adapter or Eeprom access.
6763 * hw: Struct containing variables accessed by shared code
6765 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6766 * E1000_SUCCESS at any other case.
6768 ***************************************************************************/
6770 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
6775 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6777 if(!hw->eeprom_semaphore_present)
6778 return E1000_SUCCESS;
6781 /* Get the FW semaphore. */
6782 timeout = hw->eeprom.word_size + 1;
6784 swsm = E1000_READ_REG(hw, SWSM);
6785 swsm |= E1000_SWSM_SWESMBI;
6786 E1000_WRITE_REG(hw, SWSM, swsm);
6787 /* if we managed to set the bit we got the semaphore. */
6788 swsm = E1000_READ_REG(hw, SWSM);
6789 if(swsm & E1000_SWSM_SWESMBI)
6797 /* Release semaphores */
6798 e1000_put_hw_eeprom_semaphore(hw);
6799 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6800 return -E1000_ERR_EEPROM;
6803 return E1000_SUCCESS;
6806 /***************************************************************************
6807 * This function clears HW semaphore bits.
6809 * hw: Struct containing variables accessed by shared code
6813 ***************************************************************************/
6815 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
6819 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6821 if(!hw->eeprom_semaphore_present)
6824 swsm = E1000_READ_REG(hw, SWSM);
6825 swsm &= ~(E1000_SWSM_SWESMBI);
6826 E1000_WRITE_REG(hw, SWSM, swsm);
6829 /******************************************************************************
6830 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6831 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6832 * the caller to figure out how to deal with it.
6834 * hw - Struct containing variables accessed by shared code
6836 * returns: - E1000_BLK_PHY_RESET
6839 *****************************************************************************/
6841 e1000_check_phy_reset_block(struct e1000_hw *hw)
6845 if (hw->mac_type > e1000_82547_rev_2)
6846 manc = E1000_READ_REG(hw, MANC);
6847 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
6848 E1000_BLK_PHY_RESET : E1000_SUCCESS;
6852 e1000_arc_subsystem_valid(struct e1000_hw *hw)
6856 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6857 * may not be provided a DMA clock when no manageability features are
6858 * enabled. We do not want to perform any reads/writes to these registers
6859 * if this is the case. We read FWSM to determine the manageability mode.
6861 switch (hw->mac_type) {
6865 fwsm = E1000_READ_REG(hw, FWSM);
6866 if((fwsm & E1000_FWSM_MODE_MASK) != 0)