1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table[] =
40 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
42 static const u16 e1000_igp_2_cable_length_table[] =
43 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
44 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
45 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
46 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
47 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
48 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
49 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
51 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
52 ARRAY_SIZE(e1000_igp_2_cable_length_table)
55 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
56 * @hw: pointer to the HW structure
58 * Read the PHY management control register and check whether a PHY reset
59 * is blocked. If a reset is not blocked return 0, otherwise
60 * return E1000_BLK_PHY_RESET (12).
62 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
68 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
69 E1000_BLK_PHY_RESET : 0;
73 * e1000e_get_phy_id - Retrieve the PHY ID and revision
74 * @hw: pointer to the HW structure
76 * Reads the PHY registers and stores the PHY ID and possibly the PHY
77 * revision in the hardware structure.
79 s32 e1000e_get_phy_id(struct e1000_hw *hw)
81 struct e1000_phy_info *phy = &hw->phy;
85 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
89 phy->id = (u32)(phy_id << 16);
91 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
95 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
96 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
102 * e1000e_phy_reset_dsp - Reset PHY DSP
103 * @hw: pointer to the HW structure
105 * Reset the digital signal processor.
107 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
111 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
115 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
119 * e1000_read_phy_reg_mdic - Read MDI control register
120 * @hw: pointer to the HW structure
121 * @offset: register offset to be read
122 * @data: pointer to the read data
124 * Reads the MDI control register in the PHY at offset and stores the
125 * information read to data.
127 static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
129 struct e1000_phy_info *phy = &hw->phy;
132 if (offset > MAX_PHY_REG_ADDRESS) {
133 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
134 return -E1000_ERR_PARAM;
138 * Set up Op-code, Phy Address, and register offset in the MDI
139 * Control register. The MAC will take care of interfacing with the
140 * PHY to retrieve the desired data.
142 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
143 (phy->addr << E1000_MDIC_PHY_SHIFT) |
144 (E1000_MDIC_OP_READ));
149 * Poll the ready bit to see if the MDI read completed
150 * Increasing the time out as testing showed failures with
153 for (i = 0; i < 64; i++) {
156 if (mdic & E1000_MDIC_READY)
159 if (!(mdic & E1000_MDIC_READY)) {
160 hw_dbg(hw, "MDI Read did not complete\n");
161 return -E1000_ERR_PHY;
163 if (mdic & E1000_MDIC_ERROR) {
164 hw_dbg(hw, "MDI Error\n");
165 return -E1000_ERR_PHY;
173 * e1000_write_phy_reg_mdic - Write MDI control register
174 * @hw: pointer to the HW structure
175 * @offset: register offset to write to
176 * @data: data to write to register at offset
178 * Writes data to MDI control register in the PHY at offset.
180 static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
182 struct e1000_phy_info *phy = &hw->phy;
185 if (offset > MAX_PHY_REG_ADDRESS) {
186 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
187 return -E1000_ERR_PARAM;
191 * Set up Op-code, Phy Address, and register offset in the MDI
192 * Control register. The MAC will take care of interfacing with the
193 * PHY to retrieve the desired data.
195 mdic = (((u32)data) |
196 (offset << E1000_MDIC_REG_SHIFT) |
197 (phy->addr << E1000_MDIC_PHY_SHIFT) |
198 (E1000_MDIC_OP_WRITE));
202 /* Poll the ready bit to see if the MDI read completed */
203 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
206 if (mdic & E1000_MDIC_READY)
209 if (!(mdic & E1000_MDIC_READY)) {
210 hw_dbg(hw, "MDI Write did not complete\n");
211 return -E1000_ERR_PHY;
218 * e1000e_read_phy_reg_m88 - Read m88 PHY register
219 * @hw: pointer to the HW structure
220 * @offset: register offset to be read
221 * @data: pointer to the read data
223 * Acquires semaphore, if necessary, then reads the PHY register at offset
224 * and storing the retrieved information in data. Release any acquired
225 * semaphores before exiting.
227 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
231 ret_val = hw->phy.ops.acquire_phy(hw);
235 ret_val = e1000_read_phy_reg_mdic(hw,
236 MAX_PHY_REG_ADDRESS & offset,
239 hw->phy.ops.release_phy(hw);
245 * e1000e_write_phy_reg_m88 - Write m88 PHY register
246 * @hw: pointer to the HW structure
247 * @offset: register offset to write to
248 * @data: data to write at register offset
250 * Acquires semaphore, if necessary, then writes the data to PHY register
251 * at the offset. Release any acquired semaphores before exiting.
253 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
257 ret_val = hw->phy.ops.acquire_phy(hw);
261 ret_val = e1000_write_phy_reg_mdic(hw,
262 MAX_PHY_REG_ADDRESS & offset,
265 hw->phy.ops.release_phy(hw);
271 * e1000e_read_phy_reg_igp - Read igp PHY register
272 * @hw: pointer to the HW structure
273 * @offset: register offset to be read
274 * @data: pointer to the read data
276 * Acquires semaphore, if necessary, then reads the PHY register at offset
277 * and storing the retrieved information in data. Release any acquired
278 * semaphores before exiting.
280 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
284 ret_val = hw->phy.ops.acquire_phy(hw);
288 if (offset > MAX_PHY_MULTI_PAGE_REG) {
289 ret_val = e1000_write_phy_reg_mdic(hw,
290 IGP01E1000_PHY_PAGE_SELECT,
293 hw->phy.ops.release_phy(hw);
298 ret_val = e1000_read_phy_reg_mdic(hw,
299 MAX_PHY_REG_ADDRESS & offset,
302 hw->phy.ops.release_phy(hw);
308 * e1000e_write_phy_reg_igp - Write igp PHY register
309 * @hw: pointer to the HW structure
310 * @offset: register offset to write to
311 * @data: data to write at register offset
313 * Acquires semaphore, if necessary, then writes the data to PHY register
314 * at the offset. Release any acquired semaphores before exiting.
316 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
320 ret_val = hw->phy.ops.acquire_phy(hw);
324 if (offset > MAX_PHY_MULTI_PAGE_REG) {
325 ret_val = e1000_write_phy_reg_mdic(hw,
326 IGP01E1000_PHY_PAGE_SELECT,
329 hw->phy.ops.release_phy(hw);
334 ret_val = e1000_write_phy_reg_mdic(hw,
335 MAX_PHY_REG_ADDRESS & offset,
338 hw->phy.ops.release_phy(hw);
344 * e1000e_read_kmrn_reg - Read kumeran register
345 * @hw: pointer to the HW structure
346 * @offset: register offset to be read
347 * @data: pointer to the read data
349 * Acquires semaphore, if necessary. Then reads the PHY register at offset
350 * using the kumeran interface. The information retrieved is stored in data.
351 * Release any acquired semaphores before exiting.
353 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
358 ret_val = hw->phy.ops.acquire_phy(hw);
362 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
363 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
364 ew32(KMRNCTRLSTA, kmrnctrlsta);
368 kmrnctrlsta = er32(KMRNCTRLSTA);
369 *data = (u16)kmrnctrlsta;
371 hw->phy.ops.release_phy(hw);
377 * e1000e_write_kmrn_reg - Write kumeran register
378 * @hw: pointer to the HW structure
379 * @offset: register offset to write to
380 * @data: data to write at register offset
382 * Acquires semaphore, if necessary. Then write the data to PHY register
383 * at the offset using the kumeran interface. Release any acquired semaphores
386 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
391 ret_val = hw->phy.ops.acquire_phy(hw);
395 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
396 E1000_KMRNCTRLSTA_OFFSET) | data;
397 ew32(KMRNCTRLSTA, kmrnctrlsta);
400 hw->phy.ops.release_phy(hw);
406 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
407 * @hw: pointer to the HW structure
409 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
410 * and downshift values are set also.
412 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
414 struct e1000_phy_info *phy = &hw->phy;
418 /* Enable CRS on Tx. This must be set for half-duplex operation. */
419 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
423 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
427 * MDI/MDI-X = 0 (default)
428 * 0 - Auto for all speeds
431 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
433 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
437 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
440 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
443 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
447 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
453 * disable_polarity_correction = 0 (default)
454 * Automatic Correction for Reversed Cable Polarity
458 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
459 if (phy->disable_polarity_correction == 1)
460 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
462 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
466 if (phy->revision < 4) {
468 * Force TX_CLK in the Extended PHY Specific Control Register
471 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
475 phy_data |= M88E1000_EPSCR_TX_CLK_25;
477 if ((phy->revision == 2) &&
478 (phy->id == M88E1111_I_PHY_ID)) {
479 /* 82573L PHY - set the downshift counter to 5x. */
480 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
481 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
483 /* Configure Master and Slave downshift values */
484 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
485 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
486 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
487 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
489 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
494 /* Commit the changes. */
495 ret_val = e1000e_commit_phy(hw);
497 hw_dbg(hw, "Error committing the PHY changes\n");
503 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
504 * @hw: pointer to the HW structure
506 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
509 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
511 struct e1000_phy_info *phy = &hw->phy;
515 ret_val = e1000_phy_hw_reset(hw);
517 hw_dbg(hw, "Error resetting the PHY.\n");
521 /* Wait 15ms for MAC to configure PHY from NVM settings. */
524 /* disable lplu d0 during driver init */
525 ret_val = e1000_set_d0_lplu_state(hw, 0);
527 hw_dbg(hw, "Error Disabling LPLU D0\n");
530 /* Configure mdi-mdix settings */
531 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
535 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
539 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
542 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
546 data |= IGP01E1000_PSCR_AUTO_MDIX;
549 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
553 /* set auto-master slave resolution settings */
554 if (hw->mac.autoneg) {
556 * when autonegotiation advertisement is only 1000Mbps then we
557 * should disable SmartSpeed and enable Auto MasterSlave
558 * resolution as hardware default.
560 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
561 /* Disable SmartSpeed */
562 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
567 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
568 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
573 /* Set auto Master/Slave resolution process */
574 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
578 data &= ~CR_1000T_MS_ENABLE;
579 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
584 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
588 /* load defaults for future use */
589 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
590 ((data & CR_1000T_MS_VALUE) ?
591 e1000_ms_force_master :
592 e1000_ms_force_slave) :
595 switch (phy->ms_type) {
596 case e1000_ms_force_master:
597 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
599 case e1000_ms_force_slave:
600 data |= CR_1000T_MS_ENABLE;
601 data &= ~(CR_1000T_MS_VALUE);
604 data &= ~CR_1000T_MS_ENABLE;
608 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
615 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
616 * @hw: pointer to the HW structure
618 * Reads the MII auto-neg advertisement register and/or the 1000T control
619 * register and if the PHY is already setup for auto-negotiation, then
620 * return successful. Otherwise, setup advertisement and flow control to
621 * the appropriate values for the wanted auto-negotiation.
623 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
625 struct e1000_phy_info *phy = &hw->phy;
627 u16 mii_autoneg_adv_reg;
628 u16 mii_1000t_ctrl_reg = 0;
630 phy->autoneg_advertised &= phy->autoneg_mask;
632 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
633 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
637 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
638 /* Read the MII 1000Base-T Control Register (Address 9). */
639 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
645 * Need to parse both autoneg_advertised and fc and set up
646 * the appropriate PHY registers. First we will parse for
647 * autoneg_advertised software override. Since we can advertise
648 * a plethora of combinations, we need to check each bit
653 * First we clear all the 10/100 mb speed bits in the Auto-Neg
654 * Advertisement Register (Address 4) and the 1000 mb speed bits in
655 * the 1000Base-T Control Register (Address 9).
657 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
658 NWAY_AR_100TX_HD_CAPS |
659 NWAY_AR_10T_FD_CAPS |
660 NWAY_AR_10T_HD_CAPS);
661 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
663 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
665 /* Do we want to advertise 10 Mb Half Duplex? */
666 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
667 hw_dbg(hw, "Advertise 10mb Half duplex\n");
668 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
671 /* Do we want to advertise 10 Mb Full Duplex? */
672 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
673 hw_dbg(hw, "Advertise 10mb Full duplex\n");
674 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
677 /* Do we want to advertise 100 Mb Half Duplex? */
678 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
679 hw_dbg(hw, "Advertise 100mb Half duplex\n");
680 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
683 /* Do we want to advertise 100 Mb Full Duplex? */
684 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
685 hw_dbg(hw, "Advertise 100mb Full duplex\n");
686 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
689 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
690 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
691 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
693 /* Do we want to advertise 1000 Mb Full Duplex? */
694 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
695 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
696 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
700 * Check for a software override of the flow control settings, and
701 * setup the PHY advertisement registers accordingly. If
702 * auto-negotiation is enabled, then software will have to set the
703 * "PAUSE" bits to the correct value in the Auto-Negotiation
704 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
707 * The possible values of the "fc" parameter are:
708 * 0: Flow control is completely disabled
709 * 1: Rx flow control is enabled (we can receive pause frames
710 * but not send pause frames).
711 * 2: Tx flow control is enabled (we can send pause frames
712 * but we do not support receiving pause frames).
713 * 3: Both Rx and Tx flow control (symmetric) are enabled.
714 * other: No software override. The flow control configuration
715 * in the EEPROM is used.
717 switch (hw->fc.type) {
720 * Flow control (Rx & Tx) is completely disabled by a
721 * software over-ride.
723 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
725 case e1000_fc_rx_pause:
727 * Rx Flow control is enabled, and Tx Flow control is
728 * disabled, by a software over-ride.
730 * Since there really isn't a way to advertise that we are
731 * capable of Rx Pause ONLY, we will advertise that we
732 * support both symmetric and asymmetric Rx PAUSE. Later
733 * (in e1000e_config_fc_after_link_up) we will disable the
734 * hw's ability to send PAUSE frames.
736 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
738 case e1000_fc_tx_pause:
740 * Tx Flow control is enabled, and Rx Flow control is
741 * disabled, by a software over-ride.
743 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
744 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
748 * Flow control (both Rx and Tx) is enabled by a software
751 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
754 hw_dbg(hw, "Flow control param set incorrectly\n");
755 ret_val = -E1000_ERR_CONFIG;
759 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
763 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
765 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
766 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
773 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
774 * @hw: pointer to the HW structure
776 * Performs initial bounds checking on autoneg advertisement parameter, then
777 * configure to advertise the full capability. Setup the PHY to autoneg
778 * and restart the negotiation process between the link partner. If
779 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
781 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
783 struct e1000_phy_info *phy = &hw->phy;
788 * Perform some bounds checking on the autoneg advertisement
791 phy->autoneg_advertised &= phy->autoneg_mask;
794 * If autoneg_advertised is zero, we assume it was not defaulted
795 * by the calling code so we set to advertise full capability.
797 if (phy->autoneg_advertised == 0)
798 phy->autoneg_advertised = phy->autoneg_mask;
800 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
801 ret_val = e1000_phy_setup_autoneg(hw);
803 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
806 hw_dbg(hw, "Restarting Auto-Neg\n");
809 * Restart auto-negotiation by setting the Auto Neg Enable bit and
810 * the Auto Neg Restart bit in the PHY control register.
812 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
816 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
817 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
822 * Does the user want to wait for Auto-Neg to complete here, or
823 * check at a later time (for example, callback routine).
825 if (phy->autoneg_wait_to_complete) {
826 ret_val = e1000_wait_autoneg(hw);
828 hw_dbg(hw, "Error while waiting for "
829 "autoneg to complete\n");
834 hw->mac.get_link_status = 1;
840 * e1000e_setup_copper_link - Configure copper link settings
841 * @hw: pointer to the HW structure
843 * Calls the appropriate function to configure the link for auto-neg or forced
844 * speed and duplex. Then we check for link, once link is established calls
845 * to configure collision distance and flow control are called. If link is
846 * not established, we return -E1000_ERR_PHY (-2).
848 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
853 if (hw->mac.autoneg) {
855 * Setup autoneg and flow control advertisement and perform
858 ret_val = e1000_copper_link_autoneg(hw);
863 * PHY will be set to 10H, 10F, 100H or 100F
864 * depending on user settings.
866 hw_dbg(hw, "Forcing Speed and Duplex\n");
867 ret_val = e1000_phy_force_speed_duplex(hw);
869 hw_dbg(hw, "Error Forcing Speed and Duplex\n");
875 * Check link status. Wait up to 100 microseconds for link to become
878 ret_val = e1000e_phy_has_link_generic(hw,
879 COPPER_LINK_UP_LIMIT,
886 hw_dbg(hw, "Valid link established!!!\n");
887 e1000e_config_collision_dist(hw);
888 ret_val = e1000e_config_fc_after_link_up(hw);
890 hw_dbg(hw, "Unable to establish link!!!\n");
897 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
898 * @hw: pointer to the HW structure
900 * Calls the PHY setup function to force speed and duplex. Clears the
901 * auto-crossover to force MDI manually. Waits for link and returns
902 * successful if link up is successful, else -E1000_ERR_PHY (-2).
904 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
906 struct e1000_phy_info *phy = &hw->phy;
911 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
915 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
917 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
922 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
923 * forced whenever speed and duplex are forced.
925 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
929 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
930 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
932 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
936 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
940 if (phy->autoneg_wait_to_complete) {
941 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
943 ret_val = e1000e_phy_has_link_generic(hw,
951 hw_dbg(hw, "Link taking longer than expected.\n");
954 ret_val = e1000e_phy_has_link_generic(hw,
966 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
967 * @hw: pointer to the HW structure
969 * Calls the PHY setup function to force speed and duplex. Clears the
970 * auto-crossover to force MDI manually. Resets the PHY to commit the
971 * changes. If time expires while waiting for link up, we reset the DSP.
972 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
973 * successful completion, else return corresponding error code.
975 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
977 struct e1000_phy_info *phy = &hw->phy;
983 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
984 * forced whenever speed and duplex are forced.
986 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
990 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
991 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
995 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
997 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1001 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1003 /* Reset the phy to commit changes. */
1004 phy_data |= MII_CR_RESET;
1006 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1012 if (phy->autoneg_wait_to_complete) {
1013 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
1015 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1022 * We didn't get link.
1023 * Reset the DSP and cross our fingers.
1025 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1029 ret_val = e1000e_phy_reset_dsp(hw);
1035 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1041 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1046 * Resetting the phy means we need to re-force TX_CLK in the
1047 * Extended PHY Specific Control Register to 25MHz clock from
1048 * the reset value of 2.5MHz.
1050 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1051 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1056 * In addition, we must re-enable CRS on Tx for both half and full
1059 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1063 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1064 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1070 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1071 * @hw: pointer to the HW structure
1072 * @phy_ctrl: pointer to current value of PHY_CONTROL
1074 * Forces speed and duplex on the PHY by doing the following: disable flow
1075 * control, force speed/duplex on the MAC, disable auto speed detection,
1076 * disable auto-negotiation, configure duplex, configure speed, configure
1077 * the collision distance, write configuration to CTRL register. The
1078 * caller must write to the PHY_CONTROL register for these settings to
1081 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1083 struct e1000_mac_info *mac = &hw->mac;
1086 /* Turn off flow control when forcing speed/duplex */
1087 hw->fc.type = e1000_fc_none;
1089 /* Force speed/duplex on the mac */
1091 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1092 ctrl &= ~E1000_CTRL_SPD_SEL;
1094 /* Disable Auto Speed Detection */
1095 ctrl &= ~E1000_CTRL_ASDE;
1097 /* Disable autoneg on the phy */
1098 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1100 /* Forcing Full or Half Duplex? */
1101 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1102 ctrl &= ~E1000_CTRL_FD;
1103 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1104 hw_dbg(hw, "Half Duplex\n");
1106 ctrl |= E1000_CTRL_FD;
1107 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1108 hw_dbg(hw, "Full Duplex\n");
1111 /* Forcing 10mb or 100mb? */
1112 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1113 ctrl |= E1000_CTRL_SPD_100;
1114 *phy_ctrl |= MII_CR_SPEED_100;
1115 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1116 hw_dbg(hw, "Forcing 100mb\n");
1118 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1119 *phy_ctrl |= MII_CR_SPEED_10;
1120 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1121 hw_dbg(hw, "Forcing 10mb\n");
1124 e1000e_config_collision_dist(hw);
1130 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1131 * @hw: pointer to the HW structure
1132 * @active: boolean used to enable/disable lplu
1134 * Success returns 0, Failure returns 1
1136 * The low power link up (lplu) state is set to the power management level D3
1137 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1138 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1139 * is used during Dx states where the power conservation is most important.
1140 * During driver activity, SmartSpeed should be enabled so performance is
1143 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1145 struct e1000_phy_info *phy = &hw->phy;
1149 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1154 data &= ~IGP02E1000_PM_D3_LPLU;
1155 ret_val = e1e_wphy(hw,
1156 IGP02E1000_PHY_POWER_MGMT,
1161 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1162 * during Dx states where the power conservation is most
1163 * important. During driver activity we should enable
1164 * SmartSpeed, so performance is maintained.
1166 if (phy->smart_speed == e1000_smart_speed_on) {
1167 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1172 data |= IGP01E1000_PSCFR_SMART_SPEED;
1173 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1177 } else if (phy->smart_speed == e1000_smart_speed_off) {
1178 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1183 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1184 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1189 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1190 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1191 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1192 data |= IGP02E1000_PM_D3_LPLU;
1193 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1197 /* When LPLU is enabled, we should disable SmartSpeed */
1198 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1202 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1203 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1210 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1211 * @hw: pointer to the HW structure
1213 * Success returns 0, Failure returns 1
1215 * A downshift is detected by querying the PHY link health.
1217 s32 e1000e_check_downshift(struct e1000_hw *hw)
1219 struct e1000_phy_info *phy = &hw->phy;
1221 u16 phy_data, offset, mask;
1223 switch (phy->type) {
1225 case e1000_phy_gg82563:
1226 offset = M88E1000_PHY_SPEC_STATUS;
1227 mask = M88E1000_PSSR_DOWNSHIFT;
1229 case e1000_phy_igp_2:
1230 case e1000_phy_igp_3:
1231 offset = IGP01E1000_PHY_LINK_HEALTH;
1232 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1235 /* speed downshift not supported */
1236 phy->speed_downgraded = 0;
1240 ret_val = e1e_rphy(hw, offset, &phy_data);
1243 phy->speed_downgraded = (phy_data & mask);
1249 * e1000_check_polarity_m88 - Checks the polarity.
1250 * @hw: pointer to the HW structure
1252 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1254 * Polarity is determined based on the PHY specific status register.
1256 static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1258 struct e1000_phy_info *phy = &hw->phy;
1262 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1265 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1266 ? e1000_rev_polarity_reversed
1267 : e1000_rev_polarity_normal;
1273 * e1000_check_polarity_igp - Checks the polarity.
1274 * @hw: pointer to the HW structure
1276 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1278 * Polarity is determined based on the PHY port status register, and the
1279 * current speed (since there is no polarity at 100Mbps).
1281 static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1283 struct e1000_phy_info *phy = &hw->phy;
1285 u16 data, offset, mask;
1288 * Polarity is determined based on the speed of
1291 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1295 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1296 IGP01E1000_PSSR_SPEED_1000MBPS) {
1297 offset = IGP01E1000_PHY_PCS_INIT_REG;
1298 mask = IGP01E1000_PHY_POLARITY_MASK;
1301 * This really only applies to 10Mbps since
1302 * there is no polarity for 100Mbps (always 0).
1304 offset = IGP01E1000_PHY_PORT_STATUS;
1305 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1308 ret_val = e1e_rphy(hw, offset, &data);
1311 phy->cable_polarity = (data & mask)
1312 ? e1000_rev_polarity_reversed
1313 : e1000_rev_polarity_normal;
1319 * e1000_wait_autoneg - Wait for auto-neg completion
1320 * @hw: pointer to the HW structure
1322 * Waits for auto-negotiation to complete or for the auto-negotiation time
1323 * limit to expire, which ever happens first.
1325 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1330 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1331 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1332 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1335 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1338 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1344 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1351 * e1000e_phy_has_link_generic - Polls PHY for link
1352 * @hw: pointer to the HW structure
1353 * @iterations: number of times to poll for link
1354 * @usec_interval: delay between polling attempts
1355 * @success: pointer to whether polling was successful or not
1357 * Polls the PHY status register for link, 'iterations' number of times.
1359 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1360 u32 usec_interval, bool *success)
1365 for (i = 0; i < iterations; i++) {
1367 * Some PHYs require the PHY_STATUS register to be read
1368 * twice due to the link bit being sticky. No harm doing
1369 * it across the board.
1371 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1374 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1377 if (phy_status & MII_SR_LINK_STATUS)
1379 if (usec_interval >= 1000)
1380 mdelay(usec_interval/1000);
1382 udelay(usec_interval);
1385 *success = (i < iterations);
1391 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1392 * @hw: pointer to the HW structure
1394 * Reads the PHY specific status register to retrieve the cable length
1395 * information. The cable length is determined by averaging the minimum and
1396 * maximum values to get the "average" cable length. The m88 PHY has four
1397 * possible cable length values, which are:
1398 * Register Value Cable Length
1402 * 3 110 - 140 meters
1405 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1407 struct e1000_phy_info *phy = &hw->phy;
1409 u16 phy_data, index;
1411 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1415 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1416 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1417 phy->min_cable_length = e1000_m88_cable_length_table[index];
1418 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1420 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1426 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1427 * @hw: pointer to the HW structure
1429 * The automatic gain control (agc) normalizes the amplitude of the
1430 * received signal, adjusting for the attenuation produced by the
1431 * cable. By reading the AGC registers, which represent the
1432 * combination of course and fine gain value, the value can be put
1433 * into a lookup table to obtain the approximate cable length
1436 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1438 struct e1000_phy_info *phy = &hw->phy;
1440 u16 phy_data, i, agc_value = 0;
1441 u16 cur_agc_index, max_agc_index = 0;
1442 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1443 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1444 {IGP02E1000_PHY_AGC_A,
1445 IGP02E1000_PHY_AGC_B,
1446 IGP02E1000_PHY_AGC_C,
1447 IGP02E1000_PHY_AGC_D};
1449 /* Read the AGC registers for all channels */
1450 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1451 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1456 * Getting bits 15:9, which represent the combination of
1457 * course and fine gain values. The result is a number
1458 * that can be put into the lookup table to obtain the
1459 * approximate cable length.
1461 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1462 IGP02E1000_AGC_LENGTH_MASK;
1464 /* Array index bound check. */
1465 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1466 (cur_agc_index == 0))
1467 return -E1000_ERR_PHY;
1469 /* Remove min & max AGC values from calculation. */
1470 if (e1000_igp_2_cable_length_table[min_agc_index] >
1471 e1000_igp_2_cable_length_table[cur_agc_index])
1472 min_agc_index = cur_agc_index;
1473 if (e1000_igp_2_cable_length_table[max_agc_index] <
1474 e1000_igp_2_cable_length_table[cur_agc_index])
1475 max_agc_index = cur_agc_index;
1477 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1480 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1481 e1000_igp_2_cable_length_table[max_agc_index]);
1482 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1484 /* Calculate cable length with the error range of +/- 10 meters. */
1485 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1486 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1487 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1489 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1495 * e1000e_get_phy_info_m88 - Retrieve PHY information
1496 * @hw: pointer to the HW structure
1498 * Valid for only copper links. Read the PHY status register (sticky read)
1499 * to verify that link is up. Read the PHY special control register to
1500 * determine the polarity and 10base-T extended distance. Read the PHY
1501 * special status register to determine MDI/MDIx and current speed. If
1502 * speed is 1000, then determine cable length, local and remote receiver.
1504 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1506 struct e1000_phy_info *phy = &hw->phy;
1511 if (hw->phy.media_type != e1000_media_type_copper) {
1512 hw_dbg(hw, "Phy info is only valid for copper media\n");
1513 return -E1000_ERR_CONFIG;
1516 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1521 hw_dbg(hw, "Phy info is only valid if link is up\n");
1522 return -E1000_ERR_CONFIG;
1525 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1529 phy->polarity_correction = (phy_data &
1530 M88E1000_PSCR_POLARITY_REVERSAL);
1532 ret_val = e1000_check_polarity_m88(hw);
1536 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1540 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1542 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1543 ret_val = e1000_get_cable_length(hw);
1547 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1551 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1552 ? e1000_1000t_rx_status_ok
1553 : e1000_1000t_rx_status_not_ok;
1555 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1556 ? e1000_1000t_rx_status_ok
1557 : e1000_1000t_rx_status_not_ok;
1559 /* Set values to "undefined" */
1560 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1561 phy->local_rx = e1000_1000t_rx_status_undefined;
1562 phy->remote_rx = e1000_1000t_rx_status_undefined;
1569 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1570 * @hw: pointer to the HW structure
1572 * Read PHY status to determine if link is up. If link is up, then
1573 * set/determine 10base-T extended distance and polarity correction. Read
1574 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1575 * determine on the cable length, local and remote receiver.
1577 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1579 struct e1000_phy_info *phy = &hw->phy;
1584 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1589 hw_dbg(hw, "Phy info is only valid if link is up\n");
1590 return -E1000_ERR_CONFIG;
1593 phy->polarity_correction = 1;
1595 ret_val = e1000_check_polarity_igp(hw);
1599 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1603 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
1605 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1606 IGP01E1000_PSSR_SPEED_1000MBPS) {
1607 ret_val = e1000_get_cable_length(hw);
1611 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
1615 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1616 ? e1000_1000t_rx_status_ok
1617 : e1000_1000t_rx_status_not_ok;
1619 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1620 ? e1000_1000t_rx_status_ok
1621 : e1000_1000t_rx_status_not_ok;
1623 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1624 phy->local_rx = e1000_1000t_rx_status_undefined;
1625 phy->remote_rx = e1000_1000t_rx_status_undefined;
1632 * e1000e_phy_sw_reset - PHY software reset
1633 * @hw: pointer to the HW structure
1635 * Does a software reset of the PHY by reading the PHY control register and
1636 * setting/write the control register reset bit to the PHY.
1638 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
1643 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1647 phy_ctrl |= MII_CR_RESET;
1648 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1658 * e1000e_phy_hw_reset_generic - PHY hardware reset
1659 * @hw: pointer to the HW structure
1661 * Verify the reset block is not blocking us from resetting. Acquire
1662 * semaphore (if necessary) and read/set/write the device control reset
1663 * bit in the PHY. Wait the appropriate delay time for the device to
1664 * reset and release the semaphore (if necessary).
1666 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1668 struct e1000_phy_info *phy = &hw->phy;
1672 ret_val = e1000_check_reset_block(hw);
1676 ret_val = phy->ops.acquire_phy(hw);
1681 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
1684 udelay(phy->reset_delay_us);
1691 phy->ops.release_phy(hw);
1693 return e1000_get_phy_cfg_done(hw);
1697 * e1000e_get_cfg_done - Generic configuration done
1698 * @hw: pointer to the HW structure
1700 * Generic function to wait 10 milli-seconds for configuration to complete
1701 * and return success.
1703 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
1709 /* Internal function pointers */
1712 * e1000_get_phy_cfg_done - Generic PHY configuration done
1713 * @hw: pointer to the HW structure
1715 * Return success if silicon family did not implement a family specific
1716 * get_cfg_done function.
1718 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1720 if (hw->phy.ops.get_cfg_done)
1721 return hw->phy.ops.get_cfg_done(hw);
1727 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1728 * @hw: pointer to the HW structure
1730 * When the silicon family has not implemented a forced speed/duplex
1731 * function for the PHY, simply return 0.
1733 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1735 if (hw->phy.ops.force_speed_duplex)
1736 return hw->phy.ops.force_speed_duplex(hw);
1742 * e1000e_get_phy_type_from_id - Get PHY type from id
1743 * @phy_id: phy_id read from the phy
1745 * Returns the phy type from the id.
1747 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1749 enum e1000_phy_type phy_type = e1000_phy_unknown;
1752 case M88E1000_I_PHY_ID:
1753 case M88E1000_E_PHY_ID:
1754 case M88E1111_I_PHY_ID:
1755 case M88E1011_I_PHY_ID:
1756 phy_type = e1000_phy_m88;
1758 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
1759 phy_type = e1000_phy_igp_2;
1761 case GG82563_E_PHY_ID:
1762 phy_type = e1000_phy_gg82563;
1764 case IGP03E1000_E_PHY_ID:
1765 phy_type = e1000_phy_igp_3;
1768 case IFE_PLUS_E_PHY_ID:
1769 case IFE_C_E_PHY_ID:
1770 phy_type = e1000_phy_ife;
1773 phy_type = e1000_phy_unknown;
1780 * e1000e_commit_phy - Soft PHY reset
1781 * @hw: pointer to the HW structure
1783 * Performs a soft PHY reset on those that apply. This is a function pointer
1784 * entry point called by drivers.
1786 s32 e1000e_commit_phy(struct e1000_hw *hw)
1788 if (hw->phy.ops.commit_phy)
1789 return hw->phy.ops.commit_phy(hw);
1795 * e1000_set_d0_lplu_state - Sets low power link up state for D0
1796 * @hw: pointer to the HW structure
1797 * @active: boolean used to enable/disable lplu
1799 * Success returns 0, Failure returns 1
1801 * The low power link up (lplu) state is set to the power management level D0
1802 * and SmartSpeed is disabled when active is true, else clear lplu for D0
1803 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1804 * is used during Dx states where the power conservation is most important.
1805 * During driver activity, SmartSpeed should be enabled so performance is
1806 * maintained. This is a function pointer entry point called by drivers.
1808 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
1810 if (hw->phy.ops.set_d0_lplu_state)
1811 return hw->phy.ops.set_d0_lplu_state(hw, active);