1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table[] =
40 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
42 static const u16 e1000_igp_2_cable_length_table[] =
43 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
44 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
45 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
46 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
47 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
48 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
49 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
51 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
52 ARRAY_SIZE(e1000_igp_2_cable_length_table)
55 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
56 * @hw: pointer to the HW structure
58 * Read the PHY management control register and check whether a PHY reset
59 * is blocked. If a reset is not blocked return 0, otherwise
60 * return E1000_BLK_PHY_RESET (12).
62 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
68 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
69 E1000_BLK_PHY_RESET : 0;
73 * e1000e_get_phy_id - Retrieve the PHY ID and revision
74 * @hw: pointer to the HW structure
76 * Reads the PHY registers and stores the PHY ID and possibly the PHY
77 * revision in the hardware structure.
79 s32 e1000e_get_phy_id(struct e1000_hw *hw)
81 struct e1000_phy_info *phy = &hw->phy;
85 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
89 phy->id = (u32)(phy_id << 16);
91 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
95 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
96 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
102 * e1000e_phy_reset_dsp - Reset PHY DSP
103 * @hw: pointer to the HW structure
105 * Reset the digital signal processor.
107 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
111 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
115 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
119 * e1000e_read_phy_reg_mdic - Read MDI control register
120 * @hw: pointer to the HW structure
121 * @offset: register offset to be read
122 * @data: pointer to the read data
124 * Reads the MDI control register in the PHY at offset and stores the
125 * information read to data.
127 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
129 struct e1000_phy_info *phy = &hw->phy;
132 if (offset > MAX_PHY_REG_ADDRESS) {
133 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
134 return -E1000_ERR_PARAM;
138 * Set up Op-code, Phy Address, and register offset in the MDI
139 * Control register. The MAC will take care of interfacing with the
140 * PHY to retrieve the desired data.
142 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
143 (phy->addr << E1000_MDIC_PHY_SHIFT) |
144 (E1000_MDIC_OP_READ));
149 * Poll the ready bit to see if the MDI read completed
150 * Increasing the time out as testing showed failures with
153 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
156 if (mdic & E1000_MDIC_READY)
159 if (!(mdic & E1000_MDIC_READY)) {
160 hw_dbg(hw, "MDI Read did not complete\n");
161 return -E1000_ERR_PHY;
163 if (mdic & E1000_MDIC_ERROR) {
164 hw_dbg(hw, "MDI Error\n");
165 return -E1000_ERR_PHY;
173 * e1000e_write_phy_reg_mdic - Write MDI control register
174 * @hw: pointer to the HW structure
175 * @offset: register offset to write to
176 * @data: data to write to register at offset
178 * Writes data to MDI control register in the PHY at offset.
180 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
182 struct e1000_phy_info *phy = &hw->phy;
185 if (offset > MAX_PHY_REG_ADDRESS) {
186 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
187 return -E1000_ERR_PARAM;
191 * Set up Op-code, Phy Address, and register offset in the MDI
192 * Control register. The MAC will take care of interfacing with the
193 * PHY to retrieve the desired data.
195 mdic = (((u32)data) |
196 (offset << E1000_MDIC_REG_SHIFT) |
197 (phy->addr << E1000_MDIC_PHY_SHIFT) |
198 (E1000_MDIC_OP_WRITE));
203 * Poll the ready bit to see if the MDI read completed
204 * Increasing the time out as testing showed failures with
207 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
210 if (mdic & E1000_MDIC_READY)
213 if (!(mdic & E1000_MDIC_READY)) {
214 hw_dbg(hw, "MDI Write did not complete\n");
215 return -E1000_ERR_PHY;
217 if (mdic & E1000_MDIC_ERROR) {
218 hw_dbg(hw, "MDI Error\n");
219 return -E1000_ERR_PHY;
226 * e1000e_read_phy_reg_m88 - Read m88 PHY register
227 * @hw: pointer to the HW structure
228 * @offset: register offset to be read
229 * @data: pointer to the read data
231 * Acquires semaphore, if necessary, then reads the PHY register at offset
232 * and storing the retrieved information in data. Release any acquired
233 * semaphores before exiting.
235 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
239 ret_val = hw->phy.ops.acquire_phy(hw);
243 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
246 hw->phy.ops.release_phy(hw);
252 * e1000e_write_phy_reg_m88 - Write m88 PHY register
253 * @hw: pointer to the HW structure
254 * @offset: register offset to write to
255 * @data: data to write at register offset
257 * Acquires semaphore, if necessary, then writes the data to PHY register
258 * at the offset. Release any acquired semaphores before exiting.
260 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
264 ret_val = hw->phy.ops.acquire_phy(hw);
268 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
271 hw->phy.ops.release_phy(hw);
277 * e1000e_read_phy_reg_igp - Read igp PHY register
278 * @hw: pointer to the HW structure
279 * @offset: register offset to be read
280 * @data: pointer to the read data
282 * Acquires semaphore, if necessary, then reads the PHY register at offset
283 * and storing the retrieved information in data. Release any acquired
284 * semaphores before exiting.
286 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
290 ret_val = hw->phy.ops.acquire_phy(hw);
294 if (offset > MAX_PHY_MULTI_PAGE_REG) {
295 ret_val = e1000e_write_phy_reg_mdic(hw,
296 IGP01E1000_PHY_PAGE_SELECT,
299 hw->phy.ops.release_phy(hw);
304 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
307 hw->phy.ops.release_phy(hw);
313 * e1000e_write_phy_reg_igp - Write igp PHY register
314 * @hw: pointer to the HW structure
315 * @offset: register offset to write to
316 * @data: data to write at register offset
318 * Acquires semaphore, if necessary, then writes the data to PHY register
319 * at the offset. Release any acquired semaphores before exiting.
321 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
325 ret_val = hw->phy.ops.acquire_phy(hw);
329 if (offset > MAX_PHY_MULTI_PAGE_REG) {
330 ret_val = e1000e_write_phy_reg_mdic(hw,
331 IGP01E1000_PHY_PAGE_SELECT,
334 hw->phy.ops.release_phy(hw);
339 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
342 hw->phy.ops.release_phy(hw);
348 * e1000e_read_kmrn_reg - Read kumeran register
349 * @hw: pointer to the HW structure
350 * @offset: register offset to be read
351 * @data: pointer to the read data
353 * Acquires semaphore, if necessary. Then reads the PHY register at offset
354 * using the kumeran interface. The information retrieved is stored in data.
355 * Release any acquired semaphores before exiting.
357 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
362 ret_val = hw->phy.ops.acquire_phy(hw);
366 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
367 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
368 ew32(KMRNCTRLSTA, kmrnctrlsta);
372 kmrnctrlsta = er32(KMRNCTRLSTA);
373 *data = (u16)kmrnctrlsta;
375 hw->phy.ops.release_phy(hw);
381 * e1000e_write_kmrn_reg - Write kumeran register
382 * @hw: pointer to the HW structure
383 * @offset: register offset to write to
384 * @data: data to write at register offset
386 * Acquires semaphore, if necessary. Then write the data to PHY register
387 * at the offset using the kumeran interface. Release any acquired semaphores
390 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
395 ret_val = hw->phy.ops.acquire_phy(hw);
399 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
400 E1000_KMRNCTRLSTA_OFFSET) | data;
401 ew32(KMRNCTRLSTA, kmrnctrlsta);
404 hw->phy.ops.release_phy(hw);
410 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
411 * @hw: pointer to the HW structure
413 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
414 * and downshift values are set also.
416 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
418 struct e1000_phy_info *phy = &hw->phy;
422 /* Enable CRS on Tx. This must be set for half-duplex operation. */
423 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
427 /* For newer PHYs this bit is downshift enable */
428 if (phy->type == e1000_phy_m88)
429 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
433 * MDI/MDI-X = 0 (default)
434 * 0 - Auto for all speeds
437 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
439 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
443 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
446 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
449 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
453 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
459 * disable_polarity_correction = 0 (default)
460 * Automatic Correction for Reversed Cable Polarity
464 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
465 if (phy->disable_polarity_correction == 1)
466 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
468 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
472 if ((phy->type == e1000_phy_m88) && (phy->revision < 4)) {
474 * Force TX_CLK in the Extended PHY Specific Control Register
477 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
481 phy_data |= M88E1000_EPSCR_TX_CLK_25;
483 if ((phy->revision == 2) &&
484 (phy->id == M88E1111_I_PHY_ID)) {
485 /* 82573L PHY - set the downshift counter to 5x. */
486 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
487 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
489 /* Configure Master and Slave downshift values */
490 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
491 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
492 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
493 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
495 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
500 /* Commit the changes. */
501 ret_val = e1000e_commit_phy(hw);
503 hw_dbg(hw, "Error committing the PHY changes\n");
509 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
510 * @hw: pointer to the HW structure
512 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
515 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
517 struct e1000_phy_info *phy = &hw->phy;
521 ret_val = e1000_phy_hw_reset(hw);
523 hw_dbg(hw, "Error resetting the PHY.\n");
528 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
529 * timeout issues when LFS is enabled.
533 /* disable lplu d0 during driver init */
534 ret_val = e1000_set_d0_lplu_state(hw, 0);
536 hw_dbg(hw, "Error Disabling LPLU D0\n");
539 /* Configure mdi-mdix settings */
540 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
544 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
548 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
551 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
555 data |= IGP01E1000_PSCR_AUTO_MDIX;
558 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
562 /* set auto-master slave resolution settings */
563 if (hw->mac.autoneg) {
565 * when autonegotiation advertisement is only 1000Mbps then we
566 * should disable SmartSpeed and enable Auto MasterSlave
567 * resolution as hardware default.
569 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
570 /* Disable SmartSpeed */
571 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
576 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
577 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
582 /* Set auto Master/Slave resolution process */
583 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
587 data &= ~CR_1000T_MS_ENABLE;
588 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
593 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
597 /* load defaults for future use */
598 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
599 ((data & CR_1000T_MS_VALUE) ?
600 e1000_ms_force_master :
601 e1000_ms_force_slave) :
604 switch (phy->ms_type) {
605 case e1000_ms_force_master:
606 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
608 case e1000_ms_force_slave:
609 data |= CR_1000T_MS_ENABLE;
610 data &= ~(CR_1000T_MS_VALUE);
613 data &= ~CR_1000T_MS_ENABLE;
617 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
624 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
625 * @hw: pointer to the HW structure
627 * Reads the MII auto-neg advertisement register and/or the 1000T control
628 * register and if the PHY is already setup for auto-negotiation, then
629 * return successful. Otherwise, setup advertisement and flow control to
630 * the appropriate values for the wanted auto-negotiation.
632 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
634 struct e1000_phy_info *phy = &hw->phy;
636 u16 mii_autoneg_adv_reg;
637 u16 mii_1000t_ctrl_reg = 0;
639 phy->autoneg_advertised &= phy->autoneg_mask;
641 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
642 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
646 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
647 /* Read the MII 1000Base-T Control Register (Address 9). */
648 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
654 * Need to parse both autoneg_advertised and fc and set up
655 * the appropriate PHY registers. First we will parse for
656 * autoneg_advertised software override. Since we can advertise
657 * a plethora of combinations, we need to check each bit
662 * First we clear all the 10/100 mb speed bits in the Auto-Neg
663 * Advertisement Register (Address 4) and the 1000 mb speed bits in
664 * the 1000Base-T Control Register (Address 9).
666 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
667 NWAY_AR_100TX_HD_CAPS |
668 NWAY_AR_10T_FD_CAPS |
669 NWAY_AR_10T_HD_CAPS);
670 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
672 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
674 /* Do we want to advertise 10 Mb Half Duplex? */
675 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
676 hw_dbg(hw, "Advertise 10mb Half duplex\n");
677 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
680 /* Do we want to advertise 10 Mb Full Duplex? */
681 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
682 hw_dbg(hw, "Advertise 10mb Full duplex\n");
683 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
686 /* Do we want to advertise 100 Mb Half Duplex? */
687 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
688 hw_dbg(hw, "Advertise 100mb Half duplex\n");
689 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
692 /* Do we want to advertise 100 Mb Full Duplex? */
693 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
694 hw_dbg(hw, "Advertise 100mb Full duplex\n");
695 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
698 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
699 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
700 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
702 /* Do we want to advertise 1000 Mb Full Duplex? */
703 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
704 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
705 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
709 * Check for a software override of the flow control settings, and
710 * setup the PHY advertisement registers accordingly. If
711 * auto-negotiation is enabled, then software will have to set the
712 * "PAUSE" bits to the correct value in the Auto-Negotiation
713 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
716 * The possible values of the "fc" parameter are:
717 * 0: Flow control is completely disabled
718 * 1: Rx flow control is enabled (we can receive pause frames
719 * but not send pause frames).
720 * 2: Tx flow control is enabled (we can send pause frames
721 * but we do not support receiving pause frames).
722 * 3: Both Rx and Tx flow control (symmetric) are enabled.
723 * other: No software override. The flow control configuration
724 * in the EEPROM is used.
726 switch (hw->fc.type) {
729 * Flow control (Rx & Tx) is completely disabled by a
730 * software over-ride.
732 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
734 case e1000_fc_rx_pause:
736 * Rx Flow control is enabled, and Tx Flow control is
737 * disabled, by a software over-ride.
739 * Since there really isn't a way to advertise that we are
740 * capable of Rx Pause ONLY, we will advertise that we
741 * support both symmetric and asymmetric Rx PAUSE. Later
742 * (in e1000e_config_fc_after_link_up) we will disable the
743 * hw's ability to send PAUSE frames.
745 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
747 case e1000_fc_tx_pause:
749 * Tx Flow control is enabled, and Rx Flow control is
750 * disabled, by a software over-ride.
752 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
753 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
757 * Flow control (both Rx and Tx) is enabled by a software
760 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
763 hw_dbg(hw, "Flow control param set incorrectly\n");
764 ret_val = -E1000_ERR_CONFIG;
768 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
772 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
774 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
775 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
782 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
783 * @hw: pointer to the HW structure
785 * Performs initial bounds checking on autoneg advertisement parameter, then
786 * configure to advertise the full capability. Setup the PHY to autoneg
787 * and restart the negotiation process between the link partner. If
788 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
790 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
792 struct e1000_phy_info *phy = &hw->phy;
797 * Perform some bounds checking on the autoneg advertisement
800 phy->autoneg_advertised &= phy->autoneg_mask;
803 * If autoneg_advertised is zero, we assume it was not defaulted
804 * by the calling code so we set to advertise full capability.
806 if (phy->autoneg_advertised == 0)
807 phy->autoneg_advertised = phy->autoneg_mask;
809 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
810 ret_val = e1000_phy_setup_autoneg(hw);
812 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
815 hw_dbg(hw, "Restarting Auto-Neg\n");
818 * Restart auto-negotiation by setting the Auto Neg Enable bit and
819 * the Auto Neg Restart bit in the PHY control register.
821 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
825 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
826 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
831 * Does the user want to wait for Auto-Neg to complete here, or
832 * check at a later time (for example, callback routine).
834 if (phy->autoneg_wait_to_complete) {
835 ret_val = e1000_wait_autoneg(hw);
837 hw_dbg(hw, "Error while waiting for "
838 "autoneg to complete\n");
843 hw->mac.get_link_status = 1;
849 * e1000e_setup_copper_link - Configure copper link settings
850 * @hw: pointer to the HW structure
852 * Calls the appropriate function to configure the link for auto-neg or forced
853 * speed and duplex. Then we check for link, once link is established calls
854 * to configure collision distance and flow control are called. If link is
855 * not established, we return -E1000_ERR_PHY (-2).
857 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
862 if (hw->mac.autoneg) {
864 * Setup autoneg and flow control advertisement and perform
867 ret_val = e1000_copper_link_autoneg(hw);
872 * PHY will be set to 10H, 10F, 100H or 100F
873 * depending on user settings.
875 hw_dbg(hw, "Forcing Speed and Duplex\n");
876 ret_val = e1000_phy_force_speed_duplex(hw);
878 hw_dbg(hw, "Error Forcing Speed and Duplex\n");
884 * Check link status. Wait up to 100 microseconds for link to become
887 ret_val = e1000e_phy_has_link_generic(hw,
888 COPPER_LINK_UP_LIMIT,
895 hw_dbg(hw, "Valid link established!!!\n");
896 e1000e_config_collision_dist(hw);
897 ret_val = e1000e_config_fc_after_link_up(hw);
899 hw_dbg(hw, "Unable to establish link!!!\n");
906 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
907 * @hw: pointer to the HW structure
909 * Calls the PHY setup function to force speed and duplex. Clears the
910 * auto-crossover to force MDI manually. Waits for link and returns
911 * successful if link up is successful, else -E1000_ERR_PHY (-2).
913 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
915 struct e1000_phy_info *phy = &hw->phy;
920 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
924 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
926 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
931 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
932 * forced whenever speed and duplex are forced.
934 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
938 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
939 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
941 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
945 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
949 if (phy->autoneg_wait_to_complete) {
950 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
952 ret_val = e1000e_phy_has_link_generic(hw,
960 hw_dbg(hw, "Link taking longer than expected.\n");
963 ret_val = e1000e_phy_has_link_generic(hw,
975 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
976 * @hw: pointer to the HW structure
978 * Calls the PHY setup function to force speed and duplex. Clears the
979 * auto-crossover to force MDI manually. Resets the PHY to commit the
980 * changes. If time expires while waiting for link up, we reset the DSP.
981 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
982 * successful completion, else return corresponding error code.
984 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
986 struct e1000_phy_info *phy = &hw->phy;
992 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
993 * forced whenever speed and duplex are forced.
995 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
999 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1000 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1004 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
1006 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1010 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1012 /* Reset the phy to commit changes. */
1013 phy_data |= MII_CR_RESET;
1015 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1021 if (phy->autoneg_wait_to_complete) {
1022 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
1024 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1031 * We didn't get link.
1032 * Reset the DSP and cross our fingers.
1034 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1038 ret_val = e1000e_phy_reset_dsp(hw);
1044 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1050 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1055 * Resetting the phy means we need to re-force TX_CLK in the
1056 * Extended PHY Specific Control Register to 25MHz clock from
1057 * the reset value of 2.5MHz.
1059 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1060 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1065 * In addition, we must re-enable CRS on Tx for both half and full
1068 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1072 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1073 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1079 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1080 * @hw: pointer to the HW structure
1081 * @phy_ctrl: pointer to current value of PHY_CONTROL
1083 * Forces speed and duplex on the PHY by doing the following: disable flow
1084 * control, force speed/duplex on the MAC, disable auto speed detection,
1085 * disable auto-negotiation, configure duplex, configure speed, configure
1086 * the collision distance, write configuration to CTRL register. The
1087 * caller must write to the PHY_CONTROL register for these settings to
1090 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1092 struct e1000_mac_info *mac = &hw->mac;
1095 /* Turn off flow control when forcing speed/duplex */
1096 hw->fc.type = e1000_fc_none;
1098 /* Force speed/duplex on the mac */
1100 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1101 ctrl &= ~E1000_CTRL_SPD_SEL;
1103 /* Disable Auto Speed Detection */
1104 ctrl &= ~E1000_CTRL_ASDE;
1106 /* Disable autoneg on the phy */
1107 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1109 /* Forcing Full or Half Duplex? */
1110 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1111 ctrl &= ~E1000_CTRL_FD;
1112 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1113 hw_dbg(hw, "Half Duplex\n");
1115 ctrl |= E1000_CTRL_FD;
1116 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1117 hw_dbg(hw, "Full Duplex\n");
1120 /* Forcing 10mb or 100mb? */
1121 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1122 ctrl |= E1000_CTRL_SPD_100;
1123 *phy_ctrl |= MII_CR_SPEED_100;
1124 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1125 hw_dbg(hw, "Forcing 100mb\n");
1127 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1128 *phy_ctrl |= MII_CR_SPEED_10;
1129 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1130 hw_dbg(hw, "Forcing 10mb\n");
1133 e1000e_config_collision_dist(hw);
1139 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1140 * @hw: pointer to the HW structure
1141 * @active: boolean used to enable/disable lplu
1143 * Success returns 0, Failure returns 1
1145 * The low power link up (lplu) state is set to the power management level D3
1146 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1147 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1148 * is used during Dx states where the power conservation is most important.
1149 * During driver activity, SmartSpeed should be enabled so performance is
1152 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1154 struct e1000_phy_info *phy = &hw->phy;
1158 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1163 data &= ~IGP02E1000_PM_D3_LPLU;
1164 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1168 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1169 * during Dx states where the power conservation is most
1170 * important. During driver activity we should enable
1171 * SmartSpeed, so performance is maintained.
1173 if (phy->smart_speed == e1000_smart_speed_on) {
1174 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1179 data |= IGP01E1000_PSCFR_SMART_SPEED;
1180 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1184 } else if (phy->smart_speed == e1000_smart_speed_off) {
1185 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1190 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1191 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1196 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1197 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1198 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1199 data |= IGP02E1000_PM_D3_LPLU;
1200 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1204 /* When LPLU is enabled, we should disable SmartSpeed */
1205 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1209 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1210 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1217 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1218 * @hw: pointer to the HW structure
1220 * Success returns 0, Failure returns 1
1222 * A downshift is detected by querying the PHY link health.
1224 s32 e1000e_check_downshift(struct e1000_hw *hw)
1226 struct e1000_phy_info *phy = &hw->phy;
1228 u16 phy_data, offset, mask;
1230 switch (phy->type) {
1232 case e1000_phy_gg82563:
1233 offset = M88E1000_PHY_SPEC_STATUS;
1234 mask = M88E1000_PSSR_DOWNSHIFT;
1236 case e1000_phy_igp_2:
1237 case e1000_phy_igp_3:
1238 offset = IGP01E1000_PHY_LINK_HEALTH;
1239 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1242 /* speed downshift not supported */
1243 phy->speed_downgraded = 0;
1247 ret_val = e1e_rphy(hw, offset, &phy_data);
1250 phy->speed_downgraded = (phy_data & mask);
1256 * e1000_check_polarity_m88 - Checks the polarity.
1257 * @hw: pointer to the HW structure
1259 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1261 * Polarity is determined based on the PHY specific status register.
1263 static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1265 struct e1000_phy_info *phy = &hw->phy;
1269 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1272 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1273 ? e1000_rev_polarity_reversed
1274 : e1000_rev_polarity_normal;
1280 * e1000_check_polarity_igp - Checks the polarity.
1281 * @hw: pointer to the HW structure
1283 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1285 * Polarity is determined based on the PHY port status register, and the
1286 * current speed (since there is no polarity at 100Mbps).
1288 static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1290 struct e1000_phy_info *phy = &hw->phy;
1292 u16 data, offset, mask;
1295 * Polarity is determined based on the speed of
1298 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1302 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1303 IGP01E1000_PSSR_SPEED_1000MBPS) {
1304 offset = IGP01E1000_PHY_PCS_INIT_REG;
1305 mask = IGP01E1000_PHY_POLARITY_MASK;
1308 * This really only applies to 10Mbps since
1309 * there is no polarity for 100Mbps (always 0).
1311 offset = IGP01E1000_PHY_PORT_STATUS;
1312 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1315 ret_val = e1e_rphy(hw, offset, &data);
1318 phy->cable_polarity = (data & mask)
1319 ? e1000_rev_polarity_reversed
1320 : e1000_rev_polarity_normal;
1326 * e1000_wait_autoneg - Wait for auto-neg completion
1327 * @hw: pointer to the HW structure
1329 * Waits for auto-negotiation to complete or for the auto-negotiation time
1330 * limit to expire, which ever happens first.
1332 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1337 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1338 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1339 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1342 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1345 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1351 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1358 * e1000e_phy_has_link_generic - Polls PHY for link
1359 * @hw: pointer to the HW structure
1360 * @iterations: number of times to poll for link
1361 * @usec_interval: delay between polling attempts
1362 * @success: pointer to whether polling was successful or not
1364 * Polls the PHY status register for link, 'iterations' number of times.
1366 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1367 u32 usec_interval, bool *success)
1372 for (i = 0; i < iterations; i++) {
1374 * Some PHYs require the PHY_STATUS register to be read
1375 * twice due to the link bit being sticky. No harm doing
1376 * it across the board.
1378 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1381 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1384 if (phy_status & MII_SR_LINK_STATUS)
1386 if (usec_interval >= 1000)
1387 mdelay(usec_interval/1000);
1389 udelay(usec_interval);
1392 *success = (i < iterations);
1398 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1399 * @hw: pointer to the HW structure
1401 * Reads the PHY specific status register to retrieve the cable length
1402 * information. The cable length is determined by averaging the minimum and
1403 * maximum values to get the "average" cable length. The m88 PHY has four
1404 * possible cable length values, which are:
1405 * Register Value Cable Length
1409 * 3 110 - 140 meters
1412 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1414 struct e1000_phy_info *phy = &hw->phy;
1416 u16 phy_data, index;
1418 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1422 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1423 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1424 phy->min_cable_length = e1000_m88_cable_length_table[index];
1425 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1427 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1433 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1434 * @hw: pointer to the HW structure
1436 * The automatic gain control (agc) normalizes the amplitude of the
1437 * received signal, adjusting for the attenuation produced by the
1438 * cable. By reading the AGC registers, which represent the
1439 * combination of course and fine gain value, the value can be put
1440 * into a lookup table to obtain the approximate cable length
1443 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1445 struct e1000_phy_info *phy = &hw->phy;
1447 u16 phy_data, i, agc_value = 0;
1448 u16 cur_agc_index, max_agc_index = 0;
1449 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1450 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1451 {IGP02E1000_PHY_AGC_A,
1452 IGP02E1000_PHY_AGC_B,
1453 IGP02E1000_PHY_AGC_C,
1454 IGP02E1000_PHY_AGC_D};
1456 /* Read the AGC registers for all channels */
1457 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1458 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1463 * Getting bits 15:9, which represent the combination of
1464 * course and fine gain values. The result is a number
1465 * that can be put into the lookup table to obtain the
1466 * approximate cable length.
1468 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1469 IGP02E1000_AGC_LENGTH_MASK;
1471 /* Array index bound check. */
1472 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1473 (cur_agc_index == 0))
1474 return -E1000_ERR_PHY;
1476 /* Remove min & max AGC values from calculation. */
1477 if (e1000_igp_2_cable_length_table[min_agc_index] >
1478 e1000_igp_2_cable_length_table[cur_agc_index])
1479 min_agc_index = cur_agc_index;
1480 if (e1000_igp_2_cable_length_table[max_agc_index] <
1481 e1000_igp_2_cable_length_table[cur_agc_index])
1482 max_agc_index = cur_agc_index;
1484 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1487 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1488 e1000_igp_2_cable_length_table[max_agc_index]);
1489 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1491 /* Calculate cable length with the error range of +/- 10 meters. */
1492 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1493 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1494 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1496 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1502 * e1000e_get_phy_info_m88 - Retrieve PHY information
1503 * @hw: pointer to the HW structure
1505 * Valid for only copper links. Read the PHY status register (sticky read)
1506 * to verify that link is up. Read the PHY special control register to
1507 * determine the polarity and 10base-T extended distance. Read the PHY
1508 * special status register to determine MDI/MDIx and current speed. If
1509 * speed is 1000, then determine cable length, local and remote receiver.
1511 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1513 struct e1000_phy_info *phy = &hw->phy;
1518 if (hw->phy.media_type != e1000_media_type_copper) {
1519 hw_dbg(hw, "Phy info is only valid for copper media\n");
1520 return -E1000_ERR_CONFIG;
1523 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1528 hw_dbg(hw, "Phy info is only valid if link is up\n");
1529 return -E1000_ERR_CONFIG;
1532 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1536 phy->polarity_correction = (phy_data &
1537 M88E1000_PSCR_POLARITY_REVERSAL);
1539 ret_val = e1000_check_polarity_m88(hw);
1543 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1547 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1549 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1550 ret_val = e1000_get_cable_length(hw);
1554 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1558 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1559 ? e1000_1000t_rx_status_ok
1560 : e1000_1000t_rx_status_not_ok;
1562 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1563 ? e1000_1000t_rx_status_ok
1564 : e1000_1000t_rx_status_not_ok;
1566 /* Set values to "undefined" */
1567 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1568 phy->local_rx = e1000_1000t_rx_status_undefined;
1569 phy->remote_rx = e1000_1000t_rx_status_undefined;
1576 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1577 * @hw: pointer to the HW structure
1579 * Read PHY status to determine if link is up. If link is up, then
1580 * set/determine 10base-T extended distance and polarity correction. Read
1581 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1582 * determine on the cable length, local and remote receiver.
1584 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1586 struct e1000_phy_info *phy = &hw->phy;
1591 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1596 hw_dbg(hw, "Phy info is only valid if link is up\n");
1597 return -E1000_ERR_CONFIG;
1600 phy->polarity_correction = 1;
1602 ret_val = e1000_check_polarity_igp(hw);
1606 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1610 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
1612 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1613 IGP01E1000_PSSR_SPEED_1000MBPS) {
1614 ret_val = e1000_get_cable_length(hw);
1618 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
1622 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1623 ? e1000_1000t_rx_status_ok
1624 : e1000_1000t_rx_status_not_ok;
1626 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1627 ? e1000_1000t_rx_status_ok
1628 : e1000_1000t_rx_status_not_ok;
1630 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1631 phy->local_rx = e1000_1000t_rx_status_undefined;
1632 phy->remote_rx = e1000_1000t_rx_status_undefined;
1639 * e1000e_phy_sw_reset - PHY software reset
1640 * @hw: pointer to the HW structure
1642 * Does a software reset of the PHY by reading the PHY control register and
1643 * setting/write the control register reset bit to the PHY.
1645 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
1650 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1654 phy_ctrl |= MII_CR_RESET;
1655 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1665 * e1000e_phy_hw_reset_generic - PHY hardware reset
1666 * @hw: pointer to the HW structure
1668 * Verify the reset block is not blocking us from resetting. Acquire
1669 * semaphore (if necessary) and read/set/write the device control reset
1670 * bit in the PHY. Wait the appropriate delay time for the device to
1671 * reset and release the semaphore (if necessary).
1673 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1675 struct e1000_phy_info *phy = &hw->phy;
1679 ret_val = e1000_check_reset_block(hw);
1683 ret_val = phy->ops.acquire_phy(hw);
1688 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
1691 udelay(phy->reset_delay_us);
1698 phy->ops.release_phy(hw);
1700 return e1000_get_phy_cfg_done(hw);
1704 * e1000e_get_cfg_done - Generic configuration done
1705 * @hw: pointer to the HW structure
1707 * Generic function to wait 10 milli-seconds for configuration to complete
1708 * and return success.
1710 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
1716 /* Internal function pointers */
1719 * e1000_get_phy_cfg_done - Generic PHY configuration done
1720 * @hw: pointer to the HW structure
1722 * Return success if silicon family did not implement a family specific
1723 * get_cfg_done function.
1725 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1727 if (hw->phy.ops.get_cfg_done)
1728 return hw->phy.ops.get_cfg_done(hw);
1734 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1735 * @hw: pointer to the HW structure
1737 * When the silicon family has not implemented a forced speed/duplex
1738 * function for the PHY, simply return 0.
1740 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1742 if (hw->phy.ops.force_speed_duplex)
1743 return hw->phy.ops.force_speed_duplex(hw);
1749 * e1000e_get_phy_type_from_id - Get PHY type from id
1750 * @phy_id: phy_id read from the phy
1752 * Returns the phy type from the id.
1754 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1756 enum e1000_phy_type phy_type = e1000_phy_unknown;
1759 case M88E1000_I_PHY_ID:
1760 case M88E1000_E_PHY_ID:
1761 case M88E1111_I_PHY_ID:
1762 case M88E1011_I_PHY_ID:
1763 phy_type = e1000_phy_m88;
1765 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
1766 phy_type = e1000_phy_igp_2;
1768 case GG82563_E_PHY_ID:
1769 phy_type = e1000_phy_gg82563;
1771 case IGP03E1000_E_PHY_ID:
1772 phy_type = e1000_phy_igp_3;
1775 case IFE_PLUS_E_PHY_ID:
1776 case IFE_C_E_PHY_ID:
1777 phy_type = e1000_phy_ife;
1780 phy_type = e1000_phy_unknown;
1787 * e1000e_commit_phy - Soft PHY reset
1788 * @hw: pointer to the HW structure
1790 * Performs a soft PHY reset on those that apply. This is a function pointer
1791 * entry point called by drivers.
1793 s32 e1000e_commit_phy(struct e1000_hw *hw)
1795 if (hw->phy.ops.commit_phy)
1796 return hw->phy.ops.commit_phy(hw);
1802 * e1000_set_d0_lplu_state - Sets low power link up state for D0
1803 * @hw: pointer to the HW structure
1804 * @active: boolean used to enable/disable lplu
1806 * Success returns 0, Failure returns 1
1808 * The low power link up (lplu) state is set to the power management level D0
1809 * and SmartSpeed is disabled when active is true, else clear lplu for D0
1810 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1811 * is used during Dx states where the power conservation is most important.
1812 * During driver activity, SmartSpeed should be enabled so performance is
1813 * maintained. This is a function pointer entry point called by drivers.
1815 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
1817 if (hw->phy.ops.set_d0_lplu_state)
1818 return hw->phy.ops.set_d0_lplu_state(hw, active);