2 * Driver for high-speed SCC boards (those with DMA support)
3 * Copyright (C) 1997-2000 Klaus Kudielka
5 * S5SCC/DMA support by Janko Koleznik S52HI
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <linux/if_arp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/kernel.h>
33 #include <linux/netdevice.h>
34 #include <linux/rtnetlink.h>
35 #include <linux/sockios.h>
36 #include <linux/workqueue.h>
37 #include <asm/atomic.h>
38 #include <asm/bitops.h>
42 #include <asm/uaccess.h>
47 /* Number of buffers per channel */
49 #define NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (min. 2 recommended) */
50 #define NUM_RX_BUF 6 /* NUM_RX_BUF >= 1 (min. 2 recommended) */
51 #define BUF_SIZE 1576 /* BUF_SIZE >= mtu + hard_header_len */
56 #define HW_PI { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
57 0, 8, 1843200, 3686400 }
58 #define HW_PI2 { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
59 0, 8, 3686400, 7372800 }
60 #define HW_TWIN { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
61 0, 4, 6144000, 6144000 }
62 #define HW_S5 { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \
63 0, 8, 4915200, 9830400 }
65 #define HARDWARE { HW_PI, HW_PI2, HW_TWIN, HW_S5 }
67 #define TMR_0_HZ 25600 /* Frequency of timer 0 */
75 #define MAX_NUM_DEVS 32
78 /* SCC chips supported */
84 #define CHIPNAMES { "Z8530", "Z85C30", "Z85230" }
89 /* 8530 registers relative to card base */
91 #define SCCB_DATA 0x01
93 #define SCCA_DATA 0x03
95 /* 8253/8254 registers relative to card base */
101 /* Additional PI/PI2 registers relative to card base */
102 #define PI_DREQ_MASK 0x04
104 /* Additional PackeTwin registers relative to card base */
105 #define TWIN_INT_REG 0x08
106 #define TWIN_CLR_TMR1 0x09
107 #define TWIN_CLR_TMR2 0x0a
108 #define TWIN_SPARE_1 0x0b
109 #define TWIN_DMA_CFG 0x08
110 #define TWIN_SERIAL_CFG 0x09
111 #define TWIN_DMA_CLR_FF 0x0a
112 #define TWIN_SPARE_2 0x0b
115 /* PackeTwin I/O register values */
118 #define TWIN_SCC_MSK 0x01
119 #define TWIN_TMR1_MSK 0x02
120 #define TWIN_TMR2_MSK 0x04
121 #define TWIN_INT_MSK 0x07
124 #define TWIN_DTRA_ON 0x01
125 #define TWIN_DTRB_ON 0x02
126 #define TWIN_EXTCLKA 0x04
127 #define TWIN_EXTCLKB 0x08
128 #define TWIN_LOOPA_ON 0x10
129 #define TWIN_LOOPB_ON 0x20
133 #define TWIN_DMA_HDX_T1 0x08
134 #define TWIN_DMA_HDX_R1 0x0a
135 #define TWIN_DMA_HDX_T3 0x14
136 #define TWIN_DMA_HDX_R3 0x16
137 #define TWIN_DMA_FDX_T3R1 0x1b
138 #define TWIN_DMA_FDX_T1R3 0x1d
157 #define SIOCGSCCPARAM SIOCDEVPRIVATE
158 #define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)
164 int pclk_hz; /* frequency of BRG input (don't change) */
165 int brg_tc; /* BRG terminal count; BRG disabled if < 0 */
166 int nrzi; /* 0 (nrz), 1 (nrzi) */
167 int clocks; /* see dmascc_cfg documentation */
168 int txdelay; /* [1/TMR_0_HZ] */
169 int txtimeout; /* [1/HZ] */
170 int txtail; /* [1/TMR_0_HZ] */
171 int waittime; /* [1/TMR_0_HZ] */
172 int slottime; /* [1/TMR_0_HZ] */
173 int persist; /* 1 ... 256 */
174 int dma; /* -1 (disable), 0, 1, 3 */
175 int txpause; /* [1/TMR_0_HZ] */
176 int rtsoff; /* [1/TMR_0_HZ] */
177 int dcdon; /* [1/TMR_0_HZ] */
178 int dcdoff; /* [1/TMR_0_HZ] */
181 struct scc_hardware {
196 struct net_device *dev;
197 struct scc_info *info;
198 struct net_device_stats stats;
200 int card_base, scc_cmd, scc_data;
201 int tmr_cnt, tmr_ctrl, tmr_mode;
202 struct scc_param param;
203 char rx_buf[NUM_RX_BUF][BUF_SIZE];
204 int rx_len[NUM_RX_BUF];
206 struct work_struct rx_work;
207 int rx_head, rx_tail, rx_count;
209 char tx_buf[NUM_TX_BUF][BUF_SIZE];
210 int tx_len[NUM_TX_BUF];
212 int tx_head, tx_tail, tx_count;
214 unsigned long tx_start;
216 spinlock_t *register_lock; /* Per scc_info */
217 spinlock_t ring_lock;
223 struct net_device *dev[2];
224 struct scc_priv priv[2];
225 struct scc_info *next;
226 spinlock_t register_lock; /* Per device register lock */
230 /* Function declarations */
231 static int setup_adapter(int card_base, int type, int n) __init;
233 static void write_scc(struct scc_priv *priv, int reg, int val);
234 static void write_scc_data(struct scc_priv *priv, int val, int fast);
235 static int read_scc(struct scc_priv *priv, int reg);
236 static int read_scc_data(struct scc_priv *priv);
238 static int scc_open(struct net_device *dev);
239 static int scc_close(struct net_device *dev);
240 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
241 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
242 static struct net_device_stats *scc_get_stats(struct net_device *dev);
243 static int scc_set_mac_address(struct net_device *dev, void *sa);
245 static inline void tx_on(struct scc_priv *priv);
246 static inline void rx_on(struct scc_priv *priv);
247 static inline void rx_off(struct scc_priv *priv);
248 static void start_timer(struct scc_priv *priv, int t, int r15);
249 static inline unsigned char random(void);
251 static inline void z8530_isr(struct scc_info *info);
252 static irqreturn_t scc_isr(int irq, void *dev_id);
253 static void rx_isr(struct scc_priv *priv);
254 static void special_condition(struct scc_priv *priv, int rc);
255 static void rx_bh(struct work_struct *);
256 static void tx_isr(struct scc_priv *priv);
257 static void es_isr(struct scc_priv *priv);
258 static void tm_isr(struct scc_priv *priv);
261 /* Initialization variables */
263 static int io[MAX_NUM_DEVS] __initdata = { 0, };
265 /* Beware! hw[] is also used in cleanup_module(). */
266 static struct scc_hardware hw[NUM_TYPES] __initdata_or_module = HARDWARE;
269 /* Global variables */
271 static struct scc_info *first;
272 static unsigned long rand;
275 MODULE_AUTHOR("Klaus Kudielka");
276 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
277 module_param_array(io, int, NULL, 0);
278 MODULE_LICENSE("GPL");
280 static void __exit dmascc_exit(void)
283 struct scc_info *info;
288 /* Unregister devices */
289 for (i = 0; i < 2; i++)
290 unregister_netdev(info->dev[i]);
293 if (info->priv[0].type == TYPE_TWIN)
294 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
295 write_scc(&info->priv[0], R9, FHWRES);
296 release_region(info->dev[0]->base_addr,
297 hw[info->priv[0].type].io_size);
299 for (i = 0; i < 2; i++)
300 free_netdev(info->dev[i]);
308 static int __init dmascc_init(void)
311 int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
314 unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
315 counting[MAX_NUM_DEVS];
317 /* Initialize random number generator */
319 /* Cards found = 0 */
321 /* Warning message */
323 printk(KERN_INFO "dmascc: autoprobing (dangerous)\n");
325 /* Run autodetection for each card type */
326 for (h = 0; h < NUM_TYPES; h++) {
329 /* User-specified I/O address regions */
330 for (i = 0; i < hw[h].num_devs; i++)
332 for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
334 hw[h].io_region) / hw[h].io_delta;
335 if (j >= 0 && j < hw[h].num_devs
337 j * hw[h].io_delta == io[i]) {
342 /* Default I/O address regions */
343 for (i = 0; i < hw[h].num_devs; i++) {
345 hw[h].io_region + i * hw[h].io_delta;
349 /* Check valid I/O address regions */
350 for (i = 0; i < hw[h].num_devs; i++)
353 (base[i], hw[h].io_size, "dmascc"))
357 base[i] + hw[h].tmr_offset +
360 base[i] + hw[h].tmr_offset +
363 base[i] + hw[h].tmr_offset +
369 for (i = 0; i < hw[h].num_devs; i++)
371 /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
373 outb((hw[h].tmr_hz / TMR_0_HZ) & 0xFF,
375 outb((hw[h].tmr_hz / TMR_0_HZ) >> 8,
377 /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
379 outb((TMR_0_HZ / HZ * 10) & 0xFF, t1[i]);
380 outb((TMR_0_HZ / HZ * 10) >> 8, t1[i]);
384 /* Timer 2: LSB+MSB, Mode 0 */
388 /* Wait until counter registers are loaded */
389 udelay(2000000 / TMR_0_HZ);
392 while (jiffies - time < 13) {
393 for (i = 0; i < hw[h].num_devs; i++)
394 if (base[i] && counting[i]) {
395 /* Read back Timer 1: latch; read LSB; read MSB */
398 inb(t1[i]) + (inb(t1[i]) << 8);
399 /* Also check whether counter did wrap */
401 || t_val > TMR_0_HZ / HZ * 10)
403 delay[i] = jiffies - start[i];
407 /* Evaluate measurements */
408 for (i = 0; i < hw[h].num_devs; i++)
410 if ((delay[i] >= 9 && delay[i] <= 11) &&
411 /* Ok, we have found an adapter */
412 (setup_adapter(base[i], h, n) == 0))
415 release_region(base[i],
421 /* If any adapter was successfully initialized, return ok */
425 /* If no adapter found, return error */
426 printk(KERN_INFO "dmascc: no adapters found\n");
430 module_init(dmascc_init);
431 module_exit(dmascc_exit);
433 static void __init dev_setup(struct net_device *dev)
435 dev->type = ARPHRD_AX25;
436 dev->hard_header_len = AX25_MAX_HEADER_LEN;
438 dev->addr_len = AX25_ADDR_LEN;
439 dev->tx_queue_len = 64;
440 memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
441 memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
444 static int __init setup_adapter(int card_base, int type, int n)
447 struct scc_info *info;
448 struct net_device *dev;
449 struct scc_priv *priv;
452 int tmr_base = card_base + hw[type].tmr_offset;
453 int scc_base = card_base + hw[type].scc_offset;
454 char *chipnames[] = CHIPNAMES;
456 /* Initialize what is necessary for write_scc and write_scc_data */
457 info = kzalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
459 printk(KERN_ERR "dmascc: "
460 "could not allocate memory for %s at %#3x\n",
461 hw[type].name, card_base);
466 info->dev[0] = alloc_netdev(0, "", dev_setup);
468 printk(KERN_ERR "dmascc: "
469 "could not allocate memory for %s at %#3x\n",
470 hw[type].name, card_base);
474 info->dev[1] = alloc_netdev(0, "", dev_setup);
476 printk(KERN_ERR "dmascc: "
477 "could not allocate memory for %s at %#3x\n",
478 hw[type].name, card_base);
481 spin_lock_init(&info->register_lock);
483 priv = &info->priv[0];
485 priv->card_base = card_base;
486 priv->scc_cmd = scc_base + SCCA_CMD;
487 priv->scc_data = scc_base + SCCA_DATA;
488 priv->register_lock = &info->register_lock;
491 write_scc(priv, R9, FHWRES | MIE | NV);
493 /* Determine type of chip by enabling SDLC/HDLC enhancements */
494 write_scc(priv, R15, SHDLCE);
495 if (!read_scc(priv, R15)) {
496 /* WR7' not present. This is an ordinary Z8530 SCC. */
499 /* Put one character in TX FIFO */
500 write_scc_data(priv, 0, 0);
501 if (read_scc(priv, R0) & Tx_BUF_EMP) {
502 /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
505 /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
509 write_scc(priv, R15, 0);
511 /* Start IRQ auto-detection */
512 irqs = probe_irq_on();
514 /* Enable interrupts */
515 if (type == TYPE_TWIN) {
516 outb(0, card_base + TWIN_DMA_CFG);
517 inb(card_base + TWIN_CLR_TMR1);
518 inb(card_base + TWIN_CLR_TMR2);
519 info->twin_serial_cfg = TWIN_EI;
520 outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
522 write_scc(priv, R15, CTSIE);
523 write_scc(priv, R0, RES_EXT_INT);
524 write_scc(priv, R1, EXT_INT_ENAB);
528 outb(1, tmr_base + TMR_CNT1);
529 outb(0, tmr_base + TMR_CNT1);
531 /* Wait and detect IRQ */
533 while (jiffies - time < 2 + HZ / TMR_0_HZ);
534 irq = probe_irq_off(irqs);
536 /* Clear pending interrupt, disable interrupts */
537 if (type == TYPE_TWIN) {
538 inb(card_base + TWIN_CLR_TMR1);
540 write_scc(priv, R1, 0);
541 write_scc(priv, R15, 0);
542 write_scc(priv, R0, RES_EXT_INT);
547 "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
548 hw[type].name, card_base, irq);
552 /* Set up data structures */
553 for (i = 0; i < 2; i++) {
555 priv = &info->priv[i];
561 spin_lock_init(&priv->ring_lock);
562 priv->register_lock = &info->register_lock;
563 priv->card_base = card_base;
564 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
565 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
566 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
567 priv->tmr_ctrl = tmr_base + TMR_CTRL;
568 priv->tmr_mode = i ? 0xb0 : 0x70;
569 priv->param.pclk_hz = hw[type].pclk_hz;
570 priv->param.brg_tc = -1;
571 priv->param.clocks = TCTRxCP | RCRTxCP;
572 priv->param.persist = 256;
573 priv->param.dma = -1;
574 INIT_WORK(&priv->rx_work, rx_bh);
576 sprintf(dev->name, "dmascc%i", 2 * n + i);
577 dev->base_addr = card_base;
579 dev->open = scc_open;
580 dev->stop = scc_close;
581 dev->do_ioctl = scc_ioctl;
582 dev->hard_start_xmit = scc_send_packet;
583 dev->get_stats = scc_get_stats;
584 dev->hard_header = ax25_hard_header;
585 dev->rebuild_header = ax25_rebuild_header;
586 dev->set_mac_address = scc_set_mac_address;
588 if (register_netdev(info->dev[0])) {
589 printk(KERN_ERR "dmascc: could not register %s\n",
593 if (register_netdev(info->dev[1])) {
594 printk(KERN_ERR "dmascc: could not register %s\n",
602 printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n",
603 hw[type].name, chipnames[chip], card_base, irq);
607 unregister_netdev(info->dev[0]);
609 if (info->priv[0].type == TYPE_TWIN)
610 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
611 write_scc(&info->priv[0], R9, FHWRES);
612 free_netdev(info->dev[1]);
614 free_netdev(info->dev[0]);
622 /* Driver functions */
624 static void write_scc(struct scc_priv *priv, int reg, int val)
627 switch (priv->type) {
630 outb(reg, priv->scc_cmd);
631 outb(val, priv->scc_cmd);
635 outb_p(reg, priv->scc_cmd);
636 outb_p(val, priv->scc_cmd);
639 spin_lock_irqsave(priv->register_lock, flags);
640 outb_p(0, priv->card_base + PI_DREQ_MASK);
642 outb_p(reg, priv->scc_cmd);
643 outb_p(val, priv->scc_cmd);
644 outb(1, priv->card_base + PI_DREQ_MASK);
645 spin_unlock_irqrestore(priv->register_lock, flags);
651 static void write_scc_data(struct scc_priv *priv, int val, int fast)
654 switch (priv->type) {
656 outb(val, priv->scc_data);
659 outb_p(val, priv->scc_data);
663 outb_p(val, priv->scc_data);
665 spin_lock_irqsave(priv->register_lock, flags);
666 outb_p(0, priv->card_base + PI_DREQ_MASK);
667 outb_p(val, priv->scc_data);
668 outb(1, priv->card_base + PI_DREQ_MASK);
669 spin_unlock_irqrestore(priv->register_lock, flags);
676 static int read_scc(struct scc_priv *priv, int reg)
680 switch (priv->type) {
683 outb(reg, priv->scc_cmd);
684 return inb(priv->scc_cmd);
687 outb_p(reg, priv->scc_cmd);
688 return inb_p(priv->scc_cmd);
690 spin_lock_irqsave(priv->register_lock, flags);
691 outb_p(0, priv->card_base + PI_DREQ_MASK);
693 outb_p(reg, priv->scc_cmd);
694 rc = inb_p(priv->scc_cmd);
695 outb(1, priv->card_base + PI_DREQ_MASK);
696 spin_unlock_irqrestore(priv->register_lock, flags);
702 static int read_scc_data(struct scc_priv *priv)
706 switch (priv->type) {
708 return inb(priv->scc_data);
710 return inb_p(priv->scc_data);
712 spin_lock_irqsave(priv->register_lock, flags);
713 outb_p(0, priv->card_base + PI_DREQ_MASK);
714 rc = inb_p(priv->scc_data);
715 outb(1, priv->card_base + PI_DREQ_MASK);
716 spin_unlock_irqrestore(priv->register_lock, flags);
722 static int scc_open(struct net_device *dev)
724 struct scc_priv *priv = dev->priv;
725 struct scc_info *info = priv->info;
726 int card_base = priv->card_base;
728 /* Request IRQ if not already used by other channel */
729 if (!info->irq_used) {
730 if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
736 /* Request DMA if required */
737 if (priv->param.dma >= 0) {
738 if (request_dma(priv->param.dma, "dmascc")) {
739 if (--info->irq_used == 0)
740 free_irq(dev->irq, info);
743 unsigned long flags = claim_dma_lock();
744 clear_dma_ff(priv->param.dma);
745 release_dma_lock(flags);
749 /* Initialize local variables */
752 priv->rx_head = priv->rx_tail = priv->rx_count = 0;
754 priv->tx_head = priv->tx_tail = priv->tx_count = 0;
758 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
759 /* X1 clock, SDLC mode */
760 write_scc(priv, R4, SDLC | X1CLK);
762 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
763 /* 8 bit RX char, RX disable */
764 write_scc(priv, R3, Rx8);
765 /* 8 bit TX char, TX disable */
766 write_scc(priv, R5, Tx8);
767 /* SDLC address field */
768 write_scc(priv, R6, 0);
770 write_scc(priv, R7, FLAG);
771 switch (priv->chip) {
774 write_scc(priv, R15, SHDLCE);
776 write_scc(priv, R7, AUTOEOM);
777 write_scc(priv, R15, 0);
781 write_scc(priv, R15, SHDLCE);
782 /* The following bits are set (see 2.5.2.1):
783 - Automatic EOM reset
784 - Interrupt request if RX FIFO is half full
785 This bit should be ignored in DMA mode (according to the
786 documentation), but actually isn't. The receiver doesn't work if
787 it is set. Thus, we have to clear it in DMA mode.
788 - Interrupt/DMA request if TX FIFO is completely empty
789 a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
791 b) If cleared, DMA requests may follow each other very quickly,
792 filling up the TX FIFO.
793 Advantage: TX works even in case of high bus latency.
794 Disadvantage: Edge-triggered DMA request circuitry may miss
795 a request. No more data is delivered, resulting
796 in a TX FIFO underrun.
797 Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
798 The PackeTwin doesn't. I don't know about the PI, but let's
799 assume it behaves like the PI2.
801 if (priv->param.dma >= 0) {
802 if (priv->type == TYPE_TWIN)
803 write_scc(priv, R7, AUTOEOM | TXFIFOE);
805 write_scc(priv, R7, AUTOEOM);
807 write_scc(priv, R7, AUTOEOM | RXFIFOH);
809 write_scc(priv, R15, 0);
812 /* Preset CRC, NRZ(I) encoding */
813 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
815 /* Configure baud rate generator */
816 if (priv->param.brg_tc >= 0) {
817 /* Program BR generator */
818 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
819 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);
820 /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
821 PackeTwin, not connected on the PI2); set DPLL source to BRG */
822 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
824 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
826 /* Disable BR generator */
827 write_scc(priv, R14, DTRREQ | BRSRC);
830 /* Configure clocks */
831 if (priv->type == TYPE_TWIN) {
832 /* Disable external TX clock receiver */
833 outb((info->twin_serial_cfg &=
834 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
835 card_base + TWIN_SERIAL_CFG);
837 write_scc(priv, R11, priv->param.clocks);
838 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
839 /* Enable external TX clock receiver */
840 outb((info->twin_serial_cfg |=
841 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
842 card_base + TWIN_SERIAL_CFG);
845 /* Configure PackeTwin */
846 if (priv->type == TYPE_TWIN) {
847 /* Assert DTR, enable interrupts */
848 outb((info->twin_serial_cfg |= TWIN_EI |
849 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
850 card_base + TWIN_SERIAL_CFG);
853 /* Read current status */
854 priv->rr0 = read_scc(priv, R0);
855 /* Enable DCD interrupt */
856 write_scc(priv, R15, DCDIE);
858 netif_start_queue(dev);
864 static int scc_close(struct net_device *dev)
866 struct scc_priv *priv = dev->priv;
867 struct scc_info *info = priv->info;
868 int card_base = priv->card_base;
870 netif_stop_queue(dev);
872 if (priv->type == TYPE_TWIN) {
874 outb((info->twin_serial_cfg &=
875 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
876 card_base + TWIN_SERIAL_CFG);
879 /* Reset channel, free DMA and IRQ */
880 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
881 if (priv->param.dma >= 0) {
882 if (priv->type == TYPE_TWIN)
883 outb(0, card_base + TWIN_DMA_CFG);
884 free_dma(priv->param.dma);
886 if (--info->irq_used == 0)
887 free_irq(dev->irq, info);
893 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
895 struct scc_priv *priv = dev->priv;
900 (ifr->ifr_data, &priv->param,
901 sizeof(struct scc_param)))
905 if (!capable(CAP_NET_ADMIN))
907 if (netif_running(dev))
910 (&priv->param, ifr->ifr_data,
911 sizeof(struct scc_param)))
920 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev)
922 struct scc_priv *priv = dev->priv;
926 /* Temporarily stop the scheduler feeding us packets */
927 netif_stop_queue(dev);
929 /* Transfer data to DMA buffer */
931 skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1);
932 priv->tx_len[i] = skb->len - 1;
934 /* Clear interrupts while we touch our circular buffers */
936 spin_lock_irqsave(&priv->ring_lock, flags);
937 /* Move the ring buffer's head */
938 priv->tx_head = (i + 1) % NUM_TX_BUF;
941 /* If we just filled up the last buffer, leave queue stopped.
942 The higher layers must wait until we have a DMA buffer
943 to accept the data. */
944 if (priv->tx_count < NUM_TX_BUF)
945 netif_wake_queue(dev);
947 /* Set new TX state */
948 if (priv->state == IDLE) {
949 /* Assert RTS, start timer */
950 priv->state = TX_HEAD;
951 priv->tx_start = jiffies;
952 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
953 write_scc(priv, R15, 0);
954 start_timer(priv, priv->param.txdelay, 0);
957 /* Turn interrupts back on and free buffer */
958 spin_unlock_irqrestore(&priv->ring_lock, flags);
965 static struct net_device_stats *scc_get_stats(struct net_device *dev)
967 struct scc_priv *priv = dev->priv;
973 static int scc_set_mac_address(struct net_device *dev, void *sa)
975 memcpy(dev->dev_addr, ((struct sockaddr *) sa)->sa_data,
981 static inline void tx_on(struct scc_priv *priv)
986 if (priv->param.dma >= 0) {
987 n = (priv->chip == Z85230) ? 3 : 1;
988 /* Program DMA controller */
989 flags = claim_dma_lock();
990 set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
991 set_dma_addr(priv->param.dma,
992 (int) priv->tx_buf[priv->tx_tail] + n);
993 set_dma_count(priv->param.dma,
994 priv->tx_len[priv->tx_tail] - n);
995 release_dma_lock(flags);
996 /* Enable TX underrun interrupt */
997 write_scc(priv, R15, TxUIE);
999 if (priv->type == TYPE_TWIN)
1000 outb((priv->param.dma ==
1001 1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
1002 priv->card_base + TWIN_DMA_CFG);
1005 EXT_INT_ENAB | WT_FN_RDYFN |
1007 /* Write first byte(s) */
1008 spin_lock_irqsave(priv->register_lock, flags);
1009 for (i = 0; i < n; i++)
1010 write_scc_data(priv,
1011 priv->tx_buf[priv->tx_tail][i], 1);
1012 enable_dma(priv->param.dma);
1013 spin_unlock_irqrestore(priv->register_lock, flags);
1015 write_scc(priv, R15, TxUIE);
1017 EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
1020 /* Reset EOM latch if we do not have the AUTOEOM feature */
1021 if (priv->chip == Z8530)
1022 write_scc(priv, R0, RES_EOM_L);
1026 static inline void rx_on(struct scc_priv *priv)
1028 unsigned long flags;
1031 while (read_scc(priv, R0) & Rx_CH_AV)
1032 read_scc_data(priv);
1034 if (priv->param.dma >= 0) {
1035 /* Program DMA controller */
1036 flags = claim_dma_lock();
1037 set_dma_mode(priv->param.dma, DMA_MODE_READ);
1038 set_dma_addr(priv->param.dma,
1039 (int) priv->rx_buf[priv->rx_head]);
1040 set_dma_count(priv->param.dma, BUF_SIZE);
1041 release_dma_lock(flags);
1042 enable_dma(priv->param.dma);
1043 /* Configure PackeTwin DMA */
1044 if (priv->type == TYPE_TWIN) {
1045 outb((priv->param.dma ==
1046 1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1047 priv->card_base + TWIN_DMA_CFG);
1049 /* Sp. cond. intr. only, ext int enable, RX DMA enable */
1050 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1051 WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1053 /* Reset current frame */
1055 /* Intr. on all Rx characters and Sp. cond., ext int enable */
1056 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1059 write_scc(priv, R0, ERR_RES);
1060 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1064 static inline void rx_off(struct scc_priv *priv)
1066 /* Disable receiver */
1067 write_scc(priv, R3, Rx8);
1068 /* Disable DREQ / RX interrupt */
1069 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1070 outb(0, priv->card_base + TWIN_DMA_CFG);
1072 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1074 if (priv->param.dma >= 0)
1075 disable_dma(priv->param.dma);
1079 static void start_timer(struct scc_priv *priv, int t, int r15)
1081 unsigned long flags;
1083 outb(priv->tmr_mode, priv->tmr_ctrl);
1089 outb(t & 0xFF, priv->tmr_cnt);
1090 outb((t >> 8) & 0xFF, priv->tmr_cnt);
1091 if (priv->type != TYPE_TWIN) {
1092 write_scc(priv, R15, r15 | CTSIE);
1095 restore_flags(flags);
1100 static inline unsigned char random(void)
1102 /* See "Numerical Recipes in C", second edition, p. 284 */
1103 rand = rand * 1664525L + 1013904223L;
1104 return (unsigned char) (rand >> 24);
1107 static inline void z8530_isr(struct scc_info *info)
1111 while ((is = read_scc(&info->priv[0], R3)) && i--) {
1113 rx_isr(&info->priv[0]);
1114 } else if (is & CHATxIP) {
1115 tx_isr(&info->priv[0]);
1116 } else if (is & CHAEXT) {
1117 es_isr(&info->priv[0]);
1118 } else if (is & CHBRxIP) {
1119 rx_isr(&info->priv[1]);
1120 } else if (is & CHBTxIP) {
1121 tx_isr(&info->priv[1]);
1123 es_isr(&info->priv[1]);
1125 write_scc(&info->priv[0], R0, RES_H_IUS);
1129 printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n",
1132 /* Ok, no interrupts pending from this 8530. The INT line should
1137 static irqreturn_t scc_isr(int irq, void *dev_id)
1139 struct scc_info *info = dev_id;
1141 spin_lock(info->priv[0].register_lock);
1142 /* At this point interrupts are enabled, and the interrupt under service
1143 is already acknowledged, but masked off.
1145 Interrupt processing: We loop until we know that the IRQ line is
1146 low. If another positive edge occurs afterwards during the ISR,
1147 another interrupt will be triggered by the interrupt controller
1148 as soon as the IRQ level is enabled again (see asm/irq.h).
1150 Bottom-half handlers will be processed after scc_isr(). This is
1151 important, since we only have small ringbuffers and want new data
1152 to be fetched/delivered immediately. */
1154 if (info->priv[0].type == TYPE_TWIN) {
1155 int is, card_base = info->priv[0].card_base;
1156 while ((is = ~inb(card_base + TWIN_INT_REG)) &
1158 if (is & TWIN_SCC_MSK) {
1160 } else if (is & TWIN_TMR1_MSK) {
1161 inb(card_base + TWIN_CLR_TMR1);
1162 tm_isr(&info->priv[0]);
1164 inb(card_base + TWIN_CLR_TMR2);
1165 tm_isr(&info->priv[1]);
1170 spin_unlock(info->priv[0].register_lock);
1175 static void rx_isr(struct scc_priv *priv)
1177 if (priv->param.dma >= 0) {
1178 /* Check special condition and perform error reset. See 2.4.7.5. */
1179 special_condition(priv, read_scc(priv, R1));
1180 write_scc(priv, R0, ERR_RES);
1182 /* Check special condition for each character. Error reset not necessary.
1183 Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
1185 while (read_scc(priv, R0) & Rx_CH_AV) {
1186 rc = read_scc(priv, R1);
1187 if (priv->rx_ptr < BUF_SIZE)
1188 priv->rx_buf[priv->rx_head][priv->
1190 read_scc_data(priv);
1193 read_scc_data(priv);
1195 special_condition(priv, rc);
1201 static void special_condition(struct scc_priv *priv, int rc)
1204 unsigned long flags;
1206 /* See Figure 2-15. Only overrun and EOF need to be checked. */
1209 /* Receiver overrun */
1211 if (priv->param.dma < 0)
1212 write_scc(priv, R0, ERR_RES);
1213 } else if (rc & END_FR) {
1214 /* End of frame. Get byte count */
1215 if (priv->param.dma >= 0) {
1216 flags = claim_dma_lock();
1217 cb = BUF_SIZE - get_dma_residue(priv->param.dma) -
1219 release_dma_lock(flags);
1221 cb = priv->rx_ptr - 2;
1223 if (priv->rx_over) {
1224 /* We had an overrun */
1225 priv->stats.rx_errors++;
1226 if (priv->rx_over == 2)
1227 priv->stats.rx_length_errors++;
1229 priv->stats.rx_fifo_errors++;
1231 } else if (rc & CRC_ERR) {
1232 /* Count invalid CRC only if packet length >= minimum */
1234 priv->stats.rx_errors++;
1235 priv->stats.rx_crc_errors++;
1239 if (priv->rx_count < NUM_RX_BUF - 1) {
1240 /* Put good frame in FIFO */
1241 priv->rx_len[priv->rx_head] = cb;
1246 schedule_work(&priv->rx_work);
1248 priv->stats.rx_errors++;
1249 priv->stats.rx_over_errors++;
1253 /* Get ready for new frame */
1254 if (priv->param.dma >= 0) {
1255 flags = claim_dma_lock();
1256 set_dma_addr(priv->param.dma,
1257 (int) priv->rx_buf[priv->rx_head]);
1258 set_dma_count(priv->param.dma, BUF_SIZE);
1259 release_dma_lock(flags);
1267 static void rx_bh(struct work_struct *ugli_api)
1269 struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work);
1270 int i = priv->rx_tail;
1272 unsigned long flags;
1273 struct sk_buff *skb;
1274 unsigned char *data;
1276 spin_lock_irqsave(&priv->ring_lock, flags);
1277 while (priv->rx_count) {
1278 spin_unlock_irqrestore(&priv->ring_lock, flags);
1279 cb = priv->rx_len[i];
1280 /* Allocate buffer */
1281 skb = dev_alloc_skb(cb + 1);
1284 priv->stats.rx_dropped++;
1287 data = skb_put(skb, cb + 1);
1289 memcpy(&data[1], priv->rx_buf[i], cb);
1290 skb->protocol = ax25_type_trans(skb, priv->dev);
1292 priv->dev->last_rx = jiffies;
1293 priv->stats.rx_packets++;
1294 priv->stats.rx_bytes += cb;
1296 spin_lock_irqsave(&priv->ring_lock, flags);
1298 priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1301 spin_unlock_irqrestore(&priv->ring_lock, flags);
1305 static void tx_isr(struct scc_priv *priv)
1307 int i = priv->tx_tail, p = priv->tx_ptr;
1309 /* Suspend TX interrupts if we don't want to send anything.
1311 if (p == priv->tx_len[i]) {
1312 write_scc(priv, R0, RES_Tx_P);
1316 /* Write characters */
1317 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1318 write_scc_data(priv, priv->tx_buf[i][p++], 0);
1321 /* Reset EOM latch of Z8530 */
1322 if (!priv->tx_ptr && p && priv->chip == Z8530)
1323 write_scc(priv, R0, RES_EOM_L);
1329 static void es_isr(struct scc_priv *priv)
1331 int i, rr0, drr0, res;
1332 unsigned long flags;
1334 /* Read status, reset interrupt bit (open latches) */
1335 rr0 = read_scc(priv, R0);
1336 write_scc(priv, R0, RES_EXT_INT);
1337 drr0 = priv->rr0 ^ rr0;
1340 /* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since
1341 it might have already been cleared again by AUTOEOM. */
1342 if (priv->state == TX_DATA) {
1343 /* Get remaining bytes */
1345 if (priv->param.dma >= 0) {
1346 disable_dma(priv->param.dma);
1347 flags = claim_dma_lock();
1348 res = get_dma_residue(priv->param.dma);
1349 release_dma_lock(flags);
1351 res = priv->tx_len[i] - priv->tx_ptr;
1354 /* Disable DREQ / TX interrupt */
1355 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1356 outb(0, priv->card_base + TWIN_DMA_CFG);
1358 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1360 /* Update packet statistics */
1361 priv->stats.tx_errors++;
1362 priv->stats.tx_fifo_errors++;
1363 /* Other underrun interrupts may already be waiting */
1364 write_scc(priv, R0, RES_EXT_INT);
1365 write_scc(priv, R0, RES_EXT_INT);
1367 /* Update packet statistics */
1368 priv->stats.tx_packets++;
1369 priv->stats.tx_bytes += priv->tx_len[i];
1370 /* Remove frame from FIFO */
1371 priv->tx_tail = (i + 1) % NUM_TX_BUF;
1373 /* Inform upper layers */
1374 netif_wake_queue(priv->dev);
1377 write_scc(priv, R15, 0);
1378 if (priv->tx_count &&
1379 (jiffies - priv->tx_start) < priv->param.txtimeout) {
1380 priv->state = TX_PAUSE;
1381 start_timer(priv, priv->param.txpause, 0);
1383 priv->state = TX_TAIL;
1384 start_timer(priv, priv->param.txtail, 0);
1388 /* DCD transition */
1391 switch (priv->state) {
1394 priv->state = DCD_ON;
1395 write_scc(priv, R15, 0);
1396 start_timer(priv, priv->param.dcdon, 0);
1399 switch (priv->state) {
1402 priv->state = DCD_OFF;
1403 write_scc(priv, R15, 0);
1404 start_timer(priv, priv->param.dcdoff, 0);
1409 /* CTS transition */
1410 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1416 static void tm_isr(struct scc_priv *priv)
1418 switch (priv->state) {
1422 priv->state = TX_DATA;
1425 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1426 priv->state = RTS_OFF;
1427 if (priv->type != TYPE_TWIN)
1428 write_scc(priv, R15, 0);
1429 start_timer(priv, priv->param.rtsoff, 0);
1432 write_scc(priv, R15, DCDIE);
1433 priv->rr0 = read_scc(priv, R0);
1434 if (priv->rr0 & DCD) {
1435 priv->stats.collisions++;
1437 priv->state = RX_ON;
1440 start_timer(priv, priv->param.waittime, DCDIE);
1444 if (priv->tx_count) {
1445 priv->state = TX_HEAD;
1446 priv->tx_start = jiffies;
1448 TxCRC_ENAB | RTS | TxENAB | Tx8);
1449 write_scc(priv, R15, 0);
1450 start_timer(priv, priv->param.txdelay, 0);
1453 if (priv->type != TYPE_TWIN)
1454 write_scc(priv, R15, DCDIE);
1459 write_scc(priv, R15, DCDIE);
1460 priv->rr0 = read_scc(priv, R0);
1461 if (priv->rr0 & DCD) {
1463 priv->state = RX_ON;
1467 random() / priv->param.persist *
1468 priv->param.slottime, DCDIE);