2 * drivers/net/ibm_newemac/mal.c
4 * Memory Access Layer (MAL) support
6 * Copyright (c) 2004, 2005 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
9 * Based on original work by
10 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
11 * David Gibson <hermes@gibson.dropbear.id.au>,
13 * Armin Kuster <akuster@mvista.com>
14 * Copyright 2002 MontaVista Softare Inc.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
23 #include <linux/delay.h>
29 int __devinit mal_register_commac(struct mal_instance *mal,
30 struct mal_commac *commac)
34 spin_lock_irqsave(&mal->lock, flags);
36 MAL_DBG(mal, "reg(%08x, %08x)" NL,
37 commac->tx_chan_mask, commac->rx_chan_mask);
39 /* Don't let multiple commacs claim the same channel(s) */
40 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
41 (mal->rx_chan_mask & commac->rx_chan_mask)) {
42 spin_unlock_irqrestore(&mal->lock, flags);
43 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
48 mal->tx_chan_mask |= commac->tx_chan_mask;
49 mal->rx_chan_mask |= commac->rx_chan_mask;
50 list_add(&commac->list, &mal->list);
52 spin_unlock_irqrestore(&mal->lock, flags);
57 void __devexit mal_unregister_commac(struct mal_instance *mal,
58 struct mal_commac *commac)
62 spin_lock_irqsave(&mal->lock, flags);
64 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
65 commac->tx_chan_mask, commac->rx_chan_mask);
67 mal->tx_chan_mask &= ~commac->tx_chan_mask;
68 mal->rx_chan_mask &= ~commac->rx_chan_mask;
69 list_del_init(&commac->list);
71 spin_unlock_irqrestore(&mal->lock, flags);
74 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
76 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
77 size > MAL_MAX_RX_SIZE);
79 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
83 "mal%d: incorrect RX size %lu for the channel %d\n",
84 mal->index, size, channel);
88 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
92 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
94 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
96 return channel * NUM_TX_BUFF;
99 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
101 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
102 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
105 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
109 spin_lock_irqsave(&mal->lock, flags);
111 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
113 set_mal_dcrn(mal, MAL_TXCASR,
114 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
116 spin_unlock_irqrestore(&mal->lock, flags);
119 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
121 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
123 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
126 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
130 spin_lock_irqsave(&mal->lock, flags);
132 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
134 set_mal_dcrn(mal, MAL_RXCASR,
135 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
137 spin_unlock_irqrestore(&mal->lock, flags);
140 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
142 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
144 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
147 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
151 spin_lock_irqsave(&mal->lock, flags);
153 MAL_DBG(mal, "poll_add(%p)" NL, commac);
155 /* starts disabled */
156 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
158 list_add_tail(&commac->poll_list, &mal->poll_list);
160 spin_unlock_irqrestore(&mal->lock, flags);
163 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
167 spin_lock_irqsave(&mal->lock, flags);
169 MAL_DBG(mal, "poll_del(%p)" NL, commac);
171 list_del(&commac->poll_list);
173 spin_unlock_irqrestore(&mal->lock, flags);
176 /* synchronized by mal_poll() */
177 static inline void mal_enable_eob_irq(struct mal_instance *mal)
179 MAL_DBG2(mal, "enable_irq" NL);
181 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
182 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
185 /* synchronized by __LINK_STATE_RX_SCHED bit in ndev->state */
186 static inline void mal_disable_eob_irq(struct mal_instance *mal)
188 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
189 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
191 MAL_DBG2(mal, "disable_irq" NL);
194 static irqreturn_t mal_serr(int irq, void *dev_instance)
196 struct mal_instance *mal = dev_instance;
198 u32 esr = get_mal_dcrn(mal, MAL_ESR);
200 /* Clear the error status register */
201 set_mal_dcrn(mal, MAL_ESR, esr);
203 MAL_DBG(mal, "SERR %08x" NL, esr);
205 if (esr & MAL_ESR_EVB) {
206 if (esr & MAL_ESR_DE) {
207 /* We ignore Descriptor error,
208 * TXDE or RXDE interrupt will be generated anyway.
213 if (esr & MAL_ESR_PEIN) {
214 /* PLB error, it's probably buggy hardware or
215 * incorrect physical address in BD (i.e. bug)
219 "mal%d: system error, "
220 "PLB (ESR = 0x%08x)\n",
225 /* OPB error, it's probably buggy hardware or incorrect
230 "mal%d: system error, OPB (ESR = 0x%08x)\n",
236 static inline void mal_schedule_poll(struct mal_instance *mal)
238 if (likely(netif_rx_schedule_prep(&mal->poll_dev))) {
239 MAL_DBG2(mal, "schedule_poll" NL);
240 mal_disable_eob_irq(mal);
241 __netif_rx_schedule(&mal->poll_dev);
243 MAL_DBG2(mal, "already in poll" NL);
246 static irqreturn_t mal_txeob(int irq, void *dev_instance)
248 struct mal_instance *mal = dev_instance;
250 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
252 MAL_DBG2(mal, "txeob %08x" NL, r);
254 mal_schedule_poll(mal);
255 set_mal_dcrn(mal, MAL_TXEOBISR, r);
260 static irqreturn_t mal_rxeob(int irq, void *dev_instance)
262 struct mal_instance *mal = dev_instance;
264 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
266 MAL_DBG2(mal, "rxeob %08x" NL, r);
268 mal_schedule_poll(mal);
269 set_mal_dcrn(mal, MAL_RXEOBISR, r);
274 static irqreturn_t mal_txde(int irq, void *dev_instance)
276 struct mal_instance *mal = dev_instance;
278 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
279 set_mal_dcrn(mal, MAL_TXDEIR, deir);
281 MAL_DBG(mal, "txde %08x" NL, deir);
285 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
291 static irqreturn_t mal_rxde(int irq, void *dev_instance)
293 struct mal_instance *mal = dev_instance;
296 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
298 MAL_DBG(mal, "rxde %08x" NL, deir);
300 list_for_each(l, &mal->list) {
301 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
302 if (deir & mc->rx_chan_mask) {
303 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
304 mc->ops->rxde(mc->dev);
308 mal_schedule_poll(mal);
309 set_mal_dcrn(mal, MAL_RXDEIR, deir);
314 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
316 /* Spinlock-type semantics: only one caller disable poll at a time */
317 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
320 /* Synchronize with the MAL NAPI poller. */
321 while (test_bit(__LINK_STATE_RX_SCHED, &mal->poll_dev.state))
325 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
328 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
330 // XXX might want to kick a poll now...
333 static int mal_poll(struct net_device *ndev, int *budget)
335 struct mal_instance *mal = netdev_priv(ndev);
337 int rx_work_limit = min(ndev->quota, *budget), received = 0, done;
340 MAL_DBG2(mal, "poll(%d) %d ->" NL, *budget,
343 /* Process TX skbs */
344 list_for_each(l, &mal->poll_list) {
345 struct mal_commac *mc =
346 list_entry(l, struct mal_commac, poll_list);
347 mc->ops->poll_tx(mc->dev);
352 * We _might_ need something more smart here to enforce polling
355 list_for_each(l, &mal->poll_list) {
356 struct mal_commac *mc =
357 list_entry(l, struct mal_commac, poll_list);
359 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
361 n = mc->ops->poll_rx(mc->dev, rx_work_limit);
365 if (rx_work_limit <= 0) {
367 // XXX What if this is the last one ?
373 /* We need to disable IRQs to protect from RXDE IRQ here */
374 spin_lock_irqsave(&mal->lock, flags);
375 __netif_rx_complete(ndev);
376 mal_enable_eob_irq(mal);
377 spin_unlock_irqrestore(&mal->lock, flags);
381 /* Check for "rotting" packet(s) */
382 list_for_each(l, &mal->poll_list) {
383 struct mal_commac *mc =
384 list_entry(l, struct mal_commac, poll_list);
385 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
387 if (unlikely(mc->ops->peek_rx(mc->dev) ||
388 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
389 MAL_DBG2(mal, "rotting packet" NL);
390 if (netif_rx_reschedule(ndev, received))
391 mal_disable_eob_irq(mal);
393 MAL_DBG2(mal, "already in poll list" NL);
395 if (rx_work_limit > 0)
400 mc->ops->poll_tx(mc->dev);
404 ndev->quota -= received;
407 MAL_DBG2(mal, "poll() %d <- %d" NL, *budget,
413 static void mal_reset(struct mal_instance *mal)
417 MAL_DBG(mal, "reset" NL);
419 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
421 /* Wait for reset to complete (1 system clock) */
422 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
426 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
429 int mal_get_regs_len(struct mal_instance *mal)
431 return sizeof(struct emac_ethtool_regs_subhdr) +
432 sizeof(struct mal_regs);
435 void *mal_dump_regs(struct mal_instance *mal, void *buf)
437 struct emac_ethtool_regs_subhdr *hdr = buf;
438 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
441 hdr->version = mal->version;
442 hdr->index = mal->index;
444 regs->tx_count = mal->num_tx_chans;
445 regs->rx_count = mal->num_rx_chans;
447 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
448 regs->esr = get_mal_dcrn(mal, MAL_ESR);
449 regs->ier = get_mal_dcrn(mal, MAL_IER);
450 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
451 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
452 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
453 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
454 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
455 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
456 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
457 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
459 for (i = 0; i < regs->tx_count; ++i)
460 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
462 for (i = 0; i < regs->rx_count; ++i) {
463 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
464 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
469 static int __devinit mal_probe(struct of_device *ofdev,
470 const struct of_device_id *match)
472 struct mal_instance *mal;
473 int err = 0, i, bd_size;
474 int index = mal_count++;
478 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
481 "mal%d: out of memory allocating MAL structure!\n",
487 mal->version = of_device_is_compatible(ofdev->node, "ibm,mcmal2") ? 2 : 1;
489 MAL_DBG(mal, "probe" NL);
491 prop = of_get_property(ofdev->node, "num-tx-chans", NULL);
494 "mal%d: can't find MAL num-tx-chans property!\n",
499 mal->num_tx_chans = prop[0];
501 prop = of_get_property(ofdev->node, "num-rx-chans", NULL);
504 "mal%d: can't find MAL num-rx-chans property!\n",
509 mal->num_rx_chans = prop[0];
511 mal->dcr_base = dcr_resource_start(ofdev->node, 0);
512 if (mal->dcr_base == 0) {
514 "mal%d: can't find DCR resource!\n", index);
518 mal->dcr_host = dcr_map(ofdev->node, mal->dcr_base, 0x100);
519 if (!DCR_MAP_OK(mal->dcr_host)) {
521 "mal%d: failed to map DCRs !\n", index);
526 mal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);
527 mal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);
528 mal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);
529 mal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);
530 mal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);
531 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
532 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
533 mal->rxde_irq == NO_IRQ) {
535 "mal%d: failed to map interrupts !\n", index);
540 INIT_LIST_HEAD(&mal->poll_list);
541 set_bit(__LINK_STATE_START, &mal->poll_dev.state);
542 mal->poll_dev.weight = CONFIG_IBM_NEW_EMAC_POLL_WEIGHT;
543 mal->poll_dev.poll = mal_poll;
544 mal->poll_dev.priv = mal;
545 atomic_set(&mal->poll_dev.refcnt, 1);
546 INIT_LIST_HEAD(&mal->list);
547 spin_lock_init(&mal->lock);
549 /* Load power-on reset defaults */
552 /* Set the MAL configuration register */
553 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
554 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
556 /* Current Axon is not happy with priority being non-0, it can
557 * deadlock, fix it up here
559 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-axon"))
560 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
562 /* Apply configuration */
563 set_mal_dcrn(mal, MAL_CFG, cfg);
565 /* Allocate space for BD rings */
566 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
567 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
569 bd_size = sizeof(struct mal_descriptor) *
570 (NUM_TX_BUFF * mal->num_tx_chans +
571 NUM_RX_BUFF * mal->num_rx_chans);
573 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
575 if (mal->bd_virt == NULL) {
577 "mal%d: out of memory allocating RX/TX descriptors!\n",
582 memset(mal->bd_virt, 0, bd_size);
584 for (i = 0; i < mal->num_tx_chans; ++i)
585 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
586 sizeof(struct mal_descriptor) *
587 mal_tx_bd_offset(mal, i));
589 for (i = 0; i < mal->num_rx_chans; ++i)
590 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
591 sizeof(struct mal_descriptor) *
592 mal_rx_bd_offset(mal, i));
594 err = request_irq(mal->serr_irq, mal_serr, 0, "MAL SERR", mal);
597 err = request_irq(mal->txde_irq, mal_txde, 0, "MAL TX DE", mal);
600 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
603 err = request_irq(mal->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
606 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
610 /* Enable all MAL SERR interrupt sources */
611 if (mal->version == 2)
612 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
614 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
616 /* Enable EOB interrupt */
617 mal_enable_eob_irq(mal);
620 "MAL v%d %s, %d TX channels, %d RX channels\n",
621 mal->version, ofdev->node->full_name,
622 mal->num_tx_chans, mal->num_rx_chans);
624 /* Advertise this instance to the rest of the world */
626 dev_set_drvdata(&ofdev->dev, mal);
628 mal_dbg_register(mal);
633 free_irq(mal->rxde_irq, mal);
635 free_irq(mal->txeob_irq, mal);
637 free_irq(mal->txde_irq, mal);
639 free_irq(mal->serr_irq, mal);
641 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
643 dcr_unmap(mal->dcr_host, mal->dcr_base, 0x100);
650 static int __devexit mal_remove(struct of_device *ofdev)
652 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
654 MAL_DBG(mal, "remove" NL);
656 /* Syncronize with scheduled polling,
657 stolen from net/core/dev.c:dev_close()
659 clear_bit(__LINK_STATE_START, &mal->poll_dev.state);
660 netif_poll_disable(&mal->poll_dev);
662 if (!list_empty(&mal->list)) {
663 /* This is *very* bad */
665 "mal%d: commac list is not empty on remove!\n",
670 dev_set_drvdata(&ofdev->dev, NULL);
672 free_irq(mal->serr_irq, mal);
673 free_irq(mal->txde_irq, mal);
674 free_irq(mal->txeob_irq, mal);
675 free_irq(mal->rxde_irq, mal);
676 free_irq(mal->rxeob_irq, mal);
680 mal_dbg_unregister(mal);
682 dma_free_coherent(&ofdev->dev,
683 sizeof(struct mal_descriptor) *
684 (NUM_TX_BUFF * mal->num_tx_chans +
685 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
692 static struct of_device_id mal_platform_match[] =
695 .compatible = "ibm,mcmal",
698 .compatible = "ibm,mcmal2",
700 /* Backward compat */
703 .compatible = "ibm,mcmal",
707 .compatible = "ibm,mcmal2",
712 static struct of_platform_driver mal_of_driver = {
714 .match_table = mal_platform_match,
717 .remove = mal_remove,
720 int __init mal_init(void)
722 return of_register_platform_driver(&mal_of_driver);
727 of_unregister_platform_driver(&mal_of_driver);