1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
36 #include "ixgbe_type.h"
37 #include "ixgbe_common.h"
40 #define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
43 #define DPRINTK(nlevel, klevel, fmt, args...) \
44 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
45 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
46 __FUNCTION__ , ## args)))
48 /* TX/RX descriptor defines */
49 #define IXGBE_DEFAULT_TXD 1024
50 #define IXGBE_MAX_TXD 4096
51 #define IXGBE_MIN_TXD 64
53 #define IXGBE_DEFAULT_RXD 1024
54 #define IXGBE_MAX_RXD 4096
55 #define IXGBE_MIN_RXD 64
57 #define IXGBE_DEFAULT_RXQ 1
58 #define IXGBE_MAX_RXQ 1
59 #define IXGBE_MIN_RXQ 1
61 #define IXGBE_DEFAULT_ITR_RX_USECS 125 /* 8k irqs/sec */
62 #define IXGBE_DEFAULT_ITR_TX_USECS 250 /* 4k irqs/sec */
63 #define IXGBE_MIN_ITR_USECS 100 /* 500k irqs/sec */
64 #define IXGBE_MAX_ITR_USECS 10000 /* 100 irqs/sec */
67 #define IXGBE_DEFAULT_FCRTL 0x10000
68 #define IXGBE_MIN_FCRTL 0
69 #define IXGBE_MAX_FCRTL 0x7FF80
70 #define IXGBE_DEFAULT_FCRTH 0x20000
71 #define IXGBE_MIN_FCRTH 0
72 #define IXGBE_MAX_FCRTH 0x7FFF0
73 #define IXGBE_DEFAULT_FCPAUSE 0x6800 /* may be too long */
74 #define IXGBE_MIN_FCPAUSE 0
75 #define IXGBE_MAX_FCPAUSE 0xFFFF
77 /* Supported Rx Buffer Sizes */
78 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
79 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
80 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
81 #define IXGBE_RXBUFFER_2048 2048
83 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
85 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
87 /* How many Tx Descriptors do we need to call netif_wake_queue? */
88 #define IXGBE_TX_QUEUE_WAKE 16
90 /* How many Rx Buffers do we bundle into one write to the hardware ? */
91 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
93 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
94 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
97 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
98 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
100 /* wrapper around a pointer to a socket buffer,
101 * so a DMA handle can be stored along with the buffer */
102 struct ixgbe_tx_buffer {
105 unsigned long time_stamp;
110 struct ixgbe_rx_buffer {
117 struct ixgbe_queue_stats {
123 void *desc; /* descriptor ring memory */
124 dma_addr_t dma; /* phys. address of descriptor ring */
125 unsigned int size; /* length in bytes */
126 unsigned int count; /* amount of descriptors */
127 unsigned int next_to_use;
128 unsigned int next_to_clean;
130 int queue_index; /* needed for multiqueue queue management */
132 struct ixgbe_tx_buffer *tx_buffer_info;
133 struct ixgbe_rx_buffer *rx_buffer_info;
139 unsigned int total_bytes;
140 unsigned int total_packets;
142 u16 reg_idx; /* holds the special value that gets the hardware register
143 * offset associated with this ring, which is different
144 * for DCE and RSS modes */
145 struct ixgbe_queue_stats stats;
146 u8 v_idx; /* maps directly to the index for this ring in the hardware
147 * vector array, can also be used for finding the bit in EICR
148 * and friends that represents the vector for this ring */
153 char name[IFNAMSIZ + 5];
154 u16 work_limit; /* max work per interrupt */
157 #define RING_F_VMDQ 1
159 #define IXGBE_MAX_RSS_INDICES 16
160 #define IXGBE_MAX_VMDQ_INDICES 16
161 struct ixgbe_ring_feature {
166 #define MAX_RX_QUEUES 64
167 #define MAX_TX_QUEUES 32
169 /* MAX_MSIX_Q_VECTORS of these are allocated,
170 * but we only use one per queue-specific vector.
172 struct ixgbe_q_vector {
173 struct ixgbe_adapter *adapter;
174 struct napi_struct napi;
175 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
176 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
177 u8 rxr_count; /* Rx ring count assigned to this vector */
178 u8 txr_count; /* Tx ring count assigned to this vector */
184 /* Helper macros to switch between ints/sec and what the register uses.
185 * And yes, it's the same math going both ways.
187 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
188 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
189 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
191 #define IXGBE_DESC_UNUSED(R) \
192 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
193 (R)->next_to_clean - (R)->next_to_use - 1)
195 #define IXGBE_RX_DESC_ADV(R, i) \
196 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
197 #define IXGBE_TX_DESC_ADV(R, i) \
198 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
199 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
200 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
202 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
204 #define OTHER_VECTOR 1
205 #define NON_Q_VECTORS (OTHER_VECTOR)
207 #define MAX_MSIX_Q_VECTORS 16
208 #define MIN_MSIX_Q_VECTORS 2
209 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
210 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
212 /* board specific private data structure */
213 struct ixgbe_adapter {
214 struct timer_list watchdog_timer;
215 struct vlan_group *vlgrp;
218 struct work_struct reset_task;
219 struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
220 char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
222 /* Interrupt Throttle Rate */
228 struct ixgbe_ring *tx_ring; /* One per active queue */
233 u32 tx_timeout_count;
237 struct ixgbe_ring *rx_ring; /* One per active queue */
239 u64 hw_csum_rx_error;
244 int num_msix_vectors;
245 struct ixgbe_ring_feature ring_feature[3];
246 struct msix_entry *msix_entries;
249 u32 alloc_rx_page_failed;
250 u32 alloc_rx_buff_failed;
252 /* Some features need tri-state capability,
253 * thus the additional *_CAPABLE flags.
256 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1 << 0)
257 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
258 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 2)
259 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3)
260 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4)
261 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 5)
262 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 6)
263 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
265 /* OS defined structs */
266 struct net_device *netdev;
267 struct pci_dev *pdev;
268 struct net_device_stats net_stats;
270 /* structs defined in ixgbe_hw.h */
273 struct ixgbe_hw_stats stats;
275 /* Interrupt Throttle Rate */
293 extern struct ixgbe_info ixgbe_82598_info;
295 extern char ixgbe_driver_name[];
296 extern const char ixgbe_driver_version[];
298 extern int ixgbe_up(struct ixgbe_adapter *adapter);
299 extern void ixgbe_down(struct ixgbe_adapter *adapter);
300 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
301 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
302 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
303 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
304 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
305 struct ixgbe_ring *rxdr);
306 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
307 struct ixgbe_ring *txdr);
309 #endif /* _IXGBE_H_ */