2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_TX_FAST_REFILL
63 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
64 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66 #define MAX_DESCS_PER_SKB 1
70 * Registers shared between all ports.
72 #define PHY_ADDR 0x0000
73 #define SMI_REG 0x0004
74 #define SMI_BUSY 0x10000000
75 #define SMI_READ_VALID 0x08000000
76 #define SMI_OPCODE_READ 0x04000000
77 #define SMI_OPCODE_WRITE 0x00000000
78 #define ERR_INT_CAUSE 0x0080
79 #define ERR_INT_SMI_DONE 0x00000010
80 #define ERR_INT_MASK 0x0084
81 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
82 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
83 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
84 #define WINDOW_BAR_ENABLE 0x0290
85 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
90 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
91 #define UNICAST_PROMISCUOUS_MODE 0x00000001
92 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
93 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
94 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
95 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
96 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
97 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
98 #define TX_FIFO_EMPTY 0x00000400
99 #define TX_IN_PROGRESS 0x00000080
100 #define PORT_SPEED_MASK 0x00000030
101 #define PORT_SPEED_1000 0x00000010
102 #define PORT_SPEED_100 0x00000020
103 #define PORT_SPEED_10 0x00000000
104 #define FLOW_CONTROL_ENABLED 0x00000008
105 #define FULL_DUPLEX 0x00000004
106 #define LINK_UP 0x00000002
107 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
108 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
109 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
110 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
111 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
112 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
113 #define INT_TX_END_0 0x00080000
114 #define INT_TX_END 0x07f80000
115 #define INT_RX 0x0007fbfc
116 #define INT_EXT 0x00000002
117 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
118 #define INT_EXT_LINK 0x00100000
119 #define INT_EXT_PHY 0x00010000
120 #define INT_EXT_TX_ERROR_0 0x00000100
121 #define INT_EXT_TX_0 0x00000001
122 #define INT_EXT_TX 0x0000ffff
123 #define INT_MASK(p) (0x0468 + ((p) << 10))
124 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
125 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
126 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
127 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
128 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
129 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
130 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
131 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
132 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
133 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
134 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
135 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
136 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
137 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
138 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
139 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
143 * SDMA configuration register.
145 #define RX_BURST_SIZE_16_64BIT (4 << 1)
146 #define BLM_RX_NO_SWAP (1 << 4)
147 #define BLM_TX_NO_SWAP (1 << 5)
148 #define TX_BURST_SIZE_16_64BIT (4 << 22)
150 #if defined(__BIG_ENDIAN)
151 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
152 RX_BURST_SIZE_16_64BIT | \
153 TX_BURST_SIZE_16_64BIT
154 #elif defined(__LITTLE_ENDIAN)
155 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
156 RX_BURST_SIZE_16_64BIT | \
159 TX_BURST_SIZE_16_64BIT
161 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
166 * Port serial control register.
168 #define SET_MII_SPEED_TO_100 (1 << 24)
169 #define SET_GMII_SPEED_TO_1000 (1 << 23)
170 #define SET_FULL_DUPLEX_MODE (1 << 21)
171 #define MAX_RX_PACKET_9700BYTE (5 << 17)
172 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
173 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
174 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
175 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
176 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
177 #define FORCE_LINK_PASS (1 << 1)
178 #define SERIAL_PORT_ENABLE (1 << 0)
180 #define DEFAULT_RX_QUEUE_SIZE 400
181 #define DEFAULT_TX_QUEUE_SIZE 800
187 #if defined(__BIG_ENDIAN)
189 u16 byte_cnt; /* Descriptor buffer byte count */
190 u16 buf_size; /* Buffer size */
191 u32 cmd_sts; /* Descriptor command status */
192 u32 next_desc_ptr; /* Next descriptor pointer */
193 u32 buf_ptr; /* Descriptor buffer pointer */
197 u16 byte_cnt; /* buffer byte count */
198 u16 l4i_chk; /* CPU provided TCP checksum */
199 u32 cmd_sts; /* Command/status field */
200 u32 next_desc_ptr; /* Pointer to next descriptor */
201 u32 buf_ptr; /* pointer to buffer for this descriptor*/
203 #elif defined(__LITTLE_ENDIAN)
205 u32 cmd_sts; /* Descriptor command status */
206 u16 buf_size; /* Buffer size */
207 u16 byte_cnt; /* Descriptor buffer byte count */
208 u32 buf_ptr; /* Descriptor buffer pointer */
209 u32 next_desc_ptr; /* Next descriptor pointer */
213 u32 cmd_sts; /* Command/status field */
214 u16 l4i_chk; /* CPU provided TCP checksum */
215 u16 byte_cnt; /* buffer byte count */
216 u32 buf_ptr; /* pointer to buffer for this descriptor*/
217 u32 next_desc_ptr; /* Pointer to next descriptor */
220 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
223 /* RX & TX descriptor command */
224 #define BUFFER_OWNED_BY_DMA 0x80000000
226 /* RX & TX descriptor status */
227 #define ERROR_SUMMARY 0x00000001
229 /* RX descriptor status */
230 #define LAYER_4_CHECKSUM_OK 0x40000000
231 #define RX_ENABLE_INTERRUPT 0x20000000
232 #define RX_FIRST_DESC 0x08000000
233 #define RX_LAST_DESC 0x04000000
235 /* TX descriptor command */
236 #define TX_ENABLE_INTERRUPT 0x00800000
237 #define GEN_CRC 0x00400000
238 #define TX_FIRST_DESC 0x00200000
239 #define TX_LAST_DESC 0x00100000
240 #define ZERO_PADDING 0x00080000
241 #define GEN_IP_V4_CHECKSUM 0x00040000
242 #define GEN_TCP_UDP_CHECKSUM 0x00020000
243 #define UDP_FRAME 0x00010000
244 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
245 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
247 #define TX_IHL_SHIFT 11
250 /* global *******************************************************************/
251 struct mv643xx_eth_shared_private {
253 * Ethernet controller base address.
258 * Protects access to SMI_REG, which is shared between ports.
260 struct mutex phy_lock;
263 * If we have access to the error interrupt pin (which is
264 * somewhat misnamed as it not only reflects internal errors
265 * but also reflects SMI completion), use that to wait for
266 * SMI access completion instead of polling the SMI busy bit.
269 wait_queue_head_t smi_busy_wait;
272 * Per-port MBUS window access register value.
277 * Hardware-specific parameters.
280 int extended_rx_coal_limit;
281 int tx_bw_control_moved;
285 /* per-port *****************************************************************/
286 struct mib_counters {
287 u64 good_octets_received;
288 u32 bad_octets_received;
289 u32 internal_mac_transmit_err;
290 u32 good_frames_received;
291 u32 bad_frames_received;
292 u32 broadcast_frames_received;
293 u32 multicast_frames_received;
294 u32 frames_64_octets;
295 u32 frames_65_to_127_octets;
296 u32 frames_128_to_255_octets;
297 u32 frames_256_to_511_octets;
298 u32 frames_512_to_1023_octets;
299 u32 frames_1024_to_max_octets;
300 u64 good_octets_sent;
301 u32 good_frames_sent;
302 u32 excessive_collision;
303 u32 multicast_frames_sent;
304 u32 broadcast_frames_sent;
305 u32 unrec_mac_control_received;
307 u32 good_fc_received;
309 u32 undersize_received;
310 u32 fragments_received;
311 u32 oversize_received;
313 u32 mac_receive_error;
328 struct rx_desc *rx_desc_area;
329 dma_addr_t rx_desc_dma;
330 int rx_desc_area_size;
331 struct sk_buff **rx_skb;
333 struct timer_list rx_oom;
345 struct tx_desc *tx_desc_area;
346 dma_addr_t tx_desc_dma;
347 int tx_desc_area_size;
348 struct sk_buff **tx_skb;
351 struct mv643xx_eth_private {
352 struct mv643xx_eth_shared_private *shared;
355 struct net_device *dev;
357 struct mv643xx_eth_shared_private *shared_smi;
362 struct mib_counters mib_counters;
363 struct work_struct tx_timeout_task;
364 struct mii_if_info mii;
369 int default_rx_ring_size;
370 unsigned long rx_desc_sram_addr;
371 int rx_desc_sram_size;
374 struct napi_struct napi;
375 struct rx_queue rxq[8];
380 int default_tx_ring_size;
381 unsigned long tx_desc_sram_addr;
382 int tx_desc_sram_size;
385 struct tx_queue txq[8];
386 #ifdef MV643XX_ETH_TX_FAST_REFILL
387 int tx_clean_threshold;
392 /* port register accessors **************************************************/
393 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
395 return readl(mp->shared->base + offset);
398 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
400 writel(data, mp->shared->base + offset);
404 /* rxq/txq helper functions *************************************************/
405 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
407 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
410 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
412 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
415 static void rxq_enable(struct rx_queue *rxq)
417 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
418 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
421 static void rxq_disable(struct rx_queue *rxq)
423 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
424 u8 mask = 1 << rxq->index;
426 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
427 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
431 static void txq_reset_hw_ptr(struct tx_queue *txq)
433 struct mv643xx_eth_private *mp = txq_to_mp(txq);
434 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
437 addr = (u32)txq->tx_desc_dma;
438 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
442 static void txq_enable(struct tx_queue *txq)
444 struct mv643xx_eth_private *mp = txq_to_mp(txq);
445 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
448 static void txq_disable(struct tx_queue *txq)
450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
451 u8 mask = 1 << txq->index;
453 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
454 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
458 static void __txq_maybe_wake(struct tx_queue *txq)
460 struct mv643xx_eth_private *mp = txq_to_mp(txq);
463 * netif_{stop,wake}_queue() flow control only applies to
466 BUG_ON(txq->index != mp->txq_primary);
468 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
469 netif_wake_queue(mp->dev);
473 /* rx ***********************************************************************/
474 static void txq_reclaim(struct tx_queue *txq, int force);
476 static void rxq_refill(struct rx_queue *rxq)
478 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
481 spin_lock_irqsave(&mp->lock, flags);
483 while (rxq->rx_desc_count < rxq->rx_ring_size) {
490 * Reserve 2+14 bytes for an ethernet header (the
491 * hardware automatically prepends 2 bytes of dummy
492 * data to each received packet), 16 bytes for up to
493 * four VLAN tags, and 4 bytes for the trailing FCS
496 skb_size = mp->dev->mtu + 36;
499 * Make sure that the skb size is a multiple of 8
500 * bytes, as the lower three bits of the receive
501 * descriptor's buffer size field are ignored by
504 skb_size = (skb_size + 7) & ~7;
506 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
510 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
512 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
514 rxq->rx_desc_count++;
516 rx = rxq->rx_used_desc++;
517 if (rxq->rx_used_desc == rxq->rx_ring_size)
518 rxq->rx_used_desc = 0;
520 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
521 skb_size, DMA_FROM_DEVICE);
522 rxq->rx_desc_area[rx].buf_size = skb_size;
523 rxq->rx_skb[rx] = skb;
525 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
530 * The hardware automatically prepends 2 bytes of
531 * dummy data to each received packet, so that the
532 * IP header ends up 16-byte aligned.
537 if (rxq->rx_desc_count != rxq->rx_ring_size)
538 mod_timer(&rxq->rx_oom, jiffies + (HZ / 10));
540 spin_unlock_irqrestore(&mp->lock, flags);
543 static inline void rxq_refill_timer_wrapper(unsigned long data)
545 rxq_refill((struct rx_queue *)data);
548 static int rxq_process(struct rx_queue *rxq, int budget)
550 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
551 struct net_device_stats *stats = &mp->dev->stats;
555 while (rx < budget && rxq->rx_desc_count) {
556 struct rx_desc *rx_desc;
557 unsigned int cmd_sts;
561 spin_lock_irqsave(&mp->lock, flags);
563 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
565 cmd_sts = rx_desc->cmd_sts;
566 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
567 spin_unlock_irqrestore(&mp->lock, flags);
572 skb = rxq->rx_skb[rxq->rx_curr_desc];
573 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
576 if (rxq->rx_curr_desc == rxq->rx_ring_size)
577 rxq->rx_curr_desc = 0;
579 spin_unlock_irqrestore(&mp->lock, flags);
581 dma_unmap_single(NULL, rx_desc->buf_ptr,
582 rx_desc->buf_size, DMA_FROM_DEVICE);
583 rxq->rx_desc_count--;
589 * Note that the descriptor byte count includes 2 dummy
590 * bytes automatically inserted by the hardware at the
591 * start of the packet (which we don't count), and a 4
592 * byte CRC at the end of the packet (which we do count).
595 stats->rx_bytes += rx_desc->byte_cnt - 2;
598 * In case we received a packet without first / last bits
599 * on, or the error summary bit is set, the packet needs
602 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
603 (RX_FIRST_DESC | RX_LAST_DESC))
604 || (cmd_sts & ERROR_SUMMARY)) {
607 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
608 (RX_FIRST_DESC | RX_LAST_DESC)) {
610 dev_printk(KERN_ERR, &mp->dev->dev,
611 "received packet spanning "
612 "multiple descriptors\n");
615 if (cmd_sts & ERROR_SUMMARY)
621 * The -4 is for the CRC in the trailer of the
624 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
626 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
627 skb->ip_summed = CHECKSUM_UNNECESSARY;
629 (cmd_sts & 0x0007fff8) >> 3);
631 skb->protocol = eth_type_trans(skb, mp->dev);
632 netif_receive_skb(skb);
635 mp->dev->last_rx = jiffies;
643 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
645 struct mv643xx_eth_private *mp;
649 mp = container_of(napi, struct mv643xx_eth_private, napi);
651 #ifdef MV643XX_ETH_TX_FAST_REFILL
652 if (++mp->tx_clean_threshold > 5) {
653 mp->tx_clean_threshold = 0;
654 for (i = 0; i < 8; i++)
655 if (mp->txq_mask & (1 << i))
656 txq_reclaim(mp->txq + i, 0);
658 if (netif_carrier_ok(mp->dev)) {
659 spin_lock_irq(&mp->lock);
660 __txq_maybe_wake(mp->txq + mp->txq_primary);
661 spin_unlock_irq(&mp->lock);
667 for (i = 7; rx < budget && i >= 0; i--)
668 if (mp->rxq_mask & (1 << i))
669 rx += rxq_process(mp->rxq + i, budget - rx);
672 netif_rx_complete(mp->dev, napi);
673 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
680 /* tx ***********************************************************************/
681 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
685 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
686 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
687 if (fragp->size <= 8 && fragp->page_offset & 7)
694 static int txq_alloc_desc_index(struct tx_queue *txq)
698 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
700 tx_desc_curr = txq->tx_curr_desc++;
701 if (txq->tx_curr_desc == txq->tx_ring_size)
702 txq->tx_curr_desc = 0;
704 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
709 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
711 int nr_frags = skb_shinfo(skb)->nr_frags;
714 for (frag = 0; frag < nr_frags; frag++) {
715 skb_frag_t *this_frag;
717 struct tx_desc *desc;
719 this_frag = &skb_shinfo(skb)->frags[frag];
720 tx_index = txq_alloc_desc_index(txq);
721 desc = &txq->tx_desc_area[tx_index];
724 * The last fragment will generate an interrupt
725 * which will free the skb on TX completion.
727 if (frag == nr_frags - 1) {
728 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
729 ZERO_PADDING | TX_LAST_DESC |
731 txq->tx_skb[tx_index] = skb;
733 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
734 txq->tx_skb[tx_index] = NULL;
738 desc->byte_cnt = this_frag->size;
739 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
740 this_frag->page_offset,
746 static inline __be16 sum16_as_be(__sum16 sum)
748 return (__force __be16)sum;
751 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
753 struct mv643xx_eth_private *mp = txq_to_mp(txq);
754 int nr_frags = skb_shinfo(skb)->nr_frags;
756 struct tx_desc *desc;
760 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
762 tx_index = txq_alloc_desc_index(txq);
763 desc = &txq->tx_desc_area[tx_index];
766 txq_submit_frag_skb(txq, skb);
768 length = skb_headlen(skb);
769 txq->tx_skb[tx_index] = NULL;
771 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
773 txq->tx_skb[tx_index] = skb;
776 desc->byte_cnt = length;
777 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
779 if (skb->ip_summed == CHECKSUM_PARTIAL) {
782 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
783 skb->protocol != htons(ETH_P_8021Q));
785 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
787 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
789 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
790 switch (mac_hdr_len - ETH_HLEN) {
794 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
797 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
800 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
801 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
805 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
806 "mac header length is %d?!\n", mac_hdr_len);
810 switch (ip_hdr(skb)->protocol) {
812 cmd_sts |= UDP_FRAME;
813 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
816 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
822 /* Errata BTS #50, IHL must be 5 if no HW checksum */
823 cmd_sts |= 5 << TX_IHL_SHIFT;
827 /* ensure all other descriptors are written before first cmd_sts */
829 desc->cmd_sts = cmd_sts;
831 /* clear TX_END interrupt status */
832 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
833 rdl(mp, INT_CAUSE(mp->port_num));
835 /* ensure all descriptors are written before poking hardware */
839 txq->tx_desc_count += nr_frags + 1;
842 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
844 struct mv643xx_eth_private *mp = netdev_priv(dev);
845 struct net_device_stats *stats = &dev->stats;
846 struct tx_queue *txq;
849 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
851 dev_printk(KERN_DEBUG, &dev->dev,
852 "failed to linearize skb with tiny "
853 "unaligned fragment\n");
854 return NETDEV_TX_BUSY;
857 spin_lock_irqsave(&mp->lock, flags);
859 txq = mp->txq + mp->txq_primary;
861 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
862 spin_unlock_irqrestore(&mp->lock, flags);
863 if (txq->index == mp->txq_primary && net_ratelimit())
864 dev_printk(KERN_ERR, &dev->dev,
865 "primary tx queue full?!\n");
870 txq_submit_skb(txq, skb);
871 stats->tx_bytes += skb->len;
873 dev->trans_start = jiffies;
875 if (txq->index == mp->txq_primary) {
878 entries_left = txq->tx_ring_size - txq->tx_desc_count;
879 if (entries_left < MAX_DESCS_PER_SKB)
880 netif_stop_queue(dev);
883 spin_unlock_irqrestore(&mp->lock, flags);
889 /* tx rate control **********************************************************/
891 * Set total maximum TX rate (shared by all TX queues for this port)
892 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
894 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
900 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
901 if (token_rate > 1023)
904 mtu = (mp->dev->mtu + 255) >> 8;
908 bucket_size = (burst + 255) >> 8;
909 if (bucket_size > 65535)
912 if (mp->shared->tx_bw_control_moved) {
913 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
914 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
915 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
917 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
918 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
919 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
923 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
925 struct mv643xx_eth_private *mp = txq_to_mp(txq);
929 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
930 if (token_rate > 1023)
933 bucket_size = (burst + 255) >> 8;
934 if (bucket_size > 65535)
937 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
938 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
939 (bucket_size << 10) | token_rate);
942 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
944 struct mv643xx_eth_private *mp = txq_to_mp(txq);
949 * Turn on fixed priority mode.
951 if (mp->shared->tx_bw_control_moved)
952 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
954 off = TXQ_FIX_PRIO_CONF(mp->port_num);
957 val |= 1 << txq->index;
961 static void txq_set_wrr(struct tx_queue *txq, int weight)
963 struct mv643xx_eth_private *mp = txq_to_mp(txq);
968 * Turn off fixed priority mode.
970 if (mp->shared->tx_bw_control_moved)
971 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
973 off = TXQ_FIX_PRIO_CONF(mp->port_num);
976 val &= ~(1 << txq->index);
980 * Configure WRR weight for this queue.
982 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
985 val = (val & ~0xff) | (weight & 0xff);
990 /* mii management interface *************************************************/
991 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
993 struct mv643xx_eth_shared_private *msp = dev_id;
995 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
996 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
997 wake_up(&msp->smi_busy_wait);
1004 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1006 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1009 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1011 if (msp->err_interrupt == NO_IRQ) {
1014 for (i = 0; !smi_is_done(msp); i++) {
1023 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1024 msecs_to_jiffies(100)))
1030 static int smi_reg_read(struct mv643xx_eth_private *mp,
1031 unsigned int addr, unsigned int reg)
1033 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1034 void __iomem *smi_reg = msp->base + SMI_REG;
1037 mutex_lock(&msp->phy_lock);
1039 if (smi_wait_ready(msp)) {
1040 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1045 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1047 if (smi_wait_ready(msp)) {
1048 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1053 ret = readl(smi_reg);
1054 if (!(ret & SMI_READ_VALID)) {
1055 printk("%s: SMI bus read not valid\n", mp->dev->name);
1063 mutex_unlock(&msp->phy_lock);
1068 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1069 unsigned int reg, unsigned int value)
1071 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1072 void __iomem *smi_reg = msp->base + SMI_REG;
1074 mutex_lock(&msp->phy_lock);
1076 if (smi_wait_ready(msp)) {
1077 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1078 mutex_unlock(&msp->phy_lock);
1082 writel(SMI_OPCODE_WRITE | (reg << 21) |
1083 (addr << 16) | (value & 0xffff), smi_reg);
1085 mutex_unlock(&msp->phy_lock);
1091 /* mib counters *************************************************************/
1092 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1094 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1097 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1101 for (i = 0; i < 0x80; i += 4)
1105 static void mib_counters_update(struct mv643xx_eth_private *mp)
1107 struct mib_counters *p = &mp->mib_counters;
1109 p->good_octets_received += mib_read(mp, 0x00);
1110 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1111 p->bad_octets_received += mib_read(mp, 0x08);
1112 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1113 p->good_frames_received += mib_read(mp, 0x10);
1114 p->bad_frames_received += mib_read(mp, 0x14);
1115 p->broadcast_frames_received += mib_read(mp, 0x18);
1116 p->multicast_frames_received += mib_read(mp, 0x1c);
1117 p->frames_64_octets += mib_read(mp, 0x20);
1118 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1119 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1120 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1121 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1122 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1123 p->good_octets_sent += mib_read(mp, 0x38);
1124 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1125 p->good_frames_sent += mib_read(mp, 0x40);
1126 p->excessive_collision += mib_read(mp, 0x44);
1127 p->multicast_frames_sent += mib_read(mp, 0x48);
1128 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1129 p->unrec_mac_control_received += mib_read(mp, 0x50);
1130 p->fc_sent += mib_read(mp, 0x54);
1131 p->good_fc_received += mib_read(mp, 0x58);
1132 p->bad_fc_received += mib_read(mp, 0x5c);
1133 p->undersize_received += mib_read(mp, 0x60);
1134 p->fragments_received += mib_read(mp, 0x64);
1135 p->oversize_received += mib_read(mp, 0x68);
1136 p->jabber_received += mib_read(mp, 0x6c);
1137 p->mac_receive_error += mib_read(mp, 0x70);
1138 p->bad_crc_event += mib_read(mp, 0x74);
1139 p->collision += mib_read(mp, 0x78);
1140 p->late_collision += mib_read(mp, 0x7c);
1144 /* ethtool ******************************************************************/
1145 struct mv643xx_eth_stats {
1146 char stat_string[ETH_GSTRING_LEN];
1153 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1154 offsetof(struct net_device, stats.m), -1 }
1156 #define MIBSTAT(m) \
1157 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1158 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1160 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1169 MIBSTAT(good_octets_received),
1170 MIBSTAT(bad_octets_received),
1171 MIBSTAT(internal_mac_transmit_err),
1172 MIBSTAT(good_frames_received),
1173 MIBSTAT(bad_frames_received),
1174 MIBSTAT(broadcast_frames_received),
1175 MIBSTAT(multicast_frames_received),
1176 MIBSTAT(frames_64_octets),
1177 MIBSTAT(frames_65_to_127_octets),
1178 MIBSTAT(frames_128_to_255_octets),
1179 MIBSTAT(frames_256_to_511_octets),
1180 MIBSTAT(frames_512_to_1023_octets),
1181 MIBSTAT(frames_1024_to_max_octets),
1182 MIBSTAT(good_octets_sent),
1183 MIBSTAT(good_frames_sent),
1184 MIBSTAT(excessive_collision),
1185 MIBSTAT(multicast_frames_sent),
1186 MIBSTAT(broadcast_frames_sent),
1187 MIBSTAT(unrec_mac_control_received),
1189 MIBSTAT(good_fc_received),
1190 MIBSTAT(bad_fc_received),
1191 MIBSTAT(undersize_received),
1192 MIBSTAT(fragments_received),
1193 MIBSTAT(oversize_received),
1194 MIBSTAT(jabber_received),
1195 MIBSTAT(mac_receive_error),
1196 MIBSTAT(bad_crc_event),
1198 MIBSTAT(late_collision),
1201 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1203 struct mv643xx_eth_private *mp = netdev_priv(dev);
1206 err = mii_ethtool_gset(&mp->mii, cmd);
1209 * The MAC does not support 1000baseT_Half.
1211 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1212 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1217 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1219 struct mv643xx_eth_private *mp = netdev_priv(dev);
1222 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1224 cmd->supported = SUPPORTED_MII;
1225 cmd->advertising = ADVERTISED_MII;
1226 switch (port_status & PORT_SPEED_MASK) {
1228 cmd->speed = SPEED_10;
1230 case PORT_SPEED_100:
1231 cmd->speed = SPEED_100;
1233 case PORT_SPEED_1000:
1234 cmd->speed = SPEED_1000;
1240 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1241 cmd->port = PORT_MII;
1242 cmd->phy_address = 0;
1243 cmd->transceiver = XCVR_INTERNAL;
1244 cmd->autoneg = AUTONEG_DISABLE;
1251 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1253 struct mv643xx_eth_private *mp = netdev_priv(dev);
1256 * The MAC does not support 1000baseT_Half.
1258 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1260 return mii_ethtool_sset(&mp->mii, cmd);
1263 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1268 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1269 struct ethtool_drvinfo *drvinfo)
1271 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1272 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1273 strncpy(drvinfo->fw_version, "N/A", 32);
1274 strncpy(drvinfo->bus_info, "platform", 32);
1275 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1278 static int mv643xx_eth_nway_reset(struct net_device *dev)
1280 struct mv643xx_eth_private *mp = netdev_priv(dev);
1282 return mii_nway_restart(&mp->mii);
1285 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1290 static u32 mv643xx_eth_get_link(struct net_device *dev)
1292 struct mv643xx_eth_private *mp = netdev_priv(dev);
1294 return mii_link_ok(&mp->mii);
1297 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1302 static void mv643xx_eth_get_strings(struct net_device *dev,
1303 uint32_t stringset, uint8_t *data)
1307 if (stringset == ETH_SS_STATS) {
1308 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1309 memcpy(data + i * ETH_GSTRING_LEN,
1310 mv643xx_eth_stats[i].stat_string,
1316 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1317 struct ethtool_stats *stats,
1320 struct mv643xx_eth_private *mp = netdev_priv(dev);
1323 mib_counters_update(mp);
1325 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1326 const struct mv643xx_eth_stats *stat;
1329 stat = mv643xx_eth_stats + i;
1331 if (stat->netdev_off >= 0)
1332 p = ((void *)mp->dev) + stat->netdev_off;
1334 p = ((void *)mp) + stat->mp_off;
1336 data[i] = (stat->sizeof_stat == 8) ?
1337 *(uint64_t *)p : *(uint32_t *)p;
1341 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1343 if (sset == ETH_SS_STATS)
1344 return ARRAY_SIZE(mv643xx_eth_stats);
1349 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1350 .get_settings = mv643xx_eth_get_settings,
1351 .set_settings = mv643xx_eth_set_settings,
1352 .get_drvinfo = mv643xx_eth_get_drvinfo,
1353 .nway_reset = mv643xx_eth_nway_reset,
1354 .get_link = mv643xx_eth_get_link,
1355 .set_sg = ethtool_op_set_sg,
1356 .get_strings = mv643xx_eth_get_strings,
1357 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1358 .get_sset_count = mv643xx_eth_get_sset_count,
1361 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1362 .get_settings = mv643xx_eth_get_settings_phyless,
1363 .set_settings = mv643xx_eth_set_settings_phyless,
1364 .get_drvinfo = mv643xx_eth_get_drvinfo,
1365 .nway_reset = mv643xx_eth_nway_reset_phyless,
1366 .get_link = mv643xx_eth_get_link_phyless,
1367 .set_sg = ethtool_op_set_sg,
1368 .get_strings = mv643xx_eth_get_strings,
1369 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1370 .get_sset_count = mv643xx_eth_get_sset_count,
1374 /* address handling *********************************************************/
1375 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1380 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1381 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1383 addr[0] = (mac_h >> 24) & 0xff;
1384 addr[1] = (mac_h >> 16) & 0xff;
1385 addr[2] = (mac_h >> 8) & 0xff;
1386 addr[3] = mac_h & 0xff;
1387 addr[4] = (mac_l >> 8) & 0xff;
1388 addr[5] = mac_l & 0xff;
1391 static void init_mac_tables(struct mv643xx_eth_private *mp)
1395 for (i = 0; i < 0x100; i += 4) {
1396 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1397 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1400 for (i = 0; i < 0x10; i += 4)
1401 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1404 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1405 int table, unsigned char entry)
1407 unsigned int table_reg;
1409 /* Set "accepts frame bit" at specified table entry */
1410 table_reg = rdl(mp, table + (entry & 0xfc));
1411 table_reg |= 0x01 << (8 * (entry & 3));
1412 wrl(mp, table + (entry & 0xfc), table_reg);
1415 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1421 mac_l = (addr[4] << 8) | addr[5];
1422 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1424 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1425 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1427 table = UNICAST_TABLE(mp->port_num);
1428 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1431 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1433 struct mv643xx_eth_private *mp = netdev_priv(dev);
1435 /* +2 is for the offset of the HW addr type */
1436 memcpy(dev->dev_addr, addr + 2, 6);
1438 init_mac_tables(mp);
1439 uc_addr_set(mp, dev->dev_addr);
1444 static int addr_crc(unsigned char *addr)
1449 for (i = 0; i < 6; i++) {
1452 crc = (crc ^ addr[i]) << 8;
1453 for (j = 7; j >= 0; j--) {
1454 if (crc & (0x100 << j))
1462 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1464 struct mv643xx_eth_private *mp = netdev_priv(dev);
1466 struct dev_addr_list *addr;
1469 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1470 if (dev->flags & IFF_PROMISC)
1471 port_config |= UNICAST_PROMISCUOUS_MODE;
1473 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1474 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1476 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1477 int port_num = mp->port_num;
1478 u32 accept = 0x01010101;
1480 for (i = 0; i < 0x100; i += 4) {
1481 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1482 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1487 for (i = 0; i < 0x100; i += 4) {
1488 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1489 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1492 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1493 u8 *a = addr->da_addr;
1496 if (addr->da_addrlen != 6)
1499 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1500 table = SPECIAL_MCAST_TABLE(mp->port_num);
1501 set_filter_table_entry(mp, table, a[5]);
1503 int crc = addr_crc(a);
1505 table = OTHER_MCAST_TABLE(mp->port_num);
1506 set_filter_table_entry(mp, table, crc);
1512 /* rx/tx queue initialisation ***********************************************/
1513 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1515 struct rx_queue *rxq = mp->rxq + index;
1516 struct rx_desc *rx_desc;
1522 rxq->rx_ring_size = mp->default_rx_ring_size;
1524 rxq->rx_desc_count = 0;
1525 rxq->rx_curr_desc = 0;
1526 rxq->rx_used_desc = 0;
1528 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1530 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1531 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1532 mp->rx_desc_sram_size);
1533 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1535 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1540 if (rxq->rx_desc_area == NULL) {
1541 dev_printk(KERN_ERR, &mp->dev->dev,
1542 "can't allocate rx ring (%d bytes)\n", size);
1545 memset(rxq->rx_desc_area, 0, size);
1547 rxq->rx_desc_area_size = size;
1548 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1550 if (rxq->rx_skb == NULL) {
1551 dev_printk(KERN_ERR, &mp->dev->dev,
1552 "can't allocate rx skb ring\n");
1556 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1557 for (i = 0; i < rxq->rx_ring_size; i++) {
1561 if (nexti == rxq->rx_ring_size)
1564 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1565 nexti * sizeof(struct rx_desc);
1568 init_timer(&rxq->rx_oom);
1569 rxq->rx_oom.data = (unsigned long)rxq;
1570 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1576 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1577 iounmap(rxq->rx_desc_area);
1579 dma_free_coherent(NULL, size,
1587 static void rxq_deinit(struct rx_queue *rxq)
1589 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1594 del_timer_sync(&rxq->rx_oom);
1596 for (i = 0; i < rxq->rx_ring_size; i++) {
1597 if (rxq->rx_skb[i]) {
1598 dev_kfree_skb(rxq->rx_skb[i]);
1599 rxq->rx_desc_count--;
1603 if (rxq->rx_desc_count) {
1604 dev_printk(KERN_ERR, &mp->dev->dev,
1605 "error freeing rx ring -- %d skbs stuck\n",
1606 rxq->rx_desc_count);
1609 if (rxq->index == mp->rxq_primary &&
1610 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1611 iounmap(rxq->rx_desc_area);
1613 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1614 rxq->rx_desc_area, rxq->rx_desc_dma);
1619 static int txq_init(struct mv643xx_eth_private *mp, int index)
1621 struct tx_queue *txq = mp->txq + index;
1622 struct tx_desc *tx_desc;
1628 txq->tx_ring_size = mp->default_tx_ring_size;
1630 txq->tx_desc_count = 0;
1631 txq->tx_curr_desc = 0;
1632 txq->tx_used_desc = 0;
1634 size = txq->tx_ring_size * sizeof(struct tx_desc);
1636 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1637 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1638 mp->tx_desc_sram_size);
1639 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1641 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1646 if (txq->tx_desc_area == NULL) {
1647 dev_printk(KERN_ERR, &mp->dev->dev,
1648 "can't allocate tx ring (%d bytes)\n", size);
1651 memset(txq->tx_desc_area, 0, size);
1653 txq->tx_desc_area_size = size;
1654 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1656 if (txq->tx_skb == NULL) {
1657 dev_printk(KERN_ERR, &mp->dev->dev,
1658 "can't allocate tx skb ring\n");
1662 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1663 for (i = 0; i < txq->tx_ring_size; i++) {
1664 struct tx_desc *txd = tx_desc + i;
1668 if (nexti == txq->tx_ring_size)
1672 txd->next_desc_ptr = txq->tx_desc_dma +
1673 nexti * sizeof(struct tx_desc);
1680 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1681 iounmap(txq->tx_desc_area);
1683 dma_free_coherent(NULL, size,
1691 static void txq_reclaim(struct tx_queue *txq, int force)
1693 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1694 unsigned long flags;
1696 spin_lock_irqsave(&mp->lock, flags);
1697 while (txq->tx_desc_count > 0) {
1699 struct tx_desc *desc;
1701 struct sk_buff *skb;
1705 tx_index = txq->tx_used_desc;
1706 desc = &txq->tx_desc_area[tx_index];
1707 cmd_sts = desc->cmd_sts;
1709 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1712 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1715 txq->tx_used_desc = tx_index + 1;
1716 if (txq->tx_used_desc == txq->tx_ring_size)
1717 txq->tx_used_desc = 0;
1718 txq->tx_desc_count--;
1720 addr = desc->buf_ptr;
1721 count = desc->byte_cnt;
1722 skb = txq->tx_skb[tx_index];
1723 txq->tx_skb[tx_index] = NULL;
1725 if (cmd_sts & ERROR_SUMMARY) {
1726 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1727 mp->dev->stats.tx_errors++;
1731 * Drop mp->lock while we free the skb.
1733 spin_unlock_irqrestore(&mp->lock, flags);
1735 if (cmd_sts & TX_FIRST_DESC)
1736 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1738 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1741 dev_kfree_skb_irq(skb);
1743 spin_lock_irqsave(&mp->lock, flags);
1745 spin_unlock_irqrestore(&mp->lock, flags);
1748 static void txq_deinit(struct tx_queue *txq)
1750 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1753 txq_reclaim(txq, 1);
1755 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1757 if (txq->index == mp->txq_primary &&
1758 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1759 iounmap(txq->tx_desc_area);
1761 dma_free_coherent(NULL, txq->tx_desc_area_size,
1762 txq->tx_desc_area, txq->tx_desc_dma);
1768 /* netdev ops and related ***************************************************/
1769 static void handle_link_event(struct mv643xx_eth_private *mp)
1771 struct net_device *dev = mp->dev;
1777 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1778 if (!(port_status & LINK_UP)) {
1779 if (netif_carrier_ok(dev)) {
1782 printk(KERN_INFO "%s: link down\n", dev->name);
1784 netif_carrier_off(dev);
1785 netif_stop_queue(dev);
1787 for (i = 0; i < 8; i++) {
1788 struct tx_queue *txq = mp->txq + i;
1790 if (mp->txq_mask & (1 << i)) {
1791 txq_reclaim(txq, 1);
1792 txq_reset_hw_ptr(txq);
1799 switch (port_status & PORT_SPEED_MASK) {
1803 case PORT_SPEED_100:
1806 case PORT_SPEED_1000:
1813 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1814 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1816 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1817 "flow control %sabled\n", dev->name,
1818 speed, duplex ? "full" : "half",
1821 if (!netif_carrier_ok(dev)) {
1822 netif_carrier_on(dev);
1823 netif_wake_queue(dev);
1827 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1829 struct net_device *dev = (struct net_device *)dev_id;
1830 struct mv643xx_eth_private *mp = netdev_priv(dev);
1834 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1835 (INT_TX_END | INT_RX | INT_EXT);
1840 if (int_cause & INT_EXT) {
1841 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1842 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1843 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1846 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1847 handle_link_event(mp);
1850 * RxBuffer or RxError set for any of the 8 queues?
1852 if (int_cause & INT_RX) {
1853 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1854 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1855 rdl(mp, INT_MASK(mp->port_num));
1857 netif_rx_schedule(dev, &mp->napi);
1861 * TxBuffer or TxError set for any of the 8 queues?
1863 if (int_cause_ext & INT_EXT_TX) {
1866 for (i = 0; i < 8; i++)
1867 if (mp->txq_mask & (1 << i))
1868 txq_reclaim(mp->txq + i, 0);
1871 * Enough space again in the primary TX queue for a
1874 if (netif_carrier_ok(dev)) {
1875 spin_lock(&mp->lock);
1876 __txq_maybe_wake(mp->txq + mp->txq_primary);
1877 spin_unlock(&mp->lock);
1882 * Any TxEnd interrupts?
1884 if (int_cause & INT_TX_END) {
1887 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1889 spin_lock(&mp->lock);
1890 for (i = 0; i < 8; i++) {
1891 struct tx_queue *txq = mp->txq + i;
1895 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1899 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1900 expected_ptr = (u32)txq->tx_desc_dma +
1901 txq->tx_curr_desc * sizeof(struct tx_desc);
1903 if (hw_desc_ptr != expected_ptr)
1906 spin_unlock(&mp->lock);
1912 static void phy_reset(struct mv643xx_eth_private *mp)
1916 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1921 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1925 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1926 } while (data >= 0 && data & BMCR_RESET);
1929 static void port_start(struct mv643xx_eth_private *mp)
1935 * Perform PHY reset, if there is a PHY.
1937 if (mp->phy_addr != -1) {
1938 struct ethtool_cmd cmd;
1940 mv643xx_eth_get_settings(mp->dev, &cmd);
1942 mv643xx_eth_set_settings(mp->dev, &cmd);
1946 * Configure basic link parameters.
1948 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1950 pscr |= SERIAL_PORT_ENABLE;
1951 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1953 pscr |= DO_NOT_FORCE_LINK_FAIL;
1954 if (mp->phy_addr == -1)
1955 pscr |= FORCE_LINK_PASS;
1956 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1958 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1961 * Configure TX path and queues.
1963 tx_set_rate(mp, 1000000000, 16777216);
1964 for (i = 0; i < 8; i++) {
1965 struct tx_queue *txq = mp->txq + i;
1967 if ((mp->txq_mask & (1 << i)) == 0)
1970 txq_reset_hw_ptr(txq);
1971 txq_set_rate(txq, 1000000000, 16777216);
1972 txq_set_fixed_prio_mode(txq);
1976 * Add configured unicast address to address filter table.
1978 uc_addr_set(mp, mp->dev->dev_addr);
1981 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1982 * frames to RX queue #0.
1984 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1987 * Treat BPDUs as normal multicasts, and disable partition mode.
1989 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1992 * Enable the receive queues.
1994 for (i = 0; i < 8; i++) {
1995 struct rx_queue *rxq = mp->rxq + i;
1996 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1999 if ((mp->rxq_mask & (1 << i)) == 0)
2002 addr = (u32)rxq->rx_desc_dma;
2003 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2010 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2012 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2015 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2016 if (mp->shared->extended_rx_coal_limit) {
2020 val |= (coal & 0x8000) << 10;
2021 val |= (coal & 0x7fff) << 7;
2026 val |= (coal & 0x3fff) << 8;
2028 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2031 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2033 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2037 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2040 static int mv643xx_eth_open(struct net_device *dev)
2042 struct mv643xx_eth_private *mp = netdev_priv(dev);
2046 wrl(mp, INT_CAUSE(mp->port_num), 0);
2047 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2048 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2050 err = request_irq(dev->irq, mv643xx_eth_irq,
2051 IRQF_SHARED, dev->name, dev);
2053 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2057 init_mac_tables(mp);
2059 for (i = 0; i < 8; i++) {
2060 if ((mp->rxq_mask & (1 << i)) == 0)
2063 err = rxq_init(mp, i);
2066 if (mp->rxq_mask & (1 << i))
2067 rxq_deinit(mp->rxq + i);
2071 rxq_refill(mp->rxq + i);
2074 for (i = 0; i < 8; i++) {
2075 if ((mp->txq_mask & (1 << i)) == 0)
2078 err = txq_init(mp, i);
2081 if (mp->txq_mask & (1 << i))
2082 txq_deinit(mp->txq + i);
2087 napi_enable(&mp->napi);
2089 netif_carrier_off(dev);
2090 netif_stop_queue(dev);
2097 wrl(mp, INT_MASK_EXT(mp->port_num),
2098 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2100 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2106 for (i = 0; i < 8; i++)
2107 if (mp->rxq_mask & (1 << i))
2108 rxq_deinit(mp->rxq + i);
2110 free_irq(dev->irq, dev);
2115 static void port_reset(struct mv643xx_eth_private *mp)
2120 for (i = 0; i < 8; i++) {
2121 if (mp->rxq_mask & (1 << i))
2122 rxq_disable(mp->rxq + i);
2123 if (mp->txq_mask & (1 << i))
2124 txq_disable(mp->txq + i);
2128 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2130 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2135 /* Reset the Enable bit in the Configuration Register */
2136 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2137 data &= ~(SERIAL_PORT_ENABLE |
2138 DO_NOT_FORCE_LINK_FAIL |
2140 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2143 static int mv643xx_eth_stop(struct net_device *dev)
2145 struct mv643xx_eth_private *mp = netdev_priv(dev);
2148 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2149 rdl(mp, INT_MASK(mp->port_num));
2151 napi_disable(&mp->napi);
2153 netif_carrier_off(dev);
2154 netif_stop_queue(dev);
2156 free_irq(dev->irq, dev);
2159 mib_counters_update(mp);
2161 for (i = 0; i < 8; i++) {
2162 if (mp->rxq_mask & (1 << i))
2163 rxq_deinit(mp->rxq + i);
2164 if (mp->txq_mask & (1 << i))
2165 txq_deinit(mp->txq + i);
2171 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2173 struct mv643xx_eth_private *mp = netdev_priv(dev);
2175 if (mp->phy_addr != -1)
2176 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2181 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2183 struct mv643xx_eth_private *mp = netdev_priv(dev);
2185 if (new_mtu < 64 || new_mtu > 9500)
2189 tx_set_rate(mp, 1000000000, 16777216);
2191 if (!netif_running(dev))
2195 * Stop and then re-open the interface. This will allocate RX
2196 * skbs of the new MTU.
2197 * There is a possible danger that the open will not succeed,
2198 * due to memory being full.
2200 mv643xx_eth_stop(dev);
2201 if (mv643xx_eth_open(dev)) {
2202 dev_printk(KERN_ERR, &dev->dev,
2203 "fatal error on re-opening device after "
2210 static void tx_timeout_task(struct work_struct *ugly)
2212 struct mv643xx_eth_private *mp;
2214 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2215 if (netif_running(mp->dev)) {
2216 netif_stop_queue(mp->dev);
2221 __txq_maybe_wake(mp->txq + mp->txq_primary);
2225 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2227 struct mv643xx_eth_private *mp = netdev_priv(dev);
2229 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2231 schedule_work(&mp->tx_timeout_task);
2234 #ifdef CONFIG_NET_POLL_CONTROLLER
2235 static void mv643xx_eth_netpoll(struct net_device *dev)
2237 struct mv643xx_eth_private *mp = netdev_priv(dev);
2239 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2240 rdl(mp, INT_MASK(mp->port_num));
2242 mv643xx_eth_irq(dev->irq, dev);
2244 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2248 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2250 struct mv643xx_eth_private *mp = netdev_priv(dev);
2251 return smi_reg_read(mp, addr, reg);
2254 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2256 struct mv643xx_eth_private *mp = netdev_priv(dev);
2257 smi_reg_write(mp, addr, reg, val);
2261 /* platform glue ************************************************************/
2263 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2264 struct mbus_dram_target_info *dram)
2266 void __iomem *base = msp->base;
2271 for (i = 0; i < 6; i++) {
2272 writel(0, base + WINDOW_BASE(i));
2273 writel(0, base + WINDOW_SIZE(i));
2275 writel(0, base + WINDOW_REMAP_HIGH(i));
2281 for (i = 0; i < dram->num_cs; i++) {
2282 struct mbus_dram_window *cs = dram->cs + i;
2284 writel((cs->base & 0xffff0000) |
2285 (cs->mbus_attr << 8) |
2286 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2287 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2289 win_enable &= ~(1 << i);
2290 win_protect |= 3 << (2 * i);
2293 writel(win_enable, base + WINDOW_BAR_ENABLE);
2294 msp->win_protect = win_protect;
2297 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2300 * Check whether we have a 14-bit coal limit field in bits
2301 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2302 * SDMA config register.
2304 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2305 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2306 msp->extended_rx_coal_limit = 1;
2308 msp->extended_rx_coal_limit = 0;
2311 * Check whether the TX rate control registers are in the
2312 * old or the new place.
2314 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2315 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2316 msp->tx_bw_control_moved = 1;
2318 msp->tx_bw_control_moved = 0;
2321 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2323 static int mv643xx_eth_version_printed = 0;
2324 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2325 struct mv643xx_eth_shared_private *msp;
2326 struct resource *res;
2329 if (!mv643xx_eth_version_printed++)
2330 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2331 "driver version %s\n", mv643xx_eth_driver_version);
2334 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2339 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2342 memset(msp, 0, sizeof(*msp));
2344 msp->base = ioremap(res->start, res->end - res->start + 1);
2345 if (msp->base == NULL)
2348 mutex_init(&msp->phy_lock);
2350 msp->err_interrupt = NO_IRQ;
2351 init_waitqueue_head(&msp->smi_busy_wait);
2354 * Check whether the error interrupt is hooked up.
2356 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2360 err = request_irq(res->start, mv643xx_eth_err_irq,
2361 IRQF_SHARED, "mv643xx_eth", msp);
2363 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2364 msp->err_interrupt = res->start;
2369 * (Re-)program MBUS remapping windows if we are asked to.
2371 if (pd != NULL && pd->dram != NULL)
2372 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2375 * Detect hardware parameters.
2377 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2378 infer_hw_params(msp);
2380 platform_set_drvdata(pdev, msp);
2390 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2392 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2394 if (msp->err_interrupt != NO_IRQ)
2395 free_irq(msp->err_interrupt, msp);
2402 static struct platform_driver mv643xx_eth_shared_driver = {
2403 .probe = mv643xx_eth_shared_probe,
2404 .remove = mv643xx_eth_shared_remove,
2406 .name = MV643XX_ETH_SHARED_NAME,
2407 .owner = THIS_MODULE,
2411 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2413 int addr_shift = 5 * mp->port_num;
2416 data = rdl(mp, PHY_ADDR);
2417 data &= ~(0x1f << addr_shift);
2418 data |= (phy_addr & 0x1f) << addr_shift;
2419 wrl(mp, PHY_ADDR, data);
2422 static int phy_addr_get(struct mv643xx_eth_private *mp)
2426 data = rdl(mp, PHY_ADDR);
2428 return (data >> (5 * mp->port_num)) & 0x1f;
2431 static void set_params(struct mv643xx_eth_private *mp,
2432 struct mv643xx_eth_platform_data *pd)
2434 struct net_device *dev = mp->dev;
2436 if (is_valid_ether_addr(pd->mac_addr))
2437 memcpy(dev->dev_addr, pd->mac_addr, 6);
2439 uc_addr_get(mp, dev->dev_addr);
2441 if (pd->phy_addr == -1) {
2442 mp->shared_smi = NULL;
2445 mp->shared_smi = mp->shared;
2446 if (pd->shared_smi != NULL)
2447 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2449 if (pd->force_phy_addr || pd->phy_addr) {
2450 mp->phy_addr = pd->phy_addr & 0x3f;
2451 phy_addr_set(mp, mp->phy_addr);
2453 mp->phy_addr = phy_addr_get(mp);
2457 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2458 if (pd->rx_queue_size)
2459 mp->default_rx_ring_size = pd->rx_queue_size;
2460 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2461 mp->rx_desc_sram_size = pd->rx_sram_size;
2463 if (pd->rx_queue_mask)
2464 mp->rxq_mask = pd->rx_queue_mask;
2466 mp->rxq_mask = 0x01;
2467 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2469 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2470 if (pd->tx_queue_size)
2471 mp->default_tx_ring_size = pd->tx_queue_size;
2472 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2473 mp->tx_desc_sram_size = pd->tx_sram_size;
2475 if (pd->tx_queue_mask)
2476 mp->txq_mask = pd->tx_queue_mask;
2478 mp->txq_mask = 0x01;
2479 mp->txq_primary = fls(mp->txq_mask) - 1;
2482 static int phy_detect(struct mv643xx_eth_private *mp)
2487 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2491 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2494 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2498 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2501 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2506 static int phy_init(struct mv643xx_eth_private *mp,
2507 struct mv643xx_eth_platform_data *pd)
2509 struct ethtool_cmd cmd;
2512 err = phy_detect(mp);
2514 dev_printk(KERN_INFO, &mp->dev->dev,
2515 "no PHY detected at addr %d\n", mp->phy_addr);
2520 mp->mii.phy_id = mp->phy_addr;
2521 mp->mii.phy_id_mask = 0x3f;
2522 mp->mii.reg_num_mask = 0x1f;
2523 mp->mii.dev = mp->dev;
2524 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2525 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2527 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2529 memset(&cmd, 0, sizeof(cmd));
2531 cmd.port = PORT_MII;
2532 cmd.transceiver = XCVR_INTERNAL;
2533 cmd.phy_address = mp->phy_addr;
2534 if (pd->speed == 0) {
2535 cmd.autoneg = AUTONEG_ENABLE;
2536 cmd.speed = SPEED_100;
2537 cmd.advertising = ADVERTISED_10baseT_Half |
2538 ADVERTISED_10baseT_Full |
2539 ADVERTISED_100baseT_Half |
2540 ADVERTISED_100baseT_Full;
2541 if (mp->mii.supports_gmii)
2542 cmd.advertising |= ADVERTISED_1000baseT_Full;
2544 cmd.autoneg = AUTONEG_DISABLE;
2545 cmd.speed = pd->speed;
2546 cmd.duplex = pd->duplex;
2549 mv643xx_eth_set_settings(mp->dev, &cmd);
2554 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2558 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2559 if (pscr & SERIAL_PORT_ENABLE) {
2560 pscr &= ~SERIAL_PORT_ENABLE;
2561 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2564 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2565 if (mp->phy_addr == -1) {
2566 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2567 if (speed == SPEED_1000)
2568 pscr |= SET_GMII_SPEED_TO_1000;
2569 else if (speed == SPEED_100)
2570 pscr |= SET_MII_SPEED_TO_100;
2572 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2574 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2575 if (duplex == DUPLEX_FULL)
2576 pscr |= SET_FULL_DUPLEX_MODE;
2579 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2582 static int mv643xx_eth_probe(struct platform_device *pdev)
2584 struct mv643xx_eth_platform_data *pd;
2585 struct mv643xx_eth_private *mp;
2586 struct net_device *dev;
2587 struct resource *res;
2588 DECLARE_MAC_BUF(mac);
2591 pd = pdev->dev.platform_data;
2593 dev_printk(KERN_ERR, &pdev->dev,
2594 "no mv643xx_eth_platform_data\n");
2598 if (pd->shared == NULL) {
2599 dev_printk(KERN_ERR, &pdev->dev,
2600 "no mv643xx_eth_platform_data->shared\n");
2604 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2608 mp = netdev_priv(dev);
2609 platform_set_drvdata(pdev, mp);
2611 mp->shared = platform_get_drvdata(pd->shared);
2612 mp->port_num = pd->port_number;
2616 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2620 spin_lock_init(&mp->lock);
2622 mib_counters_clear(mp);
2623 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2625 if (mp->phy_addr != -1) {
2626 err = phy_init(mp, pd);
2630 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2632 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2634 init_pscr(mp, pd->speed, pd->duplex);
2637 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2639 dev->irq = res->start;
2641 dev->hard_start_xmit = mv643xx_eth_xmit;
2642 dev->open = mv643xx_eth_open;
2643 dev->stop = mv643xx_eth_stop;
2644 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2645 dev->set_mac_address = mv643xx_eth_set_mac_address;
2646 dev->do_ioctl = mv643xx_eth_ioctl;
2647 dev->change_mtu = mv643xx_eth_change_mtu;
2648 dev->tx_timeout = mv643xx_eth_tx_timeout;
2649 #ifdef CONFIG_NET_POLL_CONTROLLER
2650 dev->poll_controller = mv643xx_eth_netpoll;
2652 dev->watchdog_timeo = 2 * HZ;
2655 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2657 * Zero copy can only work if we use Discovery II memory. Else, we will
2658 * have to map the buffers to ISA memory which is only 16 MB
2660 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2661 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2664 SET_NETDEV_DEV(dev, &pdev->dev);
2666 if (mp->shared->win_protect)
2667 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2669 err = register_netdev(dev);
2673 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2674 mp->port_num, print_mac(mac, dev->dev_addr));
2676 if (dev->features & NETIF_F_SG)
2677 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2679 if (dev->features & NETIF_F_IP_CSUM)
2680 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2682 if (mp->tx_desc_sram_size > 0)
2683 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2693 static int mv643xx_eth_remove(struct platform_device *pdev)
2695 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2697 unregister_netdev(mp->dev);
2698 flush_scheduled_work();
2699 free_netdev(mp->dev);
2701 platform_set_drvdata(pdev, NULL);
2706 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2708 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2710 /* Mask all interrupts on ethernet port */
2711 wrl(mp, INT_MASK(mp->port_num), 0);
2712 rdl(mp, INT_MASK(mp->port_num));
2714 if (netif_running(mp->dev))
2718 static struct platform_driver mv643xx_eth_driver = {
2719 .probe = mv643xx_eth_probe,
2720 .remove = mv643xx_eth_remove,
2721 .shutdown = mv643xx_eth_shutdown,
2723 .name = MV643XX_ETH_NAME,
2724 .owner = THIS_MODULE,
2728 static int __init mv643xx_eth_init_module(void)
2732 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2734 rc = platform_driver_register(&mv643xx_eth_driver);
2736 platform_driver_unregister(&mv643xx_eth_shared_driver);
2741 module_init(mv643xx_eth_init_module);
2743 static void __exit mv643xx_eth_cleanup_module(void)
2745 platform_driver_unregister(&mv643xx_eth_driver);
2746 platform_driver_unregister(&mv643xx_eth_shared_driver);
2748 module_exit(mv643xx_eth_cleanup_module);
2750 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2751 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2752 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2753 MODULE_LICENSE("GPL");
2754 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2755 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);