1 #ifndef __MYRI10GE_MCP_H__
2 #define __MYRI10GE_MCP_H__
4 #define MXGEFW_VERSION_MAJOR 1
5 #define MXGEFW_VERSION_MINOR 4
22 u32 data0; /* will be low portion if data > 32 bits */
24 u32 data1; /* will be high portion if data > 32 bits */
25 u32 data2; /* currently unused.. */
27 struct mcp_dma_addr response_addr;
33 struct mcp_cmd_response {
39 * flags used in mcp_kreq_ether_send_t:
41 * The SMALL flag is only needed in the first segment. It is raised
42 * for packets that are total less or equal 512 bytes.
44 * The CKSUM flag must be set in all segments.
46 * The PADDED flags is set if the packet needs to be padded, and it
47 * must be set for all segments.
49 * The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
50 * length of all previous segments was odd.
53 #define MXGEFW_FLAGS_SMALL 0x1
54 #define MXGEFW_FLAGS_TSO_HDR 0x1
55 #define MXGEFW_FLAGS_FIRST 0x2
56 #define MXGEFW_FLAGS_ALIGN_ODD 0x4
57 #define MXGEFW_FLAGS_CKSUM 0x8
58 #define MXGEFW_FLAGS_TSO_LAST 0x8
59 #define MXGEFW_FLAGS_NO_TSO 0x10
60 #define MXGEFW_FLAGS_TSO_CHOP 0x10
61 #define MXGEFW_FLAGS_TSO_PLD 0x20
63 #define MXGEFW_SEND_SMALL_SIZE 1520
64 #define MXGEFW_MAX_MTU 9400
66 union mcp_pso_or_cumlen {
67 u16 pseudo_hdr_offset;
71 #define MXGEFW_MAX_SEND_DESC 12
75 struct mcp_kreq_ether_send {
78 u16 pseudo_hdr_offset;
82 u8 cksum_offset; /* where to start computing cksum */
83 u8 flags; /* as defined above */
87 struct mcp_kreq_ether_recv {
94 #define MXGEFW_BOOT_HANDOFF 0xfc0000
95 #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0
97 #define MXGEFW_ETH_CMD 0xf80000
98 #define MXGEFW_ETH_SEND_4 0x200000
99 #define MXGEFW_ETH_SEND_1 0x240000
100 #define MXGEFW_ETH_SEND_2 0x280000
101 #define MXGEFW_ETH_SEND_3 0x2c0000
102 #define MXGEFW_ETH_RECV_SMALL 0x300000
103 #define MXGEFW_ETH_RECV_BIG 0x340000
105 #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
106 #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
108 enum myri10ge_mcp_cmd_type {
110 /* Reset the mcp, it is left in a safe state, waiting
111 * for the driver to set all its parameters */
114 /* get the version number of the current firmware..
115 * (may be available in the eeprom strings..? */
116 MXGEFW_GET_MCP_VERSION,
118 /* Parameters which must be set by the driver before it can
119 * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
120 * MXGEFW_CMD_RESET is issued */
122 MXGEFW_CMD_SET_INTRQ_DMA,
123 MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */
124 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */
126 /* Parameters which refer to lanai SRAM addresses where the
127 * driver must issue PIO writes for various things */
129 MXGEFW_CMD_GET_SEND_OFFSET,
130 MXGEFW_CMD_GET_SMALL_RX_OFFSET,
131 MXGEFW_CMD_GET_BIG_RX_OFFSET,
132 MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
133 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
135 /* Parameters which refer to rings stored on the MCP,
136 * and whose size is controlled by the mcp */
138 MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */
139 MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */
141 /* Parameters which refer to rings stored in the host,
142 * and whose size is controlled by the host. Note that
143 * all must be physically contiguous and must contain
144 * a power of 2 number of entries. */
146 MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */
148 /* command to bring ethernet interface up. Above parameters
149 * (plus mtu & mac address) must have been exchanged prior
150 * to issuing this command */
151 MXGEFW_CMD_ETHERNET_UP,
153 /* command to bring ethernet interface down. No further sends
154 * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
155 * is issued, and all interrupt queues must be flushed prior
156 * to ack'ing this command */
158 MXGEFW_CMD_ETHERNET_DOWN,
160 /* commands the driver may issue live, without resetting
161 * the nic. Note that increasing the mtu "live" should
162 * only be done if the driver has already supplied buffers
163 * sufficiently large to handle the new mtu. Decreasing
164 * the mtu live is safe */
167 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */
168 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */
169 MXGEFW_CMD_SET_STATS_DMA,
171 MXGEFW_ENABLE_PROMISC,
172 MXGEFW_DISABLE_PROMISC,
173 MXGEFW_SET_MAC_ADDRESS,
175 MXGEFW_ENABLE_FLOW_CONTROL,
176 MXGEFW_DISABLE_FLOW_CONTROL,
179 * data0,data1 = DMA address
180 * data2 = RDMA length (MSH), WDMA length (LSH)
181 * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
186 enum myri10ge_mcp_cmd_status {
189 MXGEFW_CMD_ERROR_RANGE,
190 MXGEFW_CMD_ERROR_BUSY,
191 MXGEFW_CMD_ERROR_EMPTY,
192 MXGEFW_CMD_ERROR_CLOSED,
193 MXGEFW_CMD_ERROR_HASH_ERROR,
194 MXGEFW_CMD_ERROR_BAD_PORT,
195 MXGEFW_CMD_ERROR_RESOURCES
199 struct mcp_irq_data {
203 u32 dropped_link_overflow;
204 u32 dropped_link_error_or_filtered;
207 u32 dropped_no_small_buffer;
208 u32 dropped_no_big_buffer;
209 u32 rdma_tags_available;
217 #endif /* __MYRI10GE_MCP_H__ */