2 * Copyright (C) 2006-2007 PA Semi, Inc
4 * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <asm/dma-mapping.h>
30 #include <linux/skbuff.h>
33 #include <linux/tcp.h>
34 #include <net/checksum.h>
38 #include "pasemi_mac.h"
43 * - Get rid of pci_{read,write}_config(), map registers with ioremap
48 * - Other performance improvements
52 /* Must be a power of two */
53 #define RX_RING_SIZE 512
54 #define TX_RING_SIZE 512
56 #define TX_DESC(mac, num) ((mac)->tx->desc[(num) & (TX_RING_SIZE-1)])
57 #define TX_DESC_INFO(mac, num) ((mac)->tx->desc_info[(num) & (TX_RING_SIZE-1)])
58 #define RX_DESC(mac, num) ((mac)->rx->desc[(num) & (RX_RING_SIZE-1)])
59 #define RX_DESC_INFO(mac, num) ((mac)->rx->desc_info[(num) & (RX_RING_SIZE-1)])
60 #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
62 #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
64 static struct pasdma_status *dma_status;
66 static int pasemi_get_mac_addr(struct pasemi_mac *mac)
68 struct pci_dev *pdev = mac->pdev;
69 struct device_node *dn = pci_device_to_OF_node(pdev);
75 "No device node for mac, not configuring\n");
79 maddr = get_property(dn, "mac-address", NULL);
82 "no mac address in device tree, not configuring\n");
86 if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
87 &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
89 "can't parse mac address, not configuring\n");
93 memcpy(mac->mac_addr, addr, sizeof(addr));
97 static int pasemi_mac_setup_rx_resources(struct net_device *dev)
99 struct pasemi_mac_rxring *ring;
100 struct pasemi_mac *mac = netdev_priv(dev);
101 int chan_id = mac->dma_rxch;
103 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
108 spin_lock_init(&ring->lock);
110 ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
111 RX_RING_SIZE, GFP_KERNEL);
113 if (!ring->desc_info)
116 /* Allocate descriptors */
117 ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
119 sizeof(struct pas_dma_xct_descr),
120 &ring->dma, GFP_KERNEL);
125 memset(ring->desc, 0, RX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
127 ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
128 RX_RING_SIZE * sizeof(u64),
129 &ring->buf_dma, GFP_KERNEL);
133 memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
135 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id),
136 PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
138 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id),
139 PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
140 PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
142 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id),
143 PAS_DMA_RXCHAN_CFG_HBU(1));
145 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if),
146 PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
148 pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if),
149 PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
150 PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
152 ring->next_to_fill = 0;
153 ring->next_to_clean = 0;
155 snprintf(ring->irq_name, sizeof(ring->irq_name),
162 dma_free_coherent(&mac->dma_pdev->dev,
163 RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
164 mac->rx->desc, mac->rx->dma);
166 kfree(ring->desc_info);
174 static int pasemi_mac_setup_tx_resources(struct net_device *dev)
176 struct pasemi_mac *mac = netdev_priv(dev);
178 int chan_id = mac->dma_txch;
179 struct pasemi_mac_txring *ring;
181 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
185 spin_lock_init(&ring->lock);
187 ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
188 TX_RING_SIZE, GFP_KERNEL);
189 if (!ring->desc_info)
192 /* Allocate descriptors */
193 ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
195 sizeof(struct pas_dma_xct_descr),
196 &ring->dma, GFP_KERNEL);
200 memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
202 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id),
203 PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
204 val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
205 val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2);
207 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val);
209 pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id),
210 PAS_DMA_TXCHAN_CFG_TY_IFACE |
211 PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
212 PAS_DMA_TXCHAN_CFG_UP |
213 PAS_DMA_TXCHAN_CFG_WT(2));
215 ring->next_to_use = 0;
216 ring->next_to_clean = 0;
218 snprintf(ring->irq_name, sizeof(ring->irq_name),
225 kfree(ring->desc_info);
232 static void pasemi_mac_free_tx_resources(struct net_device *dev)
234 struct pasemi_mac *mac = netdev_priv(dev);
236 struct pasemi_mac_buffer *info;
237 struct pas_dma_xct_descr *dp;
239 for (i = 0; i < TX_RING_SIZE; i++) {
240 info = &TX_DESC_INFO(mac, i);
241 dp = &TX_DESC(mac, i);
244 pci_unmap_single(mac->dma_pdev,
248 dev_kfree_skb_any(info->skb);
257 dma_free_coherent(&mac->dma_pdev->dev,
258 TX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
259 mac->tx->desc, mac->tx->dma);
261 kfree(mac->tx->desc_info);
266 static void pasemi_mac_free_rx_resources(struct net_device *dev)
268 struct pasemi_mac *mac = netdev_priv(dev);
270 struct pasemi_mac_buffer *info;
271 struct pas_dma_xct_descr *dp;
273 for (i = 0; i < RX_RING_SIZE; i++) {
274 info = &RX_DESC_INFO(mac, i);
275 dp = &RX_DESC(mac, i);
278 pci_unmap_single(mac->dma_pdev,
282 dev_kfree_skb_any(info->skb);
291 dma_free_coherent(&mac->dma_pdev->dev,
292 RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
293 mac->rx->desc, mac->rx->dma);
295 dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
296 mac->rx->buffers, mac->rx->buf_dma);
298 kfree(mac->rx->desc_info);
303 static void pasemi_mac_replenish_rx_ring(struct net_device *dev)
305 struct pasemi_mac *mac = netdev_priv(dev);
307 int start = mac->rx->next_to_fill;
308 unsigned int limit, count;
310 limit = (mac->rx->next_to_clean + RX_RING_SIZE -
311 mac->rx->next_to_fill) & (RX_RING_SIZE - 1);
313 /* Check to see if we're doing first-time setup */
314 if (unlikely(mac->rx->next_to_clean == 0 && mac->rx->next_to_fill == 0))
315 limit = RX_RING_SIZE;
321 for (count = limit; count; count--) {
322 struct pasemi_mac_buffer *info = &RX_DESC_INFO(mac, i);
323 u64 *buff = &RX_BUFF(mac, i);
327 /* skb might still be in there for recycle on short receives */
331 skb = dev_alloc_skb(BUF_SIZE);
336 dma = pci_map_single(mac->dma_pdev, skb->data, skb->len,
339 if (unlikely(dma_mapping_error(dma))) {
340 dev_kfree_skb_irq(info->skb);
346 *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
352 pci_write_config_dword(mac->dma_pdev,
353 PAS_DMA_RXCHAN_INCR(mac->dma_rxch),
355 pci_write_config_dword(mac->dma_pdev,
356 PAS_DMA_RXINT_INCR(mac->dma_if),
359 mac->rx->next_to_fill += limit - count;
362 static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
364 unsigned int reg, stat;
365 /* Re-enable packet count interrupts: finally
366 * ack the packet count interrupt we got in rx_intr.
369 pci_read_config_dword(mac->iob_pdev,
370 PAS_IOB_DMA_RXCH_STAT(mac->dma_rxch),
373 reg = PAS_IOB_DMA_RXCH_RESET_PCNT(stat & PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
374 | PAS_IOB_DMA_RXCH_RESET_PINTC;
376 pci_write_config_dword(mac->iob_pdev,
377 PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch),
381 static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
383 unsigned int reg, stat;
385 /* Re-enable packet count interrupts */
386 pci_read_config_dword(mac->iob_pdev,
387 PAS_IOB_DMA_TXCH_STAT(mac->dma_txch), &stat);
389 reg = PAS_IOB_DMA_TXCH_RESET_PCNT(stat & PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
390 | PAS_IOB_DMA_TXCH_RESET_PINTC;
392 pci_write_config_dword(mac->iob_pdev,
393 PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
397 static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
401 struct pas_dma_xct_descr *dp;
402 struct pasemi_mac_buffer *info;
408 spin_lock(&mac->rx->lock);
410 n = mac->rx->next_to_clean;
412 for (count = limit; count; count--) {
416 dp = &RX_DESC(mac, n);
419 if (!(macrx & XCT_MACRX_O))
425 /* We have to scan for our skb since there's no way
426 * to back-map them from the descriptor, and if we
427 * have several receive channels then they might not
428 * show up in the same order as they were put on the
432 dma = (dp->ptr & XCT_PTR_ADDR_M);
433 for (i = n; i < (n + RX_RING_SIZE); i++) {
434 info = &RX_DESC_INFO(mac, i);
435 if (info->dma == dma)
442 pci_unmap_single(mac->dma_pdev, dma, skb->len,
445 len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
448 struct sk_buff *new_skb =
449 netdev_alloc_skb(mac->netdev, len + NET_IP_ALIGN);
451 skb_reserve(new_skb, NET_IP_ALIGN);
452 memcpy(new_skb->data - NET_IP_ALIGN,
453 skb->data - NET_IP_ALIGN,
455 /* save the skb in buffer_info as good */
458 /* else just continue with the old one */
464 skb->protocol = eth_type_trans(skb, mac->netdev);
466 if ((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK) {
467 skb->ip_summed = CHECKSUM_COMPLETE;
468 skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
471 skb->ip_summed = CHECKSUM_NONE;
473 mac->stats.rx_bytes += len;
474 mac->stats.rx_packets++;
476 netif_receive_skb(skb);
484 mac->rx->next_to_clean += limit - count;
485 pasemi_mac_replenish_rx_ring(mac->netdev);
487 spin_unlock(&mac->rx->lock);
492 static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
495 struct pasemi_mac_buffer *info;
496 struct pas_dma_xct_descr *dp;
500 spin_lock_irqsave(&mac->tx->lock, flags);
502 start = mac->tx->next_to_clean;
505 for (i = start; i < mac->tx->next_to_use; i++) {
506 dp = &TX_DESC(mac, i);
507 if (!dp || (dp->mactx & XCT_MACTX_O))
512 info = &TX_DESC_INFO(mac, i);
514 pci_unmap_single(mac->dma_pdev, info->dma,
515 info->skb->len, PCI_DMA_TODEVICE);
516 dev_kfree_skb_irq(info->skb);
523 mac->tx->next_to_clean += count;
524 spin_unlock_irqrestore(&mac->tx->lock, flags);
526 netif_wake_queue(mac->netdev);
532 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
534 struct net_device *dev = data;
535 struct pasemi_mac *mac = netdev_priv(dev);
538 if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
541 if (*mac->rx_status & PAS_STATUS_ERROR)
542 printk("rx_status reported error\n");
544 /* Don't reset packet count so it won't fire again but clear
548 pci_read_config_dword(mac->dma_pdev, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), ®);
551 if (*mac->rx_status & PAS_STATUS_SOFT)
552 reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
553 if (*mac->rx_status & PAS_STATUS_ERROR)
554 reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
555 if (*mac->rx_status & PAS_STATUS_TIMER)
556 reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
558 netif_rx_schedule(dev);
560 pci_write_config_dword(mac->iob_pdev,
561 PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
567 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
569 struct net_device *dev = data;
570 struct pasemi_mac *mac = netdev_priv(dev);
573 if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
576 pasemi_mac_clean_tx(mac);
578 reg = PAS_IOB_DMA_TXCH_RESET_PINTC;
580 if (*mac->tx_status & PAS_STATUS_SOFT)
581 reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
582 if (*mac->tx_status & PAS_STATUS_ERROR)
583 reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
585 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch),
591 static int pasemi_mac_open(struct net_device *dev)
593 struct pasemi_mac *mac = netdev_priv(dev);
598 /* enable rx section */
599 pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD,
600 PAS_DMA_COM_RXCMD_EN);
602 /* enable tx section */
603 pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD,
604 PAS_DMA_COM_TXCMD_EN);
606 flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
607 PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
608 PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
610 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags);
612 flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
613 PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
615 flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
617 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
618 PAS_IOB_DMA_RXCH_CFG_CNTTH(1));
620 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
621 PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
623 /* Clear out any residual packet count state from firmware */
624 pasemi_mac_restart_rx_intr(mac);
625 pasemi_mac_restart_tx_intr(mac);
627 /* 0xffffff is max value, about 16ms */
628 pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
629 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
631 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
633 ret = pasemi_mac_setup_rx_resources(dev);
635 goto out_rx_resources;
637 ret = pasemi_mac_setup_tx_resources(dev);
639 goto out_tx_resources;
641 pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL,
642 PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
643 PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
646 pci_write_config_dword(mac->dma_pdev,
647 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
648 PAS_DMA_RXINT_RCMDSTA_EN);
650 /* enable rx channel */
651 pci_write_config_dword(mac->dma_pdev,
652 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
653 PAS_DMA_RXCHAN_CCMDSTA_EN |
654 PAS_DMA_RXCHAN_CCMDSTA_DU);
656 /* enable tx channel */
657 pci_write_config_dword(mac->dma_pdev,
658 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
659 PAS_DMA_TXCHAN_TCMDSTA_EN);
661 pasemi_mac_replenish_rx_ring(dev);
663 netif_start_queue(dev);
664 netif_poll_enable(dev);
666 /* Interrupts are a bit different for our DMA controller: While
667 * it's got one a regular PCI device header, the interrupt there
668 * is really the base of the range it's using. Each tx and rx
669 * channel has it's own interrupt source.
672 base_irq = virq_to_hw(mac->dma_pdev->irq);
674 mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
675 mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
677 ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
678 mac->tx->irq_name, dev);
680 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
681 base_irq + mac->dma_txch, ret);
685 ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
686 mac->rx->irq_name, dev);
688 dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
689 base_irq + 20 + mac->dma_rxch, ret);
696 free_irq(mac->tx_irq, dev);
698 netif_poll_disable(dev);
699 netif_stop_queue(dev);
700 pasemi_mac_free_tx_resources(dev);
702 pasemi_mac_free_rx_resources(dev);
708 #define MAX_RETRIES 5000
710 static int pasemi_mac_close(struct net_device *dev)
712 struct pasemi_mac *mac = netdev_priv(dev);
716 netif_stop_queue(dev);
718 /* Clean out any pending buffers */
719 pasemi_mac_clean_tx(mac);
720 pasemi_mac_clean_rx(mac, RX_RING_SIZE);
722 /* Disable interface */
723 pci_write_config_dword(mac->dma_pdev,
724 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
725 PAS_DMA_TXCHAN_TCMDSTA_ST);
726 pci_write_config_dword(mac->dma_pdev,
727 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
728 PAS_DMA_RXINT_RCMDSTA_ST);
729 pci_write_config_dword(mac->dma_pdev,
730 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
731 PAS_DMA_RXCHAN_CCMDSTA_ST);
733 for (retries = 0; retries < MAX_RETRIES; retries++) {
734 pci_read_config_dword(mac->dma_pdev,
735 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
737 if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT))
742 if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
743 dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
745 for (retries = 0; retries < MAX_RETRIES; retries++) {
746 pci_read_config_dword(mac->dma_pdev,
747 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
749 if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT))
754 if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
755 dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
757 for (retries = 0; retries < MAX_RETRIES; retries++) {
758 pci_read_config_dword(mac->dma_pdev,
759 PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
761 if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT))
766 if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
767 dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
769 /* Then, disable the channel. This must be done separately from
770 * stopping, since you can't disable when active.
773 pci_write_config_dword(mac->dma_pdev,
774 PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
775 pci_write_config_dword(mac->dma_pdev,
776 PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
777 pci_write_config_dword(mac->dma_pdev,
778 PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
780 free_irq(mac->tx_irq, dev);
781 free_irq(mac->rx_irq, dev);
784 pasemi_mac_free_rx_resources(dev);
785 pasemi_mac_free_tx_resources(dev);
790 static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
792 struct pasemi_mac *mac = netdev_priv(dev);
793 struct pasemi_mac_txring *txring;
794 struct pasemi_mac_buffer *info;
795 struct pas_dma_xct_descr *dp;
800 dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
802 if (skb->ip_summed == CHECKSUM_PARTIAL) {
803 const unsigned char *nh = skb_network_header(skb);
805 switch (ip_hdr(skb)->protocol) {
807 dflags |= XCT_MACTX_CSUM_TCP;
808 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
809 dflags |= XCT_MACTX_IPO(nh - skb->data);
812 dflags |= XCT_MACTX_CSUM_UDP;
813 dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
814 dflags |= XCT_MACTX_IPO(nh - skb->data);
819 map = pci_map_single(mac->dma_pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
821 if (dma_mapping_error(map))
822 return NETDEV_TX_BUSY;
826 spin_lock_irqsave(&txring->lock, flags);
828 if (txring->next_to_clean - txring->next_to_use == TX_RING_SIZE) {
829 spin_unlock_irqrestore(&txring->lock, flags);
830 pasemi_mac_clean_tx(mac);
831 spin_lock_irqsave(&txring->lock, flags);
833 if (txring->next_to_clean - txring->next_to_use ==
835 /* Still no room -- stop the queue and wait for tx
836 * intr when there's room.
838 netif_stop_queue(dev);
844 dp = &TX_DESC(mac, txring->next_to_use);
845 info = &TX_DESC_INFO(mac, txring->next_to_use);
847 dp->mactx = dflags | XCT_MACTX_LLEN(skb->len);
848 dp->ptr = XCT_PTR_LEN(skb->len) | XCT_PTR_ADDR(map);
852 txring->next_to_use++;
853 mac->stats.tx_packets++;
854 mac->stats.tx_bytes += skb->len;
856 spin_unlock_irqrestore(&txring->lock, flags);
858 pci_write_config_dword(mac->dma_pdev,
859 PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1);
864 spin_unlock_irqrestore(&txring->lock, flags);
865 pci_unmap_single(mac->dma_pdev, map, skb->len, PCI_DMA_TODEVICE);
866 return NETDEV_TX_BUSY;
869 static struct net_device_stats *pasemi_mac_get_stats(struct net_device *dev)
871 struct pasemi_mac *mac = netdev_priv(dev);
876 static void pasemi_mac_set_rx_mode(struct net_device *dev)
878 struct pasemi_mac *mac = netdev_priv(dev);
881 pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
883 /* Set promiscuous */
884 if (dev->flags & IFF_PROMISC)
885 flags |= PAS_MAC_CFG_PCFG_PR;
887 flags &= ~PAS_MAC_CFG_PCFG_PR;
889 pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
893 static int pasemi_mac_poll(struct net_device *dev, int *budget)
895 int pkts, limit = min(*budget, dev->quota);
896 struct pasemi_mac *mac = netdev_priv(dev);
898 pkts = pasemi_mac_clean_rx(mac, limit);
904 /* all done, no more packets present */
905 netif_rx_complete(dev);
907 pasemi_mac_restart_rx_intr(mac);
910 /* used up our quantum, so reschedule */
916 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
918 static int index = 0;
919 struct net_device *dev;
920 struct pasemi_mac *mac;
923 err = pci_enable_device(pdev);
927 dev = alloc_etherdev(sizeof(struct pasemi_mac));
930 "pasemi_mac: Could not allocate ethernet device.\n");
932 goto out_disable_device;
935 SET_MODULE_OWNER(dev);
936 pci_set_drvdata(pdev, dev);
937 SET_NETDEV_DEV(dev, &pdev->dev);
939 mac = netdev_priv(dev);
943 mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
945 if (!mac->dma_pdev) {
946 dev_err(&pdev->dev, "Can't find DMA Controller\n");
948 goto out_free_netdev;
951 mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
953 if (!mac->iob_pdev) {
954 dev_err(&pdev->dev, "Can't find I/O Bridge\n");
956 goto out_put_dma_pdev;
959 /* These should come out of the device tree eventually */
960 mac->dma_txch = index;
961 mac->dma_rxch = index;
963 /* We probe GMAC before XAUI, but the DMA interfaces are
964 * in XAUI, GMAC order.
967 mac->dma_if = index + 2;
969 mac->dma_if = index - 4;
972 switch (pdev->device) {
974 mac->type = MAC_TYPE_GMAC;
977 mac->type = MAC_TYPE_XAUI;
984 /* get mac addr from device tree */
985 if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
989 memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
991 dev->open = pasemi_mac_open;
992 dev->stop = pasemi_mac_close;
993 dev->hard_start_xmit = pasemi_mac_start_tx;
994 dev->get_stats = pasemi_mac_get_stats;
995 dev->set_multicast_list = pasemi_mac_set_rx_mode;
997 dev->poll = pasemi_mac_poll;
998 dev->features = NETIF_F_HW_CSUM;
1000 /* The dma status structure is located in the I/O bridge, and
1001 * is cache coherent.
1004 /* XXXOJN This should come from the device tree */
1005 dma_status = __ioremap(0xfd800000, 0x1000, 0);
1007 mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
1008 mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
1010 err = register_netdev(dev);
1013 dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1017 printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
1018 "hw addr %02x:%02x:%02x:%02x:%02x:%02x\n",
1019 dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1020 mac->dma_if, mac->dma_txch, mac->dma_rxch,
1021 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1022 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1027 pci_dev_put(mac->iob_pdev);
1029 pci_dev_put(mac->dma_pdev);
1033 pci_disable_device(pdev);
1038 static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
1040 struct net_device *netdev = pci_get_drvdata(pdev);
1041 struct pasemi_mac *mac;
1046 mac = netdev_priv(netdev);
1048 unregister_netdev(netdev);
1050 pci_disable_device(pdev);
1051 pci_dev_put(mac->dma_pdev);
1052 pci_dev_put(mac->iob_pdev);
1054 pci_set_drvdata(pdev, NULL);
1055 free_netdev(netdev);
1058 static struct pci_device_id pasemi_mac_pci_tbl[] = {
1059 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
1063 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1065 static struct pci_driver pasemi_mac_driver = {
1066 .name = "pasemi_mac",
1067 .id_table = pasemi_mac_pci_tbl,
1068 .probe = pasemi_mac_probe,
1069 .remove = __devexit_p(pasemi_mac_remove),
1072 static void __exit pasemi_mac_cleanup_module(void)
1074 pci_unregister_driver(&pasemi_mac_driver);
1075 __iounmap(dma_status);
1079 int pasemi_mac_init_module(void)
1081 return pci_register_driver(&pasemi_mac_driver);
1084 MODULE_LICENSE("GPL");
1085 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
1086 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
1088 module_init(pasemi_mac_init_module);
1089 module_exit(pasemi_mac_cleanup_module);