1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.32"
26 #define DRV_RELDATE "18.Mar.2006"
27 #define PFX DRV_NAME ": "
29 static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
54 #include <asm/uaccess.h>
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
60 static struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
71 { } /* terminate list */
74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
76 static int cards_found;
81 static unsigned int pcnet32_portlist[] __initdata =
82 { 0x300, 0x320, 0x340, 0x360, 0 };
84 static int pcnet32_debug = 0;
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb; /* check for VLB cards ? */
88 static struct net_device *pcnet32_dev;
90 static int max_interrupt_work = 2;
91 static int rx_copybreak = 200;
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
103 #define PCNET32_DMA_MASK 0xffffffff
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
109 * table to translate option values from tulip
110 * to internal options
112 static const unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Loopback test (offline)"
136 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
138 #define PCNET32_NUM_REGS 136
140 #define MAX_UNITS 8 /* More are supported, limit only on options */
141 static int options[MAX_UNITS];
142 static int full_duplex[MAX_UNITS];
143 static int homepna[MAX_UNITS];
146 * Theory of Operation
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
160 #ifndef PCNET32_LOG_TX_BUFFERS
161 #define PCNET32_LOG_TX_BUFFERS 4
162 #define PCNET32_LOG_RX_BUFFERS 5
163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164 #define PCNET32_LOG_MAX_RX_BUFFERS 9
167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
173 #define PKT_BUF_SZ 1544
175 /* Offsets from base I/O address. */
176 #define PCNET32_WIO_RDP 0x10
177 #define PCNET32_WIO_RAP 0x12
178 #define PCNET32_WIO_RESET 0x14
179 #define PCNET32_WIO_BDP 0x16
181 #define PCNET32_DWIO_RDP 0x10
182 #define PCNET32_DWIO_RAP 0x14
183 #define PCNET32_DWIO_RESET 0x18
184 #define PCNET32_DWIO_BDP 0x1C
186 #define PCNET32_TOTAL_SIZE 0x20
189 #define CSR0_INIT 0x1
190 #define CSR0_START 0x2
191 #define CSR0_STOP 0x4
192 #define CSR0_TXPOLL 0x8
193 #define CSR0_INTEN 0x40
194 #define CSR0_IDON 0x0100
195 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196 #define PCNET32_INIT_LOW 1
197 #define PCNET32_INIT_HIGH 2
201 #define CSR5_SUSPEND 0x0001
203 #define PCNET32_MC_FILTER 8
205 #define PCNET32_79C970A 0x2621
207 /* The PCNET32 Rx and Tx ring descriptors. */
208 struct pcnet32_rx_head {
210 s16 buf_length; /* two`s complement of length */
216 struct pcnet32_tx_head {
218 s16 length; /* two`s complement of length */
224 /* The PCNET32 32-Bit initialization block, described in databook. */
225 struct pcnet32_init_block {
231 /* Receive and transmit ring base, along with extra bits. */
236 /* PCnet32 access functions */
237 struct pcnet32_access {
238 u16 (*read_csr) (unsigned long, int);
239 void (*write_csr) (unsigned long, int, u16);
240 u16 (*read_bcr) (unsigned long, int);
241 void (*write_bcr) (unsigned long, int, u16);
242 u16 (*read_rap) (unsigned long);
243 void (*write_rap) (unsigned long, u16);
244 void (*reset) (unsigned long);
248 * The first field of pcnet32_private is read by the ethernet device
249 * so the structure should be allocated using pci_alloc_consistent().
251 struct pcnet32_private {
252 struct pcnet32_init_block init_block;
253 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
254 struct pcnet32_rx_head *rx_ring;
255 struct pcnet32_tx_head *tx_ring;
256 dma_addr_t dma_addr;/* DMA address of beginning of this
257 object, returned by pci_alloc_consistent */
258 struct pci_dev *pci_dev;
260 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
261 struct sk_buff **tx_skbuff;
262 struct sk_buff **rx_skbuff;
263 dma_addr_t *tx_dma_addr;
264 dma_addr_t *rx_dma_addr;
265 struct pcnet32_access a;
266 spinlock_t lock; /* Guard lock */
267 unsigned int cur_rx, cur_tx; /* The next free ring entry */
268 unsigned int rx_ring_size; /* current rx ring size */
269 unsigned int tx_ring_size; /* current tx ring size */
270 unsigned int rx_mod_mask; /* rx ring modular mask */
271 unsigned int tx_mod_mask; /* tx ring modular mask */
272 unsigned short rx_len_bits;
273 unsigned short tx_len_bits;
274 dma_addr_t rx_ring_dma_addr;
275 dma_addr_t tx_ring_dma_addr;
276 unsigned int dirty_rx, /* ring entries to be freed. */
279 struct net_device_stats stats;
281 char phycount; /* number of phys found */
283 unsigned int shared_irq:1, /* shared irq possible */
284 dxsuflo:1, /* disable transmit stop on uflo */
285 mii:1; /* mii port available */
286 struct net_device *next;
287 struct mii_if_info mii_if;
288 struct timer_list watchdog_timer;
289 struct timer_list blink_timer;
290 u32 msg_enable; /* debug message level */
292 /* each bit indicates an available PHY */
294 unsigned short chip_version; /* which variant this is */
297 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
298 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
299 static int pcnet32_open(struct net_device *);
300 static int pcnet32_init_ring(struct net_device *);
301 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
302 static void pcnet32_tx_timeout(struct net_device *dev);
303 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
304 static int pcnet32_close(struct net_device *);
305 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
306 static void pcnet32_load_multicast(struct net_device *dev);
307 static void pcnet32_set_multicast_list(struct net_device *);
308 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
309 static void pcnet32_watchdog(struct net_device *);
310 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
311 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
313 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
314 static void pcnet32_ethtool_test(struct net_device *dev,
315 struct ethtool_test *eth_test, u64 * data);
316 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
317 static int pcnet32_phys_id(struct net_device *dev, u32 data);
318 static void pcnet32_led_blink_callback(struct net_device *dev);
319 static int pcnet32_get_regs_len(struct net_device *dev);
320 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
322 static void pcnet32_purge_tx_ring(struct net_device *dev);
323 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
324 static void pcnet32_free_ring(struct net_device *dev);
325 static void pcnet32_check_media(struct net_device *dev, int verbose);
327 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
329 outw(index, addr + PCNET32_WIO_RAP);
330 return inw(addr + PCNET32_WIO_RDP);
333 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
335 outw(index, addr + PCNET32_WIO_RAP);
336 outw(val, addr + PCNET32_WIO_RDP);
339 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
341 outw(index, addr + PCNET32_WIO_RAP);
342 return inw(addr + PCNET32_WIO_BDP);
345 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
347 outw(index, addr + PCNET32_WIO_RAP);
348 outw(val, addr + PCNET32_WIO_BDP);
351 static u16 pcnet32_wio_read_rap(unsigned long addr)
353 return inw(addr + PCNET32_WIO_RAP);
356 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
358 outw(val, addr + PCNET32_WIO_RAP);
361 static void pcnet32_wio_reset(unsigned long addr)
363 inw(addr + PCNET32_WIO_RESET);
366 static int pcnet32_wio_check(unsigned long addr)
368 outw(88, addr + PCNET32_WIO_RAP);
369 return (inw(addr + PCNET32_WIO_RAP) == 88);
372 static struct pcnet32_access pcnet32_wio = {
373 .read_csr = pcnet32_wio_read_csr,
374 .write_csr = pcnet32_wio_write_csr,
375 .read_bcr = pcnet32_wio_read_bcr,
376 .write_bcr = pcnet32_wio_write_bcr,
377 .read_rap = pcnet32_wio_read_rap,
378 .write_rap = pcnet32_wio_write_rap,
379 .reset = pcnet32_wio_reset
382 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
384 outl(index, addr + PCNET32_DWIO_RAP);
385 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
388 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
390 outl(index, addr + PCNET32_DWIO_RAP);
391 outl(val, addr + PCNET32_DWIO_RDP);
394 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
396 outl(index, addr + PCNET32_DWIO_RAP);
397 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
400 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
402 outl(index, addr + PCNET32_DWIO_RAP);
403 outl(val, addr + PCNET32_DWIO_BDP);
406 static u16 pcnet32_dwio_read_rap(unsigned long addr)
408 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
411 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
413 outl(val, addr + PCNET32_DWIO_RAP);
416 static void pcnet32_dwio_reset(unsigned long addr)
418 inl(addr + PCNET32_DWIO_RESET);
421 static int pcnet32_dwio_check(unsigned long addr)
423 outl(88, addr + PCNET32_DWIO_RAP);
424 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
427 static struct pcnet32_access pcnet32_dwio = {
428 .read_csr = pcnet32_dwio_read_csr,
429 .write_csr = pcnet32_dwio_write_csr,
430 .read_bcr = pcnet32_dwio_read_bcr,
431 .write_bcr = pcnet32_dwio_write_bcr,
432 .read_rap = pcnet32_dwio_read_rap,
433 .write_rap = pcnet32_dwio_write_rap,
434 .reset = pcnet32_dwio_reset
437 static void pcnet32_netif_stop(struct net_device *dev)
439 dev->trans_start = jiffies;
440 netif_poll_disable(dev);
441 netif_tx_disable(dev);
444 static void pcnet32_netif_start(struct net_device *dev)
446 netif_wake_queue(dev);
447 netif_poll_enable(dev);
451 * Allocate space for the new sized tx ring.
453 * Save new resources.
454 * Any failure keeps old resources.
455 * Must be called with lp->lock held.
457 static void pcnet32_realloc_tx_ring(struct net_device *dev,
458 struct pcnet32_private *lp,
461 dma_addr_t new_ring_dma_addr;
462 dma_addr_t *new_dma_addr_list;
463 struct pcnet32_tx_head *new_tx_ring;
464 struct sk_buff **new_skb_list;
466 pcnet32_purge_tx_ring(dev);
468 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
469 sizeof(struct pcnet32_tx_head) *
472 if (new_tx_ring == NULL) {
473 if (netif_msg_drv(lp))
475 "%s: Consistent memory allocation failed.\n",
479 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
481 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
483 if (!new_dma_addr_list) {
484 if (netif_msg_drv(lp))
486 "%s: Memory allocation failed.\n", dev->name);
487 goto free_new_tx_ring;
490 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
493 if (netif_msg_drv(lp))
495 "%s: Memory allocation failed.\n", dev->name);
499 kfree(lp->tx_skbuff);
500 kfree(lp->tx_dma_addr);
501 pci_free_consistent(lp->pci_dev,
502 sizeof(struct pcnet32_tx_head) *
503 lp->tx_ring_size, lp->tx_ring,
504 lp->tx_ring_dma_addr);
506 lp->tx_ring_size = (1 << size);
507 lp->tx_mod_mask = lp->tx_ring_size - 1;
508 lp->tx_len_bits = (size << 12);
509 lp->tx_ring = new_tx_ring;
510 lp->tx_ring_dma_addr = new_ring_dma_addr;
511 lp->tx_dma_addr = new_dma_addr_list;
512 lp->tx_skbuff = new_skb_list;
516 kfree(new_dma_addr_list);
518 pci_free_consistent(lp->pci_dev,
519 sizeof(struct pcnet32_tx_head) *
527 * Allocate space for the new sized rx ring.
528 * Re-use old receive buffers.
529 * alloc extra buffers
530 * free unneeded buffers
531 * free unneeded buffers
532 * Save new resources.
533 * Any failure keeps old resources.
534 * Must be called with lp->lock held.
536 static void pcnet32_realloc_rx_ring(struct net_device *dev,
537 struct pcnet32_private *lp,
540 dma_addr_t new_ring_dma_addr;
541 dma_addr_t *new_dma_addr_list;
542 struct pcnet32_rx_head *new_rx_ring;
543 struct sk_buff **new_skb_list;
546 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
547 sizeof(struct pcnet32_rx_head) *
550 if (new_rx_ring == NULL) {
551 if (netif_msg_drv(lp))
553 "%s: Consistent memory allocation failed.\n",
557 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
559 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
561 if (!new_dma_addr_list) {
562 if (netif_msg_drv(lp))
564 "%s: Memory allocation failed.\n", dev->name);
565 goto free_new_rx_ring;
568 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
571 if (netif_msg_drv(lp))
573 "%s: Memory allocation failed.\n", dev->name);
577 /* first copy the current receive buffers */
578 overlap = min(size, lp->rx_ring_size);
579 for (new = 0; new < overlap; new++) {
580 new_rx_ring[new] = lp->rx_ring[new];
581 new_dma_addr_list[new] = lp->rx_dma_addr[new];
582 new_skb_list[new] = lp->rx_skbuff[new];
584 /* now allocate any new buffers needed */
585 for (; new < size; new++ ) {
586 struct sk_buff *rx_skbuff;
587 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
588 if (!(rx_skbuff = new_skb_list[new])) {
589 /* keep the original lists and buffers */
590 if (netif_msg_drv(lp))
592 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
596 skb_reserve(rx_skbuff, 2);
598 new_dma_addr_list[new] =
599 pci_map_single(lp->pci_dev, rx_skbuff->data,
600 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
601 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
602 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
603 new_rx_ring[new].status = le16_to_cpu(0x8000);
605 /* and free any unneeded buffers */
606 for (; new < lp->rx_ring_size; new++) {
607 if (lp->rx_skbuff[new]) {
608 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
609 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
610 dev_kfree_skb(lp->rx_skbuff[new]);
614 kfree(lp->rx_skbuff);
615 kfree(lp->rx_dma_addr);
616 pci_free_consistent(lp->pci_dev,
617 sizeof(struct pcnet32_rx_head) *
618 lp->rx_ring_size, lp->rx_ring,
619 lp->rx_ring_dma_addr);
621 lp->rx_ring_size = (1 << size);
622 lp->rx_mod_mask = lp->rx_ring_size - 1;
623 lp->rx_len_bits = (size << 4);
624 lp->rx_ring = new_rx_ring;
625 lp->rx_ring_dma_addr = new_ring_dma_addr;
626 lp->rx_dma_addr = new_dma_addr_list;
627 lp->rx_skbuff = new_skb_list;
631 for (; --new >= lp->rx_ring_size; ) {
632 if (new_skb_list[new]) {
633 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
634 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
635 dev_kfree_skb(new_skb_list[new]);
640 kfree(new_dma_addr_list);
642 pci_free_consistent(lp->pci_dev,
643 sizeof(struct pcnet32_rx_head) *
650 static void pcnet32_purge_rx_ring(struct net_device *dev)
652 struct pcnet32_private *lp = dev->priv;
655 /* free all allocated skbuffs */
656 for (i = 0; i < lp->rx_ring_size; i++) {
657 lp->rx_ring[i].status = 0; /* CPU owns buffer */
658 wmb(); /* Make sure adapter sees owner change */
659 if (lp->rx_skbuff[i]) {
660 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
661 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
662 dev_kfree_skb_any(lp->rx_skbuff[i]);
664 lp->rx_skbuff[i] = NULL;
665 lp->rx_dma_addr[i] = 0;
669 #ifdef CONFIG_NET_POLL_CONTROLLER
670 static void pcnet32_poll_controller(struct net_device *dev)
672 disable_irq(dev->irq);
673 pcnet32_interrupt(0, dev, NULL);
674 enable_irq(dev->irq);
678 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
680 struct pcnet32_private *lp = dev->priv;
685 spin_lock_irqsave(&lp->lock, flags);
686 mii_ethtool_gset(&lp->mii_if, cmd);
687 spin_unlock_irqrestore(&lp->lock, flags);
693 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
695 struct pcnet32_private *lp = dev->priv;
700 spin_lock_irqsave(&lp->lock, flags);
701 r = mii_ethtool_sset(&lp->mii_if, cmd);
702 spin_unlock_irqrestore(&lp->lock, flags);
707 static void pcnet32_get_drvinfo(struct net_device *dev,
708 struct ethtool_drvinfo *info)
710 struct pcnet32_private *lp = dev->priv;
712 strcpy(info->driver, DRV_NAME);
713 strcpy(info->version, DRV_VERSION);
715 strcpy(info->bus_info, pci_name(lp->pci_dev));
717 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
720 static u32 pcnet32_get_link(struct net_device *dev)
722 struct pcnet32_private *lp = dev->priv;
726 spin_lock_irqsave(&lp->lock, flags);
728 r = mii_link_ok(&lp->mii_if);
729 } else if (lp->chip_version >= PCNET32_79C970A) {
730 ulong ioaddr = dev->base_addr; /* card base I/O address */
731 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
732 } else { /* can not detect link on really old chips */
735 spin_unlock_irqrestore(&lp->lock, flags);
740 static u32 pcnet32_get_msglevel(struct net_device *dev)
742 struct pcnet32_private *lp = dev->priv;
743 return lp->msg_enable;
746 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
748 struct pcnet32_private *lp = dev->priv;
749 lp->msg_enable = value;
752 static int pcnet32_nway_reset(struct net_device *dev)
754 struct pcnet32_private *lp = dev->priv;
759 spin_lock_irqsave(&lp->lock, flags);
760 r = mii_nway_restart(&lp->mii_if);
761 spin_unlock_irqrestore(&lp->lock, flags);
766 static void pcnet32_get_ringparam(struct net_device *dev,
767 struct ethtool_ringparam *ering)
769 struct pcnet32_private *lp = dev->priv;
771 ering->tx_max_pending = TX_MAX_RING_SIZE;
772 ering->tx_pending = lp->tx_ring_size;
773 ering->rx_max_pending = RX_MAX_RING_SIZE;
774 ering->rx_pending = lp->rx_ring_size;
777 static int pcnet32_set_ringparam(struct net_device *dev,
778 struct ethtool_ringparam *ering)
780 struct pcnet32_private *lp = dev->priv;
783 ulong ioaddr = dev->base_addr;
786 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
789 if (netif_running(dev))
790 pcnet32_netif_stop(dev);
792 spin_lock_irqsave(&lp->lock, flags);
793 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
795 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
797 /* set the minimum ring size to 4, to allow the loopback test to work
800 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
801 if (size <= (1 << i))
804 if ((1 << i) != lp->tx_ring_size)
805 pcnet32_realloc_tx_ring(dev, lp, i);
807 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
808 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
809 if (size <= (1 << i))
812 if ((1 << i) != lp->rx_ring_size)
813 pcnet32_realloc_rx_ring(dev, lp, i);
815 dev->weight = lp->rx_ring_size / 2;
817 if (netif_running(dev)) {
818 pcnet32_netif_start(dev);
819 pcnet32_restart(dev, CSR0_NORMAL);
822 spin_unlock_irqrestore(&lp->lock, flags);
824 if (netif_msg_drv(lp))
826 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
827 lp->rx_ring_size, lp->tx_ring_size);
832 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
835 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
838 static int pcnet32_self_test_count(struct net_device *dev)
840 return PCNET32_TEST_LEN;
843 static void pcnet32_ethtool_test(struct net_device *dev,
844 struct ethtool_test *test, u64 * data)
846 struct pcnet32_private *lp = dev->priv;
849 if (test->flags == ETH_TEST_FL_OFFLINE) {
850 rc = pcnet32_loopback_test(dev, data);
852 if (netif_msg_hw(lp))
853 printk(KERN_DEBUG "%s: Loopback test failed.\n",
855 test->flags |= ETH_TEST_FL_FAILED;
856 } else if (netif_msg_hw(lp))
857 printk(KERN_DEBUG "%s: Loopback test passed.\n",
859 } else if (netif_msg_hw(lp))
861 "%s: No tests to run (specify 'Offline' on ethtool).",
863 } /* end pcnet32_ethtool_test */
865 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
867 struct pcnet32_private *lp = dev->priv;
868 struct pcnet32_access *a = &lp->a; /* access to registers */
869 ulong ioaddr = dev->base_addr; /* card base I/O address */
870 struct sk_buff *skb; /* sk buff */
871 int x, i; /* counters */
872 int numbuffs = 4; /* number of TX/RX buffers and descs */
873 u16 status = 0x8300; /* TX ring status */
874 u16 teststatus; /* test of ring status */
875 int rc; /* return code */
876 int size; /* size of packets */
877 unsigned char *packet; /* source packet data */
878 static const int data_len = 60; /* length of source packets */
882 rc = 1; /* default to fail */
884 if (netif_running(dev))
887 spin_lock_irqsave(&lp->lock, flags);
888 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
890 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
892 /* Reset the PCNET32 */
894 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
896 /* switch pcnet32 to 32bit mode */
897 lp->a.write_bcr(ioaddr, 20, 2);
899 /* purge & init rings but don't actually restart */
900 pcnet32_restart(dev, 0x0000);
902 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
904 /* Initialize Transmit buffers. */
905 size = data_len + 15;
906 for (x = 0; x < numbuffs; x++) {
907 if (!(skb = dev_alloc_skb(size))) {
908 if (netif_msg_hw(lp))
910 "%s: Cannot allocate skb at line: %d!\n",
911 dev->name, __LINE__);
915 skb_put(skb, size); /* create space for data */
916 lp->tx_skbuff[x] = skb;
917 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
918 lp->tx_ring[x].misc = 0;
920 /* put DA and SA into the skb */
921 for (i = 0; i < 6; i++)
922 *packet++ = dev->dev_addr[i];
923 for (i = 0; i < 6; i++)
924 *packet++ = dev->dev_addr[i];
930 /* fill packet with data */
931 for (i = 0; i < data_len; i++)
935 pci_map_single(lp->pci_dev, skb->data, skb->len,
937 lp->tx_ring[x].base =
938 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
939 wmb(); /* Make sure owner changes after all others are visible */
940 lp->tx_ring[x].status = le16_to_cpu(status);
944 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
945 a->write_bcr(ioaddr, 32, x | 0x0002);
947 /* set int loopback in CSR15 */
948 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
949 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
951 teststatus = le16_to_cpu(0x8000);
952 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
954 /* Check status of descriptors */
955 for (x = 0; x < numbuffs; x++) {
958 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
959 spin_unlock_irqrestore(&lp->lock, flags);
961 spin_lock_irqsave(&lp->lock, flags);
966 if (netif_msg_hw(lp))
967 printk("%s: Desc %d failed to reset!\n",
973 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
975 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
976 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
978 for (x = 0; x < numbuffs; x++) {
979 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
980 skb = lp->rx_skbuff[x];
981 for (i = 0; i < size; i++) {
982 printk("%02x ", *(skb->data + i));
990 while (x < numbuffs && !rc) {
991 skb = lp->rx_skbuff[x];
992 packet = lp->tx_skbuff[x]->data;
993 for (i = 0; i < size; i++) {
994 if (*(skb->data + i) != packet[i]) {
995 if (netif_msg_hw(lp))
997 "%s: Error in compare! %2x - %02x %02x\n",
998 dev->name, i, *(skb->data + i),
1009 pcnet32_purge_tx_ring(dev);
1011 x = a->read_csr(ioaddr, CSR15);
1012 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1014 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1015 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1017 if (netif_running(dev)) {
1018 spin_unlock_irqrestore(&lp->lock, flags);
1021 pcnet32_purge_rx_ring(dev);
1022 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1023 spin_unlock_irqrestore(&lp->lock, flags);
1027 } /* end pcnet32_loopback_test */
1029 static void pcnet32_led_blink_callback(struct net_device *dev)
1031 struct pcnet32_private *lp = dev->priv;
1032 struct pcnet32_access *a = &lp->a;
1033 ulong ioaddr = dev->base_addr;
1034 unsigned long flags;
1037 spin_lock_irqsave(&lp->lock, flags);
1038 for (i = 4; i < 8; i++) {
1039 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1041 spin_unlock_irqrestore(&lp->lock, flags);
1043 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1046 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1048 struct pcnet32_private *lp = dev->priv;
1049 struct pcnet32_access *a = &lp->a;
1050 ulong ioaddr = dev->base_addr;
1051 unsigned long flags;
1054 if (!lp->blink_timer.function) {
1055 init_timer(&lp->blink_timer);
1056 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1057 lp->blink_timer.data = (unsigned long)dev;
1060 /* Save the current value of the bcrs */
1061 spin_lock_irqsave(&lp->lock, flags);
1062 for (i = 4; i < 8; i++) {
1063 regs[i - 4] = a->read_bcr(ioaddr, i);
1065 spin_unlock_irqrestore(&lp->lock, flags);
1067 mod_timer(&lp->blink_timer, jiffies);
1068 set_current_state(TASK_INTERRUPTIBLE);
1070 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1071 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1073 msleep_interruptible(data * 1000);
1074 del_timer_sync(&lp->blink_timer);
1076 /* Restore the original value of the bcrs */
1077 spin_lock_irqsave(&lp->lock, flags);
1078 for (i = 4; i < 8; i++) {
1079 a->write_bcr(ioaddr, i, regs[i - 4]);
1081 spin_unlock_irqrestore(&lp->lock, flags);
1087 * lp->lock must be held.
1089 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1093 struct pcnet32_private *lp = dev->priv;
1094 struct pcnet32_access *a = &lp->a;
1095 ulong ioaddr = dev->base_addr;
1098 /* really old chips have to be stopped. */
1099 if (lp->chip_version < PCNET32_79C970A)
1102 /* set SUSPEND (SPND) - CSR5 bit 0 */
1103 csr5 = a->read_csr(ioaddr, CSR5);
1104 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1106 /* poll waiting for bit to be set */
1108 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1109 spin_unlock_irqrestore(&lp->lock, *flags);
1114 spin_lock_irqsave(&lp->lock, *flags);
1117 if (netif_msg_hw(lp))
1119 "%s: Error getting into suspend!\n",
1128 static int pcnet32_rx(struct net_device *dev)
1130 struct pcnet32_private *lp = dev->priv;
1131 int entry = lp->cur_rx & lp->rx_mod_mask;
1132 int boguscnt = lp->rx_ring_size / 2;
1134 /* If we own the next entry, it's a new packet. Send it up. */
1135 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1136 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1138 if (status != 0x03) { /* There was an error. */
1140 * There is a tricky error noted by John Murphy,
1141 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1142 * buffers it's possible for a jabber packet to use two
1143 * buffers, with only the last correctly noting the error.
1145 if (status & 0x01) /* Only count a general error at the */
1146 lp->stats.rx_errors++; /* end of a packet. */
1148 lp->stats.rx_frame_errors++;
1150 lp->stats.rx_over_errors++;
1152 lp->stats.rx_crc_errors++;
1154 lp->stats.rx_fifo_errors++;
1155 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1157 /* Malloc up new buffer, compatible with net-2e. */
1159 (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)
1161 struct sk_buff *skb;
1163 /* Discard oversize frames. */
1164 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1165 if (netif_msg_drv(lp))
1167 "%s: Impossible packet size %d!\n",
1168 dev->name, pkt_len);
1169 lp->stats.rx_errors++;
1170 } else if (pkt_len < 60) {
1171 if (netif_msg_rx_err(lp))
1172 printk(KERN_ERR "%s: Runt packet!\n",
1174 lp->stats.rx_errors++;
1176 int rx_in_place = 0;
1178 if (pkt_len > rx_copybreak) {
1179 struct sk_buff *newskb;
1182 dev_alloc_skb(PKT_BUF_SZ))) {
1183 skb_reserve(newskb, 2);
1184 skb = lp->rx_skbuff[entry];
1185 pci_unmap_single(lp->pci_dev,
1190 PCI_DMA_FROMDEVICE);
1191 skb_put(skb, pkt_len);
1192 lp->rx_skbuff[entry] = newskb;
1194 lp->rx_dma_addr[entry] =
1195 pci_map_single(lp->pci_dev,
1199 PCI_DMA_FROMDEVICE);
1200 lp->rx_ring[entry].base =
1208 skb = dev_alloc_skb(pkt_len + 2);
1213 if (netif_msg_drv(lp))
1215 "%s: Memory squeeze, deferring packet.\n",
1217 for (i = 0; i < lp->rx_ring_size; i++)
1227 if (i > lp->rx_ring_size - 2) {
1228 lp->stats.rx_dropped++;
1229 lp->rx_ring[entry].status |=
1230 le16_to_cpu(0x8000);
1231 wmb(); /* Make sure adapter sees owner change */
1238 skb_reserve(skb, 2); /* 16 byte align */
1239 skb_put(skb, pkt_len); /* Make room */
1240 pci_dma_sync_single_for_cpu(lp->pci_dev,
1246 PCI_DMA_FROMDEVICE);
1247 eth_copy_and_sum(skb,
1248 (unsigned char *)(lp->
1253 pci_dma_sync_single_for_device(lp->
1260 PCI_DMA_FROMDEVICE);
1262 lp->stats.rx_bytes += skb->len;
1263 skb->protocol = eth_type_trans(skb, dev);
1265 dev->last_rx = jiffies;
1266 lp->stats.rx_packets++;
1270 * The docs say that the buffer length isn't touched, but Andrew Boyd
1271 * of QNX reports that some revs of the 79C965 clear it.
1273 lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
1274 wmb(); /* Make sure owner changes after all others are visible */
1275 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1276 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1277 if (--boguscnt <= 0)
1278 break; /* don't stay in loop forever */
1284 static int pcnet32_tx(struct net_device *dev, u16 csr0)
1286 struct pcnet32_private *lp = dev->priv;
1287 unsigned int dirty_tx = lp->dirty_tx;
1289 int must_restart = 0;
1291 while (dirty_tx != lp->cur_tx) {
1292 int entry = dirty_tx & lp->tx_mod_mask;
1293 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1296 break; /* It still hasn't been Txed */
1298 lp->tx_ring[entry].base = 0;
1300 if (status & 0x4000) {
1301 /* There was an major error, log it. */
1302 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1303 lp->stats.tx_errors++;
1304 if (netif_msg_tx_err(lp))
1306 "%s: Tx error status=%04x err_status=%08x\n",
1309 if (err_status & 0x04000000)
1310 lp->stats.tx_aborted_errors++;
1311 if (err_status & 0x08000000)
1312 lp->stats.tx_carrier_errors++;
1313 if (err_status & 0x10000000)
1314 lp->stats.tx_window_errors++;
1316 if (err_status & 0x40000000) {
1317 lp->stats.tx_fifo_errors++;
1318 /* Ackk! On FIFO errors the Tx unit is turned off! */
1319 /* Remove this verbosity later! */
1320 if (netif_msg_tx_err(lp))
1322 "%s: Tx FIFO error! CSR0=%4.4x\n",
1327 if (err_status & 0x40000000) {
1328 lp->stats.tx_fifo_errors++;
1329 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1330 /* Ackk! On FIFO errors the Tx unit is turned off! */
1331 /* Remove this verbosity later! */
1332 if (netif_msg_tx_err
1335 "%s: Tx FIFO error! CSR0=%4.4x\n",
1342 if (status & 0x1800)
1343 lp->stats.collisions++;
1344 lp->stats.tx_packets++;
1347 /* We must free the original skb */
1348 if (lp->tx_skbuff[entry]) {
1349 pci_unmap_single(lp->pci_dev,
1350 lp->tx_dma_addr[entry],
1351 lp->tx_skbuff[entry]->
1352 len, PCI_DMA_TODEVICE);
1353 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1354 lp->tx_skbuff[entry] = NULL;
1355 lp->tx_dma_addr[entry] = 0;
1361 (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask +
1363 if (delta > lp->tx_ring_size) {
1364 if (netif_msg_drv(lp))
1366 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1367 dev->name, dirty_tx, lp->cur_tx,
1369 dirty_tx += lp->tx_ring_size;
1370 delta -= lp->tx_ring_size;
1374 netif_queue_stopped(dev) &&
1375 delta < lp->tx_ring_size - 2) {
1376 /* The ring is no longer full, clear tbusy. */
1378 netif_wake_queue(dev);
1380 lp->dirty_tx = dirty_tx;
1382 return must_restart;
1385 #define PCNET32_REGS_PER_PHY 32
1386 #define PCNET32_MAX_PHYS 32
1387 static int pcnet32_get_regs_len(struct net_device *dev)
1389 struct pcnet32_private *lp = dev->priv;
1390 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1392 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1395 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1400 struct pcnet32_private *lp = dev->priv;
1401 struct pcnet32_access *a = &lp->a;
1402 ulong ioaddr = dev->base_addr;
1403 unsigned long flags;
1405 spin_lock_irqsave(&lp->lock, flags);
1407 csr0 = a->read_csr(ioaddr, CSR0);
1408 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1409 pcnet32_suspend(dev, &flags, 1);
1411 /* read address PROM */
1412 for (i = 0; i < 16; i += 2)
1413 *buff++ = inw(ioaddr + i);
1415 /* read control and status registers */
1416 for (i = 0; i < 90; i++) {
1417 *buff++ = a->read_csr(ioaddr, i);
1420 *buff++ = a->read_csr(ioaddr, 112);
1421 *buff++ = a->read_csr(ioaddr, 114);
1423 /* read bus configuration registers */
1424 for (i = 0; i < 30; i++) {
1425 *buff++ = a->read_bcr(ioaddr, i);
1427 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1428 for (i = 31; i < 36; i++) {
1429 *buff++ = a->read_bcr(ioaddr, i);
1432 /* read mii phy registers */
1435 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1436 if (lp->phymask & (1 << j)) {
1437 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1438 lp->a.write_bcr(ioaddr, 33,
1440 *buff++ = lp->a.read_bcr(ioaddr, 34);
1446 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1449 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1450 csr5 = a->read_csr(ioaddr, CSR5);
1451 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1454 spin_unlock_irqrestore(&lp->lock, flags);
1457 static struct ethtool_ops pcnet32_ethtool_ops = {
1458 .get_settings = pcnet32_get_settings,
1459 .set_settings = pcnet32_set_settings,
1460 .get_drvinfo = pcnet32_get_drvinfo,
1461 .get_msglevel = pcnet32_get_msglevel,
1462 .set_msglevel = pcnet32_set_msglevel,
1463 .nway_reset = pcnet32_nway_reset,
1464 .get_link = pcnet32_get_link,
1465 .get_ringparam = pcnet32_get_ringparam,
1466 .set_ringparam = pcnet32_set_ringparam,
1467 .get_tx_csum = ethtool_op_get_tx_csum,
1468 .get_sg = ethtool_op_get_sg,
1469 .get_tso = ethtool_op_get_tso,
1470 .get_strings = pcnet32_get_strings,
1471 .self_test_count = pcnet32_self_test_count,
1472 .self_test = pcnet32_ethtool_test,
1473 .phys_id = pcnet32_phys_id,
1474 .get_regs_len = pcnet32_get_regs_len,
1475 .get_regs = pcnet32_get_regs,
1476 .get_perm_addr = ethtool_op_get_perm_addr,
1479 /* only probes for non-PCI devices, the rest are handled by
1480 * pci_register_driver via pcnet32_probe_pci */
1482 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1484 unsigned int *port, ioaddr;
1486 /* search for PCnet32 VLB cards at known addresses */
1487 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1489 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1490 /* check if there is really a pcnet chip on that ioaddr */
1491 if ((inb(ioaddr + 14) == 0x57)
1492 && (inb(ioaddr + 15) == 0x57)) {
1493 pcnet32_probe1(ioaddr, 0, NULL);
1495 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1501 static int __devinit
1502 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1504 unsigned long ioaddr;
1507 err = pci_enable_device(pdev);
1509 if (pcnet32_debug & NETIF_MSG_PROBE)
1511 "failed to enable device -- err=%d\n", err);
1514 pci_set_master(pdev);
1516 ioaddr = pci_resource_start(pdev, 0);
1518 if (pcnet32_debug & NETIF_MSG_PROBE)
1520 "card has no PCI IO resources, aborting\n");
1524 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1525 if (pcnet32_debug & NETIF_MSG_PROBE)
1527 "architecture does not support 32bit PCI busmaster DMA\n");
1530 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1532 if (pcnet32_debug & NETIF_MSG_PROBE)
1534 "io address range already allocated\n");
1538 err = pcnet32_probe1(ioaddr, 1, pdev);
1540 pci_disable_device(pdev);
1546 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1547 * pdev will be NULL when called from pcnet32_probe_vlbus.
1549 static int __devinit
1550 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1552 struct pcnet32_private *lp;
1553 dma_addr_t lp_dma_addr;
1555 int fdx, mii, fset, dxsuflo;
1558 struct net_device *dev;
1559 struct pcnet32_access *a = NULL;
1563 /* reset the chip */
1564 pcnet32_wio_reset(ioaddr);
1566 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1567 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1570 pcnet32_dwio_reset(ioaddr);
1571 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1572 && pcnet32_dwio_check(ioaddr)) {
1575 goto err_release_region;
1579 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1580 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1581 printk(KERN_INFO " PCnet chip version is %#x.\n",
1583 if ((chip_version & 0xfff) != 0x003) {
1584 if (pcnet32_debug & NETIF_MSG_PROBE)
1585 printk(KERN_INFO PFX "Unsupported chip version.\n");
1586 goto err_release_region;
1589 /* initialize variables */
1590 fdx = mii = fset = dxsuflo = 0;
1591 chip_version = (chip_version >> 12) & 0xffff;
1593 switch (chip_version) {
1595 chipname = "PCnet/PCI 79C970"; /* PCI */
1599 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1601 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1604 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1608 chipname = "PCnet/FAST 79C971"; /* PCI */
1614 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1620 chipname = "PCnet/FAST III 79C973"; /* PCI */
1625 chipname = "PCnet/Home 79C978"; /* PCI */
1628 * This is based on specs published at www.amd.com. This section
1629 * assumes that a card with a 79C978 wants to go into standard
1630 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1631 * and the module option homepna=1 can select this instead.
1633 media = a->read_bcr(ioaddr, 49);
1634 media &= ~3; /* default to 10Mb ethernet */
1635 if (cards_found < MAX_UNITS && homepna[cards_found])
1636 media |= 1; /* switch to home wiring mode */
1637 if (pcnet32_debug & NETIF_MSG_PROBE)
1638 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1639 (media & 1) ? "1" : "10");
1640 a->write_bcr(ioaddr, 49, media);
1643 chipname = "PCnet/FAST III 79C975"; /* PCI */
1648 chipname = "PCnet/PRO 79C976";
1653 if (pcnet32_debug & NETIF_MSG_PROBE)
1654 printk(KERN_INFO PFX
1655 "PCnet version %#x, no PCnet32 chip.\n",
1657 goto err_release_region;
1661 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1662 * starting until the packet is loaded. Strike one for reliability, lose
1663 * one for latency - although on PCI this isnt a big loss. Older chips
1664 * have FIFO's smaller than a packet, so you can't do this.
1665 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1669 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1670 a->write_csr(ioaddr, 80,
1671 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1675 dev = alloc_etherdev(0);
1677 if (pcnet32_debug & NETIF_MSG_PROBE)
1678 printk(KERN_ERR PFX "Memory allocation failed.\n");
1680 goto err_release_region;
1682 SET_NETDEV_DEV(dev, &pdev->dev);
1684 if (pcnet32_debug & NETIF_MSG_PROBE)
1685 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1687 /* In most chips, after a chip reset, the ethernet address is read from the
1688 * station address PROM at the base address and programmed into the
1689 * "Physical Address Registers" CSR12-14.
1690 * As a precautionary measure, we read the PROM values and complain if
1691 * they disagree with the CSRs. If they miscompare, and the PROM addr
1692 * is valid, then the PROM addr is used.
1694 for (i = 0; i < 3; i++) {
1696 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1697 /* There may be endianness issues here. */
1698 dev->dev_addr[2 * i] = val & 0x0ff;
1699 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1702 /* read PROM address and compare with CSR address */
1703 for (i = 0; i < 6; i++)
1704 promaddr[i] = inb(ioaddr + i);
1706 if (memcmp(promaddr, dev->dev_addr, 6)
1707 || !is_valid_ether_addr(dev->dev_addr)) {
1708 if (is_valid_ether_addr(promaddr)) {
1709 if (pcnet32_debug & NETIF_MSG_PROBE) {
1710 printk(" warning: CSR address invalid,\n");
1712 " using instead PROM address of");
1714 memcpy(dev->dev_addr, promaddr, 6);
1717 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1719 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1720 if (!is_valid_ether_addr(dev->perm_addr))
1721 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1723 if (pcnet32_debug & NETIF_MSG_PROBE) {
1724 for (i = 0; i < 6; i++)
1725 printk(" %2.2x", dev->dev_addr[i]);
1727 /* Version 0x2623 and 0x2624 */
1728 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1729 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1730 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1733 printk(" 20 bytes,");
1736 printk(" 64 bytes,");
1739 printk(" 128 bytes,");
1742 printk("~220 bytes,");
1745 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1746 printk(" BCR18(%x):", i & 0xffff);
1748 printk("BurstWrEn ");
1750 printk("BurstRdEn ");
1755 i = a->read_bcr(ioaddr, 25);
1756 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1757 i = a->read_bcr(ioaddr, 26);
1758 printk(" SRAM_BND=0x%04x,", i << 8);
1759 i = a->read_bcr(ioaddr, 27);
1765 dev->base_addr = ioaddr;
1766 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1768 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1769 if (pcnet32_debug & NETIF_MSG_PROBE)
1771 "Consistent memory allocation failed.\n");
1773 goto err_free_netdev;
1776 memset(lp, 0, sizeof(*lp));
1777 lp->dma_addr = lp_dma_addr;
1780 spin_lock_init(&lp->lock);
1782 SET_MODULE_OWNER(dev);
1783 SET_NETDEV_DEV(dev, &pdev->dev);
1785 lp->name = chipname;
1786 lp->shared_irq = shared;
1787 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1788 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1789 lp->tx_mod_mask = lp->tx_ring_size - 1;
1790 lp->rx_mod_mask = lp->rx_ring_size - 1;
1791 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1792 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1793 lp->mii_if.full_duplex = fdx;
1794 lp->mii_if.phy_id_mask = 0x1f;
1795 lp->mii_if.reg_num_mask = 0x1f;
1796 lp->dxsuflo = dxsuflo;
1798 lp->chip_version = chip_version;
1799 lp->msg_enable = pcnet32_debug;
1800 if ((cards_found >= MAX_UNITS)
1801 || (options[cards_found] > sizeof(options_mapping)))
1802 lp->options = PCNET32_PORT_ASEL;
1804 lp->options = options_mapping[options[cards_found]];
1805 lp->mii_if.dev = dev;
1806 lp->mii_if.mdio_read = mdio_read;
1807 lp->mii_if.mdio_write = mdio_write;
1809 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1810 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1811 lp->options |= PCNET32_PORT_FD;
1814 if (pcnet32_debug & NETIF_MSG_PROBE)
1815 printk(KERN_ERR PFX "No access methods\n");
1817 goto err_free_consistent;
1821 /* prior to register_netdev, dev->name is not yet correct */
1822 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1826 /* detect special T1/E1 WAN card by checking for MAC address */
1827 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1828 && dev->dev_addr[2] == 0x75)
1829 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1831 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1832 lp->init_block.tlen_rlen =
1833 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1834 for (i = 0; i < 6; i++)
1835 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1836 lp->init_block.filter[0] = 0x00000000;
1837 lp->init_block.filter[1] = 0x00000000;
1838 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1839 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1841 /* switch pcnet32 to 32bit mode */
1842 a->write_bcr(ioaddr, 20, 2);
1844 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1845 init_block)) & 0xffff);
1846 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1847 init_block)) >> 16);
1849 if (pdev) { /* use the IRQ provided by PCI */
1850 dev->irq = pdev->irq;
1851 if (pcnet32_debug & NETIF_MSG_PROBE)
1852 printk(" assigned IRQ %d.\n", dev->irq);
1854 unsigned long irq_mask = probe_irq_on();
1857 * To auto-IRQ we enable the initialization-done and DMA error
1858 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1861 /* Trigger an initialization just for the interrupt. */
1862 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1865 dev->irq = probe_irq_off(irq_mask);
1867 if (pcnet32_debug & NETIF_MSG_PROBE)
1868 printk(", failed to detect IRQ line.\n");
1872 if (pcnet32_debug & NETIF_MSG_PROBE)
1873 printk(", probed IRQ %d.\n", dev->irq);
1876 /* Set the mii phy_id so that we can query the link state */
1878 /* lp->phycount and lp->phymask are set to 0 by memset above */
1880 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1882 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1883 unsigned short id1, id2;
1885 id1 = mdio_read(dev, i, MII_PHYSID1);
1888 id2 = mdio_read(dev, i, MII_PHYSID2);
1891 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1892 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1894 lp->phymask |= (1 << i);
1895 lp->mii_if.phy_id = i;
1896 if (pcnet32_debug & NETIF_MSG_PROBE)
1897 printk(KERN_INFO PFX
1898 "Found PHY %04x:%04x at address %d.\n",
1901 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1902 if (lp->phycount > 1) {
1903 lp->options |= PCNET32_PORT_MII;
1907 init_timer(&lp->watchdog_timer);
1908 lp->watchdog_timer.data = (unsigned long)dev;
1909 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1911 /* The PCNET32-specific entries in the device structure. */
1912 dev->open = &pcnet32_open;
1913 dev->hard_start_xmit = &pcnet32_start_xmit;
1914 dev->stop = &pcnet32_close;
1915 dev->get_stats = &pcnet32_get_stats;
1916 dev->set_multicast_list = &pcnet32_set_multicast_list;
1917 dev->do_ioctl = &pcnet32_ioctl;
1918 dev->ethtool_ops = &pcnet32_ethtool_ops;
1919 dev->tx_timeout = pcnet32_tx_timeout;
1920 dev->watchdog_timeo = (5 * HZ);
1922 #ifdef CONFIG_NET_POLL_CONTROLLER
1923 dev->poll_controller = pcnet32_poll_controller;
1926 /* Fill in the generic fields of the device structure. */
1927 if (register_netdev(dev))
1931 pci_set_drvdata(pdev, dev);
1933 lp->next = pcnet32_dev;
1937 if (pcnet32_debug & NETIF_MSG_PROBE)
1938 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1941 /* enable LED writes */
1942 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1947 pcnet32_free_ring(dev);
1948 err_free_consistent:
1949 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1953 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1957 /* if any allocation fails, caller must also call pcnet32_free_ring */
1958 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
1960 struct pcnet32_private *lp = dev->priv;
1962 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1963 sizeof(struct pcnet32_tx_head) *
1965 &lp->tx_ring_dma_addr);
1966 if (lp->tx_ring == NULL) {
1967 if (netif_msg_drv(lp))
1968 printk("\n" KERN_ERR PFX
1969 "%s: Consistent memory allocation failed.\n",
1974 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1975 sizeof(struct pcnet32_rx_head) *
1977 &lp->rx_ring_dma_addr);
1978 if (lp->rx_ring == NULL) {
1979 if (netif_msg_drv(lp))
1980 printk("\n" KERN_ERR PFX
1981 "%s: Consistent memory allocation failed.\n",
1986 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1988 if (!lp->tx_dma_addr) {
1989 if (netif_msg_drv(lp))
1990 printk("\n" KERN_ERR PFX
1991 "%s: Memory allocation failed.\n", name);
1995 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1997 if (!lp->rx_dma_addr) {
1998 if (netif_msg_drv(lp))
1999 printk("\n" KERN_ERR PFX
2000 "%s: Memory allocation failed.\n", name);
2004 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2006 if (!lp->tx_skbuff) {
2007 if (netif_msg_drv(lp))
2008 printk("\n" KERN_ERR PFX
2009 "%s: Memory allocation failed.\n", name);
2013 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2015 if (!lp->rx_skbuff) {
2016 if (netif_msg_drv(lp))
2017 printk("\n" KERN_ERR PFX
2018 "%s: Memory allocation failed.\n", name);
2025 static void pcnet32_free_ring(struct net_device *dev)
2027 struct pcnet32_private *lp = dev->priv;
2029 kfree(lp->tx_skbuff);
2030 lp->tx_skbuff = NULL;
2032 kfree(lp->rx_skbuff);
2033 lp->rx_skbuff = NULL;
2035 kfree(lp->tx_dma_addr);
2036 lp->tx_dma_addr = NULL;
2038 kfree(lp->rx_dma_addr);
2039 lp->rx_dma_addr = NULL;
2042 pci_free_consistent(lp->pci_dev,
2043 sizeof(struct pcnet32_tx_head) *
2044 lp->tx_ring_size, lp->tx_ring,
2045 lp->tx_ring_dma_addr);
2050 pci_free_consistent(lp->pci_dev,
2051 sizeof(struct pcnet32_rx_head) *
2052 lp->rx_ring_size, lp->rx_ring,
2053 lp->rx_ring_dma_addr);
2058 static int pcnet32_open(struct net_device *dev)
2060 struct pcnet32_private *lp = dev->priv;
2061 unsigned long ioaddr = dev->base_addr;
2065 unsigned long flags;
2067 if (request_irq(dev->irq, &pcnet32_interrupt,
2068 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2073 spin_lock_irqsave(&lp->lock, flags);
2074 /* Check for a valid station address */
2075 if (!is_valid_ether_addr(dev->dev_addr)) {
2080 /* Reset the PCNET32 */
2081 lp->a.reset(ioaddr);
2083 /* switch pcnet32 to 32bit mode */
2084 lp->a.write_bcr(ioaddr, 20, 2);
2086 if (netif_msg_ifup(lp))
2088 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2089 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2090 (u32) (lp->rx_ring_dma_addr),
2091 (u32) (lp->dma_addr +
2092 offsetof(struct pcnet32_private, init_block)));
2094 /* set/reset autoselect bit */
2095 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2096 if (lp->options & PCNET32_PORT_ASEL)
2098 lp->a.write_bcr(ioaddr, 2, val);
2100 /* handle full duplex setting */
2101 if (lp->mii_if.full_duplex) {
2102 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2103 if (lp->options & PCNET32_PORT_FD) {
2105 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2107 } else if (lp->options & PCNET32_PORT_ASEL) {
2108 /* workaround of xSeries250, turn on for 79C975 only */
2109 if (lp->chip_version == 0x2627)
2112 lp->a.write_bcr(ioaddr, 9, val);
2115 /* set/reset GPSI bit in test register */
2116 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2117 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2119 lp->a.write_csr(ioaddr, 124, val);
2121 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2122 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2123 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2124 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2125 if (lp->options & PCNET32_PORT_ASEL) {
2126 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2127 if (netif_msg_link(lp))
2129 "%s: Setting 100Mb-Full Duplex.\n",
2133 if (lp->phycount < 2) {
2135 * 24 Jun 2004 according AMD, in order to change the PHY,
2136 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2137 * duplex, and/or enable auto negotiation, and clear DANAS
2139 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2140 lp->a.write_bcr(ioaddr, 32,
2141 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2142 /* disable Auto Negotiation, set 10Mpbs, HD */
2143 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2144 if (lp->options & PCNET32_PORT_FD)
2146 if (lp->options & PCNET32_PORT_100)
2148 lp->a.write_bcr(ioaddr, 32, val);
2150 if (lp->options & PCNET32_PORT_ASEL) {
2151 lp->a.write_bcr(ioaddr, 32,
2152 lp->a.read_bcr(ioaddr,
2154 /* enable auto negotiate, setup, disable fd */
2155 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2157 lp->a.write_bcr(ioaddr, 32, val);
2164 struct ethtool_cmd ecmd;
2167 * There is really no good other way to handle multiple PHYs
2168 * other than turning off all automatics
2170 val = lp->a.read_bcr(ioaddr, 2);
2171 lp->a.write_bcr(ioaddr, 2, val & ~2);
2172 val = lp->a.read_bcr(ioaddr, 32);
2173 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2175 if (!(lp->options & PCNET32_PORT_ASEL)) {
2177 ecmd.port = PORT_MII;
2178 ecmd.transceiver = XCVR_INTERNAL;
2179 ecmd.autoneg = AUTONEG_DISABLE;
2182 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2183 bcr9 = lp->a.read_bcr(ioaddr, 9);
2185 if (lp->options & PCNET32_PORT_FD) {
2186 ecmd.duplex = DUPLEX_FULL;
2189 ecmd.duplex = DUPLEX_HALF;
2192 lp->a.write_bcr(ioaddr, 9, bcr9);
2195 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2196 if (lp->phymask & (1 << i)) {
2197 /* isolate all but the first PHY */
2198 bmcr = mdio_read(dev, i, MII_BMCR);
2199 if (first_phy == -1) {
2201 mdio_write(dev, i, MII_BMCR,
2202 bmcr & ~BMCR_ISOLATE);
2204 mdio_write(dev, i, MII_BMCR,
2205 bmcr | BMCR_ISOLATE);
2207 /* use mii_ethtool_sset to setup PHY */
2208 lp->mii_if.phy_id = i;
2209 ecmd.phy_address = i;
2210 if (lp->options & PCNET32_PORT_ASEL) {
2211 mii_ethtool_gset(&lp->mii_if, &ecmd);
2212 ecmd.autoneg = AUTONEG_ENABLE;
2214 mii_ethtool_sset(&lp->mii_if, &ecmd);
2217 lp->mii_if.phy_id = first_phy;
2218 if (netif_msg_link(lp))
2219 printk(KERN_INFO "%s: Using PHY number %d.\n",
2220 dev->name, first_phy);
2224 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2225 val = lp->a.read_csr(ioaddr, CSR3);
2227 lp->a.write_csr(ioaddr, CSR3, val);
2231 lp->init_block.mode =
2232 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2233 pcnet32_load_multicast(dev);
2235 if (pcnet32_init_ring(dev)) {
2240 /* Re-initialize the PCNET32, and start it when done. */
2241 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
2242 offsetof(struct pcnet32_private,
2243 init_block)) & 0xffff);
2244 lp->a.write_csr(ioaddr, 2,
2246 offsetof(struct pcnet32_private, init_block)) >> 16);
2248 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2249 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2251 netif_start_queue(dev);
2253 if (lp->chip_version >= PCNET32_79C970A) {
2254 /* Print the link status and start the watchdog */
2255 pcnet32_check_media(dev, 1);
2256 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2261 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2264 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2265 * reports that doing so triggers a bug in the '974.
2267 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2269 if (netif_msg_ifup(lp))
2271 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2273 (u32) (lp->dma_addr +
2274 offsetof(struct pcnet32_private, init_block)),
2275 lp->a.read_csr(ioaddr, CSR0));
2277 spin_unlock_irqrestore(&lp->lock, flags);
2279 return 0; /* Always succeed */
2282 /* free any allocated skbuffs */
2283 pcnet32_purge_rx_ring(dev);
2286 * Switch back to 16bit mode to avoid problems with dumb
2287 * DOS packet driver after a warm reboot
2289 lp->a.write_bcr(ioaddr, 20, 4);
2292 spin_unlock_irqrestore(&lp->lock, flags);
2293 free_irq(dev->irq, dev);
2298 * The LANCE has been halted for one reason or another (busmaster memory
2299 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2300 * etc.). Modern LANCE variants always reload their ring-buffer
2301 * configuration when restarted, so we must reinitialize our ring
2302 * context before restarting. As part of this reinitialization,
2303 * find all packets still on the Tx ring and pretend that they had been
2304 * sent (in effect, drop the packets on the floor) - the higher-level
2305 * protocols will time out and retransmit. It'd be better to shuffle
2306 * these skbs to a temp list and then actually re-Tx them after
2307 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2310 static void pcnet32_purge_tx_ring(struct net_device *dev)
2312 struct pcnet32_private *lp = dev->priv;
2315 for (i = 0; i < lp->tx_ring_size; i++) {
2316 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2317 wmb(); /* Make sure adapter sees owner change */
2318 if (lp->tx_skbuff[i]) {
2319 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2320 lp->tx_skbuff[i]->len,
2322 dev_kfree_skb_any(lp->tx_skbuff[i]);
2324 lp->tx_skbuff[i] = NULL;
2325 lp->tx_dma_addr[i] = 0;
2329 /* Initialize the PCNET32 Rx and Tx rings. */
2330 static int pcnet32_init_ring(struct net_device *dev)
2332 struct pcnet32_private *lp = dev->priv;
2336 lp->cur_rx = lp->cur_tx = 0;
2337 lp->dirty_rx = lp->dirty_tx = 0;
2339 for (i = 0; i < lp->rx_ring_size; i++) {
2340 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2341 if (rx_skbuff == NULL) {
2343 (rx_skbuff = lp->rx_skbuff[i] =
2344 dev_alloc_skb(PKT_BUF_SZ))) {
2345 /* there is not much, we can do at this point */
2346 if (netif_msg_drv(lp))
2348 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2352 skb_reserve(rx_skbuff, 2);
2356 if (lp->rx_dma_addr[i] == 0)
2357 lp->rx_dma_addr[i] =
2358 pci_map_single(lp->pci_dev, rx_skbuff->data,
2359 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2360 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2361 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2362 wmb(); /* Make sure owner changes after all others are visible */
2363 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2365 /* The Tx buffer address is filled in as needed, but we do need to clear
2366 * the upper ownership bit. */
2367 for (i = 0; i < lp->tx_ring_size; i++) {
2368 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2369 wmb(); /* Make sure adapter sees owner change */
2370 lp->tx_ring[i].base = 0;
2371 lp->tx_dma_addr[i] = 0;
2374 lp->init_block.tlen_rlen =
2375 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2376 for (i = 0; i < 6; i++)
2377 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2378 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2379 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2380 wmb(); /* Make sure all changes are visible */
2384 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2385 * then flush the pending transmit operations, re-initialize the ring,
2386 * and tell the chip to initialize.
2388 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2390 struct pcnet32_private *lp = dev->priv;
2391 unsigned long ioaddr = dev->base_addr;
2395 for (i = 0; i < 100; i++)
2396 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2399 if (i >= 100 && netif_msg_drv(lp))
2401 "%s: pcnet32_restart timed out waiting for stop.\n",
2404 pcnet32_purge_tx_ring(dev);
2405 if (pcnet32_init_ring(dev))
2409 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2412 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2415 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2418 static void pcnet32_tx_timeout(struct net_device *dev)
2420 struct pcnet32_private *lp = dev->priv;
2421 unsigned long ioaddr = dev->base_addr, flags;
2423 spin_lock_irqsave(&lp->lock, flags);
2424 /* Transmitter timeout, serious problems. */
2425 if (pcnet32_debug & NETIF_MSG_DRV)
2427 "%s: transmit timed out, status %4.4x, resetting.\n",
2428 dev->name, lp->a.read_csr(ioaddr, CSR0));
2429 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2430 lp->stats.tx_errors++;
2431 if (netif_msg_tx_err(lp)) {
2434 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2435 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2437 for (i = 0; i < lp->rx_ring_size; i++)
2438 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2439 le32_to_cpu(lp->rx_ring[i].base),
2440 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2441 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2442 le16_to_cpu(lp->rx_ring[i].status));
2443 for (i = 0; i < lp->tx_ring_size; i++)
2444 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2445 le32_to_cpu(lp->tx_ring[i].base),
2446 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2447 le32_to_cpu(lp->tx_ring[i].misc),
2448 le16_to_cpu(lp->tx_ring[i].status));
2451 pcnet32_restart(dev, CSR0_NORMAL);
2453 dev->trans_start = jiffies;
2454 netif_wake_queue(dev);
2456 spin_unlock_irqrestore(&lp->lock, flags);
2459 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2461 struct pcnet32_private *lp = dev->priv;
2462 unsigned long ioaddr = dev->base_addr;
2465 unsigned long flags;
2467 spin_lock_irqsave(&lp->lock, flags);
2469 if (netif_msg_tx_queued(lp)) {
2471 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2472 dev->name, lp->a.read_csr(ioaddr, CSR0));
2475 /* Default status -- will not enable Successful-TxDone
2476 * interrupt when that option is available to us.
2480 /* Fill in a Tx ring entry */
2482 /* Mask to ring buffer boundary. */
2483 entry = lp->cur_tx & lp->tx_mod_mask;
2485 /* Caution: the write order is important here, set the status
2486 * with the "ownership" bits last. */
2488 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
2490 lp->tx_ring[entry].misc = 0x00000000;
2492 lp->tx_skbuff[entry] = skb;
2493 lp->tx_dma_addr[entry] =
2494 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2495 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2496 wmb(); /* Make sure owner changes after all others are visible */
2497 lp->tx_ring[entry].status = le16_to_cpu(status);
2500 lp->stats.tx_bytes += skb->len;
2502 /* Trigger an immediate send poll. */
2503 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2505 dev->trans_start = jiffies;
2507 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2509 netif_stop_queue(dev);
2511 spin_unlock_irqrestore(&lp->lock, flags);
2515 /* The PCNET32 interrupt handler. */
2517 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2519 struct net_device *dev = dev_id;
2520 struct pcnet32_private *lp;
2521 unsigned long ioaddr;
2523 int boguscnt = max_interrupt_work;
2527 if (pcnet32_debug & NETIF_MSG_INTR)
2528 printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2533 ioaddr = dev->base_addr;
2536 spin_lock(&lp->lock);
2538 while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
2539 if (csr0 == 0xffff) {
2540 break; /* PCMCIA remove happened */
2542 /* Acknowledge all of the current interrupt sources ASAP. */
2543 lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f);
2547 if (netif_msg_intr(lp))
2549 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2550 dev->name, csr0, lp->a.read_csr(ioaddr, 0));
2552 if (csr0 & 0x0400) /* Rx interrupt */
2555 if (csr0 & 0x0200) { /* Tx-done interrupt */
2556 must_restart = pcnet32_tx(dev, csr0);
2559 /* Log misc errors. */
2561 lp->stats.tx_errors++; /* Tx babble. */
2562 if (csr0 & 0x1000) {
2564 * this happens when our receive ring is full. This shouldn't
2565 * be a problem as we will see normal rx interrupts for the frames
2566 * in the receive ring. But there are some PCI chipsets (I can
2567 * reproduce this on SP3G with Intel saturn chipset) which have
2568 * sometimes problems and will fill up the receive ring with
2569 * error descriptors. In this situation we don't get a rx
2570 * interrupt, but a missed frame interrupt sooner or later.
2571 * So we try to clean up our receive ring here.
2574 lp->stats.rx_errors++; /* Missed a Rx frame. */
2576 if (csr0 & 0x0800) {
2577 if (netif_msg_drv(lp))
2579 "%s: Bus master arbitration failure, status %4.4x.\n",
2581 /* unlike for the lance, there is no restart needed */
2585 /* reset the chip to clear the error condition, then restart */
2586 lp->a.reset(ioaddr);
2587 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2588 pcnet32_restart(dev, CSR0_START);
2589 netif_wake_queue(dev);
2593 /* Set interrupt enable. */
2594 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2596 if (netif_msg_intr(lp))
2597 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2598 dev->name, lp->a.read_csr(ioaddr, CSR0));
2600 spin_unlock(&lp->lock);
2605 static int pcnet32_close(struct net_device *dev)
2607 unsigned long ioaddr = dev->base_addr;
2608 struct pcnet32_private *lp = dev->priv;
2609 unsigned long flags;
2611 del_timer_sync(&lp->watchdog_timer);
2613 netif_stop_queue(dev);
2615 spin_lock_irqsave(&lp->lock, flags);
2617 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2619 if (netif_msg_ifdown(lp))
2621 "%s: Shutting down ethercard, status was %2.2x.\n",
2622 dev->name, lp->a.read_csr(ioaddr, CSR0));
2624 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2625 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2628 * Switch back to 16bit mode to avoid problems with dumb
2629 * DOS packet driver after a warm reboot
2631 lp->a.write_bcr(ioaddr, 20, 4);
2633 spin_unlock_irqrestore(&lp->lock, flags);
2635 free_irq(dev->irq, dev);
2637 spin_lock_irqsave(&lp->lock, flags);
2639 pcnet32_purge_rx_ring(dev);
2640 pcnet32_purge_tx_ring(dev);
2642 spin_unlock_irqrestore(&lp->lock, flags);
2647 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2649 struct pcnet32_private *lp = dev->priv;
2650 unsigned long ioaddr = dev->base_addr;
2651 unsigned long flags;
2653 spin_lock_irqsave(&lp->lock, flags);
2654 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2655 spin_unlock_irqrestore(&lp->lock, flags);
2660 /* taken from the sunlance driver, which it took from the depca driver */
2661 static void pcnet32_load_multicast(struct net_device *dev)
2663 struct pcnet32_private *lp = dev->priv;
2664 volatile struct pcnet32_init_block *ib = &lp->init_block;
2665 volatile u16 *mcast_table = (u16 *) & ib->filter;
2666 struct dev_mc_list *dmi = dev->mc_list;
2667 unsigned long ioaddr = dev->base_addr;
2672 /* set all multicast bits */
2673 if (dev->flags & IFF_ALLMULTI) {
2674 ib->filter[0] = 0xffffffff;
2675 ib->filter[1] = 0xffffffff;
2676 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2677 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2678 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2679 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2682 /* clear the multicast filter */
2687 for (i = 0; i < dev->mc_count; i++) {
2688 addrs = dmi->dmi_addr;
2691 /* multicast address? */
2695 crc = ether_crc_le(6, addrs);
2697 mcast_table[crc >> 4] =
2698 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2699 (1 << (crc & 0xf)));
2701 for (i = 0; i < 4; i++)
2702 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2703 le16_to_cpu(mcast_table[i]));
2708 * Set or clear the multicast filter for this adaptor.
2710 static void pcnet32_set_multicast_list(struct net_device *dev)
2712 unsigned long ioaddr = dev->base_addr, flags;
2713 struct pcnet32_private *lp = dev->priv;
2714 int csr15, suspended;
2716 spin_lock_irqsave(&lp->lock, flags);
2717 suspended = pcnet32_suspend(dev, &flags, 0);
2718 csr15 = lp->a.read_csr(ioaddr, CSR15);
2719 if (dev->flags & IFF_PROMISC) {
2720 /* Log any net taps. */
2721 if (netif_msg_hw(lp))
2722 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2724 lp->init_block.mode =
2725 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2727 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2729 lp->init_block.mode =
2730 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2731 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2732 pcnet32_load_multicast(dev);
2737 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2738 csr5 = lp->a.read_csr(ioaddr, CSR5);
2739 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2741 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2742 pcnet32_restart(dev, CSR0_NORMAL);
2743 netif_wake_queue(dev);
2746 spin_unlock_irqrestore(&lp->lock, flags);
2749 /* This routine assumes that the lp->lock is held */
2750 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2752 struct pcnet32_private *lp = dev->priv;
2753 unsigned long ioaddr = dev->base_addr;
2759 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2760 val_out = lp->a.read_bcr(ioaddr, 34);
2765 /* This routine assumes that the lp->lock is held */
2766 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2768 struct pcnet32_private *lp = dev->priv;
2769 unsigned long ioaddr = dev->base_addr;
2774 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2775 lp->a.write_bcr(ioaddr, 34, val);
2778 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2780 struct pcnet32_private *lp = dev->priv;
2782 unsigned long flags;
2784 /* SIOC[GS]MIIxxx ioctls */
2786 spin_lock_irqsave(&lp->lock, flags);
2787 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2788 spin_unlock_irqrestore(&lp->lock, flags);
2796 static int pcnet32_check_otherphy(struct net_device *dev)
2798 struct pcnet32_private *lp = dev->priv;
2799 struct mii_if_info mii = lp->mii_if;
2803 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2804 if (i == lp->mii_if.phy_id)
2805 continue; /* skip active phy */
2806 if (lp->phymask & (1 << i)) {
2808 if (mii_link_ok(&mii)) {
2809 /* found PHY with active link */
2810 if (netif_msg_link(lp))
2812 "%s: Using PHY number %d.\n",
2815 /* isolate inactive phy */
2817 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2818 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2819 bmcr | BMCR_ISOLATE);
2821 /* de-isolate new phy */
2822 bmcr = mdio_read(dev, i, MII_BMCR);
2823 mdio_write(dev, i, MII_BMCR,
2824 bmcr & ~BMCR_ISOLATE);
2826 /* set new phy address */
2827 lp->mii_if.phy_id = i;
2836 * Show the status of the media. Similar to mii_check_media however it
2837 * correctly shows the link speed for all (tested) pcnet32 variants.
2838 * Devices with no mii just report link state without speed.
2840 * Caller is assumed to hold and release the lp->lock.
2843 static void pcnet32_check_media(struct net_device *dev, int verbose)
2845 struct pcnet32_private *lp = dev->priv;
2847 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2851 curr_link = mii_link_ok(&lp->mii_if);
2853 ulong ioaddr = dev->base_addr; /* card base I/O address */
2854 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2857 if (prev_link || verbose) {
2858 netif_carrier_off(dev);
2859 if (netif_msg_link(lp))
2860 printk(KERN_INFO "%s: link down\n", dev->name);
2862 if (lp->phycount > 1) {
2863 curr_link = pcnet32_check_otherphy(dev);
2866 } else if (verbose || !prev_link) {
2867 netif_carrier_on(dev);
2869 if (netif_msg_link(lp)) {
2870 struct ethtool_cmd ecmd;
2871 mii_ethtool_gset(&lp->mii_if, &ecmd);
2873 "%s: link up, %sMbps, %s-duplex\n",
2875 (ecmd.speed == SPEED_100) ? "100" : "10",
2877 DUPLEX_FULL) ? "full" : "half");
2879 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2880 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2881 if (lp->mii_if.full_duplex)
2885 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2888 if (netif_msg_link(lp))
2889 printk(KERN_INFO "%s: link up\n", dev->name);
2895 * Check for loss of link and link establishment.
2896 * Can not use mii_check_media because it does nothing if mode is forced.
2899 static void pcnet32_watchdog(struct net_device *dev)
2901 struct pcnet32_private *lp = dev->priv;
2902 unsigned long flags;
2904 /* Print the link status if it has changed */
2905 spin_lock_irqsave(&lp->lock, flags);
2906 pcnet32_check_media(dev, 0);
2907 spin_unlock_irqrestore(&lp->lock, flags);
2909 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2912 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2914 struct net_device *dev = pci_get_drvdata(pdev);
2917 struct pcnet32_private *lp = dev->priv;
2919 unregister_netdev(dev);
2920 pcnet32_free_ring(dev);
2921 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2922 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2924 pci_disable_device(pdev);
2925 pci_set_drvdata(pdev, NULL);
2929 static struct pci_driver pcnet32_driver = {
2931 .probe = pcnet32_probe_pci,
2932 .remove = __devexit_p(pcnet32_remove_one),
2933 .id_table = pcnet32_pci_tbl,
2936 /* An additional parameter that may be passed in... */
2937 static int debug = -1;
2938 static int tx_start_pt = -1;
2939 static int pcnet32_have_pci;
2941 module_param(debug, int, 0);
2942 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2943 module_param(max_interrupt_work, int, 0);
2944 MODULE_PARM_DESC(max_interrupt_work,
2945 DRV_NAME " maximum events handled per interrupt");
2946 module_param(rx_copybreak, int, 0);
2947 MODULE_PARM_DESC(rx_copybreak,
2948 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2949 module_param(tx_start_pt, int, 0);
2950 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2951 module_param(pcnet32vlb, int, 0);
2952 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2953 module_param_array(options, int, NULL, 0);
2954 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2955 module_param_array(full_duplex, int, NULL, 0);
2956 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2957 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2958 module_param_array(homepna, int, NULL, 0);
2959 MODULE_PARM_DESC(homepna,
2961 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2963 MODULE_AUTHOR("Thomas Bogendoerfer");
2964 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2965 MODULE_LICENSE("GPL");
2967 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2969 static int __init pcnet32_init_module(void)
2971 printk(KERN_INFO "%s", version);
2973 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2975 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2976 tx_start = tx_start_pt;
2978 /* find the PCI devices */
2979 if (!pci_register_driver(&pcnet32_driver))
2980 pcnet32_have_pci = 1;
2982 /* should we find any remaining VLbus devices ? */
2984 pcnet32_probe_vlbus(pcnet32_portlist);
2986 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2987 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2989 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2992 static void __exit pcnet32_cleanup_module(void)
2994 struct net_device *next_dev;
2996 while (pcnet32_dev) {
2997 struct pcnet32_private *lp = pcnet32_dev->priv;
2998 next_dev = lp->next;
2999 unregister_netdev(pcnet32_dev);
3000 pcnet32_free_ring(pcnet32_dev);
3001 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3002 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
3003 free_netdev(pcnet32_dev);
3004 pcnet32_dev = next_dev;
3007 if (pcnet32_have_pci)
3008 pci_unregister_driver(&pcnet32_driver);
3011 module_init(pcnet32_init_module);
3012 module_exit(pcnet32_cleanup_module);