1 /************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
17 #define BIT(loc) (0x8000000000000000ULL >> (loc))
18 #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19 #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
34 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
35 #define MAX_FLICKER_TIME 60000 /* 60 Secs */
37 /* Maximum outstanding splits to be configured into xena. */
38 typedef enum xena_max_outstanding_splits {
39 XENA_ONE_SPLIT_TRANSACTION = 0,
40 XENA_TWO_SPLIT_TRANSACTION = 1,
41 XENA_THREE_SPLIT_TRANSACTION = 2,
42 XENA_FOUR_SPLIT_TRANSACTION = 3,
43 XENA_EIGHT_SPLIT_TRANSACTION = 4,
44 XENA_TWELVE_SPLIT_TRANSACTION = 5,
45 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
46 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
47 } xena_max_outstanding_splits;
48 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
50 /* OS concerned variables and constants */
51 #define WATCH_DOG_TIMEOUT 15*HZ
53 #define ALIGN_SIZE 127
54 #define PCIX_COMMAND_REGISTER 0x62
57 * Debug related variables.
59 /* different debug levels. */
66 /* Global variable that defines the present debug level of the driver. */
67 int debug_level = ERR_DBG; /* Default level. */
69 /* DEBUG message print. */
70 #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
72 /* Protocol assist features of the NIC */
73 #define L3_CKSUM_OK 0xFFFF
74 #define L4_CKSUM_OK 0xFFFF
75 #define S2IO_JUMBO_SIZE 9600
77 /* Driver statistics maintained by driver */
79 unsigned long long single_ecc_errs;
80 unsigned long long double_ecc_errs;
83 /* The statistics block of Xena */
84 typedef struct stat_block {
85 /* Tx MAC statistics counters. */
91 u64 tmac_pause_ctrl_frms;
94 u32 tmac_any_err_frms;
96 u64 tmac_ttl_less_fb_octets;
97 u64 tmac_vld_ip_octets;
106 /* Rx MAC Statistics counters. */
107 u32 rmac_data_octets;
109 u64 rmac_fcs_err_frms;
111 u32 rmac_vld_bcst_frms;
112 u32 rmac_vld_mcst_frms;
113 u32 rmac_out_rng_len_err_frms;
114 u32 rmac_in_rng_len_err_frms;
116 u64 rmac_pause_ctrl_frms;
117 u64 rmac_unsup_ctrl_frms;
118 u32 rmac_accepted_ucst_frms;
120 u32 rmac_discarded_frms;
121 u32 rmac_accepted_nucst_frms;
123 u32 rmac_drop_events;
124 u64 rmac_ttl_less_fb_octets;
127 u32 rmac_usized_frms;
130 u32 rmac_osized_frms;
132 u32 rmac_jabber_frms;
133 u64 rmac_ttl_64_frms;
134 u64 rmac_ttl_65_127_frms;
136 u64 rmac_ttl_128_255_frms;
137 u64 rmac_ttl_256_511_frms;
139 u64 rmac_ttl_512_1023_frms;
140 u64 rmac_ttl_1024_1518_frms;
149 u32 rmac_err_drp_udp;
151 u64 rmac_xgmii_err_sym;
170 u64 rmac_xgmii_data_err_cnt;
171 u64 rmac_xgmii_ctrl_err_cnt;
173 u32 rmac_accepted_ip;
175 /* PCI/PCI-X Read transaction statistics. */
179 u32 new_rd_req_rtry_cnt;
181 /* PCI/PCI-X Write/Read transaction statistics. */
183 u32 wr_rtry_rd_ack_cnt;
184 u32 new_wr_req_rtry_cnt;
189 /* PCI/PCI-X Write / DMA Transaction statistics. */
191 u32 rd_rtry_wr_ack_cnt;
201 * Structures representing different init time configuration
202 * parameters of the NIC.
205 #define MAX_TX_FIFOS 8
206 #define MAX_RX_RINGS 8
208 /* FIFO mappings for all possible number of fifos configured */
209 int fifo_map[][MAX_TX_FIFOS] = {
210 {0, 0, 0, 0, 0, 0, 0, 0},
211 {0, 0, 0, 0, 1, 1, 1, 1},
212 {0, 0, 0, 1, 1, 1, 2, 2},
213 {0, 0, 1, 1, 2, 2, 3, 3},
214 {0, 0, 1, 1, 2, 2, 3, 4},
215 {0, 0, 1, 1, 2, 3, 4, 5},
216 {0, 0, 1, 2, 3, 4, 5, 6},
217 {0, 1, 2, 3, 4, 5, 6, 7},
220 /* Maintains Per FIFO related information. */
221 typedef struct tx_fifo_config {
222 #define MAX_AVAILABLE_TXDS 8192
223 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
224 /* Priority definition */
225 #define TX_FIFO_PRI_0 0 /*Highest */
226 #define TX_FIFO_PRI_1 1
227 #define TX_FIFO_PRI_2 2
228 #define TX_FIFO_PRI_3 3
229 #define TX_FIFO_PRI_4 4
230 #define TX_FIFO_PRI_5 5
231 #define TX_FIFO_PRI_6 6
232 #define TX_FIFO_PRI_7 7 /*lowest */
233 u8 fifo_priority; /* specifies pointer level for FIFO */
234 /* user should not set twos fifos with same pri */
236 #define NO_SNOOP_TXD 0x01
237 #define NO_SNOOP_TXD_BUFFER 0x02
241 /* Maintains per Ring related information */
242 typedef struct rx_ring_config {
243 u32 num_rxd; /*No of RxDs per Rx Ring */
244 #define RX_RING_PRI_0 0 /* highest */
245 #define RX_RING_PRI_1 1
246 #define RX_RING_PRI_2 2
247 #define RX_RING_PRI_3 3
248 #define RX_RING_PRI_4 4
249 #define RX_RING_PRI_5 5
250 #define RX_RING_PRI_6 6
251 #define RX_RING_PRI_7 7 /* lowest */
253 u8 ring_priority; /*Specifies service priority of ring */
254 /* OSM should not set any two rings with same priority */
255 u8 ring_org; /*Organization of ring */
256 #define RING_ORG_BUFF1 0x01
257 #define RX_RING_ORG_BUFF3 0x03
258 #define RX_RING_ORG_BUFF5 0x05
261 #define NO_SNOOP_RXD 0x01
262 #define NO_SNOOP_RXD_BUFFER 0x02
265 /* This structure provides contains values of the tunable parameters
268 struct config_param {
270 u32 tx_fifo_num; /*Number of Tx FIFOs */
272 u8 fifo_mapping[MAX_TX_FIFOS];
273 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
274 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
276 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
279 u32 rx_ring_num; /*Number of receive rings */
280 #define MAX_RX_BLOCKS_PER_RING 150
282 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
284 #define HEADER_ETHERNET_II_802_3_SIZE 14
285 #define HEADER_802_2_SIZE 3
286 #define HEADER_SNAP_SIZE 5
287 #define HEADER_VLAN_SIZE 4
290 #define MAX_PYLD 1500
291 #define MAX_MTU (MAX_PYLD+18)
292 #define MAX_MTU_VLAN (MAX_PYLD+22)
293 #define MAX_PYLD_JUMBO 9600
294 #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
295 #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
299 /* Structure representing MAC Addrs */
300 typedef struct mac_addr {
301 u8 mac_addr[ETH_ALEN];
304 /* Structure that represent every FIFO element in the BAR1
307 typedef struct _TxFIFO_element {
311 #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
312 #define TX_FIFO_FIRST_LIST BIT(14)
313 #define TX_FIFO_LAST_LIST BIT(15)
314 #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
315 #define TX_FIFO_SPECIAL_FUNC BIT(23)
316 #define TX_FIFO_DS_NO_SNOOP BIT(31)
317 #define TX_FIFO_BUFF_NO_SNOOP BIT(30)
320 /* Tx descriptor structure */
321 typedef struct _TxD {
324 #define TXD_LIST_OWN_XENA BIT(7)
325 #define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
326 #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
327 #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
328 #define TXD_GATHER_CODE (BIT(22) | BIT(23))
329 #define TXD_GATHER_CODE_FIRST BIT(22)
330 #define TXD_GATHER_CODE_LAST BIT(23)
331 #define TXD_TCP_LSO_EN BIT(30)
332 #define TXD_UDP_COF_EN BIT(31)
333 #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
334 #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
337 #define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
338 #define TXD_TX_CKO_IPV4_EN BIT(5)
339 #define TXD_TX_CKO_TCP_EN BIT(6)
340 #define TXD_TX_CKO_UDP_EN BIT(7)
341 #define TXD_VLAN_ENABLE BIT(15)
342 #define TXD_VLAN_TAG(val) vBIT(val,16,16)
343 #define TXD_INT_NUMBER(val) vBIT(val,34,6)
344 #define TXD_INT_TYPE_PER_LIST BIT(47)
345 #define TXD_INT_TYPE_UTILZ BIT(46)
346 #define TXD_SET_MARKER vBIT(0x6,0,4)
349 u64 Host_Control; /* reserved for host */
352 /* Structure to hold the phy and virt addr of every TxDL. */
353 typedef struct list_info_hold {
354 dma_addr_t list_phy_addr;
355 void *list_virt_addr;
358 /* Rx descriptor structure */
359 typedef struct _RxD_t {
360 u64 Host_Control; /* reserved for host */
362 #define RXD_OWN_XENA BIT(7)
363 #define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
364 #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
365 #define RXD_FRAME_PROTO_IPV4 BIT(27)
366 #define RXD_FRAME_PROTO_IPV6 BIT(28)
367 #define RXD_FRAME_IP_FRAG BIT(29)
368 #define RXD_FRAME_PROTO_TCP BIT(30)
369 #define RXD_FRAME_PROTO_UDP BIT(31)
370 #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
371 #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
372 #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
375 #define THE_RXD_MARK 0x3
376 #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
377 #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
379 #ifndef CONFIG_2BUFF_MODE
380 #define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
381 #define SET_BUFFER0_SIZE(val) vBIT(val,2,14)
383 #define MASK_BUFFER0_SIZE vBIT(0xFF,2,14)
384 #define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
385 #define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
386 #define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
387 #define SET_BUFFER1_SIZE(val) vBIT(val,16,16)
388 #define SET_BUFFER2_SIZE(val) vBIT(val,32,16)
391 #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
392 #define SET_VLAN_TAG(val) vBIT(val,48,16)
393 #define SET_NUM_TAG(val) vBIT(val,16,32)
395 #ifndef CONFIG_2BUFF_MODE
396 #define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
398 #define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
400 #define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
402 #define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
409 #ifdef CONFIG_2BUFF_MODE
415 /* Structure that represents the Rx descriptor block which contains
416 * 128 Rx descriptors.
418 #ifndef CONFIG_2BUFF_MODE
419 typedef struct _RxD_block {
420 #define MAX_RXDS_PER_BLOCK 127
421 RxD_t rxd[MAX_RXDS_PER_BLOCK];
424 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
425 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
427 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
428 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
429 * the upper 32 bits should
433 typedef struct _RxD_block {
434 #define MAX_RXDS_PER_BLOCK 85
435 RxD_t rxd[MAX_RXDS_PER_BLOCK];
437 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
438 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
440 u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
442 #define SIZE_OF_BLOCK 4096
444 /* Structure to hold virtual addresses of Buf0 and Buf1 in
446 typedef struct bufAdd {
454 /* Structure which stores all the MAC control parameters */
456 /* This structure stores the offset of the RxD in the ring
457 * from which the Rx Interrupt processor can start picking
458 * up the RxDs for processing.
460 typedef struct _rx_curr_get_info_t {
464 } rx_curr_get_info_t;
466 typedef rx_curr_get_info_t rx_curr_put_info_t;
468 /* This structure stores the offset of the TxDl in the FIFO
469 * from which the Tx Interrupt processor can start picking
470 * up the TxDLs for send complete interrupt processing.
475 } tx_curr_get_info_t;
477 typedef tx_curr_get_info_t tx_curr_put_info_t;
479 /* Structure that holds the Phy and virt addresses of the Blocks */
480 typedef struct rx_block_info {
481 RxD_t *block_virt_addr;
482 dma_addr_t block_dma_addr;
485 /* pre declaration of the nic structure */
486 typedef struct s2io_nic nic_t;
488 /* Ring specific structure */
489 typedef struct ring_info {
490 /* The ring number */
494 * Place holders for the virtual and physical addresses of
497 rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
502 * Put pointer info which indictes which RxD has to be replenished
505 rx_curr_put_info_t rx_curr_put_info;
508 * Get pointer info which indictes which is the last RxD that was
509 * processed by the driver.
511 rx_curr_get_info_t rx_curr_get_info;
513 #ifndef CONFIG_S2IO_NAPI
514 /* Index to the absolute position of the put pointer of Rx ring */
518 #ifdef CONFIG_2BUFF_MODE
519 /* Buffer Address store. */
525 /* Fifo specific structure */
526 typedef struct fifo_info {
530 /* Maximum TxDs per TxDL */
533 /* Place holder of all the TX List's Phy and Virt addresses. */
534 list_info_hold_t *list_info;
537 * Current offset within the tx FIFO where driver would write
540 tx_curr_put_info_t tx_curr_put_info;
543 * Current offset within tx FIFO from where the driver would start freeing
546 tx_curr_get_info_t tx_curr_get_info;
551 /* Infomation related to the Tx and Rx FIFOs and Rings of Xena
552 * is maintained in this structure.
554 typedef struct mac_info {
556 /* logical pointer of start of each Tx FIFO */
557 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
559 /* Fifo specific structure */
560 fifo_info_t fifos[MAX_TX_FIFOS];
563 /* Ring specific structure */
564 ring_info_t rings[MAX_RX_RINGS];
567 u16 mc_pause_threshold_q0q3;
568 u16 mc_pause_threshold_q4q7;
570 void *stats_mem; /* orignal pointer to allocated mem */
571 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
573 StatInfo_t *stats_info; /* Logical address of the stat block */
576 /* structure representing the user defined MAC addresses */
582 /* Default Tunable parameters of the NIC. */
583 #define DEFAULT_FIFO_LEN 4096
584 #define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
585 #define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
586 #define SMALL_BLK_CNT 30
587 #define LARGE_BLK_CNT 100
589 /* Structure representing one instance of the NIC */
591 #ifdef CONFIG_S2IO_NAPI
593 * Count of packets to be processed in a given iteration, it will be indicated
594 * by the quota field of the device structure when NAPI is enabled.
598 struct net_device *dev;
599 mac_info_t mac_control;
600 struct config_param config;
601 struct pci_dev *pdev;
604 #define MAX_MAC_SUPPORTED 16
605 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
607 macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
608 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
610 struct net_device_stats stats;
612 int device_close_flag;
613 int device_enabled_once;
616 struct tasklet_struct task;
617 volatile unsigned long tasklet_status;
619 /* Space to back up the PCI config space */
620 u32 config_space[256 / sizeof(u32)];
622 atomic_t rx_bufs_left[MAX_RX_RINGS];
625 #ifndef CONFIG_S2IO_NAPI
632 #define MAX_ADDRS_SUPPORTED 64
635 usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
646 /* Id timer, used to blink NIC to physically identify NIC. */
647 struct timer_list id_timer;
649 /* Restart timer, used to restart NIC if the device is stuck and
650 * a schedule task that will set the correct Link state once the
651 * NIC's PHY has stabilized after a state change.
654 struct tq_struct rst_timer_task;
655 struct tq_struct set_link_task;
657 struct work_struct rst_timer_task;
658 struct work_struct set_link_task;
661 /* Flag that can be used to turn on or turn off the Rx checksum
666 /* after blink, the adapter must be restored with original
671 /* Last known link state. */
680 volatile unsigned long link_state;
683 #define RESET_ERROR 1;
686 /* OS related system calls */
688 static inline u64 readq(void __iomem *addr)
691 ret = readl(addr + 4);
693 (u64) ret |= readl(addr);
700 static inline void writeq(u64 val, void __iomem *addr)
702 writel((u32) (val), addr);
703 writel((u32) (val >> 32), (addr + 4));
706 /* In 32 bit modes, some registers have to be written in a
707 * particular order to expect correct hardware operation. The
708 * macro SPECIAL_REG_WRITE is used to perform such ordered
709 * writes. Defines UF (Upper First) and LF (Lower First) will
710 * be used to specify the required write order.
714 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
717 writel((u32) (val), addr);
718 writel((u32) (val >> 32), (addr + 4));
720 writel((u32) (val >> 32), (addr + 4));
721 writel((u32) (val), addr);
725 #define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
728 /* Interrupt related values of Xena */
730 #define ENABLE_INTRS 1
731 #define DISABLE_INTRS 2
733 /* Highest level interrupt blocks */
734 #define TX_PIC_INTR (0x0001<<0)
735 #define TX_DMA_INTR (0x0001<<1)
736 #define TX_MAC_INTR (0x0001<<2)
737 #define TX_XGXS_INTR (0x0001<<3)
738 #define TX_TRAFFIC_INTR (0x0001<<4)
739 #define RX_PIC_INTR (0x0001<<5)
740 #define RX_DMA_INTR (0x0001<<6)
741 #define RX_MAC_INTR (0x0001<<7)
742 #define RX_XGXS_INTR (0x0001<<8)
743 #define RX_TRAFFIC_INTR (0x0001<<9)
744 #define MC_INTR (0x0001<<10)
745 #define ENA_ALL_INTRS ( TX_PIC_INTR | \
757 /* Interrupt masks for the general interrupt mask register */
758 #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
760 #define TXPIC_INT_M BIT(0)
761 #define TXDMA_INT_M BIT(1)
762 #define TXMAC_INT_M BIT(2)
763 #define TXXGXS_INT_M BIT(3)
764 #define TXTRAFFIC_INT_M BIT(8)
765 #define PIC_RX_INT_M BIT(32)
766 #define RXDMA_INT_M BIT(33)
767 #define RXMAC_INT_M BIT(34)
768 #define MC_INT_M BIT(35)
769 #define RXXGXS_INT_M BIT(36)
770 #define RXTRAFFIC_INT_M BIT(40)
772 /* PIC level Interrupts TODO*/
774 /* DMA level Inressupts */
775 #define TXDMA_PFC_INT_M BIT(0)
776 #define TXDMA_PCC_INT_M BIT(2)
778 /* PFC block interrupts */
779 #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
781 /* PCC block interrupts. */
782 #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
785 #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
787 * Prototype declaration.
789 static int __devinit s2io_init_nic(struct pci_dev *pdev,
790 const struct pci_device_id *pre);
791 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
792 static int init_shared_mem(struct s2io_nic *sp);
793 static void free_shared_mem(struct s2io_nic *sp);
794 static int init_nic(struct s2io_nic *nic);
795 static void rx_intr_handler(ring_info_t *ring_data);
796 static void tx_intr_handler(fifo_info_t *fifo_data);
797 static void alarm_intr_handler(struct s2io_nic *sp);
799 static int s2io_starter(void);
800 void s2io_closer(void);
801 static void s2io_tx_watchdog(struct net_device *dev);
802 static void s2io_tasklet(unsigned long dev_addr);
803 static void s2io_set_multicast(struct net_device *dev);
804 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
805 void s2io_link(nic_t * sp, int link);
806 void s2io_reset(nic_t * sp);
807 #if defined(CONFIG_S2IO_NAPI)
808 static int s2io_poll(struct net_device *dev, int *budget);
810 static void s2io_init_pci(nic_t * sp);
811 int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
812 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
813 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
814 static struct ethtool_ops netdev_ethtool_ops;
815 static void s2io_set_link(unsigned long data);
816 int s2io_set_swapper(nic_t * sp);
817 static void s2io_card_down(nic_t *nic);
818 static int s2io_card_up(nic_t *nic);
819 int get_xena_rev_id(struct pci_dev *pdev);