2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.22"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
69 #define TX_MIN_PENDING 64
70 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
150 static void sky2_set_multicast(struct net_device *dev);
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (!(ctrl & GM_SMI_CT_BUSY))
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
210 __gm_phy_read(hw, port, reg, &v);
215 static void sky2_power_on(struct sky2_hw *hw)
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
255 sky2_read32(hw, B2_GP_IO);
259 static void sky2_power_aux(struct sky2_hw *hw)
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
433 adv |= fiber_fc_adv[sky2->flow_mode];
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
445 switch (sky2->speed) {
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
463 reg |= gm_fc_disable[sky2->flow_mode];
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
472 gma_write16(hw, port, GM_GP_CTRL, reg);
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
670 /* enable Power Down */
671 ctrl |= PHY_M_PC_POW_D_ENA;
672 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
675 /* set IEEE compatible Power Down Mode (dev. #4.99) */
676 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
679 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
680 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
681 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
682 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
683 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
686 /* Force a renegotiation */
687 static void sky2_phy_reinit(struct sky2_port *sky2)
689 spin_lock_bh(&sky2->phy_lock);
690 sky2_phy_init(sky2->hw, sky2->port);
691 spin_unlock_bh(&sky2->phy_lock);
694 /* Put device in state to listen for Wake On Lan */
695 static void sky2_wol_init(struct sky2_port *sky2)
697 struct sky2_hw *hw = sky2->hw;
698 unsigned port = sky2->port;
699 enum flow_control save_mode;
703 /* Bring hardware out of reset */
704 sky2_write16(hw, B0_CTST, CS_RST_CLR);
705 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
707 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
708 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
711 * sky2_reset will re-enable on resume
713 save_mode = sky2->flow_mode;
714 ctrl = sky2->advertising;
716 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
717 sky2->flow_mode = FC_NONE;
719 spin_lock_bh(&sky2->phy_lock);
720 sky2_phy_power_up(hw, port);
721 sky2_phy_init(hw, port);
722 spin_unlock_bh(&sky2->phy_lock);
724 sky2->flow_mode = save_mode;
725 sky2->advertising = ctrl;
727 /* Set GMAC to no flow control and auto update for speed/duplex */
728 gma_write16(hw, port, GM_GP_CTRL,
729 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
730 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
732 /* Set WOL address */
733 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
734 sky2->netdev->dev_addr, ETH_ALEN);
736 /* Turn on appropriate WOL control bits */
737 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
739 if (sky2->wol & WAKE_PHY)
740 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
742 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
744 if (sky2->wol & WAKE_MAGIC)
745 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
747 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
749 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
750 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
752 /* Turn on legacy PCI-Express PME mode */
753 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
754 reg1 |= PCI_Y2_PME_LEGACY;
755 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
758 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
762 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
764 struct net_device *dev = hw->dev[port];
766 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
767 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
768 hw->chip_id == CHIP_ID_YUKON_FE_P ||
769 hw->chip_id == CHIP_ID_YUKON_SUPR) {
770 /* Yukon-Extreme B0 and further Extreme devices */
771 /* enable Store & Forward mode for TX */
773 if (dev->mtu <= ETH_DATA_LEN)
774 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
775 TX_JUMBO_DIS | TX_STFW_ENA);
778 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
779 TX_JUMBO_ENA| TX_STFW_ENA);
781 if (dev->mtu <= ETH_DATA_LEN)
782 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
784 /* set Tx GMAC FIFO Almost Empty Threshold */
785 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
786 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
788 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
790 /* Can't do offload because of lack of store/forward */
791 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
796 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
798 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
802 const u8 *addr = hw->dev[port]->dev_addr;
804 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
805 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
807 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
809 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
810 /* WA DEV_472 -- looks like crossed wires on port 2 */
811 /* clear GMAC 1 Control reset */
812 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
814 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
815 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
816 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
817 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
818 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
821 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
823 /* Enable Transmit FIFO Underrun */
824 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
826 spin_lock_bh(&sky2->phy_lock);
827 sky2_phy_power_up(hw, port);
828 sky2_phy_init(hw, port);
829 spin_unlock_bh(&sky2->phy_lock);
832 reg = gma_read16(hw, port, GM_PHY_ADDR);
833 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
835 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
836 gma_read16(hw, port, i);
837 gma_write16(hw, port, GM_PHY_ADDR, reg);
839 /* transmit control */
840 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
842 /* receive control reg: unicast + multicast + no FCS */
843 gma_write16(hw, port, GM_RX_CTRL,
844 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
846 /* transmit flow control */
847 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
849 /* transmit parameter */
850 gma_write16(hw, port, GM_TX_PARAM,
851 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
852 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
853 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
854 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
856 /* serial mode register */
857 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
858 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
860 if (hw->dev[port]->mtu > ETH_DATA_LEN)
861 reg |= GM_SMOD_JUMBO_ENA;
863 gma_write16(hw, port, GM_SERIAL_MODE, reg);
865 /* virtual address for data */
866 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
868 /* physical address: used for pause frames */
869 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
871 /* ignore counter overflows */
872 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
873 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
874 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
876 /* Configure Rx MAC FIFO */
877 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
878 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
879 if (hw->chip_id == CHIP_ID_YUKON_EX ||
880 hw->chip_id == CHIP_ID_YUKON_FE_P)
881 rx_reg |= GMF_RX_OVER_ON;
883 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
885 if (hw->chip_id == CHIP_ID_YUKON_XL) {
886 /* Hardware errata - clear flush mask */
887 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
889 /* Flush Rx MAC FIFO on any flow control or error */
890 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
893 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
894 reg = RX_GMF_FL_THR_DEF + 1;
895 /* Another magic mystery workaround from sk98lin */
896 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
897 hw->chip_rev == CHIP_REV_YU_FE2_A0)
899 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
901 /* Configure Tx MAC FIFO */
902 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
903 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
905 /* On chips without ram buffer, pause is controled by MAC level */
906 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
907 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
908 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
910 sky2_set_tx_stfwd(hw, port);
913 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
914 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
915 /* disable dynamic watermark */
916 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
917 reg &= ~TX_DYN_WM_ENA;
918 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
922 /* Assign Ram Buffer allocation to queue */
923 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
927 /* convert from K bytes to qwords used for hw register */
930 end = start + space - 1;
932 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
933 sky2_write32(hw, RB_ADDR(q, RB_START), start);
934 sky2_write32(hw, RB_ADDR(q, RB_END), end);
935 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
936 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
938 if (q == Q_R1 || q == Q_R2) {
939 u32 tp = space - space/4;
941 /* On receive queue's set the thresholds
942 * give receiver priority when > 3/4 full
943 * send pause when down to 2K
945 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
946 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
949 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
950 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
952 /* Enable store & forward on Tx queue's because
953 * Tx FIFO is only 1K on Yukon
955 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
958 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
959 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
962 /* Setup Bus Memory Interface */
963 static void sky2_qset(struct sky2_hw *hw, u16 q)
965 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
966 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
967 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
968 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
971 /* Setup prefetch unit registers. This is the interface between
972 * hardware and driver list elements
974 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
977 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
978 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
979 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
980 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
981 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
984 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
987 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
989 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
991 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
996 static void tx_init(struct sky2_port *sky2)
998 struct sky2_tx_le *le;
1000 sky2->tx_prod = sky2->tx_cons = 0;
1001 sky2->tx_tcpsum = 0;
1002 sky2->tx_last_mss = 0;
1004 le = get_tx_le(sky2);
1006 le->opcode = OP_ADDR64 | HW_OWNER;
1009 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1010 struct sky2_tx_le *le)
1012 return sky2->tx_ring + (le - sky2->tx_le);
1015 /* Update chip's next pointer */
1016 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1018 /* Make sure write' to descriptors are complete before we tell hardware */
1020 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1022 /* Synchronize I/O on since next processor may write to tail */
1027 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1029 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1030 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1035 /* Build description to hardware for one receive segment */
1036 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1037 dma_addr_t map, unsigned len)
1039 struct sky2_rx_le *le;
1041 if (sizeof(dma_addr_t) > sizeof(u32)) {
1042 le = sky2_next_rx(sky2);
1043 le->addr = cpu_to_le32(upper_32_bits(map));
1044 le->opcode = OP_ADDR64 | HW_OWNER;
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32((u32) map);
1049 le->length = cpu_to_le16(len);
1050 le->opcode = op | HW_OWNER;
1053 /* Build description to hardware for one possibly fragmented skb */
1054 static void sky2_rx_submit(struct sky2_port *sky2,
1055 const struct rx_ring_info *re)
1059 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1061 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1062 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1066 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1069 struct sk_buff *skb = re->skb;
1072 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1073 pci_unmap_len_set(re, data_size, size);
1075 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1076 re->frag_addr[i] = pci_map_page(pdev,
1077 skb_shinfo(skb)->frags[i].page,
1078 skb_shinfo(skb)->frags[i].page_offset,
1079 skb_shinfo(skb)->frags[i].size,
1080 PCI_DMA_FROMDEVICE);
1083 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1085 struct sk_buff *skb = re->skb;
1088 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1089 PCI_DMA_FROMDEVICE);
1091 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1092 pci_unmap_page(pdev, re->frag_addr[i],
1093 skb_shinfo(skb)->frags[i].size,
1094 PCI_DMA_FROMDEVICE);
1097 /* Tell chip where to start receive checksum.
1098 * Actually has two checksums, but set both same to avoid possible byte
1101 static void rx_set_checksum(struct sky2_port *sky2)
1103 struct sky2_rx_le *le = sky2_next_rx(sky2);
1105 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1107 le->opcode = OP_TCPSTART | HW_OWNER;
1109 sky2_write32(sky2->hw,
1110 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1111 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1115 * The RX Stop command will not work for Yukon-2 if the BMU does not
1116 * reach the end of packet and since we can't make sure that we have
1117 * incoming data, we must reset the BMU while it is not doing a DMA
1118 * transfer. Since it is possible that the RX path is still active,
1119 * the RX RAM buffer will be stopped first, so any possible incoming
1120 * data will not trigger a DMA. After the RAM buffer is stopped, the
1121 * BMU is polled until any DMA in progress is ended and only then it
1124 static void sky2_rx_stop(struct sky2_port *sky2)
1126 struct sky2_hw *hw = sky2->hw;
1127 unsigned rxq = rxqaddr[sky2->port];
1130 /* disable the RAM Buffer receive queue */
1131 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1133 for (i = 0; i < 0xffff; i++)
1134 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1135 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1138 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1139 sky2->netdev->name);
1141 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1143 /* reset the Rx prefetch unit */
1144 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1148 /* Clean out receive buffer area, assumes receiver hardware stopped */
1149 static void sky2_rx_clean(struct sky2_port *sky2)
1153 memset(sky2->rx_le, 0, RX_LE_BYTES);
1154 for (i = 0; i < sky2->rx_pending; i++) {
1155 struct rx_ring_info *re = sky2->rx_ring + i;
1158 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1165 /* Basic MII support */
1166 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1168 struct mii_ioctl_data *data = if_mii(ifr);
1169 struct sky2_port *sky2 = netdev_priv(dev);
1170 struct sky2_hw *hw = sky2->hw;
1171 int err = -EOPNOTSUPP;
1173 if (!netif_running(dev))
1174 return -ENODEV; /* Phy still in reset */
1178 data->phy_id = PHY_ADDR_MARV;
1184 spin_lock_bh(&sky2->phy_lock);
1185 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1186 spin_unlock_bh(&sky2->phy_lock);
1188 data->val_out = val;
1193 if (!capable(CAP_NET_ADMIN))
1196 spin_lock_bh(&sky2->phy_lock);
1197 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1199 spin_unlock_bh(&sky2->phy_lock);
1205 #ifdef SKY2_VLAN_TAG_USED
1206 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1209 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1211 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1214 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1216 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1221 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1223 struct sky2_port *sky2 = netdev_priv(dev);
1224 struct sky2_hw *hw = sky2->hw;
1225 u16 port = sky2->port;
1227 netif_tx_lock_bh(dev);
1228 napi_disable(&hw->napi);
1231 sky2_set_vlan_mode(hw, port, grp != NULL);
1233 sky2_read32(hw, B0_Y2_SP_LISR);
1234 napi_enable(&hw->napi);
1235 netif_tx_unlock_bh(dev);
1240 * Allocate an skb for receiving. If the MTU is large enough
1241 * make the skb non-linear with a fragment list of pages.
1243 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1245 struct sk_buff *skb;
1248 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1249 unsigned char *start;
1251 * Workaround for a bug in FIFO that cause hang
1252 * if the FIFO if the receive buffer is not 64 byte aligned.
1253 * The buffer returned from netdev_alloc_skb is
1254 * aligned except if slab debugging is enabled.
1256 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1259 start = PTR_ALIGN(skb->data, 8);
1260 skb_reserve(skb, start - skb->data);
1262 skb = netdev_alloc_skb(sky2->netdev,
1263 sky2->rx_data_size + NET_IP_ALIGN);
1266 skb_reserve(skb, NET_IP_ALIGN);
1269 for (i = 0; i < sky2->rx_nfrags; i++) {
1270 struct page *page = alloc_page(GFP_ATOMIC);
1274 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1284 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1286 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1290 * Allocate and setup receiver buffer pool.
1291 * Normal case this ends up creating one list element for skb
1292 * in the receive ring. Worst case if using large MTU and each
1293 * allocation falls on a different 64 bit region, that results
1294 * in 6 list elements per ring entry.
1295 * One element is used for checksum enable/disable, and one
1296 * extra to avoid wrap.
1298 static int sky2_rx_start(struct sky2_port *sky2)
1300 struct sky2_hw *hw = sky2->hw;
1301 struct rx_ring_info *re;
1302 unsigned rxq = rxqaddr[sky2->port];
1303 unsigned i, size, thresh;
1305 sky2->rx_put = sky2->rx_next = 0;
1308 /* On PCI express lowering the watermark gives better performance */
1309 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1310 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1312 /* These chips have no ram buffer?
1313 * MAC Rx RAM Read is controlled by hardware */
1314 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1315 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1316 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1317 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1319 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1321 if (!(hw->flags & SKY2_HW_NEW_LE))
1322 rx_set_checksum(sky2);
1324 /* Space needed for frame data + headers rounded up */
1325 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1327 /* Stopping point for hardware truncation */
1328 thresh = (size - 8) / sizeof(u32);
1330 sky2->rx_nfrags = size >> PAGE_SHIFT;
1331 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1333 /* Compute residue after pages */
1334 size -= sky2->rx_nfrags << PAGE_SHIFT;
1336 /* Optimize to handle small packets and headers */
1337 if (size < copybreak)
1339 if (size < ETH_HLEN)
1342 sky2->rx_data_size = size;
1345 for (i = 0; i < sky2->rx_pending; i++) {
1346 re = sky2->rx_ring + i;
1348 re->skb = sky2_rx_alloc(sky2);
1352 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1353 sky2_rx_submit(sky2, re);
1357 * The receiver hangs if it receives frames larger than the
1358 * packet buffer. As a workaround, truncate oversize frames, but
1359 * the register is limited to 9 bits, so if you do frames > 2052
1360 * you better get the MTU right!
1363 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1365 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1366 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1369 /* Tell chip about available buffers */
1370 sky2_rx_update(sky2, rxq);
1373 sky2_rx_clean(sky2);
1377 /* Bring up network interface. */
1378 static int sky2_up(struct net_device *dev)
1380 struct sky2_port *sky2 = netdev_priv(dev);
1381 struct sky2_hw *hw = sky2->hw;
1382 unsigned port = sky2->port;
1384 int cap, err = -ENOMEM;
1385 struct net_device *otherdev = hw->dev[sky2->port^1];
1388 * On dual port PCI-X card, there is an problem where status
1389 * can be received out of order due to split transactions
1391 if (otherdev && netif_running(otherdev) &&
1392 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1395 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1396 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1397 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1401 if (netif_msg_ifup(sky2))
1402 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1404 netif_carrier_off(dev);
1406 /* must be power of 2 */
1407 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1409 sizeof(struct sky2_tx_le),
1414 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1421 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1425 memset(sky2->rx_le, 0, RX_LE_BYTES);
1427 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1432 sky2_mac_init(hw, port);
1434 /* Register is number of 4K blocks on internal RAM buffer. */
1435 ramsize = sky2_read8(hw, B2_E_0) * 4;
1439 hw->flags |= SKY2_HW_RAM_BUFFER;
1440 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1442 rxspace = ramsize / 2;
1444 rxspace = 8 + (2*(ramsize - 16))/3;
1446 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1447 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1449 /* Make sure SyncQ is disabled */
1450 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1454 sky2_qset(hw, txqaddr[port]);
1456 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1457 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1458 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1460 /* Set almost empty threshold */
1461 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1462 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1463 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1465 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1468 #ifdef SKY2_VLAN_TAG_USED
1469 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1472 err = sky2_rx_start(sky2);
1476 /* Enable interrupts from phy/mac for port */
1477 imask = sky2_read32(hw, B0_IMSK);
1478 imask |= portirq_msk[port];
1479 sky2_write32(hw, B0_IMSK, imask);
1481 sky2_set_multicast(dev);
1486 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1487 sky2->rx_le, sky2->rx_le_map);
1491 pci_free_consistent(hw->pdev,
1492 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1493 sky2->tx_le, sky2->tx_le_map);
1496 kfree(sky2->tx_ring);
1497 kfree(sky2->rx_ring);
1499 sky2->tx_ring = NULL;
1500 sky2->rx_ring = NULL;
1504 /* Modular subtraction in ring */
1505 static inline int tx_dist(unsigned tail, unsigned head)
1507 return (head - tail) & (TX_RING_SIZE - 1);
1510 /* Number of list elements available for next tx */
1511 static inline int tx_avail(const struct sky2_port *sky2)
1513 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1516 /* Estimate of number of transmit list elements required */
1517 static unsigned tx_le_req(const struct sk_buff *skb)
1521 count = sizeof(dma_addr_t) / sizeof(u32);
1522 count += skb_shinfo(skb)->nr_frags * count;
1524 if (skb_is_gso(skb))
1527 if (skb->ip_summed == CHECKSUM_PARTIAL)
1534 * Put one packet in ring for transmit.
1535 * A single packet can generate multiple list elements, and
1536 * the number of ring elements will probably be less than the number
1537 * of list elements used.
1539 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1541 struct sky2_port *sky2 = netdev_priv(dev);
1542 struct sky2_hw *hw = sky2->hw;
1543 struct sky2_tx_le *le = NULL;
1544 struct tx_ring_info *re;
1550 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1551 return NETDEV_TX_BUSY;
1553 if (unlikely(netif_msg_tx_queued(sky2)))
1554 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1555 dev->name, sky2->tx_prod, skb->len);
1557 len = skb_headlen(skb);
1558 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1560 /* Send high bits if needed */
1561 if (sizeof(dma_addr_t) > sizeof(u32)) {
1562 le = get_tx_le(sky2);
1563 le->addr = cpu_to_le32(upper_32_bits(mapping));
1564 le->opcode = OP_ADDR64 | HW_OWNER;
1567 /* Check for TCP Segmentation Offload */
1568 mss = skb_shinfo(skb)->gso_size;
1571 if (!(hw->flags & SKY2_HW_NEW_LE))
1572 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1574 if (mss != sky2->tx_last_mss) {
1575 le = get_tx_le(sky2);
1576 le->addr = cpu_to_le32(mss);
1578 if (hw->flags & SKY2_HW_NEW_LE)
1579 le->opcode = OP_MSS | HW_OWNER;
1581 le->opcode = OP_LRGLEN | HW_OWNER;
1582 sky2->tx_last_mss = mss;
1587 #ifdef SKY2_VLAN_TAG_USED
1588 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1589 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1591 le = get_tx_le(sky2);
1593 le->opcode = OP_VLAN|HW_OWNER;
1595 le->opcode |= OP_VLAN;
1596 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1601 /* Handle TCP checksum offload */
1602 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1603 /* On Yukon EX (some versions) encoding change. */
1604 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1605 ctrl |= CALSUM; /* auto checksum */
1607 const unsigned offset = skb_transport_offset(skb);
1610 tcpsum = offset << 16; /* sum start */
1611 tcpsum |= offset + skb->csum_offset; /* sum write */
1613 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1614 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1617 if (tcpsum != sky2->tx_tcpsum) {
1618 sky2->tx_tcpsum = tcpsum;
1620 le = get_tx_le(sky2);
1621 le->addr = cpu_to_le32(tcpsum);
1622 le->length = 0; /* initial checksum value */
1623 le->ctrl = 1; /* one packet */
1624 le->opcode = OP_TCPLISW | HW_OWNER;
1629 le = get_tx_le(sky2);
1630 le->addr = cpu_to_le32((u32) mapping);
1631 le->length = cpu_to_le16(len);
1633 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1635 re = tx_le_re(sky2, le);
1637 pci_unmap_addr_set(re, mapaddr, mapping);
1638 pci_unmap_len_set(re, maplen, len);
1640 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1641 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1643 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1644 frag->size, PCI_DMA_TODEVICE);
1646 if (sizeof(dma_addr_t) > sizeof(u32)) {
1647 le = get_tx_le(sky2);
1648 le->addr = cpu_to_le32(upper_32_bits(mapping));
1650 le->opcode = OP_ADDR64 | HW_OWNER;
1653 le = get_tx_le(sky2);
1654 le->addr = cpu_to_le32((u32) mapping);
1655 le->length = cpu_to_le16(frag->size);
1657 le->opcode = OP_BUFFER | HW_OWNER;
1659 re = tx_le_re(sky2, le);
1661 pci_unmap_addr_set(re, mapaddr, mapping);
1662 pci_unmap_len_set(re, maplen, frag->size);
1667 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1668 netif_stop_queue(dev);
1670 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1672 dev->trans_start = jiffies;
1673 return NETDEV_TX_OK;
1677 * Free ring elements from starting at tx_cons until "done"
1679 * NB: the hardware will tell us about partial completion of multi-part
1680 * buffers so make sure not to free skb to early.
1682 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1684 struct net_device *dev = sky2->netdev;
1685 struct pci_dev *pdev = sky2->hw->pdev;
1688 BUG_ON(done >= TX_RING_SIZE);
1690 for (idx = sky2->tx_cons; idx != done;
1691 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1692 struct sky2_tx_le *le = sky2->tx_le + idx;
1693 struct tx_ring_info *re = sky2->tx_ring + idx;
1695 switch(le->opcode & ~HW_OWNER) {
1698 pci_unmap_single(pdev,
1699 pci_unmap_addr(re, mapaddr),
1700 pci_unmap_len(re, maplen),
1704 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1705 pci_unmap_len(re, maplen),
1710 if (le->ctrl & EOP) {
1711 if (unlikely(netif_msg_tx_done(sky2)))
1712 printk(KERN_DEBUG "%s: tx done %u\n",
1715 dev->stats.tx_packets++;
1716 dev->stats.tx_bytes += re->skb->len;
1718 dev_kfree_skb_any(re->skb);
1719 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1723 sky2->tx_cons = idx;
1726 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1727 netif_wake_queue(dev);
1730 /* Cleanup all untransmitted buffers, assume transmitter not running */
1731 static void sky2_tx_clean(struct net_device *dev)
1733 struct sky2_port *sky2 = netdev_priv(dev);
1735 netif_tx_lock_bh(dev);
1736 sky2_tx_complete(sky2, sky2->tx_prod);
1737 netif_tx_unlock_bh(dev);
1740 /* Network shutdown */
1741 static int sky2_down(struct net_device *dev)
1743 struct sky2_port *sky2 = netdev_priv(dev);
1744 struct sky2_hw *hw = sky2->hw;
1745 unsigned port = sky2->port;
1749 /* Never really got started! */
1753 if (netif_msg_ifdown(sky2))
1754 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1756 /* Disable port IRQ */
1757 imask = sky2_read32(hw, B0_IMSK);
1758 imask &= ~portirq_msk[port];
1759 sky2_write32(hw, B0_IMSK, imask);
1761 synchronize_irq(hw->pdev->irq);
1763 sky2_gmac_reset(hw, port);
1765 /* Stop transmitter */
1766 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1767 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1769 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1770 RB_RST_SET | RB_DIS_OP_MD);
1772 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1773 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1774 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1776 /* Make sure no packets are pending */
1777 napi_synchronize(&hw->napi);
1779 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1781 /* Workaround shared GMAC reset */
1782 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1783 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1784 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1786 /* Disable Force Sync bit and Enable Alloc bit */
1787 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1788 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1790 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1791 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1792 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1794 /* Reset the PCI FIFO of the async Tx queue */
1795 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1796 BMU_RST_SET | BMU_FIFO_RST);
1798 /* Reset the Tx prefetch units */
1799 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1802 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1807 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1809 sky2_phy_power_down(hw, port);
1811 /* turn off LED's */
1812 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1815 sky2_rx_clean(sky2);
1817 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1818 sky2->rx_le, sky2->rx_le_map);
1819 kfree(sky2->rx_ring);
1821 pci_free_consistent(hw->pdev,
1822 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1823 sky2->tx_le, sky2->tx_le_map);
1824 kfree(sky2->tx_ring);
1829 sky2->rx_ring = NULL;
1830 sky2->tx_ring = NULL;
1835 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1837 if (hw->flags & SKY2_HW_FIBRE_PHY)
1840 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1841 if (aux & PHY_M_PS_SPEED_100)
1847 switch (aux & PHY_M_PS_SPEED_MSK) {
1848 case PHY_M_PS_SPEED_1000:
1850 case PHY_M_PS_SPEED_100:
1857 static void sky2_link_up(struct sky2_port *sky2)
1859 struct sky2_hw *hw = sky2->hw;
1860 unsigned port = sky2->port;
1862 static const char *fc_name[] = {
1870 reg = gma_read16(hw, port, GM_GP_CTRL);
1871 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1872 gma_write16(hw, port, GM_GP_CTRL, reg);
1874 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1876 netif_carrier_on(sky2->netdev);
1878 mod_timer(&hw->watchdog_timer, jiffies + 1);
1880 /* Turn on link LED */
1881 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1882 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1884 if (netif_msg_link(sky2))
1885 printk(KERN_INFO PFX
1886 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1887 sky2->netdev->name, sky2->speed,
1888 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1889 fc_name[sky2->flow_status]);
1892 static void sky2_link_down(struct sky2_port *sky2)
1894 struct sky2_hw *hw = sky2->hw;
1895 unsigned port = sky2->port;
1898 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1900 reg = gma_read16(hw, port, GM_GP_CTRL);
1901 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1902 gma_write16(hw, port, GM_GP_CTRL, reg);
1904 netif_carrier_off(sky2->netdev);
1906 /* Turn on link LED */
1907 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1909 if (netif_msg_link(sky2))
1910 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1912 sky2_phy_init(hw, port);
1915 static enum flow_control sky2_flow(int rx, int tx)
1918 return tx ? FC_BOTH : FC_RX;
1920 return tx ? FC_TX : FC_NONE;
1923 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1925 struct sky2_hw *hw = sky2->hw;
1926 unsigned port = sky2->port;
1929 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1930 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1931 if (lpa & PHY_M_AN_RF) {
1932 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1936 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1937 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1938 sky2->netdev->name);
1942 sky2->speed = sky2_phy_speed(hw, aux);
1943 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1945 /* Since the pause result bits seem to in different positions on
1946 * different chips. look at registers.
1948 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1949 /* Shift for bits in fiber PHY */
1950 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1951 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1953 if (advert & ADVERTISE_1000XPAUSE)
1954 advert |= ADVERTISE_PAUSE_CAP;
1955 if (advert & ADVERTISE_1000XPSE_ASYM)
1956 advert |= ADVERTISE_PAUSE_ASYM;
1957 if (lpa & LPA_1000XPAUSE)
1958 lpa |= LPA_PAUSE_CAP;
1959 if (lpa & LPA_1000XPAUSE_ASYM)
1960 lpa |= LPA_PAUSE_ASYM;
1963 sky2->flow_status = FC_NONE;
1964 if (advert & ADVERTISE_PAUSE_CAP) {
1965 if (lpa & LPA_PAUSE_CAP)
1966 sky2->flow_status = FC_BOTH;
1967 else if (advert & ADVERTISE_PAUSE_ASYM)
1968 sky2->flow_status = FC_RX;
1969 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1970 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1971 sky2->flow_status = FC_TX;
1974 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1975 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1976 sky2->flow_status = FC_NONE;
1978 if (sky2->flow_status & FC_TX)
1979 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1981 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1986 /* Interrupt from PHY */
1987 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1989 struct net_device *dev = hw->dev[port];
1990 struct sky2_port *sky2 = netdev_priv(dev);
1991 u16 istatus, phystat;
1993 if (!netif_running(dev))
1996 spin_lock(&sky2->phy_lock);
1997 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1998 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2000 if (netif_msg_intr(sky2))
2001 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2002 sky2->netdev->name, istatus, phystat);
2004 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2005 if (sky2_autoneg_done(sky2, phystat) == 0)
2010 if (istatus & PHY_M_IS_LSP_CHANGE)
2011 sky2->speed = sky2_phy_speed(hw, phystat);
2013 if (istatus & PHY_M_IS_DUP_CHANGE)
2015 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2017 if (istatus & PHY_M_IS_LST_CHANGE) {
2018 if (phystat & PHY_M_PS_LINK_UP)
2021 sky2_link_down(sky2);
2024 spin_unlock(&sky2->phy_lock);
2027 /* Transmit timeout is only called if we are running, carrier is up
2028 * and tx queue is full (stopped).
2030 static void sky2_tx_timeout(struct net_device *dev)
2032 struct sky2_port *sky2 = netdev_priv(dev);
2033 struct sky2_hw *hw = sky2->hw;
2035 if (netif_msg_timer(sky2))
2036 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2038 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2039 dev->name, sky2->tx_cons, sky2->tx_prod,
2040 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2041 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2043 /* can't restart safely under softirq */
2044 schedule_work(&hw->restart_work);
2047 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2049 struct sky2_port *sky2 = netdev_priv(dev);
2050 struct sky2_hw *hw = sky2->hw;
2051 unsigned port = sky2->port;
2056 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2059 if (new_mtu > ETH_DATA_LEN &&
2060 (hw->chip_id == CHIP_ID_YUKON_FE ||
2061 hw->chip_id == CHIP_ID_YUKON_FE_P))
2064 if (!netif_running(dev)) {
2069 imask = sky2_read32(hw, B0_IMSK);
2070 sky2_write32(hw, B0_IMSK, 0);
2072 dev->trans_start = jiffies; /* prevent tx timeout */
2073 netif_stop_queue(dev);
2074 napi_disable(&hw->napi);
2076 synchronize_irq(hw->pdev->irq);
2078 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2079 sky2_set_tx_stfwd(hw, port);
2081 ctl = gma_read16(hw, port, GM_GP_CTRL);
2082 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2084 sky2_rx_clean(sky2);
2088 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2089 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2091 if (dev->mtu > ETH_DATA_LEN)
2092 mode |= GM_SMOD_JUMBO_ENA;
2094 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2096 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2098 err = sky2_rx_start(sky2);
2099 sky2_write32(hw, B0_IMSK, imask);
2101 sky2_read32(hw, B0_Y2_SP_LISR);
2102 napi_enable(&hw->napi);
2107 gma_write16(hw, port, GM_GP_CTRL, ctl);
2109 netif_wake_queue(dev);
2115 /* For small just reuse existing skb for next receive */
2116 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2117 const struct rx_ring_info *re,
2120 struct sk_buff *skb;
2122 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2124 skb_reserve(skb, 2);
2125 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2126 length, PCI_DMA_FROMDEVICE);
2127 skb_copy_from_linear_data(re->skb, skb->data, length);
2128 skb->ip_summed = re->skb->ip_summed;
2129 skb->csum = re->skb->csum;
2130 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2131 length, PCI_DMA_FROMDEVICE);
2132 re->skb->ip_summed = CHECKSUM_NONE;
2133 skb_put(skb, length);
2138 /* Adjust length of skb with fragments to match received data */
2139 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2140 unsigned int length)
2145 /* put header into skb */
2146 size = min(length, hdr_space);
2151 num_frags = skb_shinfo(skb)->nr_frags;
2152 for (i = 0; i < num_frags; i++) {
2153 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2156 /* don't need this page */
2157 __free_page(frag->page);
2158 --skb_shinfo(skb)->nr_frags;
2160 size = min(length, (unsigned) PAGE_SIZE);
2163 skb->data_len += size;
2164 skb->truesize += size;
2171 /* Normal packet - take skb from ring element and put in a new one */
2172 static struct sk_buff *receive_new(struct sky2_port *sky2,
2173 struct rx_ring_info *re,
2174 unsigned int length)
2176 struct sk_buff *skb, *nskb;
2177 unsigned hdr_space = sky2->rx_data_size;
2179 /* Don't be tricky about reusing pages (yet) */
2180 nskb = sky2_rx_alloc(sky2);
2181 if (unlikely(!nskb))
2185 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2187 prefetch(skb->data);
2189 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2191 if (skb_shinfo(skb)->nr_frags)
2192 skb_put_frags(skb, hdr_space, length);
2194 skb_put(skb, length);
2199 * Receive one packet.
2200 * For larger packets, get new buffer.
2202 static struct sk_buff *sky2_receive(struct net_device *dev,
2203 u16 length, u32 status)
2205 struct sky2_port *sky2 = netdev_priv(dev);
2206 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2207 struct sk_buff *skb = NULL;
2208 u16 count = (status & GMR_FS_LEN) >> 16;
2210 #ifdef SKY2_VLAN_TAG_USED
2211 /* Account for vlan tag */
2212 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2216 if (unlikely(netif_msg_rx_status(sky2)))
2217 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2218 dev->name, sky2->rx_next, status, length);
2220 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2221 prefetch(sky2->rx_ring + sky2->rx_next);
2223 /* This chip has hardware problems that generates bogus status.
2224 * So do only marginal checking and expect higher level protocols
2225 * to handle crap frames.
2227 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2228 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2232 if (status & GMR_FS_ANY_ERR)
2235 if (!(status & GMR_FS_RX_OK))
2238 /* if length reported by DMA does not match PHY, packet was truncated */
2239 if (length != count)
2243 if (length < copybreak)
2244 skb = receive_copy(sky2, re, length);
2246 skb = receive_new(sky2, re, length);
2248 sky2_rx_submit(sky2, re);
2253 /* Truncation of overlength packets
2254 causes PHY length to not match MAC length */
2255 ++dev->stats.rx_length_errors;
2256 if (netif_msg_rx_err(sky2) && net_ratelimit())
2257 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2258 dev->name, status, length);
2262 ++dev->stats.rx_errors;
2263 if (status & GMR_FS_RX_FF_OV) {
2264 dev->stats.rx_over_errors++;
2268 if (netif_msg_rx_err(sky2) && net_ratelimit())
2269 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2270 dev->name, status, length);
2272 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2273 dev->stats.rx_length_errors++;
2274 if (status & GMR_FS_FRAGMENT)
2275 dev->stats.rx_frame_errors++;
2276 if (status & GMR_FS_CRC_ERR)
2277 dev->stats.rx_crc_errors++;
2282 /* Transmit complete */
2283 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2285 struct sky2_port *sky2 = netdev_priv(dev);
2287 if (netif_running(dev)) {
2289 sky2_tx_complete(sky2, last);
2290 netif_tx_unlock(dev);
2294 /* Process status response ring */
2295 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2298 unsigned rx[2] = { 0, 0 };
2302 struct sky2_port *sky2;
2303 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2305 struct net_device *dev;
2306 struct sk_buff *skb;
2309 u8 opcode = le->opcode;
2311 if (!(opcode & HW_OWNER))
2314 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2316 port = le->css & CSS_LINK_BIT;
2317 dev = hw->dev[port];
2318 sky2 = netdev_priv(dev);
2319 length = le16_to_cpu(le->length);
2320 status = le32_to_cpu(le->status);
2323 switch (opcode & ~HW_OWNER) {
2326 skb = sky2_receive(dev, length, status);
2327 if (unlikely(!skb)) {
2328 dev->stats.rx_dropped++;
2332 /* This chip reports checksum status differently */
2333 if (hw->flags & SKY2_HW_NEW_LE) {
2334 if (sky2->rx_csum &&
2335 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2336 (le->css & CSS_TCPUDPCSOK))
2337 skb->ip_summed = CHECKSUM_UNNECESSARY;
2339 skb->ip_summed = CHECKSUM_NONE;
2342 skb->protocol = eth_type_trans(skb, dev);
2343 dev->stats.rx_packets++;
2344 dev->stats.rx_bytes += skb->len;
2345 dev->last_rx = jiffies;
2347 #ifdef SKY2_VLAN_TAG_USED
2348 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2349 vlan_hwaccel_receive_skb(skb,
2351 be16_to_cpu(sky2->rx_tag));
2354 netif_receive_skb(skb);
2356 /* Stop after net poll weight */
2357 if (++work_done >= to_do)
2361 #ifdef SKY2_VLAN_TAG_USED
2363 sky2->rx_tag = length;
2367 sky2->rx_tag = length;
2374 /* If this happens then driver assuming wrong format */
2375 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2376 if (net_ratelimit())
2377 printk(KERN_NOTICE "%s: unexpected"
2378 " checksum status\n",
2383 /* Both checksum counters are programmed to start at
2384 * the same offset, so unless there is a problem they
2385 * should match. This failure is an early indication that
2386 * hardware receive checksumming won't work.
2388 if (likely(status >> 16 == (status & 0xffff))) {
2389 skb = sky2->rx_ring[sky2->rx_next].skb;
2390 skb->ip_summed = CHECKSUM_COMPLETE;
2391 skb->csum = status & 0xffff;
2393 printk(KERN_NOTICE PFX "%s: hardware receive "
2394 "checksum problem (status = %#x)\n",
2397 sky2_write32(sky2->hw,
2398 Q_ADDR(rxqaddr[port], Q_CSR),
2404 /* TX index reports status for both ports */
2405 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2406 sky2_tx_done(hw->dev[0], status & 0xfff);
2408 sky2_tx_done(hw->dev[1],
2409 ((status >> 24) & 0xff)
2410 | (u16)(length & 0xf) << 8);
2414 if (net_ratelimit())
2415 printk(KERN_WARNING PFX
2416 "unknown status opcode 0x%x\n", opcode);
2418 } while (hw->st_idx != idx);
2420 /* Fully processed status ring so clear irq */
2421 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2425 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2428 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2433 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2435 struct net_device *dev = hw->dev[port];
2437 if (net_ratelimit())
2438 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2441 if (status & Y2_IS_PAR_RD1) {
2442 if (net_ratelimit())
2443 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2446 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2449 if (status & Y2_IS_PAR_WR1) {
2450 if (net_ratelimit())
2451 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2454 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2457 if (status & Y2_IS_PAR_MAC1) {
2458 if (net_ratelimit())
2459 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2460 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2463 if (status & Y2_IS_PAR_RX1) {
2464 if (net_ratelimit())
2465 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2466 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2469 if (status & Y2_IS_TCP_TXA1) {
2470 if (net_ratelimit())
2471 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2473 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2477 static void sky2_hw_intr(struct sky2_hw *hw)
2479 struct pci_dev *pdev = hw->pdev;
2480 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2481 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2485 if (status & Y2_IS_TIST_OV)
2486 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2488 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2491 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2492 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2493 if (net_ratelimit())
2494 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2497 sky2_pci_write16(hw, PCI_STATUS,
2498 pci_err | PCI_STATUS_ERROR_BITS);
2499 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2502 if (status & Y2_IS_PCI_EXP) {
2503 /* PCI-Express uncorrectable Error occurred */
2506 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2507 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2508 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2510 if (net_ratelimit())
2511 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2513 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2514 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2517 if (status & Y2_HWE_L1_MASK)
2518 sky2_hw_error(hw, 0, status);
2520 if (status & Y2_HWE_L1_MASK)
2521 sky2_hw_error(hw, 1, status);
2524 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2526 struct net_device *dev = hw->dev[port];
2527 struct sky2_port *sky2 = netdev_priv(dev);
2528 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2530 if (netif_msg_intr(sky2))
2531 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2534 if (status & GM_IS_RX_CO_OV)
2535 gma_read16(hw, port, GM_RX_IRQ_SRC);
2537 if (status & GM_IS_TX_CO_OV)
2538 gma_read16(hw, port, GM_TX_IRQ_SRC);
2540 if (status & GM_IS_RX_FF_OR) {
2541 ++dev->stats.rx_fifo_errors;
2542 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2545 if (status & GM_IS_TX_FF_UR) {
2546 ++dev->stats.tx_fifo_errors;
2547 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2551 /* This should never happen it is a bug. */
2552 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2553 u16 q, unsigned ring_size)
2555 struct net_device *dev = hw->dev[port];
2556 struct sky2_port *sky2 = netdev_priv(dev);
2558 const u64 *le = (q == Q_R1 || q == Q_R2)
2559 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2561 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2562 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2563 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2564 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2566 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2569 static int sky2_rx_hung(struct net_device *dev)
2571 struct sky2_port *sky2 = netdev_priv(dev);
2572 struct sky2_hw *hw = sky2->hw;
2573 unsigned port = sky2->port;
2574 unsigned rxq = rxqaddr[port];
2575 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2576 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2577 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2578 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2580 /* If idle and MAC or PCI is stuck */
2581 if (sky2->check.last == dev->last_rx &&
2582 ((mac_rp == sky2->check.mac_rp &&
2583 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2584 /* Check if the PCI RX hang */
2585 (fifo_rp == sky2->check.fifo_rp &&
2586 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2587 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2588 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2589 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2592 sky2->check.last = dev->last_rx;
2593 sky2->check.mac_rp = mac_rp;
2594 sky2->check.mac_lev = mac_lev;
2595 sky2->check.fifo_rp = fifo_rp;
2596 sky2->check.fifo_lev = fifo_lev;
2601 static void sky2_watchdog(unsigned long arg)
2603 struct sky2_hw *hw = (struct sky2_hw *) arg;
2605 /* Check for lost IRQ once a second */
2606 if (sky2_read32(hw, B0_ISRC)) {
2607 napi_schedule(&hw->napi);
2611 for (i = 0; i < hw->ports; i++) {
2612 struct net_device *dev = hw->dev[i];
2613 if (!netif_running(dev))
2617 /* For chips with Rx FIFO, check if stuck */
2618 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2619 sky2_rx_hung(dev)) {
2620 pr_info(PFX "%s: receiver hang detected\n",
2622 schedule_work(&hw->restart_work);
2631 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2634 /* Hardware/software error handling */
2635 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2637 if (net_ratelimit())
2638 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2640 if (status & Y2_IS_HW_ERR)
2643 if (status & Y2_IS_IRQ_MAC1)
2644 sky2_mac_intr(hw, 0);
2646 if (status & Y2_IS_IRQ_MAC2)
2647 sky2_mac_intr(hw, 1);
2649 if (status & Y2_IS_CHK_RX1)
2650 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2652 if (status & Y2_IS_CHK_RX2)
2653 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2655 if (status & Y2_IS_CHK_TXA1)
2656 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2658 if (status & Y2_IS_CHK_TXA2)
2659 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2662 static int sky2_poll(struct napi_struct *napi, int work_limit)
2664 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2665 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2669 if (unlikely(status & Y2_IS_ERROR))
2670 sky2_err_intr(hw, status);
2672 if (status & Y2_IS_IRQ_PHY1)
2673 sky2_phy_intr(hw, 0);
2675 if (status & Y2_IS_IRQ_PHY2)
2676 sky2_phy_intr(hw, 1);
2678 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2679 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2681 if (work_done >= work_limit)
2685 /* Bug/Errata workaround?
2686 * Need to kick the TX irq moderation timer.
2688 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2689 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2690 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2692 napi_complete(napi);
2693 sky2_read32(hw, B0_Y2_SP_LISR);
2699 static irqreturn_t sky2_intr(int irq, void *dev_id)
2701 struct sky2_hw *hw = dev_id;
2704 /* Reading this mask interrupts as side effect */
2705 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2706 if (status == 0 || status == ~0)
2709 prefetch(&hw->st_le[hw->st_idx]);
2711 napi_schedule(&hw->napi);
2716 #ifdef CONFIG_NET_POLL_CONTROLLER
2717 static void sky2_netpoll(struct net_device *dev)
2719 struct sky2_port *sky2 = netdev_priv(dev);
2721 napi_schedule(&sky2->hw->napi);
2725 /* Chip internal frequency for clock calculations */
2726 static u32 sky2_mhz(const struct sky2_hw *hw)
2728 switch (hw->chip_id) {
2729 case CHIP_ID_YUKON_EC:
2730 case CHIP_ID_YUKON_EC_U:
2731 case CHIP_ID_YUKON_EX:
2732 case CHIP_ID_YUKON_SUPR:
2733 case CHIP_ID_YUKON_UL_2:
2736 case CHIP_ID_YUKON_FE:
2739 case CHIP_ID_YUKON_FE_P:
2742 case CHIP_ID_YUKON_XL:
2750 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2752 return sky2_mhz(hw) * us;
2755 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2757 return clk / sky2_mhz(hw);
2761 static int __devinit sky2_init(struct sky2_hw *hw)
2765 /* Enable all clocks and check for bad PCI access */
2766 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2768 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2770 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2771 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2773 switch(hw->chip_id) {
2774 case CHIP_ID_YUKON_XL:
2775 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2778 case CHIP_ID_YUKON_EC_U:
2779 hw->flags = SKY2_HW_GIGABIT
2781 | SKY2_HW_ADV_POWER_CTL;
2784 case CHIP_ID_YUKON_EX:
2785 hw->flags = SKY2_HW_GIGABIT
2788 | SKY2_HW_ADV_POWER_CTL;
2790 /* New transmit checksum */
2791 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2792 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2795 case CHIP_ID_YUKON_EC:
2796 /* This rev is really old, and requires untested workarounds */
2797 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2798 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2801 hw->flags = SKY2_HW_GIGABIT;
2804 case CHIP_ID_YUKON_FE:
2807 case CHIP_ID_YUKON_FE_P:
2808 hw->flags = SKY2_HW_NEWER_PHY
2810 | SKY2_HW_AUTO_TX_SUM
2811 | SKY2_HW_ADV_POWER_CTL;
2814 case CHIP_ID_YUKON_SUPR:
2815 hw->flags = SKY2_HW_GIGABIT
2818 | SKY2_HW_AUTO_TX_SUM
2819 | SKY2_HW_ADV_POWER_CTL;
2822 case CHIP_ID_YUKON_UL_2:
2823 hw->flags = SKY2_HW_GIGABIT
2824 | SKY2_HW_ADV_POWER_CTL;
2828 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2833 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2834 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2835 hw->flags |= SKY2_HW_FIBRE_PHY;
2838 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2839 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2840 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2847 static void sky2_reset(struct sky2_hw *hw)
2849 struct pci_dev *pdev = hw->pdev;
2852 u32 hwe_mask = Y2_HWE_ALL_MASK;
2855 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2856 status = sky2_read16(hw, HCU_CCSR);
2857 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2858 HCU_CCSR_UC_STATE_MSK);
2859 sky2_write16(hw, HCU_CCSR, status);
2861 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2862 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2865 sky2_write8(hw, B0_CTST, CS_RST_SET);
2866 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2868 /* allow writes to PCI config */
2869 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2871 /* clear PCI errors, if any */
2872 status = sky2_pci_read16(hw, PCI_STATUS);
2873 status |= PCI_STATUS_ERROR_BITS;
2874 sky2_pci_write16(hw, PCI_STATUS, status);
2876 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2878 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2880 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2883 /* If error bit is stuck on ignore it */
2884 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2885 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2887 hwe_mask |= Y2_IS_PCI_EXP;
2891 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2893 for (i = 0; i < hw->ports; i++) {
2894 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2895 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2897 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2898 hw->chip_id == CHIP_ID_YUKON_SUPR)
2899 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2900 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2904 /* Clear I2C IRQ noise */
2905 sky2_write32(hw, B2_I2C_IRQ, 1);
2907 /* turn off hardware timer (unused) */
2908 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2909 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2911 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2913 /* Turn off descriptor polling */
2914 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2916 /* Turn off receive timestamp */
2917 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2918 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2920 /* enable the Tx Arbiters */
2921 for (i = 0; i < hw->ports; i++)
2922 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2924 /* Initialize ram interface */
2925 for (i = 0; i < hw->ports; i++) {
2926 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2928 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2929 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2930 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2931 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2932 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2933 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2934 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2935 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2936 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2937 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2938 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2939 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2942 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2944 for (i = 0; i < hw->ports; i++)
2945 sky2_gmac_reset(hw, i);
2947 memset(hw->st_le, 0, STATUS_LE_BYTES);
2950 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2951 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2953 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2954 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2956 /* Set the list last index */
2957 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2959 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2960 sky2_write8(hw, STAT_FIFO_WM, 16);
2962 /* set Status-FIFO ISR watermark */
2963 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2964 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2966 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2968 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2969 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2970 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2972 /* enable status unit */
2973 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2975 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2976 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2977 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2980 static void sky2_restart(struct work_struct *work)
2982 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2983 struct net_device *dev;
2987 for (i = 0; i < hw->ports; i++) {
2989 if (netif_running(dev))
2993 napi_disable(&hw->napi);
2994 sky2_write32(hw, B0_IMSK, 0);
2996 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2997 napi_enable(&hw->napi);
2999 for (i = 0; i < hw->ports; i++) {
3001 if (netif_running(dev)) {
3004 printk(KERN_INFO PFX "%s: could not restart %d\n",
3014 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3016 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3019 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3021 const struct sky2_port *sky2 = netdev_priv(dev);
3023 wol->supported = sky2_wol_supported(sky2->hw);
3024 wol->wolopts = sky2->wol;
3027 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3029 struct sky2_port *sky2 = netdev_priv(dev);
3030 struct sky2_hw *hw = sky2->hw;
3032 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3035 sky2->wol = wol->wolopts;
3037 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3038 hw->chip_id == CHIP_ID_YUKON_EX ||
3039 hw->chip_id == CHIP_ID_YUKON_FE_P)
3040 sky2_write32(hw, B0_CTST, sky2->wol
3041 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3043 if (!netif_running(dev))
3044 sky2_wol_init(sky2);
3048 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3050 if (sky2_is_copper(hw)) {
3051 u32 modes = SUPPORTED_10baseT_Half
3052 | SUPPORTED_10baseT_Full
3053 | SUPPORTED_100baseT_Half
3054 | SUPPORTED_100baseT_Full
3055 | SUPPORTED_Autoneg | SUPPORTED_TP;
3057 if (hw->flags & SKY2_HW_GIGABIT)
3058 modes |= SUPPORTED_1000baseT_Half
3059 | SUPPORTED_1000baseT_Full;
3062 return SUPPORTED_1000baseT_Half
3063 | SUPPORTED_1000baseT_Full
3068 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3070 struct sky2_port *sky2 = netdev_priv(dev);
3071 struct sky2_hw *hw = sky2->hw;
3073 ecmd->transceiver = XCVR_INTERNAL;
3074 ecmd->supported = sky2_supported_modes(hw);
3075 ecmd->phy_address = PHY_ADDR_MARV;
3076 if (sky2_is_copper(hw)) {
3077 ecmd->port = PORT_TP;
3078 ecmd->speed = sky2->speed;
3080 ecmd->speed = SPEED_1000;
3081 ecmd->port = PORT_FIBRE;
3084 ecmd->advertising = sky2->advertising;
3085 ecmd->autoneg = sky2->autoneg;
3086 ecmd->duplex = sky2->duplex;
3090 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3092 struct sky2_port *sky2 = netdev_priv(dev);
3093 const struct sky2_hw *hw = sky2->hw;
3094 u32 supported = sky2_supported_modes(hw);
3096 if (ecmd->autoneg == AUTONEG_ENABLE) {
3097 ecmd->advertising = supported;
3103 switch (ecmd->speed) {
3105 if (ecmd->duplex == DUPLEX_FULL)
3106 setting = SUPPORTED_1000baseT_Full;
3107 else if (ecmd->duplex == DUPLEX_HALF)
3108 setting = SUPPORTED_1000baseT_Half;
3113 if (ecmd->duplex == DUPLEX_FULL)
3114 setting = SUPPORTED_100baseT_Full;
3115 else if (ecmd->duplex == DUPLEX_HALF)
3116 setting = SUPPORTED_100baseT_Half;
3122 if (ecmd->duplex == DUPLEX_FULL)
3123 setting = SUPPORTED_10baseT_Full;
3124 else if (ecmd->duplex == DUPLEX_HALF)
3125 setting = SUPPORTED_10baseT_Half;
3133 if ((setting & supported) == 0)
3136 sky2->speed = ecmd->speed;
3137 sky2->duplex = ecmd->duplex;
3140 sky2->autoneg = ecmd->autoneg;
3141 sky2->advertising = ecmd->advertising;
3143 if (netif_running(dev)) {
3144 sky2_phy_reinit(sky2);
3145 sky2_set_multicast(dev);
3151 static void sky2_get_drvinfo(struct net_device *dev,
3152 struct ethtool_drvinfo *info)
3154 struct sky2_port *sky2 = netdev_priv(dev);
3156 strcpy(info->driver, DRV_NAME);
3157 strcpy(info->version, DRV_VERSION);
3158 strcpy(info->fw_version, "N/A");
3159 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3162 static const struct sky2_stat {
3163 char name[ETH_GSTRING_LEN];
3166 { "tx_bytes", GM_TXO_OK_HI },
3167 { "rx_bytes", GM_RXO_OK_HI },
3168 { "tx_broadcast", GM_TXF_BC_OK },
3169 { "rx_broadcast", GM_RXF_BC_OK },
3170 { "tx_multicast", GM_TXF_MC_OK },
3171 { "rx_multicast", GM_RXF_MC_OK },
3172 { "tx_unicast", GM_TXF_UC_OK },
3173 { "rx_unicast", GM_RXF_UC_OK },
3174 { "tx_mac_pause", GM_TXF_MPAUSE },
3175 { "rx_mac_pause", GM_RXF_MPAUSE },
3176 { "collisions", GM_TXF_COL },
3177 { "late_collision",GM_TXF_LAT_COL },
3178 { "aborted", GM_TXF_ABO_COL },
3179 { "single_collisions", GM_TXF_SNG_COL },
3180 { "multi_collisions", GM_TXF_MUL_COL },
3182 { "rx_short", GM_RXF_SHT },
3183 { "rx_runt", GM_RXE_FRAG },
3184 { "rx_64_byte_packets", GM_RXF_64B },
3185 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3186 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3187 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3188 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3189 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3190 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3191 { "rx_too_long", GM_RXF_LNG_ERR },
3192 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3193 { "rx_jabber", GM_RXF_JAB_PKT },
3194 { "rx_fcs_error", GM_RXF_FCS_ERR },
3196 { "tx_64_byte_packets", GM_TXF_64B },
3197 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3198 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3199 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3200 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3201 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3202 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3203 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3206 static u32 sky2_get_rx_csum(struct net_device *dev)
3208 struct sky2_port *sky2 = netdev_priv(dev);
3210 return sky2->rx_csum;
3213 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3215 struct sky2_port *sky2 = netdev_priv(dev);
3217 sky2->rx_csum = data;
3219 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3220 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3225 static u32 sky2_get_msglevel(struct net_device *netdev)
3227 struct sky2_port *sky2 = netdev_priv(netdev);
3228 return sky2->msg_enable;
3231 static int sky2_nway_reset(struct net_device *dev)
3233 struct sky2_port *sky2 = netdev_priv(dev);
3235 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3238 sky2_phy_reinit(sky2);
3239 sky2_set_multicast(dev);
3244 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3246 struct sky2_hw *hw = sky2->hw;
3247 unsigned port = sky2->port;
3250 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3251 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3252 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3253 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3255 for (i = 2; i < count; i++)
3256 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3259 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3261 struct sky2_port *sky2 = netdev_priv(netdev);
3262 sky2->msg_enable = value;
3265 static int sky2_get_sset_count(struct net_device *dev, int sset)
3269 return ARRAY_SIZE(sky2_stats);
3275 static void sky2_get_ethtool_stats(struct net_device *dev,
3276 struct ethtool_stats *stats, u64 * data)
3278 struct sky2_port *sky2 = netdev_priv(dev);
3280 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3283 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3287 switch (stringset) {
3289 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3290 memcpy(data + i * ETH_GSTRING_LEN,
3291 sky2_stats[i].name, ETH_GSTRING_LEN);
3296 static int sky2_set_mac_address(struct net_device *dev, void *p)
3298 struct sky2_port *sky2 = netdev_priv(dev);
3299 struct sky2_hw *hw = sky2->hw;
3300 unsigned port = sky2->port;
3301 const struct sockaddr *addr = p;
3303 if (!is_valid_ether_addr(addr->sa_data))
3304 return -EADDRNOTAVAIL;
3306 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3307 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3308 dev->dev_addr, ETH_ALEN);
3309 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3310 dev->dev_addr, ETH_ALEN);
3312 /* virtual address for data */
3313 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3315 /* physical address: used for pause frames */
3316 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3321 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3325 bit = ether_crc(ETH_ALEN, addr) & 63;
3326 filter[bit >> 3] |= 1 << (bit & 7);
3329 static void sky2_set_multicast(struct net_device *dev)
3331 struct sky2_port *sky2 = netdev_priv(dev);
3332 struct sky2_hw *hw = sky2->hw;
3333 unsigned port = sky2->port;
3334 struct dev_mc_list *list = dev->mc_list;
3338 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3340 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3341 memset(filter, 0, sizeof(filter));
3343 reg = gma_read16(hw, port, GM_RX_CTRL);
3344 reg |= GM_RXCR_UCF_ENA;
3346 if (dev->flags & IFF_PROMISC) /* promiscuous */
3347 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3348 else if (dev->flags & IFF_ALLMULTI)
3349 memset(filter, 0xff, sizeof(filter));
3350 else if (dev->mc_count == 0 && !rx_pause)
3351 reg &= ~GM_RXCR_MCF_ENA;
3354 reg |= GM_RXCR_MCF_ENA;
3357 sky2_add_filter(filter, pause_mc_addr);
3359 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3360 sky2_add_filter(filter, list->dmi_addr);
3363 gma_write16(hw, port, GM_MC_ADDR_H1,
3364 (u16) filter[0] | ((u16) filter[1] << 8));
3365 gma_write16(hw, port, GM_MC_ADDR_H2,
3366 (u16) filter[2] | ((u16) filter[3] << 8));
3367 gma_write16(hw, port, GM_MC_ADDR_H3,
3368 (u16) filter[4] | ((u16) filter[5] << 8));
3369 gma_write16(hw, port, GM_MC_ADDR_H4,
3370 (u16) filter[6] | ((u16) filter[7] << 8));
3372 gma_write16(hw, port, GM_RX_CTRL, reg);
3375 /* Can have one global because blinking is controlled by
3376 * ethtool and that is always under RTNL mutex
3378 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3380 struct sky2_hw *hw = sky2->hw;
3381 unsigned port = sky2->port;
3383 spin_lock_bh(&sky2->phy_lock);
3384 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3385 hw->chip_id == CHIP_ID_YUKON_EX ||
3386 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3388 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3389 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3394 PHY_M_LEDC_LOS_CTRL(8) |
3395 PHY_M_LEDC_INIT_CTRL(8) |
3396 PHY_M_LEDC_STA1_CTRL(8) |
3397 PHY_M_LEDC_STA0_CTRL(8));
3400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3401 PHY_M_LEDC_LOS_CTRL(9) |
3402 PHY_M_LEDC_INIT_CTRL(9) |
3403 PHY_M_LEDC_STA1_CTRL(9) |
3404 PHY_M_LEDC_STA0_CTRL(9));
3407 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3408 PHY_M_LEDC_LOS_CTRL(0xa) |
3409 PHY_M_LEDC_INIT_CTRL(0xa) |
3410 PHY_M_LEDC_STA1_CTRL(0xa) |
3411 PHY_M_LEDC_STA0_CTRL(0xa));
3414 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3415 PHY_M_LEDC_LOS_CTRL(1) |
3416 PHY_M_LEDC_INIT_CTRL(8) |
3417 PHY_M_LEDC_STA1_CTRL(7) |
3418 PHY_M_LEDC_STA0_CTRL(7));
3421 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3423 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3424 PHY_M_LED_MO_DUP(mode) |
3425 PHY_M_LED_MO_10(mode) |
3426 PHY_M_LED_MO_100(mode) |
3427 PHY_M_LED_MO_1000(mode) |
3428 PHY_M_LED_MO_RX(mode) |
3429 PHY_M_LED_MO_TX(mode));
3431 spin_unlock_bh(&sky2->phy_lock);
3434 /* blink LED's for finding board */
3435 static int sky2_phys_id(struct net_device *dev, u32 data)
3437 struct sky2_port *sky2 = netdev_priv(dev);
3443 for (i = 0; i < data; i++) {
3444 sky2_led(sky2, MO_LED_ON);
3445 if (msleep_interruptible(500))
3447 sky2_led(sky2, MO_LED_OFF);
3448 if (msleep_interruptible(500))
3451 sky2_led(sky2, MO_LED_NORM);
3456 static void sky2_get_pauseparam(struct net_device *dev,
3457 struct ethtool_pauseparam *ecmd)
3459 struct sky2_port *sky2 = netdev_priv(dev);
3461 switch (sky2->flow_mode) {
3463 ecmd->tx_pause = ecmd->rx_pause = 0;
3466 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3469 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3472 ecmd->tx_pause = ecmd->rx_pause = 1;
3475 ecmd->autoneg = sky2->autoneg;
3478 static int sky2_set_pauseparam(struct net_device *dev,
3479 struct ethtool_pauseparam *ecmd)
3481 struct sky2_port *sky2 = netdev_priv(dev);
3483 sky2->autoneg = ecmd->autoneg;
3484 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3486 if (netif_running(dev))
3487 sky2_phy_reinit(sky2);
3492 static int sky2_get_coalesce(struct net_device *dev,
3493 struct ethtool_coalesce *ecmd)
3495 struct sky2_port *sky2 = netdev_priv(dev);
3496 struct sky2_hw *hw = sky2->hw;
3498 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3499 ecmd->tx_coalesce_usecs = 0;
3501 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3502 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3504 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3506 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3507 ecmd->rx_coalesce_usecs = 0;
3509 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3510 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3512 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3514 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3515 ecmd->rx_coalesce_usecs_irq = 0;
3517 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3518 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3521 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3526 /* Note: this affect both ports */
3527 static int sky2_set_coalesce(struct net_device *dev,
3528 struct ethtool_coalesce *ecmd)
3530 struct sky2_port *sky2 = netdev_priv(dev);
3531 struct sky2_hw *hw = sky2->hw;
3532 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3534 if (ecmd->tx_coalesce_usecs > tmax ||
3535 ecmd->rx_coalesce_usecs > tmax ||
3536 ecmd->rx_coalesce_usecs_irq > tmax)
3539 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3541 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3543 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3546 if (ecmd->tx_coalesce_usecs == 0)
3547 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3549 sky2_write32(hw, STAT_TX_TIMER_INI,
3550 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3551 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3553 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3555 if (ecmd->rx_coalesce_usecs == 0)
3556 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3558 sky2_write32(hw, STAT_LEV_TIMER_INI,
3559 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3560 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3562 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3564 if (ecmd->rx_coalesce_usecs_irq == 0)
3565 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3567 sky2_write32(hw, STAT_ISR_TIMER_INI,
3568 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3569 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3571 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3575 static void sky2_get_ringparam(struct net_device *dev,
3576 struct ethtool_ringparam *ering)
3578 struct sky2_port *sky2 = netdev_priv(dev);
3580 ering->rx_max_pending = RX_MAX_PENDING;
3581 ering->rx_mini_max_pending = 0;
3582 ering->rx_jumbo_max_pending = 0;
3583 ering->tx_max_pending = TX_RING_SIZE - 1;
3585 ering->rx_pending = sky2->rx_pending;
3586 ering->rx_mini_pending = 0;
3587 ering->rx_jumbo_pending = 0;
3588 ering->tx_pending = sky2->tx_pending;
3591 static int sky2_set_ringparam(struct net_device *dev,
3592 struct ethtool_ringparam *ering)
3594 struct sky2_port *sky2 = netdev_priv(dev);
3597 if (ering->rx_pending > RX_MAX_PENDING ||
3598 ering->rx_pending < 8 ||
3599 ering->tx_pending < MAX_SKB_TX_LE ||
3600 ering->tx_pending > TX_RING_SIZE - 1)
3603 if (netif_running(dev))
3606 sky2->rx_pending = ering->rx_pending;
3607 sky2->tx_pending = ering->tx_pending;
3609 if (netif_running(dev)) {
3618 static int sky2_get_regs_len(struct net_device *dev)
3624 * Returns copy of control register region
3625 * Note: ethtool_get_regs always provides full size (16k) buffer
3627 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3630 const struct sky2_port *sky2 = netdev_priv(dev);
3631 const void __iomem *io = sky2->hw->regs;
3636 for (b = 0; b < 128; b++) {
3637 /* This complicated switch statement is to make sure and
3638 * only access regions that are unreserved.
3639 * Some blocks are only valid on dual port cards.
3640 * and block 3 has some special diagnostic registers that
3645 /* skip diagnostic ram region */
3646 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3649 /* dual port cards only */
3650 case 5: /* Tx Arbiter 2 */
3652 case 14 ... 15: /* TX2 */
3653 case 17: case 19: /* Ram Buffer 2 */
3654 case 22 ... 23: /* Tx Ram Buffer 2 */
3655 case 25: /* Rx MAC Fifo 1 */
3656 case 27: /* Tx MAC Fifo 2 */
3657 case 31: /* GPHY 2 */
3658 case 40 ... 47: /* Pattern Ram 2 */
3659 case 52: case 54: /* TCP Segmentation 2 */
3660 case 112 ... 116: /* GMAC 2 */
3661 if (sky2->hw->ports == 1)
3664 case 0: /* Control */
3665 case 2: /* Mac address */
3666 case 4: /* Tx Arbiter 1 */
3667 case 7: /* PCI express reg */
3669 case 12 ... 13: /* TX1 */
3670 case 16: case 18:/* Rx Ram Buffer 1 */
3671 case 20 ... 21: /* Tx Ram Buffer 1 */
3672 case 24: /* Rx MAC Fifo 1 */
3673 case 26: /* Tx MAC Fifo 1 */
3674 case 28 ... 29: /* Descriptor and status unit */
3675 case 30: /* GPHY 1*/
3676 case 32 ... 39: /* Pattern Ram 1 */
3677 case 48: case 50: /* TCP Segmentation 1 */
3678 case 56 ... 60: /* PCI space */
3679 case 80 ... 84: /* GMAC 1 */
3680 memcpy_fromio(p, io, 128);
3692 /* In order to do Jumbo packets on these chips, need to turn off the
3693 * transmit store/forward. Therefore checksum offload won't work.
3695 static int no_tx_offload(struct net_device *dev)
3697 const struct sky2_port *sky2 = netdev_priv(dev);
3698 const struct sky2_hw *hw = sky2->hw;
3700 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3703 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3705 if (data && no_tx_offload(dev))
3708 return ethtool_op_set_tx_csum(dev, data);
3712 static int sky2_set_tso(struct net_device *dev, u32 data)
3714 if (data && no_tx_offload(dev))
3717 return ethtool_op_set_tso(dev, data);
3720 static int sky2_get_eeprom_len(struct net_device *dev)
3722 struct sky2_port *sky2 = netdev_priv(dev);
3723 struct sky2_hw *hw = sky2->hw;
3726 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3727 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3730 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3734 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3737 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3738 } while (!(offset & PCI_VPD_ADDR_F));
3740 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3744 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3746 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3747 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3749 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3750 } while (offset & PCI_VPD_ADDR_F);
3753 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3756 struct sky2_port *sky2 = netdev_priv(dev);
3757 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3758 int length = eeprom->len;
3759 u16 offset = eeprom->offset;
3764 eeprom->magic = SKY2_EEPROM_MAGIC;
3766 while (length > 0) {
3767 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3768 int n = min_t(int, length, sizeof(val));
3770 memcpy(data, &val, n);
3778 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3781 struct sky2_port *sky2 = netdev_priv(dev);
3782 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3783 int length = eeprom->len;
3784 u16 offset = eeprom->offset;
3789 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3792 while (length > 0) {
3794 int n = min_t(int, length, sizeof(val));
3796 if (n < sizeof(val))
3797 val = sky2_vpd_read(sky2->hw, cap, offset);
3798 memcpy(&val, data, n);
3800 sky2_vpd_write(sky2->hw, cap, offset, val);
3810 static const struct ethtool_ops sky2_ethtool_ops = {
3811 .get_settings = sky2_get_settings,
3812 .set_settings = sky2_set_settings,
3813 .get_drvinfo = sky2_get_drvinfo,
3814 .get_wol = sky2_get_wol,
3815 .set_wol = sky2_set_wol,
3816 .get_msglevel = sky2_get_msglevel,
3817 .set_msglevel = sky2_set_msglevel,
3818 .nway_reset = sky2_nway_reset,
3819 .get_regs_len = sky2_get_regs_len,
3820 .get_regs = sky2_get_regs,
3821 .get_link = ethtool_op_get_link,
3822 .get_eeprom_len = sky2_get_eeprom_len,
3823 .get_eeprom = sky2_get_eeprom,
3824 .set_eeprom = sky2_set_eeprom,
3825 .set_sg = ethtool_op_set_sg,
3826 .set_tx_csum = sky2_set_tx_csum,
3827 .set_tso = sky2_set_tso,
3828 .get_rx_csum = sky2_get_rx_csum,
3829 .set_rx_csum = sky2_set_rx_csum,
3830 .get_strings = sky2_get_strings,
3831 .get_coalesce = sky2_get_coalesce,
3832 .set_coalesce = sky2_set_coalesce,
3833 .get_ringparam = sky2_get_ringparam,
3834 .set_ringparam = sky2_set_ringparam,
3835 .get_pauseparam = sky2_get_pauseparam,
3836 .set_pauseparam = sky2_set_pauseparam,
3837 .phys_id = sky2_phys_id,
3838 .get_sset_count = sky2_get_sset_count,
3839 .get_ethtool_stats = sky2_get_ethtool_stats,
3842 #ifdef CONFIG_SKY2_DEBUG
3844 static struct dentry *sky2_debug;
3846 static int sky2_debug_show(struct seq_file *seq, void *v)
3848 struct net_device *dev = seq->private;
3849 const struct sky2_port *sky2 = netdev_priv(dev);
3850 struct sky2_hw *hw = sky2->hw;
3851 unsigned port = sky2->port;
3855 if (!netif_running(dev))
3858 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3859 sky2_read32(hw, B0_ISRC),
3860 sky2_read32(hw, B0_IMSK),
3861 sky2_read32(hw, B0_Y2_SP_ICR));
3863 napi_disable(&hw->napi);
3864 last = sky2_read16(hw, STAT_PUT_IDX);
3866 if (hw->st_idx == last)
3867 seq_puts(seq, "Status ring (empty)\n");
3869 seq_puts(seq, "Status ring\n");
3870 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3871 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3872 const struct sky2_status_le *le = hw->st_le + idx;
3873 seq_printf(seq, "[%d] %#x %d %#x\n",
3874 idx, le->opcode, le->length, le->status);
3876 seq_puts(seq, "\n");
3879 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3880 sky2->tx_cons, sky2->tx_prod,
3881 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3882 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3884 /* Dump contents of tx ring */
3886 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3887 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3888 const struct sky2_tx_le *le = sky2->tx_le + idx;
3889 u32 a = le32_to_cpu(le->addr);
3892 seq_printf(seq, "%u:", idx);
3895 switch(le->opcode & ~HW_OWNER) {
3897 seq_printf(seq, " %#x:", a);
3900 seq_printf(seq, " mtu=%d", a);
3903 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3906 seq_printf(seq, " csum=%#x", a);
3909 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3912 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3915 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3918 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3919 a, le16_to_cpu(le->length));
3922 if (le->ctrl & EOP) {
3923 seq_putc(seq, '\n');
3928 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3929 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3930 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3931 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3933 sky2_read32(hw, B0_Y2_SP_LISR);
3934 napi_enable(&hw->napi);
3938 static int sky2_debug_open(struct inode *inode, struct file *file)
3940 return single_open(file, sky2_debug_show, inode->i_private);
3943 static const struct file_operations sky2_debug_fops = {
3944 .owner = THIS_MODULE,
3945 .open = sky2_debug_open,
3947 .llseek = seq_lseek,
3948 .release = single_release,
3952 * Use network device events to create/remove/rename
3953 * debugfs file entries
3955 static int sky2_device_event(struct notifier_block *unused,
3956 unsigned long event, void *ptr)
3958 struct net_device *dev = ptr;
3959 struct sky2_port *sky2 = netdev_priv(dev);
3961 if (dev->open != sky2_up || !sky2_debug)
3965 case NETDEV_CHANGENAME:
3966 if (sky2->debugfs) {
3967 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3968 sky2_debug, dev->name);
3972 case NETDEV_GOING_DOWN:
3973 if (sky2->debugfs) {
3974 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3976 debugfs_remove(sky2->debugfs);
3977 sky2->debugfs = NULL;
3982 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3985 if (IS_ERR(sky2->debugfs))
3986 sky2->debugfs = NULL;
3992 static struct notifier_block sky2_notifier = {
3993 .notifier_call = sky2_device_event,
3997 static __init void sky2_debug_init(void)
4001 ent = debugfs_create_dir("sky2", NULL);
4002 if (!ent || IS_ERR(ent))
4006 register_netdevice_notifier(&sky2_notifier);
4009 static __exit void sky2_debug_cleanup(void)
4012 unregister_netdevice_notifier(&sky2_notifier);
4013 debugfs_remove(sky2_debug);
4019 #define sky2_debug_init()
4020 #define sky2_debug_cleanup()
4024 /* Initialize network device */
4025 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4027 int highmem, int wol)
4029 struct sky2_port *sky2;
4030 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4033 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4037 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4038 dev->irq = hw->pdev->irq;
4039 dev->open = sky2_up;
4040 dev->stop = sky2_down;
4041 dev->do_ioctl = sky2_ioctl;
4042 dev->hard_start_xmit = sky2_xmit_frame;
4043 dev->set_multicast_list = sky2_set_multicast;
4044 dev->set_mac_address = sky2_set_mac_address;
4045 dev->change_mtu = sky2_change_mtu;
4046 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4047 dev->tx_timeout = sky2_tx_timeout;
4048 dev->watchdog_timeo = TX_WATCHDOG;
4049 #ifdef CONFIG_NET_POLL_CONTROLLER
4051 dev->poll_controller = sky2_netpoll;
4054 sky2 = netdev_priv(dev);
4057 sky2->msg_enable = netif_msg_init(debug, default_msg);
4059 /* Auto speed and flow control */
4060 sky2->autoneg = AUTONEG_ENABLE;
4061 sky2->flow_mode = FC_BOTH;
4065 sky2->advertising = sky2_supported_modes(hw);
4066 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4069 spin_lock_init(&sky2->phy_lock);
4070 sky2->tx_pending = TX_DEF_PENDING;
4071 sky2->rx_pending = RX_DEF_PENDING;
4073 hw->dev[port] = dev;
4077 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4079 dev->features |= NETIF_F_HIGHDMA;
4081 #ifdef SKY2_VLAN_TAG_USED
4082 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4083 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4084 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4085 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4086 dev->vlan_rx_register = sky2_vlan_rx_register;
4090 /* read the mac address */
4091 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4092 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4097 static void __devinit sky2_show_addr(struct net_device *dev)
4099 const struct sky2_port *sky2 = netdev_priv(dev);
4100 DECLARE_MAC_BUF(mac);
4102 if (netif_msg_probe(sky2))
4103 printk(KERN_INFO PFX "%s: addr %s\n",
4104 dev->name, print_mac(mac, dev->dev_addr));
4107 /* Handle software interrupt used during MSI test */
4108 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4110 struct sky2_hw *hw = dev_id;
4111 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4116 if (status & Y2_IS_IRQ_SW) {
4117 hw->flags |= SKY2_HW_USE_MSI;
4118 wake_up(&hw->msi_wait);
4119 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4121 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4126 /* Test interrupt path by forcing a a software IRQ */
4127 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4129 struct pci_dev *pdev = hw->pdev;
4132 init_waitqueue_head (&hw->msi_wait);
4134 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4136 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4138 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4142 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4143 sky2_read8(hw, B0_CTST);
4145 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4147 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4148 /* MSI test failed, go back to INTx mode */
4149 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4150 "switching to INTx mode.\n");
4153 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4156 sky2_write32(hw, B0_IMSK, 0);
4157 sky2_read32(hw, B0_IMSK);
4159 free_irq(pdev->irq, hw);
4164 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4166 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4171 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4173 return value & PCI_PM_CTRL_PME_ENABLE;
4176 /* This driver supports yukon2 chipset only */
4177 static const char *sky2_name(u8 chipid, char *buf, int sz)
4179 const char *name[] = {
4181 "EC Ultra", /* 0xb4 */
4182 "Extreme", /* 0xb5 */
4186 "Supreme", /* 0xb9 */
4190 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4191 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4193 snprintf(buf, sz, "(chip %#x)", chipid);
4197 static int __devinit sky2_probe(struct pci_dev *pdev,
4198 const struct pci_device_id *ent)
4200 struct net_device *dev;
4202 int err, using_dac = 0, wol_default;
4205 err = pci_enable_device(pdev);
4207 dev_err(&pdev->dev, "cannot enable PCI device\n");
4211 err = pci_request_regions(pdev, DRV_NAME);
4213 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4214 goto err_out_disable;
4217 pci_set_master(pdev);
4219 if (sizeof(dma_addr_t) > sizeof(u32) &&
4220 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4222 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4224 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4225 "for consistent allocations\n");
4226 goto err_out_free_regions;
4229 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4231 dev_err(&pdev->dev, "no usable DMA configuration\n");
4232 goto err_out_free_regions;
4236 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4239 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4241 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4242 goto err_out_free_regions;
4247 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4249 dev_err(&pdev->dev, "cannot map device registers\n");
4250 goto err_out_free_hw;
4254 /* The sk98lin vendor driver uses hardware byte swapping but
4255 * this driver uses software swapping.
4259 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4260 reg &= ~PCI_REV_DESC;
4261 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4265 /* ring for status responses */
4266 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4268 goto err_out_iounmap;
4270 err = sky2_init(hw);
4272 goto err_out_iounmap;
4274 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4275 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4276 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4281 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4284 goto err_out_free_pci;
4287 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4288 err = sky2_test_msi(hw);
4289 if (err == -EOPNOTSUPP)
4290 pci_disable_msi(pdev);
4292 goto err_out_free_netdev;
4295 err = register_netdev(dev);
4297 dev_err(&pdev->dev, "cannot register net device\n");
4298 goto err_out_free_netdev;
4301 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4303 err = request_irq(pdev->irq, sky2_intr,
4304 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4307 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4308 goto err_out_unregister;
4310 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4311 napi_enable(&hw->napi);
4313 sky2_show_addr(dev);
4315 if (hw->ports > 1) {
4316 struct net_device *dev1;
4318 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4320 dev_warn(&pdev->dev, "allocation for second device failed\n");
4321 else if ((err = register_netdev(dev1))) {
4322 dev_warn(&pdev->dev,
4323 "register of second port failed (%d)\n", err);
4327 sky2_show_addr(dev1);
4330 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4331 INIT_WORK(&hw->restart_work, sky2_restart);
4333 pci_set_drvdata(pdev, hw);
4338 if (hw->flags & SKY2_HW_USE_MSI)
4339 pci_disable_msi(pdev);
4340 unregister_netdev(dev);
4341 err_out_free_netdev:
4344 sky2_write8(hw, B0_CTST, CS_RST_SET);
4345 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4350 err_out_free_regions:
4351 pci_release_regions(pdev);
4353 pci_disable_device(pdev);
4355 pci_set_drvdata(pdev, NULL);
4359 static void __devexit sky2_remove(struct pci_dev *pdev)
4361 struct sky2_hw *hw = pci_get_drvdata(pdev);
4367 del_timer_sync(&hw->watchdog_timer);
4368 cancel_work_sync(&hw->restart_work);
4370 for (i = hw->ports-1; i >= 0; --i)
4371 unregister_netdev(hw->dev[i]);
4373 sky2_write32(hw, B0_IMSK, 0);
4377 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4378 sky2_write8(hw, B0_CTST, CS_RST_SET);
4379 sky2_read8(hw, B0_CTST);
4381 free_irq(pdev->irq, hw);
4382 if (hw->flags & SKY2_HW_USE_MSI)
4383 pci_disable_msi(pdev);
4384 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4385 pci_release_regions(pdev);
4386 pci_disable_device(pdev);
4388 for (i = hw->ports-1; i >= 0; --i)
4389 free_netdev(hw->dev[i]);
4394 pci_set_drvdata(pdev, NULL);
4398 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4400 struct sky2_hw *hw = pci_get_drvdata(pdev);
4406 del_timer_sync(&hw->watchdog_timer);
4407 cancel_work_sync(&hw->restart_work);
4409 for (i = 0; i < hw->ports; i++) {
4410 struct net_device *dev = hw->dev[i];
4411 struct sky2_port *sky2 = netdev_priv(dev);
4413 netif_device_detach(dev);
4414 if (netif_running(dev))
4418 sky2_wol_init(sky2);
4423 sky2_write32(hw, B0_IMSK, 0);
4424 napi_disable(&hw->napi);
4427 pci_save_state(pdev);
4428 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4429 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4434 static int sky2_resume(struct pci_dev *pdev)
4436 struct sky2_hw *hw = pci_get_drvdata(pdev);
4442 err = pci_set_power_state(pdev, PCI_D0);
4446 err = pci_restore_state(pdev);
4450 pci_enable_wake(pdev, PCI_D0, 0);
4452 /* Re-enable all clocks */
4453 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4454 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4455 hw->chip_id == CHIP_ID_YUKON_FE_P)
4456 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4459 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4460 napi_enable(&hw->napi);
4462 for (i = 0; i < hw->ports; i++) {
4463 struct net_device *dev = hw->dev[i];
4465 netif_device_attach(dev);
4466 if (netif_running(dev)) {
4469 printk(KERN_ERR PFX "%s: could not up: %d\n",
4481 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4482 pci_disable_device(pdev);
4487 static void sky2_shutdown(struct pci_dev *pdev)
4489 struct sky2_hw *hw = pci_get_drvdata(pdev);
4495 del_timer_sync(&hw->watchdog_timer);
4497 for (i = 0; i < hw->ports; i++) {
4498 struct net_device *dev = hw->dev[i];
4499 struct sky2_port *sky2 = netdev_priv(dev);
4503 sky2_wol_init(sky2);
4510 pci_enable_wake(pdev, PCI_D3hot, wol);
4511 pci_enable_wake(pdev, PCI_D3cold, wol);
4513 pci_disable_device(pdev);
4514 pci_set_power_state(pdev, PCI_D3hot);
4517 static struct pci_driver sky2_driver = {
4519 .id_table = sky2_id_table,
4520 .probe = sky2_probe,
4521 .remove = __devexit_p(sky2_remove),
4523 .suspend = sky2_suspend,
4524 .resume = sky2_resume,
4526 .shutdown = sky2_shutdown,
4529 static int __init sky2_init_module(void)
4532 return pci_register_driver(&sky2_driver);
4535 static void __exit sky2_cleanup_module(void)
4537 pci_unregister_driver(&sky2_driver);
4538 sky2_debug_cleanup();
4541 module_init(sky2_init_module);
4542 module_exit(sky2_cleanup_module);
4544 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4545 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4546 MODULE_LICENSE("GPL");
4547 MODULE_VERSION(DRV_VERSION);