2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.18"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141 /* Avoid conditionals by using array */
142 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
144 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146 /* This driver supports yukon2 chipset only */
147 static const char *yukon2_name[] = {
149 "EC Ultra", /* 0xb4 */
150 "Extreme", /* 0xb5 */
156 static void sky2_set_multicast(struct net_device *dev);
158 /* Access to external PHY */
159 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
173 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
177 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
184 for (i = 0; i < PHY_RETRIES; i++) {
185 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
186 *val = gma_read16(hw, port, GM_SMI_DATA);
196 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
200 if (__gm_phy_read(hw, port, reg, &v) != 0)
201 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
206 static void sky2_power_on(struct sky2_hw *hw)
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
227 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
229 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
234 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg &= P_CTL_TIM_VMAIN_AV_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
239 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg = sky2_read32(hw, B2_GP_IO);
243 reg |= GLB_GPIO_STAT_RACE_DIS;
244 sky2_write32(hw, B2_GP_IO, reg);
246 sky2_read32(hw, B2_GP_IO);
250 static void sky2_power_aux(struct sky2_hw *hw)
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
261 /* switch power to VAUX */
262 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
268 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
287 /* flow control to advertise bits */
288 static const u16 copper_fc_adv[] = {
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
295 /* flow control to advertise bits when using 1000BaseX */
296 static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
303 /* flow control to GMA disable bits */
304 static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
312 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->flags & SKY2_HW_NEWER_PHY)) {
319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
326 if (hw->chip_id == CHIP_ID_YUKON_EC)
327 /* set downshift counter to 3x and enable downshift */
328 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
330 /* set master & slave downshift counter to 1x */
331 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
333 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
337 if (sky2_is_copper(hw)) {
338 if (!(hw->flags & SKY2_HW_GIGABIT)) {
339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
342 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
343 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
346 /* Enable Class A driver for FE+ A0 */
347 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
348 spec |= PHY_M_FESC_SEL_CL_A;
349 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
352 /* disable energy detect */
353 ctrl &= ~PHY_M_PC_EN_DET_MSK;
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
358 /* downshift on PHY 88E1112 and 88E1149 is changed */
359 if (sky2->autoneg == AUTONEG_ENABLE
360 && (hw->flags & SKY2_HW_NEWER_PHY)) {
361 /* set downshift counter to 3x and enable downshift */
362 ctrl &= ~PHY_M_PC_DSC_MSK;
363 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
367 /* workaround for deviation #4.88 (CRC errors) */
368 /* disable Automatic Crossover */
370 ctrl &= ~PHY_M_PC_MDIX_MSK;
373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
375 /* special setup for PHY 88E1112 Fiber */
376 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
377 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
379 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
381 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
382 ctrl &= ~PHY_M_MAC_MD_MSK;
383 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
384 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
386 if (hw->pmd_type == 'P') {
387 /* select page 1 to access Fiber registers */
388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
390 /* for SFP-module set SIGDET polarity to low */
391 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
392 ctrl |= PHY_M_FIB_SIGD_POL;
393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
404 if (sky2->autoneg == AUTONEG_ENABLE) {
405 if (sky2_is_copper(hw)) {
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 ct1000 |= PHY_M_1000C_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 ct1000 |= PHY_M_1000C_AHD;
410 if (sky2->advertising & ADVERTISED_100baseT_Full)
411 adv |= PHY_M_AN_100_FD;
412 if (sky2->advertising & ADVERTISED_100baseT_Half)
413 adv |= PHY_M_AN_100_HD;
414 if (sky2->advertising & ADVERTISED_10baseT_Full)
415 adv |= PHY_M_AN_10_FD;
416 if (sky2->advertising & ADVERTISED_10baseT_Half)
417 adv |= PHY_M_AN_10_HD;
419 adv |= copper_fc_adv[sky2->flow_mode];
420 } else { /* special defines for FIBER (88E1040S only) */
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 adv |= PHY_M_AN_1000X_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 adv |= PHY_M_AN_1000X_AHD;
426 adv |= fiber_fc_adv[sky2->flow_mode];
429 /* Restart Auto-negotiation */
430 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
432 /* forced speed/duplex settings */
433 ct1000 = PHY_M_1000C_MSE;
435 /* Disable auto update for duplex flow control and speed */
436 reg |= GM_GPCR_AU_ALL_DIS;
438 switch (sky2->speed) {
440 ctrl |= PHY_CT_SP1000;
441 reg |= GM_GPCR_SPEED_1000;
444 ctrl |= PHY_CT_SP100;
445 reg |= GM_GPCR_SPEED_100;
449 if (sky2->duplex == DUPLEX_FULL) {
450 reg |= GM_GPCR_DUP_FULL;
451 ctrl |= PHY_CT_DUP_MD;
452 } else if (sky2->speed < SPEED_1000)
453 sky2->flow_mode = FC_NONE;
456 reg |= gm_fc_disable[sky2->flow_mode];
458 /* Forward pause packets to GMAC? */
459 if (sky2->flow_mode & FC_RX)
460 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
465 gma_write16(hw, port, GM_GP_CTRL, reg);
467 if (hw->flags & SKY2_HW_GIGABIT)
468 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
470 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
471 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
473 /* Setup Phy LED's */
474 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
477 switch (hw->chip_id) {
478 case CHIP_ID_YUKON_FE:
479 /* on 88E3082 these bits are at 11..9 (shifted left) */
480 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
482 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
484 /* delete ACT LED control bits */
485 ctrl &= ~PHY_M_FELP_LED1_MSK;
486 /* change ACT LED control to blink mode */
487 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
488 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
491 case CHIP_ID_YUKON_FE_P:
492 /* Enable Link Partner Next Page */
493 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
494 ctrl |= PHY_M_PC_ENA_LIP_NP;
496 /* disable Energy Detect and enable scrambler */
497 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
498 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
500 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
501 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
502 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
503 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 case CHIP_ID_YUKON_XL:
509 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
511 /* select page 3 to access LED control register */
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
514 /* set LED Function Control register */
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
516 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
517 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
518 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
519 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
521 /* set Polarity Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
523 (PHY_M_POLC_LS1_P_MIX(4) |
524 PHY_M_POLC_IS0_P_MIX(4) |
525 PHY_M_POLC_LOS_CTRL(2) |
526 PHY_M_POLC_INIT_CTRL(2) |
527 PHY_M_POLC_STA1_CTRL(2) |
528 PHY_M_POLC_STA0_CTRL(2)));
530 /* restore page register */
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
534 case CHIP_ID_YUKON_EC_U:
535 case CHIP_ID_YUKON_EX:
536 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
538 /* select page 3 to access LED control register */
539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
541 /* set LED Function Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
543 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
544 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
545 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
546 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
548 /* set Blink Rate in LED Timer Control Register */
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
550 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
551 /* restore page register */
552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
556 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
557 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
558 /* turn off the Rx LED (LED_RX) */
559 ledover &= ~PHY_M_LED_MO_RX;
562 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
563 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
564 /* apply fixes in PHY AFE */
565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
567 /* increase differential signal amplitude in 10BASE-T */
568 gm_phy_write(hw, port, 0x18, 0xaa99);
569 gm_phy_write(hw, port, 0x17, 0x2011);
571 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
572 gm_phy_write(hw, port, 0x18, 0xa204);
573 gm_phy_write(hw, port, 0x17, 0x2002);
575 /* set page register to 0 */
576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
577 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
578 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
579 /* apply workaround for integrated resistors calibration */
580 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
581 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
582 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
583 /* no effect on Yukon-XL */
584 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
586 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
587 /* turn on 100 Mbps LED (LED_LINK100) */
588 ledover |= PHY_M_LED_MO_100;
592 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
596 /* Enable phy interrupt on auto-negotiation complete (or link up) */
597 if (sky2->autoneg == AUTONEG_ENABLE)
598 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
603 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
606 static const u32 phy_power[]
607 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
609 /* looks like this XL is back asswards .. */
610 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
613 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
615 /* Turn off phy power saving */
616 reg1 &= ~phy_power[port];
618 reg1 |= phy_power[port];
620 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
621 sky2_pci_read32(hw, PCI_DEV_REG1);
625 /* Force a renegotiation */
626 static void sky2_phy_reinit(struct sky2_port *sky2)
628 spin_lock_bh(&sky2->phy_lock);
629 sky2_phy_init(sky2->hw, sky2->port);
630 spin_unlock_bh(&sky2->phy_lock);
633 /* Put device in state to listen for Wake On Lan */
634 static void sky2_wol_init(struct sky2_port *sky2)
636 struct sky2_hw *hw = sky2->hw;
637 unsigned port = sky2->port;
638 enum flow_control save_mode;
642 /* Bring hardware out of reset */
643 sky2_write16(hw, B0_CTST, CS_RST_CLR);
644 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
646 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
650 * sky2_reset will re-enable on resume
652 save_mode = sky2->flow_mode;
653 ctrl = sky2->advertising;
655 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
656 sky2->flow_mode = FC_NONE;
657 sky2_phy_power(hw, port, 1);
658 sky2_phy_reinit(sky2);
660 sky2->flow_mode = save_mode;
661 sky2->advertising = ctrl;
663 /* Set GMAC to no flow control and auto update for speed/duplex */
664 gma_write16(hw, port, GM_GP_CTRL,
665 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
666 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
668 /* Set WOL address */
669 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
670 sky2->netdev->dev_addr, ETH_ALEN);
672 /* Turn on appropriate WOL control bits */
673 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
675 if (sky2->wol & WAKE_PHY)
676 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
678 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
680 if (sky2->wol & WAKE_MAGIC)
681 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
683 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
685 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
686 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
688 /* Turn on legacy PCI-Express PME mode */
689 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
690 reg1 |= PCI_Y2_PME_LEGACY;
691 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
694 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
698 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
700 struct net_device *dev = hw->dev[port];
702 if (dev->mtu <= ETH_DATA_LEN)
703 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
704 TX_JUMBO_DIS | TX_STFW_ENA);
706 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
707 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
708 TX_STFW_ENA | TX_JUMBO_ENA);
710 /* set Tx GMAC FIFO Almost Empty Threshold */
711 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
712 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
714 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
715 TX_JUMBO_ENA | TX_STFW_DIS);
717 /* Can't do offload because of lack of store/forward */
718 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
722 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
724 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
728 const u8 *addr = hw->dev[port]->dev_addr;
730 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
731 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
733 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
735 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
736 /* WA DEV_472 -- looks like crossed wires on port 2 */
737 /* clear GMAC 1 Control reset */
738 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
740 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
741 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
742 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
743 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
744 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
747 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
749 /* Enable Transmit FIFO Underrun */
750 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_init(hw, port);
754 spin_unlock_bh(&sky2->phy_lock);
757 reg = gma_read16(hw, port, GM_PHY_ADDR);
758 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
760 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
761 gma_read16(hw, port, i);
762 gma_write16(hw, port, GM_PHY_ADDR, reg);
764 /* transmit control */
765 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
767 /* receive control reg: unicast + multicast + no FCS */
768 gma_write16(hw, port, GM_RX_CTRL,
769 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
771 /* transmit flow control */
772 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
774 /* transmit parameter */
775 gma_write16(hw, port, GM_TX_PARAM,
776 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
777 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
778 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
779 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
781 /* serial mode register */
782 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
783 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
785 if (hw->dev[port]->mtu > ETH_DATA_LEN)
786 reg |= GM_SMOD_JUMBO_ENA;
788 gma_write16(hw, port, GM_SERIAL_MODE, reg);
790 /* virtual address for data */
791 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
793 /* physical address: used for pause frames */
794 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
796 /* ignore counter overflows */
797 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
798 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
799 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
801 /* Configure Rx MAC FIFO */
802 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
803 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
804 if (hw->chip_id == CHIP_ID_YUKON_EX ||
805 hw->chip_id == CHIP_ID_YUKON_FE_P)
806 rx_reg |= GMF_RX_OVER_ON;
808 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
810 /* Flush Rx MAC FIFO on any flow control or error */
811 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
813 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
814 reg = RX_GMF_FL_THR_DEF + 1;
815 /* Another magic mystery workaround from sk98lin */
816 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
817 hw->chip_rev == CHIP_REV_YU_FE2_A0)
819 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
821 /* Configure Tx MAC FIFO */
822 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
823 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
825 /* On chips without ram buffer, pause is controled by MAC level */
826 if (sky2_read8(hw, B2_E_0) == 0) {
827 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
828 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
830 sky2_set_tx_stfwd(hw, port);
835 /* Assign Ram Buffer allocation to queue */
836 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
840 /* convert from K bytes to qwords used for hw register */
843 end = start + space - 1;
845 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
846 sky2_write32(hw, RB_ADDR(q, RB_START), start);
847 sky2_write32(hw, RB_ADDR(q, RB_END), end);
848 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
849 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
851 if (q == Q_R1 || q == Q_R2) {
852 u32 tp = space - space/4;
854 /* On receive queue's set the thresholds
855 * give receiver priority when > 3/4 full
856 * send pause when down to 2K
858 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
859 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
862 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
863 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
865 /* Enable store & forward on Tx queue's because
866 * Tx FIFO is only 1K on Yukon
868 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
871 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
872 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
875 /* Setup Bus Memory Interface */
876 static void sky2_qset(struct sky2_hw *hw, u16 q)
878 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
879 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
880 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
881 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
884 /* Setup prefetch unit registers. This is the interface between
885 * hardware and driver list elements
887 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
890 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
891 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
892 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
893 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
894 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
897 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
900 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
902 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
904 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
909 static void tx_init(struct sky2_port *sky2)
911 struct sky2_tx_le *le;
913 sky2->tx_prod = sky2->tx_cons = 0;
915 sky2->tx_last_mss = 0;
917 le = get_tx_le(sky2);
919 le->opcode = OP_ADDR64 | HW_OWNER;
923 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
924 struct sky2_tx_le *le)
926 return sky2->tx_ring + (le - sky2->tx_le);
929 /* Update chip's next pointer */
930 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
932 /* Make sure write' to descriptors are complete before we tell hardware */
934 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
936 /* Synchronize I/O on since next processor may write to tail */
941 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
943 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
944 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
949 /* Build description to hardware for one receive segment */
950 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
951 dma_addr_t map, unsigned len)
953 struct sky2_rx_le *le;
954 u32 hi = upper_32_bits(map);
956 if (sky2->rx_addr64 != hi) {
957 le = sky2_next_rx(sky2);
958 le->addr = cpu_to_le32(hi);
959 le->opcode = OP_ADDR64 | HW_OWNER;
960 sky2->rx_addr64 = upper_32_bits(map + len);
963 le = sky2_next_rx(sky2);
964 le->addr = cpu_to_le32((u32) map);
965 le->length = cpu_to_le16(len);
966 le->opcode = op | HW_OWNER;
969 /* Build description to hardware for one possibly fragmented skb */
970 static void sky2_rx_submit(struct sky2_port *sky2,
971 const struct rx_ring_info *re)
975 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
977 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
978 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
982 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
985 struct sk_buff *skb = re->skb;
988 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
989 pci_unmap_len_set(re, data_size, size);
991 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
992 re->frag_addr[i] = pci_map_page(pdev,
993 skb_shinfo(skb)->frags[i].page,
994 skb_shinfo(skb)->frags[i].page_offset,
995 skb_shinfo(skb)->frags[i].size,
999 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1001 struct sk_buff *skb = re->skb;
1004 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1005 PCI_DMA_FROMDEVICE);
1007 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1008 pci_unmap_page(pdev, re->frag_addr[i],
1009 skb_shinfo(skb)->frags[i].size,
1010 PCI_DMA_FROMDEVICE);
1013 /* Tell chip where to start receive checksum.
1014 * Actually has two checksums, but set both same to avoid possible byte
1017 static void rx_set_checksum(struct sky2_port *sky2)
1019 struct sky2_rx_le *le = sky2_next_rx(sky2);
1021 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1023 le->opcode = OP_TCPSTART | HW_OWNER;
1025 sky2_write32(sky2->hw,
1026 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1027 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1031 * The RX Stop command will not work for Yukon-2 if the BMU does not
1032 * reach the end of packet and since we can't make sure that we have
1033 * incoming data, we must reset the BMU while it is not doing a DMA
1034 * transfer. Since it is possible that the RX path is still active,
1035 * the RX RAM buffer will be stopped first, so any possible incoming
1036 * data will not trigger a DMA. After the RAM buffer is stopped, the
1037 * BMU is polled until any DMA in progress is ended and only then it
1040 static void sky2_rx_stop(struct sky2_port *sky2)
1042 struct sky2_hw *hw = sky2->hw;
1043 unsigned rxq = rxqaddr[sky2->port];
1046 /* disable the RAM Buffer receive queue */
1047 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1049 for (i = 0; i < 0xffff; i++)
1050 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1051 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1054 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1055 sky2->netdev->name);
1057 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1059 /* reset the Rx prefetch unit */
1060 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1064 /* Clean out receive buffer area, assumes receiver hardware stopped */
1065 static void sky2_rx_clean(struct sky2_port *sky2)
1069 memset(sky2->rx_le, 0, RX_LE_BYTES);
1070 for (i = 0; i < sky2->rx_pending; i++) {
1071 struct rx_ring_info *re = sky2->rx_ring + i;
1074 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1081 /* Basic MII support */
1082 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1084 struct mii_ioctl_data *data = if_mii(ifr);
1085 struct sky2_port *sky2 = netdev_priv(dev);
1086 struct sky2_hw *hw = sky2->hw;
1087 int err = -EOPNOTSUPP;
1089 if (!netif_running(dev))
1090 return -ENODEV; /* Phy still in reset */
1094 data->phy_id = PHY_ADDR_MARV;
1100 spin_lock_bh(&sky2->phy_lock);
1101 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1102 spin_unlock_bh(&sky2->phy_lock);
1104 data->val_out = val;
1109 if (!capable(CAP_NET_ADMIN))
1112 spin_lock_bh(&sky2->phy_lock);
1113 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1115 spin_unlock_bh(&sky2->phy_lock);
1121 #ifdef SKY2_VLAN_TAG_USED
1122 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1124 struct sky2_port *sky2 = netdev_priv(dev);
1125 struct sky2_hw *hw = sky2->hw;
1126 u16 port = sky2->port;
1128 netif_tx_lock_bh(dev);
1129 napi_disable(&hw->napi);
1133 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1135 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1138 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1140 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1144 napi_enable(&hw->napi);
1145 netif_tx_unlock_bh(dev);
1150 * Allocate an skb for receiving. If the MTU is large enough
1151 * make the skb non-linear with a fragment list of pages.
1153 * It appears the hardware has a bug in the FIFO logic that
1154 * cause it to hang if the FIFO gets overrun and the receive buffer
1155 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1156 * aligned except if slab debugging is enabled.
1158 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1160 struct sk_buff *skb;
1164 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1168 p = (unsigned long) skb->data;
1169 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1171 for (i = 0; i < sky2->rx_nfrags; i++) {
1172 struct page *page = alloc_page(GFP_ATOMIC);
1176 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1186 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1188 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1192 * Allocate and setup receiver buffer pool.
1193 * Normal case this ends up creating one list element for skb
1194 * in the receive ring. Worst case if using large MTU and each
1195 * allocation falls on a different 64 bit region, that results
1196 * in 6 list elements per ring entry.
1197 * One element is used for checksum enable/disable, and one
1198 * extra to avoid wrap.
1200 static int sky2_rx_start(struct sky2_port *sky2)
1202 struct sky2_hw *hw = sky2->hw;
1203 struct rx_ring_info *re;
1204 unsigned rxq = rxqaddr[sky2->port];
1205 unsigned i, size, space, thresh;
1207 sky2->rx_put = sky2->rx_next = 0;
1210 /* On PCI express lowering the watermark gives better performance */
1211 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1212 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1214 /* These chips have no ram buffer?
1215 * MAC Rx RAM Read is controlled by hardware */
1216 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1217 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1218 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1219 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1221 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1223 if (!(hw->flags & SKY2_HW_NEW_LE))
1224 rx_set_checksum(sky2);
1226 /* Space needed for frame data + headers rounded up */
1227 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1229 /* Stopping point for hardware truncation */
1230 thresh = (size - 8) / sizeof(u32);
1232 /* Account for overhead of skb - to avoid order > 0 allocation */
1233 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1234 + sizeof(struct skb_shared_info);
1236 sky2->rx_nfrags = space >> PAGE_SHIFT;
1237 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1239 if (sky2->rx_nfrags != 0) {
1240 /* Compute residue after pages */
1241 space = sky2->rx_nfrags << PAGE_SHIFT;
1248 /* Optimize to handle small packets and headers */
1249 if (size < copybreak)
1251 if (size < ETH_HLEN)
1254 sky2->rx_data_size = size;
1257 for (i = 0; i < sky2->rx_pending; i++) {
1258 re = sky2->rx_ring + i;
1260 re->skb = sky2_rx_alloc(sky2);
1264 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1265 sky2_rx_submit(sky2, re);
1269 * The receiver hangs if it receives frames larger than the
1270 * packet buffer. As a workaround, truncate oversize frames, but
1271 * the register is limited to 9 bits, so if you do frames > 2052
1272 * you better get the MTU right!
1275 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1277 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1278 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1281 /* Tell chip about available buffers */
1282 sky2_rx_update(sky2, rxq);
1285 sky2_rx_clean(sky2);
1289 /* Bring up network interface. */
1290 static int sky2_up(struct net_device *dev)
1292 struct sky2_port *sky2 = netdev_priv(dev);
1293 struct sky2_hw *hw = sky2->hw;
1294 unsigned port = sky2->port;
1296 int cap, err = -ENOMEM;
1297 struct net_device *otherdev = hw->dev[sky2->port^1];
1300 * On dual port PCI-X card, there is an problem where status
1301 * can be received out of order due to split transactions
1303 if (otherdev && netif_running(otherdev) &&
1304 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1305 struct sky2_port *osky2 = netdev_priv(otherdev);
1308 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1309 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1310 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1316 if (netif_msg_ifup(sky2))
1317 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1319 netif_carrier_off(dev);
1321 /* must be power of 2 */
1322 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1324 sizeof(struct sky2_tx_le),
1329 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1336 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1340 memset(sky2->rx_le, 0, RX_LE_BYTES);
1342 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1347 sky2_phy_power(hw, port, 1);
1349 sky2_mac_init(hw, port);
1351 /* Register is number of 4K blocks on internal RAM buffer. */
1352 ramsize = sky2_read8(hw, B2_E_0) * 4;
1356 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1358 rxspace = ramsize / 2;
1360 rxspace = 8 + (2*(ramsize - 16))/3;
1362 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1363 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1365 /* Make sure SyncQ is disabled */
1366 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1370 sky2_qset(hw, txqaddr[port]);
1372 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1373 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1374 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1376 /* Set almost empty threshold */
1377 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1378 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1379 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1381 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1384 napi_enable(&hw->napi);
1386 err = sky2_rx_start(sky2);
1388 napi_disable(&hw->napi);
1392 /* Enable interrupts from phy/mac for port */
1393 imask = sky2_read32(hw, B0_IMSK);
1394 imask |= portirq_msk[port];
1395 sky2_write32(hw, B0_IMSK, imask);
1401 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1402 sky2->rx_le, sky2->rx_le_map);
1406 pci_free_consistent(hw->pdev,
1407 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1408 sky2->tx_le, sky2->tx_le_map);
1411 kfree(sky2->tx_ring);
1412 kfree(sky2->rx_ring);
1414 sky2->tx_ring = NULL;
1415 sky2->rx_ring = NULL;
1419 /* Modular subtraction in ring */
1420 static inline int tx_dist(unsigned tail, unsigned head)
1422 return (head - tail) & (TX_RING_SIZE - 1);
1425 /* Number of list elements available for next tx */
1426 static inline int tx_avail(const struct sky2_port *sky2)
1428 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1431 /* Estimate of number of transmit list elements required */
1432 static unsigned tx_le_req(const struct sk_buff *skb)
1436 count = sizeof(dma_addr_t) / sizeof(u32);
1437 count += skb_shinfo(skb)->nr_frags * count;
1439 if (skb_is_gso(skb))
1442 if (skb->ip_summed == CHECKSUM_PARTIAL)
1449 * Put one packet in ring for transmit.
1450 * A single packet can generate multiple list elements, and
1451 * the number of ring elements will probably be less than the number
1452 * of list elements used.
1454 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1456 struct sky2_port *sky2 = netdev_priv(dev);
1457 struct sky2_hw *hw = sky2->hw;
1458 struct sky2_tx_le *le = NULL;
1459 struct tx_ring_info *re;
1466 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1467 return NETDEV_TX_BUSY;
1469 if (unlikely(netif_msg_tx_queued(sky2)))
1470 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1471 dev->name, sky2->tx_prod, skb->len);
1473 len = skb_headlen(skb);
1474 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1475 addr64 = upper_32_bits(mapping);
1477 /* Send high bits if changed or crosses boundary */
1478 if (addr64 != sky2->tx_addr64 ||
1479 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1480 le = get_tx_le(sky2);
1481 le->addr = cpu_to_le32(addr64);
1482 le->opcode = OP_ADDR64 | HW_OWNER;
1483 sky2->tx_addr64 = upper_32_bits(mapping + len);
1486 /* Check for TCP Segmentation Offload */
1487 mss = skb_shinfo(skb)->gso_size;
1490 if (!(hw->flags & SKY2_HW_NEW_LE))
1491 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1493 if (mss != sky2->tx_last_mss) {
1494 le = get_tx_le(sky2);
1495 le->addr = cpu_to_le32(mss);
1497 if (hw->flags & SKY2_HW_NEW_LE)
1498 le->opcode = OP_MSS | HW_OWNER;
1500 le->opcode = OP_LRGLEN | HW_OWNER;
1501 sky2->tx_last_mss = mss;
1506 #ifdef SKY2_VLAN_TAG_USED
1507 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1508 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1510 le = get_tx_le(sky2);
1512 le->opcode = OP_VLAN|HW_OWNER;
1514 le->opcode |= OP_VLAN;
1515 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1520 /* Handle TCP checksum offload */
1521 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1522 /* On Yukon EX (some versions) encoding change. */
1523 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1524 ctrl |= CALSUM; /* auto checksum */
1526 const unsigned offset = skb_transport_offset(skb);
1529 tcpsum = offset << 16; /* sum start */
1530 tcpsum |= offset + skb->csum_offset; /* sum write */
1532 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1533 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1536 if (tcpsum != sky2->tx_tcpsum) {
1537 sky2->tx_tcpsum = tcpsum;
1539 le = get_tx_le(sky2);
1540 le->addr = cpu_to_le32(tcpsum);
1541 le->length = 0; /* initial checksum value */
1542 le->ctrl = 1; /* one packet */
1543 le->opcode = OP_TCPLISW | HW_OWNER;
1548 le = get_tx_le(sky2);
1549 le->addr = cpu_to_le32((u32) mapping);
1550 le->length = cpu_to_le16(len);
1552 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1554 re = tx_le_re(sky2, le);
1556 pci_unmap_addr_set(re, mapaddr, mapping);
1557 pci_unmap_len_set(re, maplen, len);
1559 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1560 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1562 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1563 frag->size, PCI_DMA_TODEVICE);
1564 addr64 = upper_32_bits(mapping);
1565 if (addr64 != sky2->tx_addr64) {
1566 le = get_tx_le(sky2);
1567 le->addr = cpu_to_le32(addr64);
1569 le->opcode = OP_ADDR64 | HW_OWNER;
1570 sky2->tx_addr64 = addr64;
1573 le = get_tx_le(sky2);
1574 le->addr = cpu_to_le32((u32) mapping);
1575 le->length = cpu_to_le16(frag->size);
1577 le->opcode = OP_BUFFER | HW_OWNER;
1579 re = tx_le_re(sky2, le);
1581 pci_unmap_addr_set(re, mapaddr, mapping);
1582 pci_unmap_len_set(re, maplen, frag->size);
1587 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1588 netif_stop_queue(dev);
1590 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1592 dev->trans_start = jiffies;
1593 return NETDEV_TX_OK;
1597 * Free ring elements from starting at tx_cons until "done"
1599 * NB: the hardware will tell us about partial completion of multi-part
1600 * buffers so make sure not to free skb to early.
1602 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1604 struct net_device *dev = sky2->netdev;
1605 struct pci_dev *pdev = sky2->hw->pdev;
1608 BUG_ON(done >= TX_RING_SIZE);
1610 for (idx = sky2->tx_cons; idx != done;
1611 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1612 struct sky2_tx_le *le = sky2->tx_le + idx;
1613 struct tx_ring_info *re = sky2->tx_ring + idx;
1615 switch(le->opcode & ~HW_OWNER) {
1618 pci_unmap_single(pdev,
1619 pci_unmap_addr(re, mapaddr),
1620 pci_unmap_len(re, maplen),
1624 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1625 pci_unmap_len(re, maplen),
1630 if (le->ctrl & EOP) {
1631 if (unlikely(netif_msg_tx_done(sky2)))
1632 printk(KERN_DEBUG "%s: tx done %u\n",
1635 sky2->net_stats.tx_packets++;
1636 sky2->net_stats.tx_bytes += re->skb->len;
1638 dev_kfree_skb_any(re->skb);
1639 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1643 sky2->tx_cons = idx;
1646 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1647 netif_wake_queue(dev);
1650 /* Cleanup all untransmitted buffers, assume transmitter not running */
1651 static void sky2_tx_clean(struct net_device *dev)
1653 struct sky2_port *sky2 = netdev_priv(dev);
1655 netif_tx_lock_bh(dev);
1656 sky2_tx_complete(sky2, sky2->tx_prod);
1657 netif_tx_unlock_bh(dev);
1660 /* Network shutdown */
1661 static int sky2_down(struct net_device *dev)
1663 struct sky2_port *sky2 = netdev_priv(dev);
1664 struct sky2_hw *hw = sky2->hw;
1665 unsigned port = sky2->port;
1669 /* Never really got started! */
1673 if (netif_msg_ifdown(sky2))
1674 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1676 /* Stop more packets from being queued */
1677 netif_stop_queue(dev);
1679 napi_disable(&hw->napi);
1681 /* Disable port IRQ */
1682 imask = sky2_read32(hw, B0_IMSK);
1683 imask &= ~portirq_msk[port];
1684 sky2_write32(hw, B0_IMSK, imask);
1686 sky2_gmac_reset(hw, port);
1688 /* Stop transmitter */
1689 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1690 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1692 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1693 RB_RST_SET | RB_DIS_OP_MD);
1695 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1696 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1697 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1699 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1701 /* Workaround shared GMAC reset */
1702 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1703 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1704 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1706 /* Disable Force Sync bit and Enable Alloc bit */
1707 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1708 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1710 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1711 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1712 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1714 /* Reset the PCI FIFO of the async Tx queue */
1715 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1716 BMU_RST_SET | BMU_FIFO_RST);
1718 /* Reset the Tx prefetch units */
1719 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1722 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1726 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1727 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1729 sky2_phy_power(hw, port, 0);
1731 netif_carrier_off(dev);
1733 /* turn off LED's */
1734 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1736 synchronize_irq(hw->pdev->irq);
1739 sky2_rx_clean(sky2);
1741 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1742 sky2->rx_le, sky2->rx_le_map);
1743 kfree(sky2->rx_ring);
1745 pci_free_consistent(hw->pdev,
1746 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1747 sky2->tx_le, sky2->tx_le_map);
1748 kfree(sky2->tx_ring);
1753 sky2->rx_ring = NULL;
1754 sky2->tx_ring = NULL;
1759 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1761 if (hw->flags & SKY2_HW_FIBRE_PHY)
1764 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1765 if (aux & PHY_M_PS_SPEED_100)
1771 switch (aux & PHY_M_PS_SPEED_MSK) {
1772 case PHY_M_PS_SPEED_1000:
1774 case PHY_M_PS_SPEED_100:
1781 static void sky2_link_up(struct sky2_port *sky2)
1783 struct sky2_hw *hw = sky2->hw;
1784 unsigned port = sky2->port;
1786 static const char *fc_name[] = {
1794 reg = gma_read16(hw, port, GM_GP_CTRL);
1795 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1796 gma_write16(hw, port, GM_GP_CTRL, reg);
1798 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1800 netif_carrier_on(sky2->netdev);
1802 mod_timer(&hw->watchdog_timer, jiffies + 1);
1804 /* Turn on link LED */
1805 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1806 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1808 if (hw->flags & SKY2_HW_NEWER_PHY) {
1809 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1810 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1812 switch(sky2->speed) {
1814 led |= PHY_M_LEDC_INIT_CTRL(7);
1818 led |= PHY_M_LEDC_STA1_CTRL(7);
1822 led |= PHY_M_LEDC_STA0_CTRL(7);
1826 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1827 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1828 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1831 if (netif_msg_link(sky2))
1832 printk(KERN_INFO PFX
1833 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1834 sky2->netdev->name, sky2->speed,
1835 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1836 fc_name[sky2->flow_status]);
1839 static void sky2_link_down(struct sky2_port *sky2)
1841 struct sky2_hw *hw = sky2->hw;
1842 unsigned port = sky2->port;
1845 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1847 reg = gma_read16(hw, port, GM_GP_CTRL);
1848 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1849 gma_write16(hw, port, GM_GP_CTRL, reg);
1851 netif_carrier_off(sky2->netdev);
1853 /* Turn on link LED */
1854 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1856 if (netif_msg_link(sky2))
1857 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1859 sky2_phy_init(hw, port);
1862 static enum flow_control sky2_flow(int rx, int tx)
1865 return tx ? FC_BOTH : FC_RX;
1867 return tx ? FC_TX : FC_NONE;
1870 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1872 struct sky2_hw *hw = sky2->hw;
1873 unsigned port = sky2->port;
1876 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1877 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1878 if (lpa & PHY_M_AN_RF) {
1879 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1883 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1884 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1885 sky2->netdev->name);
1889 sky2->speed = sky2_phy_speed(hw, aux);
1890 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1892 /* Since the pause result bits seem to in different positions on
1893 * different chips. look at registers.
1895 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1896 /* Shift for bits in fiber PHY */
1897 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1898 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1900 if (advert & ADVERTISE_1000XPAUSE)
1901 advert |= ADVERTISE_PAUSE_CAP;
1902 if (advert & ADVERTISE_1000XPSE_ASYM)
1903 advert |= ADVERTISE_PAUSE_ASYM;
1904 if (lpa & LPA_1000XPAUSE)
1905 lpa |= LPA_PAUSE_CAP;
1906 if (lpa & LPA_1000XPAUSE_ASYM)
1907 lpa |= LPA_PAUSE_ASYM;
1910 sky2->flow_status = FC_NONE;
1911 if (advert & ADVERTISE_PAUSE_CAP) {
1912 if (lpa & LPA_PAUSE_CAP)
1913 sky2->flow_status = FC_BOTH;
1914 else if (advert & ADVERTISE_PAUSE_ASYM)
1915 sky2->flow_status = FC_RX;
1916 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1917 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1918 sky2->flow_status = FC_TX;
1921 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1922 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1923 sky2->flow_status = FC_NONE;
1925 if (sky2->flow_status & FC_TX)
1926 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1928 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1933 /* Interrupt from PHY */
1934 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1936 struct net_device *dev = hw->dev[port];
1937 struct sky2_port *sky2 = netdev_priv(dev);
1938 u16 istatus, phystat;
1940 if (!netif_running(dev))
1943 spin_lock(&sky2->phy_lock);
1944 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1945 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1947 if (netif_msg_intr(sky2))
1948 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1949 sky2->netdev->name, istatus, phystat);
1951 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1952 if (sky2_autoneg_done(sky2, phystat) == 0)
1957 if (istatus & PHY_M_IS_LSP_CHANGE)
1958 sky2->speed = sky2_phy_speed(hw, phystat);
1960 if (istatus & PHY_M_IS_DUP_CHANGE)
1962 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1964 if (istatus & PHY_M_IS_LST_CHANGE) {
1965 if (phystat & PHY_M_PS_LINK_UP)
1968 sky2_link_down(sky2);
1971 spin_unlock(&sky2->phy_lock);
1974 /* Transmit timeout is only called if we are running, carrier is up
1975 * and tx queue is full (stopped).
1977 static void sky2_tx_timeout(struct net_device *dev)
1979 struct sky2_port *sky2 = netdev_priv(dev);
1980 struct sky2_hw *hw = sky2->hw;
1982 if (netif_msg_timer(sky2))
1983 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1985 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1986 dev->name, sky2->tx_cons, sky2->tx_prod,
1987 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1988 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1990 /* can't restart safely under softirq */
1991 schedule_work(&hw->restart_work);
1994 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1996 struct sky2_port *sky2 = netdev_priv(dev);
1997 struct sky2_hw *hw = sky2->hw;
1998 unsigned port = sky2->port;
2003 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2006 if (new_mtu > ETH_DATA_LEN &&
2007 (hw->chip_id == CHIP_ID_YUKON_FE ||
2008 hw->chip_id == CHIP_ID_YUKON_FE_P))
2011 if (!netif_running(dev)) {
2016 imask = sky2_read32(hw, B0_IMSK);
2017 sky2_write32(hw, B0_IMSK, 0);
2019 dev->trans_start = jiffies; /* prevent tx timeout */
2020 netif_stop_queue(dev);
2021 napi_disable(&hw->napi);
2023 synchronize_irq(hw->pdev->irq);
2025 if (sky2_read8(hw, B2_E_0) == 0)
2026 sky2_set_tx_stfwd(hw, port);
2028 ctl = gma_read16(hw, port, GM_GP_CTRL);
2029 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2031 sky2_rx_clean(sky2);
2035 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2036 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2038 if (dev->mtu > ETH_DATA_LEN)
2039 mode |= GM_SMOD_JUMBO_ENA;
2041 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2043 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2045 err = sky2_rx_start(sky2);
2046 sky2_write32(hw, B0_IMSK, imask);
2048 /* Unconditionally re-enable NAPI because even if we
2049 * call dev_close() that will do a napi_disable().
2051 napi_enable(&hw->napi);
2056 gma_write16(hw, port, GM_GP_CTRL, ctl);
2058 netif_wake_queue(dev);
2064 /* For small just reuse existing skb for next receive */
2065 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2066 const struct rx_ring_info *re,
2069 struct sk_buff *skb;
2071 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2073 skb_reserve(skb, 2);
2074 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2075 length, PCI_DMA_FROMDEVICE);
2076 skb_copy_from_linear_data(re->skb, skb->data, length);
2077 skb->ip_summed = re->skb->ip_summed;
2078 skb->csum = re->skb->csum;
2079 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2080 length, PCI_DMA_FROMDEVICE);
2081 re->skb->ip_summed = CHECKSUM_NONE;
2082 skb_put(skb, length);
2087 /* Adjust length of skb with fragments to match received data */
2088 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2089 unsigned int length)
2094 /* put header into skb */
2095 size = min(length, hdr_space);
2100 num_frags = skb_shinfo(skb)->nr_frags;
2101 for (i = 0; i < num_frags; i++) {
2102 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2105 /* don't need this page */
2106 __free_page(frag->page);
2107 --skb_shinfo(skb)->nr_frags;
2109 size = min(length, (unsigned) PAGE_SIZE);
2112 skb->data_len += size;
2113 skb->truesize += size;
2120 /* Normal packet - take skb from ring element and put in a new one */
2121 static struct sk_buff *receive_new(struct sky2_port *sky2,
2122 struct rx_ring_info *re,
2123 unsigned int length)
2125 struct sk_buff *skb, *nskb;
2126 unsigned hdr_space = sky2->rx_data_size;
2128 /* Don't be tricky about reusing pages (yet) */
2129 nskb = sky2_rx_alloc(sky2);
2130 if (unlikely(!nskb))
2134 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2136 prefetch(skb->data);
2138 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2140 if (skb_shinfo(skb)->nr_frags)
2141 skb_put_frags(skb, hdr_space, length);
2143 skb_put(skb, length);
2148 * Receive one packet.
2149 * For larger packets, get new buffer.
2151 static struct sk_buff *sky2_receive(struct net_device *dev,
2152 u16 length, u32 status)
2154 struct sky2_port *sky2 = netdev_priv(dev);
2155 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2156 struct sk_buff *skb = NULL;
2157 u16 count = (status & GMR_FS_LEN) >> 16;
2159 #ifdef SKY2_VLAN_TAG_USED
2160 /* Account for vlan tag */
2161 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2165 if (unlikely(netif_msg_rx_status(sky2)))
2166 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2167 dev->name, sky2->rx_next, status, length);
2169 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2170 prefetch(sky2->rx_ring + sky2->rx_next);
2172 /* This chip has hardware problems that generates bogus status.
2173 * So do only marginal checking and expect higher level protocols
2174 * to handle crap frames.
2176 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2177 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2181 if (status & GMR_FS_ANY_ERR)
2184 if (!(status & GMR_FS_RX_OK))
2187 /* if length reported by DMA does not match PHY, packet was truncated */
2188 if (length != count)
2192 if (length < copybreak)
2193 skb = receive_copy(sky2, re, length);
2195 skb = receive_new(sky2, re, length);
2197 sky2_rx_submit(sky2, re);
2202 /* Truncation of overlength packets
2203 causes PHY length to not match MAC length */
2204 ++sky2->net_stats.rx_length_errors;
2205 if (netif_msg_rx_err(sky2) && net_ratelimit())
2206 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2207 dev->name, status, length);
2211 ++sky2->net_stats.rx_errors;
2212 if (status & GMR_FS_RX_FF_OV) {
2213 sky2->net_stats.rx_over_errors++;
2217 if (netif_msg_rx_err(sky2) && net_ratelimit())
2218 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2219 dev->name, status, length);
2221 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2222 sky2->net_stats.rx_length_errors++;
2223 if (status & GMR_FS_FRAGMENT)
2224 sky2->net_stats.rx_frame_errors++;
2225 if (status & GMR_FS_CRC_ERR)
2226 sky2->net_stats.rx_crc_errors++;
2231 /* Transmit complete */
2232 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2234 struct sky2_port *sky2 = netdev_priv(dev);
2236 if (netif_running(dev)) {
2238 sky2_tx_complete(sky2, last);
2239 netif_tx_unlock(dev);
2243 /* Process status response ring */
2244 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2247 unsigned rx[2] = { 0, 0 };
2248 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2252 while (hw->st_idx != hwidx) {
2253 struct sky2_port *sky2;
2254 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2255 unsigned port = le->css & CSS_LINK_BIT;
2256 struct net_device *dev;
2257 struct sk_buff *skb;
2261 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2263 dev = hw->dev[port];
2264 sky2 = netdev_priv(dev);
2265 length = le16_to_cpu(le->length);
2266 status = le32_to_cpu(le->status);
2268 switch (le->opcode & ~HW_OWNER) {
2271 skb = sky2_receive(dev, length, status);
2272 if (unlikely(!skb)) {
2273 sky2->net_stats.rx_dropped++;
2277 /* This chip reports checksum status differently */
2278 if (hw->flags & SKY2_HW_NEW_LE) {
2279 if (sky2->rx_csum &&
2280 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2281 (le->css & CSS_TCPUDPCSOK))
2282 skb->ip_summed = CHECKSUM_UNNECESSARY;
2284 skb->ip_summed = CHECKSUM_NONE;
2287 skb->protocol = eth_type_trans(skb, dev);
2288 sky2->net_stats.rx_packets++;
2289 sky2->net_stats.rx_bytes += skb->len;
2290 dev->last_rx = jiffies;
2292 #ifdef SKY2_VLAN_TAG_USED
2293 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2294 vlan_hwaccel_receive_skb(skb,
2296 be16_to_cpu(sky2->rx_tag));
2299 netif_receive_skb(skb);
2301 /* Stop after net poll weight */
2302 if (++work_done >= to_do)
2306 #ifdef SKY2_VLAN_TAG_USED
2308 sky2->rx_tag = length;
2312 sky2->rx_tag = length;
2319 /* If this happens then driver assuming wrong format */
2320 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2321 if (net_ratelimit())
2322 printk(KERN_NOTICE "%s: unexpected"
2323 " checksum status\n",
2328 /* Both checksum counters are programmed to start at
2329 * the same offset, so unless there is a problem they
2330 * should match. This failure is an early indication that
2331 * hardware receive checksumming won't work.
2333 if (likely(status >> 16 == (status & 0xffff))) {
2334 skb = sky2->rx_ring[sky2->rx_next].skb;
2335 skb->ip_summed = CHECKSUM_COMPLETE;
2336 skb->csum = status & 0xffff;
2338 printk(KERN_NOTICE PFX "%s: hardware receive "
2339 "checksum problem (status = %#x)\n",
2342 sky2_write32(sky2->hw,
2343 Q_ADDR(rxqaddr[port], Q_CSR),
2349 /* TX index reports status for both ports */
2350 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2351 sky2_tx_done(hw->dev[0], status & 0xfff);
2353 sky2_tx_done(hw->dev[1],
2354 ((status >> 24) & 0xff)
2355 | (u16)(length & 0xf) << 8);
2359 if (net_ratelimit())
2360 printk(KERN_WARNING PFX
2361 "unknown status opcode 0x%x\n", le->opcode);
2365 /* Fully processed status ring so clear irq */
2366 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2370 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2373 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2378 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2380 struct net_device *dev = hw->dev[port];
2382 if (net_ratelimit())
2383 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2386 if (status & Y2_IS_PAR_RD1) {
2387 if (net_ratelimit())
2388 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2391 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2394 if (status & Y2_IS_PAR_WR1) {
2395 if (net_ratelimit())
2396 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2399 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2402 if (status & Y2_IS_PAR_MAC1) {
2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2405 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2408 if (status & Y2_IS_PAR_RX1) {
2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2411 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2414 if (status & Y2_IS_TCP_TXA1) {
2415 if (net_ratelimit())
2416 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2418 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2422 static void sky2_hw_intr(struct sky2_hw *hw)
2424 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2426 if (status & Y2_IS_TIST_OV)
2427 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2429 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2432 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2433 if (net_ratelimit())
2434 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2437 sky2_pci_write16(hw, PCI_STATUS,
2438 pci_err | PCI_STATUS_ERROR_BITS);
2441 if (status & Y2_IS_PCI_EXP) {
2442 /* PCI-Express uncorrectable Error occurred */
2445 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2447 if (net_ratelimit())
2448 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2451 /* clear the interrupt */
2452 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2454 if (pex_err & PEX_FATAL_ERRORS) {
2455 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2456 hwmsk &= ~Y2_IS_PCI_EXP;
2457 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2461 if (status & Y2_HWE_L1_MASK)
2462 sky2_hw_error(hw, 0, status);
2464 if (status & Y2_HWE_L1_MASK)
2465 sky2_hw_error(hw, 1, status);
2468 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2470 struct net_device *dev = hw->dev[port];
2471 struct sky2_port *sky2 = netdev_priv(dev);
2472 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2474 if (netif_msg_intr(sky2))
2475 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2478 if (status & GM_IS_RX_CO_OV)
2479 gma_read16(hw, port, GM_RX_IRQ_SRC);
2481 if (status & GM_IS_TX_CO_OV)
2482 gma_read16(hw, port, GM_TX_IRQ_SRC);
2484 if (status & GM_IS_RX_FF_OR) {
2485 ++sky2->net_stats.rx_fifo_errors;
2486 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2489 if (status & GM_IS_TX_FF_UR) {
2490 ++sky2->net_stats.tx_fifo_errors;
2491 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2495 /* This should never happen it is a bug. */
2496 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2497 u16 q, unsigned ring_size)
2499 struct net_device *dev = hw->dev[port];
2500 struct sky2_port *sky2 = netdev_priv(dev);
2502 const u64 *le = (q == Q_R1 || q == Q_R2)
2503 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2505 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2506 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2507 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2508 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2510 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2513 static int sky2_rx_hung(struct net_device *dev)
2515 struct sky2_port *sky2 = netdev_priv(dev);
2516 struct sky2_hw *hw = sky2->hw;
2517 unsigned port = sky2->port;
2518 unsigned rxq = rxqaddr[port];
2519 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2520 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2521 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2522 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2524 /* If idle and MAC or PCI is stuck */
2525 if (sky2->check.last == dev->last_rx &&
2526 ((mac_rp == sky2->check.mac_rp &&
2527 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2528 /* Check if the PCI RX hang */
2529 (fifo_rp == sky2->check.fifo_rp &&
2530 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2531 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2532 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2533 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2536 sky2->check.last = dev->last_rx;
2537 sky2->check.mac_rp = mac_rp;
2538 sky2->check.mac_lev = mac_lev;
2539 sky2->check.fifo_rp = fifo_rp;
2540 sky2->check.fifo_lev = fifo_lev;
2545 static void sky2_watchdog(unsigned long arg)
2547 struct sky2_hw *hw = (struct sky2_hw *) arg;
2549 /* Check for lost IRQ once a second */
2550 if (sky2_read32(hw, B0_ISRC)) {
2551 napi_schedule(&hw->napi);
2555 for (i = 0; i < hw->ports; i++) {
2556 struct net_device *dev = hw->dev[i];
2557 if (!netif_running(dev))
2561 /* For chips with Rx FIFO, check if stuck */
2562 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2563 sky2_rx_hung(dev)) {
2564 pr_info(PFX "%s: receiver hang detected\n",
2566 schedule_work(&hw->restart_work);
2575 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2578 /* Hardware/software error handling */
2579 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2581 if (net_ratelimit())
2582 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2584 if (status & Y2_IS_HW_ERR)
2587 if (status & Y2_IS_IRQ_MAC1)
2588 sky2_mac_intr(hw, 0);
2590 if (status & Y2_IS_IRQ_MAC2)
2591 sky2_mac_intr(hw, 1);
2593 if (status & Y2_IS_CHK_RX1)
2594 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2596 if (status & Y2_IS_CHK_RX2)
2597 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2599 if (status & Y2_IS_CHK_TXA1)
2600 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2602 if (status & Y2_IS_CHK_TXA2)
2603 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2606 static int sky2_poll(struct napi_struct *napi, int work_limit)
2608 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2609 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2612 if (unlikely(status & Y2_IS_ERROR))
2613 sky2_err_intr(hw, status);
2615 if (status & Y2_IS_IRQ_PHY1)
2616 sky2_phy_intr(hw, 0);
2618 if (status & Y2_IS_IRQ_PHY2)
2619 sky2_phy_intr(hw, 1);
2621 work_done = sky2_status_intr(hw, work_limit);
2624 if (hw->st_idx == sky2_read16(hw, STAT_PUT_IDX)) {
2625 /* Bug/Errata workaround?
2626 * Need to kick the TX irq moderation timer.
2628 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2629 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2630 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2633 napi_complete(napi);
2634 sky2_read32(hw, B0_Y2_SP_LISR);
2639 static irqreturn_t sky2_intr(int irq, void *dev_id)
2641 struct sky2_hw *hw = dev_id;
2644 /* Reading this mask interrupts as side effect */
2645 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2646 if (status == 0 || status == ~0)
2649 prefetch(&hw->st_le[hw->st_idx]);
2651 napi_schedule(&hw->napi);
2656 #ifdef CONFIG_NET_POLL_CONTROLLER
2657 static void sky2_netpoll(struct net_device *dev)
2659 struct sky2_port *sky2 = netdev_priv(dev);
2661 napi_schedule(&sky2->hw->napi);
2665 /* Chip internal frequency for clock calculations */
2666 static u32 sky2_mhz(const struct sky2_hw *hw)
2668 switch (hw->chip_id) {
2669 case CHIP_ID_YUKON_EC:
2670 case CHIP_ID_YUKON_EC_U:
2671 case CHIP_ID_YUKON_EX:
2674 case CHIP_ID_YUKON_FE:
2677 case CHIP_ID_YUKON_FE_P:
2680 case CHIP_ID_YUKON_XL:
2688 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2690 return sky2_mhz(hw) * us;
2693 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2695 return clk / sky2_mhz(hw);
2699 static int __devinit sky2_init(struct sky2_hw *hw)
2703 /* Enable all clocks */
2704 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2706 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2708 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2709 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2711 switch(hw->chip_id) {
2712 case CHIP_ID_YUKON_XL:
2713 hw->flags = SKY2_HW_GIGABIT
2714 | SKY2_HW_NEWER_PHY;
2715 if (hw->chip_rev < 3)
2716 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2720 case CHIP_ID_YUKON_EC_U:
2721 hw->flags = SKY2_HW_GIGABIT
2723 | SKY2_HW_ADV_POWER_CTL;
2726 case CHIP_ID_YUKON_EX:
2727 hw->flags = SKY2_HW_GIGABIT
2730 | SKY2_HW_ADV_POWER_CTL;
2732 /* New transmit checksum */
2733 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2734 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2737 case CHIP_ID_YUKON_EC:
2738 /* This rev is really old, and requires untested workarounds */
2739 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2740 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2743 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2746 case CHIP_ID_YUKON_FE:
2749 case CHIP_ID_YUKON_FE_P:
2750 hw->flags = SKY2_HW_NEWER_PHY
2752 | SKY2_HW_AUTO_TX_SUM
2753 | SKY2_HW_ADV_POWER_CTL;
2756 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2761 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2762 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2763 hw->flags |= SKY2_HW_FIBRE_PHY;
2767 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2768 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2769 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2776 static void sky2_reset(struct sky2_hw *hw)
2782 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2783 status = sky2_read16(hw, HCU_CCSR);
2784 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2785 HCU_CCSR_UC_STATE_MSK);
2786 sky2_write16(hw, HCU_CCSR, status);
2788 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2789 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2792 sky2_write8(hw, B0_CTST, CS_RST_SET);
2793 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2795 /* clear PCI errors, if any */
2796 status = sky2_pci_read16(hw, PCI_STATUS);
2798 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2801 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2803 /* clear any PEX errors */
2804 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2805 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2810 for (i = 0; i < hw->ports; i++) {
2811 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2812 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2814 if (hw->chip_id == CHIP_ID_YUKON_EX)
2815 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2816 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2820 /* Clear I2C IRQ noise */
2821 sky2_write32(hw, B2_I2C_IRQ, 1);
2823 /* turn off hardware timer (unused) */
2824 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2825 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2827 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2829 /* Turn off descriptor polling */
2830 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2832 /* Turn off receive timestamp */
2833 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2834 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2836 /* enable the Tx Arbiters */
2837 for (i = 0; i < hw->ports; i++)
2838 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2840 /* Initialize ram interface */
2841 for (i = 0; i < hw->ports; i++) {
2842 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2844 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2845 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2846 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2847 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2848 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2849 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2850 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2851 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2852 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2855 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2858 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2860 for (i = 0; i < hw->ports; i++)
2861 sky2_gmac_reset(hw, i);
2863 memset(hw->st_le, 0, STATUS_LE_BYTES);
2866 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2867 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2869 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2870 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2872 /* Set the list last index */
2873 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2875 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2876 sky2_write8(hw, STAT_FIFO_WM, 16);
2878 /* set Status-FIFO ISR watermark */
2879 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2880 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2882 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2884 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2885 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2886 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2888 /* enable status unit */
2889 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2891 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2892 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2893 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2896 static void sky2_restart(struct work_struct *work)
2898 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2899 struct net_device *dev;
2903 sky2_write32(hw, B0_IMSK, 0);
2904 sky2_read32(hw, B0_IMSK);
2906 for (i = 0; i < hw->ports; i++) {
2908 if (netif_running(dev))
2913 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2915 for (i = 0; i < hw->ports; i++) {
2917 if (netif_running(dev)) {
2920 printk(KERN_INFO PFX "%s: could not restart %d\n",
2930 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2932 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2935 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2937 const struct sky2_port *sky2 = netdev_priv(dev);
2939 wol->supported = sky2_wol_supported(sky2->hw);
2940 wol->wolopts = sky2->wol;
2943 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2945 struct sky2_port *sky2 = netdev_priv(dev);
2946 struct sky2_hw *hw = sky2->hw;
2948 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2951 sky2->wol = wol->wolopts;
2953 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2954 hw->chip_id == CHIP_ID_YUKON_EX ||
2955 hw->chip_id == CHIP_ID_YUKON_FE_P)
2956 sky2_write32(hw, B0_CTST, sky2->wol
2957 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2959 if (!netif_running(dev))
2960 sky2_wol_init(sky2);
2964 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2966 if (sky2_is_copper(hw)) {
2967 u32 modes = SUPPORTED_10baseT_Half
2968 | SUPPORTED_10baseT_Full
2969 | SUPPORTED_100baseT_Half
2970 | SUPPORTED_100baseT_Full
2971 | SUPPORTED_Autoneg | SUPPORTED_TP;
2973 if (hw->flags & SKY2_HW_GIGABIT)
2974 modes |= SUPPORTED_1000baseT_Half
2975 | SUPPORTED_1000baseT_Full;
2978 return SUPPORTED_1000baseT_Half
2979 | SUPPORTED_1000baseT_Full
2984 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2986 struct sky2_port *sky2 = netdev_priv(dev);
2987 struct sky2_hw *hw = sky2->hw;
2989 ecmd->transceiver = XCVR_INTERNAL;
2990 ecmd->supported = sky2_supported_modes(hw);
2991 ecmd->phy_address = PHY_ADDR_MARV;
2992 if (sky2_is_copper(hw)) {
2993 ecmd->port = PORT_TP;
2994 ecmd->speed = sky2->speed;
2996 ecmd->speed = SPEED_1000;
2997 ecmd->port = PORT_FIBRE;
3000 ecmd->advertising = sky2->advertising;
3001 ecmd->autoneg = sky2->autoneg;
3002 ecmd->duplex = sky2->duplex;
3006 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3008 struct sky2_port *sky2 = netdev_priv(dev);
3009 const struct sky2_hw *hw = sky2->hw;
3010 u32 supported = sky2_supported_modes(hw);
3012 if (ecmd->autoneg == AUTONEG_ENABLE) {
3013 ecmd->advertising = supported;
3019 switch (ecmd->speed) {
3021 if (ecmd->duplex == DUPLEX_FULL)
3022 setting = SUPPORTED_1000baseT_Full;
3023 else if (ecmd->duplex == DUPLEX_HALF)
3024 setting = SUPPORTED_1000baseT_Half;
3029 if (ecmd->duplex == DUPLEX_FULL)
3030 setting = SUPPORTED_100baseT_Full;
3031 else if (ecmd->duplex == DUPLEX_HALF)
3032 setting = SUPPORTED_100baseT_Half;
3038 if (ecmd->duplex == DUPLEX_FULL)
3039 setting = SUPPORTED_10baseT_Full;
3040 else if (ecmd->duplex == DUPLEX_HALF)
3041 setting = SUPPORTED_10baseT_Half;
3049 if ((setting & supported) == 0)
3052 sky2->speed = ecmd->speed;
3053 sky2->duplex = ecmd->duplex;
3056 sky2->autoneg = ecmd->autoneg;
3057 sky2->advertising = ecmd->advertising;
3059 if (netif_running(dev)) {
3060 sky2_phy_reinit(sky2);
3061 sky2_set_multicast(dev);
3067 static void sky2_get_drvinfo(struct net_device *dev,
3068 struct ethtool_drvinfo *info)
3070 struct sky2_port *sky2 = netdev_priv(dev);
3072 strcpy(info->driver, DRV_NAME);
3073 strcpy(info->version, DRV_VERSION);
3074 strcpy(info->fw_version, "N/A");
3075 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3078 static const struct sky2_stat {
3079 char name[ETH_GSTRING_LEN];
3082 { "tx_bytes", GM_TXO_OK_HI },
3083 { "rx_bytes", GM_RXO_OK_HI },
3084 { "tx_broadcast", GM_TXF_BC_OK },
3085 { "rx_broadcast", GM_RXF_BC_OK },
3086 { "tx_multicast", GM_TXF_MC_OK },
3087 { "rx_multicast", GM_RXF_MC_OK },
3088 { "tx_unicast", GM_TXF_UC_OK },
3089 { "rx_unicast", GM_RXF_UC_OK },
3090 { "tx_mac_pause", GM_TXF_MPAUSE },
3091 { "rx_mac_pause", GM_RXF_MPAUSE },
3092 { "collisions", GM_TXF_COL },
3093 { "late_collision",GM_TXF_LAT_COL },
3094 { "aborted", GM_TXF_ABO_COL },
3095 { "single_collisions", GM_TXF_SNG_COL },
3096 { "multi_collisions", GM_TXF_MUL_COL },
3098 { "rx_short", GM_RXF_SHT },
3099 { "rx_runt", GM_RXE_FRAG },
3100 { "rx_64_byte_packets", GM_RXF_64B },
3101 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3102 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3103 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3104 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3105 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3106 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3107 { "rx_too_long", GM_RXF_LNG_ERR },
3108 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3109 { "rx_jabber", GM_RXF_JAB_PKT },
3110 { "rx_fcs_error", GM_RXF_FCS_ERR },
3112 { "tx_64_byte_packets", GM_TXF_64B },
3113 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3114 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3115 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3116 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3117 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3118 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3119 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3122 static u32 sky2_get_rx_csum(struct net_device *dev)
3124 struct sky2_port *sky2 = netdev_priv(dev);
3126 return sky2->rx_csum;
3129 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3131 struct sky2_port *sky2 = netdev_priv(dev);
3133 sky2->rx_csum = data;
3135 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3136 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3141 static u32 sky2_get_msglevel(struct net_device *netdev)
3143 struct sky2_port *sky2 = netdev_priv(netdev);
3144 return sky2->msg_enable;
3147 static int sky2_nway_reset(struct net_device *dev)
3149 struct sky2_port *sky2 = netdev_priv(dev);
3151 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3154 sky2_phy_reinit(sky2);
3155 sky2_set_multicast(dev);
3160 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3162 struct sky2_hw *hw = sky2->hw;
3163 unsigned port = sky2->port;
3166 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3167 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3168 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3169 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3171 for (i = 2; i < count; i++)
3172 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3175 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3177 struct sky2_port *sky2 = netdev_priv(netdev);
3178 sky2->msg_enable = value;
3181 static int sky2_get_stats_count(struct net_device *dev)
3183 return ARRAY_SIZE(sky2_stats);
3186 static void sky2_get_ethtool_stats(struct net_device *dev,
3187 struct ethtool_stats *stats, u64 * data)
3189 struct sky2_port *sky2 = netdev_priv(dev);
3191 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3194 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3198 switch (stringset) {
3200 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3201 memcpy(data + i * ETH_GSTRING_LEN,
3202 sky2_stats[i].name, ETH_GSTRING_LEN);
3207 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3209 struct sky2_port *sky2 = netdev_priv(dev);
3210 return &sky2->net_stats;
3213 static int sky2_set_mac_address(struct net_device *dev, void *p)
3215 struct sky2_port *sky2 = netdev_priv(dev);
3216 struct sky2_hw *hw = sky2->hw;
3217 unsigned port = sky2->port;
3218 const struct sockaddr *addr = p;
3220 if (!is_valid_ether_addr(addr->sa_data))
3221 return -EADDRNOTAVAIL;
3223 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3224 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3225 dev->dev_addr, ETH_ALEN);
3226 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3227 dev->dev_addr, ETH_ALEN);
3229 /* virtual address for data */
3230 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3232 /* physical address: used for pause frames */
3233 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3238 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3242 bit = ether_crc(ETH_ALEN, addr) & 63;
3243 filter[bit >> 3] |= 1 << (bit & 7);
3246 static void sky2_set_multicast(struct net_device *dev)
3248 struct sky2_port *sky2 = netdev_priv(dev);
3249 struct sky2_hw *hw = sky2->hw;
3250 unsigned port = sky2->port;
3251 struct dev_mc_list *list = dev->mc_list;
3255 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3257 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3258 memset(filter, 0, sizeof(filter));
3260 reg = gma_read16(hw, port, GM_RX_CTRL);
3261 reg |= GM_RXCR_UCF_ENA;
3263 if (dev->flags & IFF_PROMISC) /* promiscuous */
3264 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3265 else if (dev->flags & IFF_ALLMULTI)
3266 memset(filter, 0xff, sizeof(filter));
3267 else if (dev->mc_count == 0 && !rx_pause)
3268 reg &= ~GM_RXCR_MCF_ENA;
3271 reg |= GM_RXCR_MCF_ENA;
3274 sky2_add_filter(filter, pause_mc_addr);
3276 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3277 sky2_add_filter(filter, list->dmi_addr);
3280 gma_write16(hw, port, GM_MC_ADDR_H1,
3281 (u16) filter[0] | ((u16) filter[1] << 8));
3282 gma_write16(hw, port, GM_MC_ADDR_H2,
3283 (u16) filter[2] | ((u16) filter[3] << 8));
3284 gma_write16(hw, port, GM_MC_ADDR_H3,
3285 (u16) filter[4] | ((u16) filter[5] << 8));
3286 gma_write16(hw, port, GM_MC_ADDR_H4,
3287 (u16) filter[6] | ((u16) filter[7] << 8));
3289 gma_write16(hw, port, GM_RX_CTRL, reg);
3292 /* Can have one global because blinking is controlled by
3293 * ethtool and that is always under RTNL mutex
3295 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3299 switch (hw->chip_id) {
3300 case CHIP_ID_YUKON_XL:
3301 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3302 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3303 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3304 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3305 PHY_M_LEDC_INIT_CTRL(7) |
3306 PHY_M_LEDC_STA1_CTRL(7) |
3307 PHY_M_LEDC_STA0_CTRL(7))
3310 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3314 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3315 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3316 on ? PHY_M_LED_ALL : 0);
3320 /* blink LED's for finding board */
3321 static int sky2_phys_id(struct net_device *dev, u32 data)
3323 struct sky2_port *sky2 = netdev_priv(dev);
3324 struct sky2_hw *hw = sky2->hw;
3325 unsigned port = sky2->port;
3326 u16 ledctrl, ledover = 0;
3331 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3332 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3336 /* save initial values */
3337 spin_lock_bh(&sky2->phy_lock);
3338 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3339 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3341 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3344 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3345 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3349 while (!interrupted && ms > 0) {
3350 sky2_led(hw, port, onoff);
3353 spin_unlock_bh(&sky2->phy_lock);
3354 interrupted = msleep_interruptible(250);
3355 spin_lock_bh(&sky2->phy_lock);
3360 /* resume regularly scheduled programming */
3361 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3362 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3363 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3364 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3367 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3368 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3370 spin_unlock_bh(&sky2->phy_lock);
3375 static void sky2_get_pauseparam(struct net_device *dev,
3376 struct ethtool_pauseparam *ecmd)
3378 struct sky2_port *sky2 = netdev_priv(dev);
3380 switch (sky2->flow_mode) {
3382 ecmd->tx_pause = ecmd->rx_pause = 0;
3385 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3388 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3391 ecmd->tx_pause = ecmd->rx_pause = 1;
3394 ecmd->autoneg = sky2->autoneg;
3397 static int sky2_set_pauseparam(struct net_device *dev,
3398 struct ethtool_pauseparam *ecmd)
3400 struct sky2_port *sky2 = netdev_priv(dev);
3402 sky2->autoneg = ecmd->autoneg;
3403 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3405 if (netif_running(dev))
3406 sky2_phy_reinit(sky2);
3411 static int sky2_get_coalesce(struct net_device *dev,
3412 struct ethtool_coalesce *ecmd)
3414 struct sky2_port *sky2 = netdev_priv(dev);
3415 struct sky2_hw *hw = sky2->hw;
3417 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3418 ecmd->tx_coalesce_usecs = 0;
3420 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3421 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3423 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3425 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3426 ecmd->rx_coalesce_usecs = 0;
3428 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3429 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3431 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3433 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3434 ecmd->rx_coalesce_usecs_irq = 0;
3436 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3437 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3440 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3445 /* Note: this affect both ports */
3446 static int sky2_set_coalesce(struct net_device *dev,
3447 struct ethtool_coalesce *ecmd)
3449 struct sky2_port *sky2 = netdev_priv(dev);
3450 struct sky2_hw *hw = sky2->hw;
3451 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3453 if (ecmd->tx_coalesce_usecs > tmax ||
3454 ecmd->rx_coalesce_usecs > tmax ||
3455 ecmd->rx_coalesce_usecs_irq > tmax)
3458 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3460 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3462 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3465 if (ecmd->tx_coalesce_usecs == 0)
3466 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3468 sky2_write32(hw, STAT_TX_TIMER_INI,
3469 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3470 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3472 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3474 if (ecmd->rx_coalesce_usecs == 0)
3475 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3477 sky2_write32(hw, STAT_LEV_TIMER_INI,
3478 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3479 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3481 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3483 if (ecmd->rx_coalesce_usecs_irq == 0)
3484 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3486 sky2_write32(hw, STAT_ISR_TIMER_INI,
3487 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3488 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3490 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3494 static void sky2_get_ringparam(struct net_device *dev,
3495 struct ethtool_ringparam *ering)
3497 struct sky2_port *sky2 = netdev_priv(dev);
3499 ering->rx_max_pending = RX_MAX_PENDING;
3500 ering->rx_mini_max_pending = 0;
3501 ering->rx_jumbo_max_pending = 0;
3502 ering->tx_max_pending = TX_RING_SIZE - 1;
3504 ering->rx_pending = sky2->rx_pending;
3505 ering->rx_mini_pending = 0;
3506 ering->rx_jumbo_pending = 0;
3507 ering->tx_pending = sky2->tx_pending;
3510 static int sky2_set_ringparam(struct net_device *dev,
3511 struct ethtool_ringparam *ering)
3513 struct sky2_port *sky2 = netdev_priv(dev);
3516 if (ering->rx_pending > RX_MAX_PENDING ||
3517 ering->rx_pending < 8 ||
3518 ering->tx_pending < MAX_SKB_TX_LE ||
3519 ering->tx_pending > TX_RING_SIZE - 1)
3522 if (netif_running(dev))
3525 sky2->rx_pending = ering->rx_pending;
3526 sky2->tx_pending = ering->tx_pending;
3528 if (netif_running(dev)) {
3533 sky2_set_multicast(dev);
3539 static int sky2_get_regs_len(struct net_device *dev)
3545 * Returns copy of control register region
3546 * Note: ethtool_get_regs always provides full size (16k) buffer
3548 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3551 const struct sky2_port *sky2 = netdev_priv(dev);
3552 const void __iomem *io = sky2->hw->regs;
3555 memset(p, 0, regs->len);
3557 memcpy_fromio(p, io, B3_RAM_ADDR);
3559 /* skip diagnostic ram region */
3560 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3562 /* copy GMAC registers */
3563 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3564 if (sky2->hw->ports > 1)
3565 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3569 /* In order to do Jumbo packets on these chips, need to turn off the
3570 * transmit store/forward. Therefore checksum offload won't work.
3572 static int no_tx_offload(struct net_device *dev)
3574 const struct sky2_port *sky2 = netdev_priv(dev);
3575 const struct sky2_hw *hw = sky2->hw;
3577 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3580 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3582 if (data && no_tx_offload(dev))
3585 return ethtool_op_set_tx_csum(dev, data);
3589 static int sky2_set_tso(struct net_device *dev, u32 data)
3591 if (data && no_tx_offload(dev))
3594 return ethtool_op_set_tso(dev, data);
3597 static int sky2_get_eeprom_len(struct net_device *dev)
3599 struct sky2_port *sky2 = netdev_priv(dev);
3602 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3603 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3606 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3608 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3610 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3612 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3615 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3617 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3618 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3621 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3624 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3627 struct sky2_port *sky2 = netdev_priv(dev);
3628 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3629 int length = eeprom->len;
3630 u16 offset = eeprom->offset;
3635 eeprom->magic = SKY2_EEPROM_MAGIC;
3637 while (length > 0) {
3638 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3639 int n = min_t(int, length, sizeof(val));
3641 memcpy(data, &val, n);
3649 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3652 struct sky2_port *sky2 = netdev_priv(dev);
3653 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3654 int length = eeprom->len;
3655 u16 offset = eeprom->offset;
3660 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3663 while (length > 0) {
3665 int n = min_t(int, length, sizeof(val));
3667 if (n < sizeof(val))
3668 val = sky2_vpd_read(sky2->hw, cap, offset);
3669 memcpy(&val, data, n);
3671 sky2_vpd_write(sky2->hw, cap, offset, val);
3681 static const struct ethtool_ops sky2_ethtool_ops = {
3682 .get_settings = sky2_get_settings,
3683 .set_settings = sky2_set_settings,
3684 .get_drvinfo = sky2_get_drvinfo,
3685 .get_wol = sky2_get_wol,
3686 .set_wol = sky2_set_wol,
3687 .get_msglevel = sky2_get_msglevel,
3688 .set_msglevel = sky2_set_msglevel,
3689 .nway_reset = sky2_nway_reset,
3690 .get_regs_len = sky2_get_regs_len,
3691 .get_regs = sky2_get_regs,
3692 .get_link = ethtool_op_get_link,
3693 .get_eeprom_len = sky2_get_eeprom_len,
3694 .get_eeprom = sky2_get_eeprom,
3695 .set_eeprom = sky2_set_eeprom,
3696 .get_sg = ethtool_op_get_sg,
3697 .set_sg = ethtool_op_set_sg,
3698 .get_tx_csum = ethtool_op_get_tx_csum,
3699 .set_tx_csum = sky2_set_tx_csum,
3700 .get_tso = ethtool_op_get_tso,
3701 .set_tso = sky2_set_tso,
3702 .get_rx_csum = sky2_get_rx_csum,
3703 .set_rx_csum = sky2_set_rx_csum,
3704 .get_strings = sky2_get_strings,
3705 .get_coalesce = sky2_get_coalesce,
3706 .set_coalesce = sky2_set_coalesce,
3707 .get_ringparam = sky2_get_ringparam,
3708 .set_ringparam = sky2_set_ringparam,
3709 .get_pauseparam = sky2_get_pauseparam,
3710 .set_pauseparam = sky2_set_pauseparam,
3711 .phys_id = sky2_phys_id,
3712 .get_stats_count = sky2_get_stats_count,
3713 .get_ethtool_stats = sky2_get_ethtool_stats,
3716 #ifdef CONFIG_SKY2_DEBUG
3718 static struct dentry *sky2_debug;
3720 static int sky2_debug_show(struct seq_file *seq, void *v)
3722 struct net_device *dev = seq->private;
3723 const struct sky2_port *sky2 = netdev_priv(dev);
3724 struct sky2_hw *hw = sky2->hw;
3725 unsigned port = sky2->port;
3729 if (!netif_running(dev))
3732 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3733 sky2_read32(hw, B0_ISRC),
3734 sky2_read32(hw, B0_IMSK),
3735 sky2_read32(hw, B0_Y2_SP_ICR));
3737 napi_disable(&hw->napi);
3738 last = sky2_read16(hw, STAT_PUT_IDX);
3740 if (hw->st_idx == last)
3741 seq_puts(seq, "Status ring (empty)\n");
3743 seq_puts(seq, "Status ring\n");
3744 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3745 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3746 const struct sky2_status_le *le = hw->st_le + idx;
3747 seq_printf(seq, "[%d] %#x %d %#x\n",
3748 idx, le->opcode, le->length, le->status);
3750 seq_puts(seq, "\n");
3753 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3754 sky2->tx_cons, sky2->tx_prod,
3755 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3756 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3758 /* Dump contents of tx ring */
3760 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3761 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3762 const struct sky2_tx_le *le = sky2->tx_le + idx;
3763 u32 a = le32_to_cpu(le->addr);
3766 seq_printf(seq, "%u:", idx);
3769 switch(le->opcode & ~HW_OWNER) {
3771 seq_printf(seq, " %#x:", a);
3774 seq_printf(seq, " mtu=%d", a);
3777 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3780 seq_printf(seq, " csum=%#x", a);
3783 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3786 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3789 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3792 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3793 a, le16_to_cpu(le->length));
3796 if (le->ctrl & EOP) {
3797 seq_putc(seq, '\n');
3802 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3803 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3804 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3805 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3807 napi_enable(&hw->napi);
3811 static int sky2_debug_open(struct inode *inode, struct file *file)
3813 return single_open(file, sky2_debug_show, inode->i_private);
3816 static const struct file_operations sky2_debug_fops = {
3817 .owner = THIS_MODULE,
3818 .open = sky2_debug_open,
3820 .llseek = seq_lseek,
3821 .release = single_release,
3825 * Use network device events to create/remove/rename
3826 * debugfs file entries
3828 static int sky2_device_event(struct notifier_block *unused,
3829 unsigned long event, void *ptr)
3831 struct net_device *dev = ptr;
3832 struct sky2_port *sky2 = netdev_priv(dev);
3834 if (dev->open != sky2_up || !sky2_debug)
3838 case NETDEV_CHANGENAME:
3839 if (sky2->debugfs) {
3840 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3841 sky2_debug, dev->name);
3845 case NETDEV_GOING_DOWN:
3846 if (sky2->debugfs) {
3847 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3849 debugfs_remove(sky2->debugfs);
3850 sky2->debugfs = NULL;
3855 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3858 if (IS_ERR(sky2->debugfs))
3859 sky2->debugfs = NULL;
3865 static struct notifier_block sky2_notifier = {
3866 .notifier_call = sky2_device_event,
3870 static __init void sky2_debug_init(void)
3874 ent = debugfs_create_dir("sky2", NULL);
3875 if (!ent || IS_ERR(ent))
3879 register_netdevice_notifier(&sky2_notifier);
3882 static __exit void sky2_debug_cleanup(void)
3885 unregister_netdevice_notifier(&sky2_notifier);
3886 debugfs_remove(sky2_debug);
3892 #define sky2_debug_init()
3893 #define sky2_debug_cleanup()
3897 /* Initialize network device */
3898 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3900 int highmem, int wol)
3902 struct sky2_port *sky2;
3903 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3906 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3910 SET_MODULE_OWNER(dev);
3911 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3912 dev->irq = hw->pdev->irq;
3913 dev->open = sky2_up;
3914 dev->stop = sky2_down;
3915 dev->do_ioctl = sky2_ioctl;
3916 dev->hard_start_xmit = sky2_xmit_frame;
3917 dev->get_stats = sky2_get_stats;
3918 dev->set_multicast_list = sky2_set_multicast;
3919 dev->set_mac_address = sky2_set_mac_address;
3920 dev->change_mtu = sky2_change_mtu;
3921 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3922 dev->tx_timeout = sky2_tx_timeout;
3923 dev->watchdog_timeo = TX_WATCHDOG;
3924 #ifdef CONFIG_NET_POLL_CONTROLLER
3925 dev->poll_controller = sky2_netpoll;
3928 sky2 = netdev_priv(dev);
3931 sky2->msg_enable = netif_msg_init(debug, default_msg);
3933 /* Auto speed and flow control */
3934 sky2->autoneg = AUTONEG_ENABLE;
3935 sky2->flow_mode = FC_BOTH;
3939 sky2->advertising = sky2_supported_modes(hw);
3943 spin_lock_init(&sky2->phy_lock);
3944 sky2->tx_pending = TX_DEF_PENDING;
3945 sky2->rx_pending = RX_DEF_PENDING;
3947 hw->dev[port] = dev;
3951 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3953 dev->features |= NETIF_F_HIGHDMA;
3955 #ifdef SKY2_VLAN_TAG_USED
3956 /* The workaround for FE+ status conflicts with VLAN tag detection. */
3957 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
3958 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
3959 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3960 dev->vlan_rx_register = sky2_vlan_rx_register;
3964 /* read the mac address */
3965 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3966 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3971 static void __devinit sky2_show_addr(struct net_device *dev)
3973 const struct sky2_port *sky2 = netdev_priv(dev);
3975 if (netif_msg_probe(sky2))
3976 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3978 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3979 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3982 /* Handle software interrupt used during MSI test */
3983 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3985 struct sky2_hw *hw = dev_id;
3986 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3991 if (status & Y2_IS_IRQ_SW) {
3992 hw->flags |= SKY2_HW_USE_MSI;
3993 wake_up(&hw->msi_wait);
3994 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3996 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4001 /* Test interrupt path by forcing a a software IRQ */
4002 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4004 struct pci_dev *pdev = hw->pdev;
4007 init_waitqueue_head (&hw->msi_wait);
4009 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4011 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4013 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4017 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4018 sky2_read8(hw, B0_CTST);
4020 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4022 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4023 /* MSI test failed, go back to INTx mode */
4024 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4025 "switching to INTx mode.\n");
4028 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4031 sky2_write32(hw, B0_IMSK, 0);
4032 sky2_read32(hw, B0_IMSK);
4034 free_irq(pdev->irq, hw);
4039 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4041 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4046 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4048 return value & PCI_PM_CTRL_PME_ENABLE;
4051 static int __devinit sky2_probe(struct pci_dev *pdev,
4052 const struct pci_device_id *ent)
4054 struct net_device *dev;
4056 int err, using_dac = 0, wol_default;
4058 err = pci_enable_device(pdev);
4060 dev_err(&pdev->dev, "cannot enable PCI device\n");
4064 err = pci_request_regions(pdev, DRV_NAME);
4066 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4067 goto err_out_disable;
4070 pci_set_master(pdev);
4072 if (sizeof(dma_addr_t) > sizeof(u32) &&
4073 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4075 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4077 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4078 "for consistent allocations\n");
4079 goto err_out_free_regions;
4082 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4084 dev_err(&pdev->dev, "no usable DMA configuration\n");
4085 goto err_out_free_regions;
4089 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4092 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4094 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4095 goto err_out_free_regions;
4100 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4102 dev_err(&pdev->dev, "cannot map device registers\n");
4103 goto err_out_free_hw;
4107 /* The sk98lin vendor driver uses hardware byte swapping but
4108 * this driver uses software swapping.
4112 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4113 reg &= ~PCI_REV_DESC;
4114 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4118 /* ring for status responses */
4119 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4122 goto err_out_iounmap;
4124 err = sky2_init(hw);
4126 goto err_out_iounmap;
4128 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4129 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4130 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4131 hw->chip_id, hw->chip_rev);
4135 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4138 goto err_out_free_pci;
4140 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4142 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4143 err = sky2_test_msi(hw);
4144 if (err == -EOPNOTSUPP)
4145 pci_disable_msi(pdev);
4147 goto err_out_free_netdev;
4150 err = register_netdev(dev);
4152 dev_err(&pdev->dev, "cannot register net device\n");
4153 goto err_out_free_netdev;
4156 err = request_irq(pdev->irq, sky2_intr,
4157 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4160 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4161 goto err_out_unregister;
4163 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4165 sky2_show_addr(dev);
4167 if (hw->ports > 1) {
4168 struct net_device *dev1;
4170 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4172 dev_warn(&pdev->dev, "allocation for second device failed\n");
4173 else if ((err = register_netdev(dev1))) {
4174 dev_warn(&pdev->dev,
4175 "register of second port failed (%d)\n", err);
4179 sky2_show_addr(dev1);
4182 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4183 INIT_WORK(&hw->restart_work, sky2_restart);
4185 pci_set_drvdata(pdev, hw);
4190 if (hw->flags & SKY2_HW_USE_MSI)
4191 pci_disable_msi(pdev);
4192 unregister_netdev(dev);
4193 err_out_free_netdev:
4196 sky2_write8(hw, B0_CTST, CS_RST_SET);
4197 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4202 err_out_free_regions:
4203 pci_release_regions(pdev);
4205 pci_disable_device(pdev);
4207 pci_set_drvdata(pdev, NULL);
4211 static void __devexit sky2_remove(struct pci_dev *pdev)
4213 struct sky2_hw *hw = pci_get_drvdata(pdev);
4214 struct net_device *dev0, *dev1;
4219 del_timer_sync(&hw->watchdog_timer);
4221 flush_scheduled_work();
4223 sky2_write32(hw, B0_IMSK, 0);
4224 synchronize_irq(hw->pdev->irq);
4229 unregister_netdev(dev1);
4230 unregister_netdev(dev0);
4234 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4235 sky2_write8(hw, B0_CTST, CS_RST_SET);
4236 sky2_read8(hw, B0_CTST);
4238 free_irq(pdev->irq, hw);
4239 if (hw->flags & SKY2_HW_USE_MSI)
4240 pci_disable_msi(pdev);
4241 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4242 pci_release_regions(pdev);
4243 pci_disable_device(pdev);
4251 pci_set_drvdata(pdev, NULL);
4255 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4257 struct sky2_hw *hw = pci_get_drvdata(pdev);
4263 for (i = 0; i < hw->ports; i++) {
4264 struct net_device *dev = hw->dev[i];
4265 struct sky2_port *sky2 = netdev_priv(dev);
4267 if (netif_running(dev))
4271 sky2_wol_init(sky2);
4276 sky2_write32(hw, B0_IMSK, 0);
4279 pci_save_state(pdev);
4280 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4281 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4286 static int sky2_resume(struct pci_dev *pdev)
4288 struct sky2_hw *hw = pci_get_drvdata(pdev);
4294 err = pci_set_power_state(pdev, PCI_D0);
4298 err = pci_restore_state(pdev);
4302 pci_enable_wake(pdev, PCI_D0, 0);
4304 /* Re-enable all clocks */
4305 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4306 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4307 hw->chip_id == CHIP_ID_YUKON_FE_P)
4308 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4312 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4314 for (i = 0; i < hw->ports; i++) {
4315 struct net_device *dev = hw->dev[i];
4316 if (netif_running(dev)) {
4319 printk(KERN_ERR PFX "%s: could not up: %d\n",
4325 sky2_set_multicast(dev);
4331 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4332 pci_disable_device(pdev);
4337 static void sky2_shutdown(struct pci_dev *pdev)
4339 struct sky2_hw *hw = pci_get_drvdata(pdev);
4345 napi_disable(&hw->napi);
4347 for (i = 0; i < hw->ports; i++) {
4348 struct net_device *dev = hw->dev[i];
4349 struct sky2_port *sky2 = netdev_priv(dev);
4353 sky2_wol_init(sky2);
4360 pci_enable_wake(pdev, PCI_D3hot, wol);
4361 pci_enable_wake(pdev, PCI_D3cold, wol);
4363 pci_disable_device(pdev);
4364 pci_set_power_state(pdev, PCI_D3hot);
4368 static struct pci_driver sky2_driver = {
4370 .id_table = sky2_id_table,
4371 .probe = sky2_probe,
4372 .remove = __devexit_p(sky2_remove),
4374 .suspend = sky2_suspend,
4375 .resume = sky2_resume,
4377 .shutdown = sky2_shutdown,
4380 static int __init sky2_init_module(void)
4383 return pci_register_driver(&sky2_driver);
4386 static void __exit sky2_cleanup_module(void)
4388 pci_unregister_driver(&sky2_driver);
4389 sky2_debug_cleanup();
4392 module_init(sky2_init_module);
4393 module_exit(sky2_cleanup_module);
4395 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4396 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4397 MODULE_LICENSE("GPL");
4398 MODULE_VERSION(DRV_VERSION);