2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.17"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 MODULE_DEVICE_TABLE(pci, sky2_id_table);
138 /* Avoid conditionals by using array */
139 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
141 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
143 /* This driver supports yukon2 chipset only */
144 static const char *yukon2_name[] = {
146 "EC Ultra", /* 0xb4 */
147 "Extreme", /* 0xb5 */
152 static void sky2_set_multicast(struct net_device *dev);
154 /* Access to external PHY */
155 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
169 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
173 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
177 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
178 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
180 for (i = 0; i < PHY_RETRIES; i++) {
181 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
182 *val = gma_read16(hw, port, GM_SMI_DATA);
192 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
196 if (__gm_phy_read(hw, port, reg, &v) != 0)
197 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
202 static void sky2_power_on(struct sky2_hw *hw)
204 /* switch power to VCC (WA for VAUX problem) */
205 sky2_write8(hw, B0_POWER_CTRL,
206 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
208 /* disable Core Clock Division, */
209 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
211 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
212 /* enable bits are inverted */
213 sky2_write8(hw, B2_Y2_CLK_GATE,
214 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
215 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
216 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
220 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
221 hw->chip_id == CHIP_ID_YUKON_EX) {
224 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
226 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
227 /* set all bits to 0 except bits 15..12 and 8 */
228 reg &= P_ASPM_CONTROL_MSK;
229 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
231 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
232 /* set all bits to 0 except bits 28 & 27 */
233 reg &= P_CTL_TIM_VMAIN_AV_MSK;
234 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
236 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
238 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
239 reg = sky2_read32(hw, B2_GP_IO);
240 reg |= GLB_GPIO_STAT_RACE_DIS;
241 sky2_write32(hw, B2_GP_IO, reg);
243 sky2_read32(hw, B2_GP_IO);
247 static void sky2_power_aux(struct sky2_hw *hw)
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
252 /* enable bits are inverted */
253 sky2_write8(hw, B2_Y2_CLK_GATE,
254 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
255 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
256 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
258 /* switch power to VAUX */
259 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
260 sky2_write8(hw, B0_POWER_CTRL,
261 (PC_VAUX_ENA | PC_VCC_ENA |
262 PC_VAUX_ON | PC_VCC_OFF));
265 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
269 /* disable all GMAC IRQ's */
270 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
271 /* disable PHY IRQs */
272 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
274 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
275 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
276 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
277 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
279 reg = gma_read16(hw, port, GM_RX_CTRL);
280 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
281 gma_write16(hw, port, GM_RX_CTRL, reg);
284 /* flow control to advertise bits */
285 static const u16 copper_fc_adv[] = {
287 [FC_TX] = PHY_M_AN_ASP,
288 [FC_RX] = PHY_M_AN_PC,
289 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
292 /* flow control to advertise bits when using 1000BaseX */
293 static const u16 fiber_fc_adv[] = {
294 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
295 [FC_TX] = PHY_M_P_ASYM_MD_X,
296 [FC_RX] = PHY_M_P_SYM_MD_X,
297 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300 /* flow control to GMA disable bits */
301 static const u16 gm_fc_disable[] = {
302 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
303 [FC_TX] = GM_GPCR_FC_RX_DIS,
304 [FC_RX] = GM_GPCR_FC_TX_DIS,
309 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
311 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
312 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
314 if (sky2->autoneg == AUTONEG_ENABLE
315 && !(hw->chip_id == CHIP_ID_YUKON_XL
316 || hw->chip_id == CHIP_ID_YUKON_EC_U
317 || hw->chip_id == CHIP_ID_YUKON_EX)) {
318 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
322 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
325 if (hw->chip_id == CHIP_ID_YUKON_EC)
326 /* set downshift counter to 3x and enable downshift */
327 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
329 /* set master & slave downshift counter to 1x */
330 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
332 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
335 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
336 if (sky2_is_copper(hw)) {
337 if (hw->chip_id == CHIP_ID_YUKON_FE) {
338 /* enable automatic crossover */
339 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
341 /* disable energy detect */
342 ctrl &= ~PHY_M_PC_EN_DET_MSK;
344 /* enable automatic crossover */
345 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
347 /* downshift on PHY 88E1112 and 88E1149 is changed */
348 if (sky2->autoneg == AUTONEG_ENABLE
349 && (hw->chip_id == CHIP_ID_YUKON_XL
350 || hw->chip_id == CHIP_ID_YUKON_EC_U
351 || hw->chip_id == CHIP_ID_YUKON_EX)) {
352 /* set downshift counter to 3x and enable downshift */
353 ctrl &= ~PHY_M_PC_DSC_MSK;
354 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
358 /* workaround for deviation #4.88 (CRC errors) */
359 /* disable Automatic Crossover */
361 ctrl &= ~PHY_M_PC_MDIX_MSK;
364 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
366 /* special setup for PHY 88E1112 Fiber */
367 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
368 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
370 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
371 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
372 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
373 ctrl &= ~PHY_M_MAC_MD_MSK;
374 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
375 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
377 if (hw->pmd_type == 'P') {
378 /* select page 1 to access Fiber registers */
379 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
381 /* for SFP-module set SIGDET polarity to low */
382 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
383 ctrl |= PHY_M_FIB_SIGD_POL;
384 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
395 if (sky2->autoneg == AUTONEG_ENABLE) {
396 if (sky2_is_copper(hw)) {
397 if (sky2->advertising & ADVERTISED_1000baseT_Full)
398 ct1000 |= PHY_M_1000C_AFD;
399 if (sky2->advertising & ADVERTISED_1000baseT_Half)
400 ct1000 |= PHY_M_1000C_AHD;
401 if (sky2->advertising & ADVERTISED_100baseT_Full)
402 adv |= PHY_M_AN_100_FD;
403 if (sky2->advertising & ADVERTISED_100baseT_Half)
404 adv |= PHY_M_AN_100_HD;
405 if (sky2->advertising & ADVERTISED_10baseT_Full)
406 adv |= PHY_M_AN_10_FD;
407 if (sky2->advertising & ADVERTISED_10baseT_Half)
408 adv |= PHY_M_AN_10_HD;
410 adv |= copper_fc_adv[sky2->flow_mode];
411 } else { /* special defines for FIBER (88E1040S only) */
412 if (sky2->advertising & ADVERTISED_1000baseT_Full)
413 adv |= PHY_M_AN_1000X_AFD;
414 if (sky2->advertising & ADVERTISED_1000baseT_Half)
415 adv |= PHY_M_AN_1000X_AHD;
417 adv |= fiber_fc_adv[sky2->flow_mode];
420 /* Restart Auto-negotiation */
421 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
423 /* forced speed/duplex settings */
424 ct1000 = PHY_M_1000C_MSE;
426 /* Disable auto update for duplex flow control and speed */
427 reg |= GM_GPCR_AU_ALL_DIS;
429 switch (sky2->speed) {
431 ctrl |= PHY_CT_SP1000;
432 reg |= GM_GPCR_SPEED_1000;
435 ctrl |= PHY_CT_SP100;
436 reg |= GM_GPCR_SPEED_100;
440 if (sky2->duplex == DUPLEX_FULL) {
441 reg |= GM_GPCR_DUP_FULL;
442 ctrl |= PHY_CT_DUP_MD;
443 } else if (sky2->speed < SPEED_1000)
444 sky2->flow_mode = FC_NONE;
447 reg |= gm_fc_disable[sky2->flow_mode];
449 /* Forward pause packets to GMAC? */
450 if (sky2->flow_mode & FC_RX)
451 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
453 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
456 gma_write16(hw, port, GM_GP_CTRL, reg);
458 if (hw->chip_id != CHIP_ID_YUKON_FE)
459 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
461 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
462 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
464 /* Setup Phy LED's */
465 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
468 switch (hw->chip_id) {
469 case CHIP_ID_YUKON_FE:
470 /* on 88E3082 these bits are at 11..9 (shifted left) */
471 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
473 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
475 /* delete ACT LED control bits */
476 ctrl &= ~PHY_M_FELP_LED1_MSK;
477 /* change ACT LED control to blink mode */
478 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
479 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
482 case CHIP_ID_YUKON_XL:
483 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
485 /* select page 3 to access LED control register */
486 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
488 /* set LED Function Control register */
489 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
490 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
491 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
492 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
493 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
495 /* set Polarity Control register */
496 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
497 (PHY_M_POLC_LS1_P_MIX(4) |
498 PHY_M_POLC_IS0_P_MIX(4) |
499 PHY_M_POLC_LOS_CTRL(2) |
500 PHY_M_POLC_INIT_CTRL(2) |
501 PHY_M_POLC_STA1_CTRL(2) |
502 PHY_M_POLC_STA0_CTRL(2)));
504 /* restore page register */
505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
508 case CHIP_ID_YUKON_EC_U:
509 case CHIP_ID_YUKON_EX:
510 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
512 /* select page 3 to access LED control register */
513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
515 /* set LED Function Control register */
516 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
517 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
518 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
519 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
520 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
522 /* set Blink Rate in LED Timer Control Register */
523 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
524 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
525 /* restore page register */
526 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
530 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
531 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
532 /* turn off the Rx LED (LED_RX) */
533 ledover &= ~PHY_M_LED_MO_RX;
536 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
537 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
538 /* apply fixes in PHY AFE */
539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
541 /* increase differential signal amplitude in 10BASE-T */
542 gm_phy_write(hw, port, 0x18, 0xaa99);
543 gm_phy_write(hw, port, 0x17, 0x2011);
545 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
546 gm_phy_write(hw, port, 0x18, 0xa204);
547 gm_phy_write(hw, port, 0x17, 0x2002);
549 /* set page register to 0 */
550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
551 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
552 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
554 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
555 /* turn on 100 Mbps LED (LED_LINK100) */
556 ledover |= PHY_M_LED_MO_100;
560 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
564 /* Enable phy interrupt on auto-negotiation complete (or link up) */
565 if (sky2->autoneg == AUTONEG_ENABLE)
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
568 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
571 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
574 static const u32 phy_power[]
575 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
577 /* looks like this XL is back asswards .. */
578 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
581 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
582 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
584 /* Turn off phy power saving */
585 reg1 &= ~phy_power[port];
587 reg1 |= phy_power[port];
589 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
590 sky2_pci_read32(hw, PCI_DEV_REG1);
591 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
595 /* Force a renegotiation */
596 static void sky2_phy_reinit(struct sky2_port *sky2)
598 spin_lock_bh(&sky2->phy_lock);
599 sky2_phy_init(sky2->hw, sky2->port);
600 spin_unlock_bh(&sky2->phy_lock);
603 /* Put device in state to listen for Wake On Lan */
604 static void sky2_wol_init(struct sky2_port *sky2)
606 struct sky2_hw *hw = sky2->hw;
607 unsigned port = sky2->port;
608 enum flow_control save_mode;
612 /* Bring hardware out of reset */
613 sky2_write16(hw, B0_CTST, CS_RST_CLR);
614 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
616 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
617 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
620 * sky2_reset will re-enable on resume
622 save_mode = sky2->flow_mode;
623 ctrl = sky2->advertising;
625 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
626 sky2->flow_mode = FC_NONE;
627 sky2_phy_power(hw, port, 1);
628 sky2_phy_reinit(sky2);
630 sky2->flow_mode = save_mode;
631 sky2->advertising = ctrl;
633 /* Set GMAC to no flow control and auto update for speed/duplex */
634 gma_write16(hw, port, GM_GP_CTRL,
635 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
636 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
638 /* Set WOL address */
639 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
640 sky2->netdev->dev_addr, ETH_ALEN);
642 /* Turn on appropriate WOL control bits */
643 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
645 if (sky2->wol & WAKE_PHY)
646 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
648 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
650 if (sky2->wol & WAKE_MAGIC)
651 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
653 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
655 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
656 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
658 /* Turn on legacy PCI-Express PME mode */
659 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
660 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
661 reg1 |= PCI_Y2_PME_LEGACY;
662 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
663 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
666 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
670 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
672 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
673 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
675 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
677 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
678 /* set Tx GMAC FIFO Almost Empty Threshold */
679 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
680 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
682 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
683 TX_JUMBO_ENA | TX_STFW_DIS);
685 /* Can't do offload because of lack of store/forward */
686 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
689 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
690 TX_JUMBO_DIS | TX_STFW_ENA);
694 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
696 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
700 const u8 *addr = hw->dev[port]->dev_addr;
702 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
703 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
705 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
708 /* WA DEV_472 -- looks like crossed wires on port 2 */
709 /* clear GMAC 1 Control reset */
710 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
712 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
713 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
714 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
715 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
716 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
719 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
721 /* Enable Transmit FIFO Underrun */
722 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_init(hw, port);
726 spin_unlock_bh(&sky2->phy_lock);
729 reg = gma_read16(hw, port, GM_PHY_ADDR);
730 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
732 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
733 gma_read16(hw, port, i);
734 gma_write16(hw, port, GM_PHY_ADDR, reg);
736 /* transmit control */
737 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
739 /* receive control reg: unicast + multicast + no FCS */
740 gma_write16(hw, port, GM_RX_CTRL,
741 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
743 /* transmit flow control */
744 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
746 /* transmit parameter */
747 gma_write16(hw, port, GM_TX_PARAM,
748 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
749 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
750 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
751 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
753 /* serial mode register */
754 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
755 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
757 if (hw->dev[port]->mtu > ETH_DATA_LEN)
758 reg |= GM_SMOD_JUMBO_ENA;
760 gma_write16(hw, port, GM_SERIAL_MODE, reg);
762 /* virtual address for data */
763 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
765 /* physical address: used for pause frames */
766 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
768 /* ignore counter overflows */
769 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
770 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
771 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
773 /* Configure Rx MAC FIFO */
774 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
775 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
776 if (hw->chip_id == CHIP_ID_YUKON_EX)
777 rx_reg |= GMF_RX_OVER_ON;
779 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
781 /* Flush Rx MAC FIFO on any flow control or error */
782 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
784 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
785 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
787 /* Configure Tx MAC FIFO */
788 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
789 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
791 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
792 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
793 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
795 sky2_set_tx_stfwd(hw, port);
800 /* Assign Ram Buffer allocation to queue */
801 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
805 /* convert from K bytes to qwords used for hw register */
808 end = start + space - 1;
810 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
811 sky2_write32(hw, RB_ADDR(q, RB_START), start);
812 sky2_write32(hw, RB_ADDR(q, RB_END), end);
813 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
814 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
816 if (q == Q_R1 || q == Q_R2) {
817 u32 tp = space - space/4;
819 /* On receive queue's set the thresholds
820 * give receiver priority when > 3/4 full
821 * send pause when down to 2K
823 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
824 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
827 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
828 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
830 /* Enable store & forward on Tx queue's because
831 * Tx FIFO is only 1K on Yukon
833 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
836 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
837 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
840 /* Setup Bus Memory Interface */
841 static void sky2_qset(struct sky2_hw *hw, u16 q)
843 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
844 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
845 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
846 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
849 /* Setup prefetch unit registers. This is the interface between
850 * hardware and driver list elements
852 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
855 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
856 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
857 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
858 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
859 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
860 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
862 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
865 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
867 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
869 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
874 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
875 struct sky2_tx_le *le)
877 return sky2->tx_ring + (le - sky2->tx_le);
880 /* Update chip's next pointer */
881 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
883 /* Make sure write' to descriptors are complete before we tell hardware */
885 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
887 /* Synchronize I/O on since next processor may write to tail */
892 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
894 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
895 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
900 /* Build description to hardware for one receive segment */
901 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
902 dma_addr_t map, unsigned len)
904 struct sky2_rx_le *le;
905 u32 hi = upper_32_bits(map);
907 if (sky2->rx_addr64 != hi) {
908 le = sky2_next_rx(sky2);
909 le->addr = cpu_to_le32(hi);
910 le->opcode = OP_ADDR64 | HW_OWNER;
911 sky2->rx_addr64 = upper_32_bits(map + len);
914 le = sky2_next_rx(sky2);
915 le->addr = cpu_to_le32((u32) map);
916 le->length = cpu_to_le16(len);
917 le->opcode = op | HW_OWNER;
920 /* Build description to hardware for one possibly fragmented skb */
921 static void sky2_rx_submit(struct sky2_port *sky2,
922 const struct rx_ring_info *re)
926 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
928 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
929 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
933 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
936 struct sk_buff *skb = re->skb;
939 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
940 pci_unmap_len_set(re, data_size, size);
942 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
943 re->frag_addr[i] = pci_map_page(pdev,
944 skb_shinfo(skb)->frags[i].page,
945 skb_shinfo(skb)->frags[i].page_offset,
946 skb_shinfo(skb)->frags[i].size,
950 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
952 struct sk_buff *skb = re->skb;
955 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
958 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
959 pci_unmap_page(pdev, re->frag_addr[i],
960 skb_shinfo(skb)->frags[i].size,
964 /* Tell chip where to start receive checksum.
965 * Actually has two checksums, but set both same to avoid possible byte
968 static void rx_set_checksum(struct sky2_port *sky2)
970 struct sky2_rx_le *le;
972 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
973 le = sky2_next_rx(sky2);
974 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
976 le->opcode = OP_TCPSTART | HW_OWNER;
978 sky2_write32(sky2->hw,
979 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
980 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
986 * The RX Stop command will not work for Yukon-2 if the BMU does not
987 * reach the end of packet and since we can't make sure that we have
988 * incoming data, we must reset the BMU while it is not doing a DMA
989 * transfer. Since it is possible that the RX path is still active,
990 * the RX RAM buffer will be stopped first, so any possible incoming
991 * data will not trigger a DMA. After the RAM buffer is stopped, the
992 * BMU is polled until any DMA in progress is ended and only then it
995 static void sky2_rx_stop(struct sky2_port *sky2)
997 struct sky2_hw *hw = sky2->hw;
998 unsigned rxq = rxqaddr[sky2->port];
1001 /* disable the RAM Buffer receive queue */
1002 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1004 for (i = 0; i < 0xffff; i++)
1005 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1006 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1009 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1010 sky2->netdev->name);
1012 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1014 /* reset the Rx prefetch unit */
1015 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1019 /* Clean out receive buffer area, assumes receiver hardware stopped */
1020 static void sky2_rx_clean(struct sky2_port *sky2)
1024 memset(sky2->rx_le, 0, RX_LE_BYTES);
1025 for (i = 0; i < sky2->rx_pending; i++) {
1026 struct rx_ring_info *re = sky2->rx_ring + i;
1029 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1036 /* Basic MII support */
1037 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1039 struct mii_ioctl_data *data = if_mii(ifr);
1040 struct sky2_port *sky2 = netdev_priv(dev);
1041 struct sky2_hw *hw = sky2->hw;
1042 int err = -EOPNOTSUPP;
1044 if (!netif_running(dev))
1045 return -ENODEV; /* Phy still in reset */
1049 data->phy_id = PHY_ADDR_MARV;
1055 spin_lock_bh(&sky2->phy_lock);
1056 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1057 spin_unlock_bh(&sky2->phy_lock);
1059 data->val_out = val;
1064 if (!capable(CAP_NET_ADMIN))
1067 spin_lock_bh(&sky2->phy_lock);
1068 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1070 spin_unlock_bh(&sky2->phy_lock);
1076 #ifdef SKY2_VLAN_TAG_USED
1077 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1079 struct sky2_port *sky2 = netdev_priv(dev);
1080 struct sky2_hw *hw = sky2->hw;
1081 u16 port = sky2->port;
1083 netif_tx_lock_bh(dev);
1084 netif_poll_disable(sky2->hw->dev[0]);
1088 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1090 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1093 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1095 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1099 netif_poll_enable(sky2->hw->dev[0]);
1100 netif_tx_unlock_bh(dev);
1105 * Allocate an skb for receiving. If the MTU is large enough
1106 * make the skb non-linear with a fragment list of pages.
1108 * It appears the hardware has a bug in the FIFO logic that
1109 * cause it to hang if the FIFO gets overrun and the receive buffer
1110 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1111 * aligned except if slab debugging is enabled.
1113 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1115 struct sk_buff *skb;
1119 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1123 p = (unsigned long) skb->data;
1124 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1126 for (i = 0; i < sky2->rx_nfrags; i++) {
1127 struct page *page = alloc_page(GFP_ATOMIC);
1131 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1141 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1143 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1147 * Allocate and setup receiver buffer pool.
1148 * Normal case this ends up creating one list element for skb
1149 * in the receive ring. Worst case if using large MTU and each
1150 * allocation falls on a different 64 bit region, that results
1151 * in 6 list elements per ring entry.
1152 * One element is used for checksum enable/disable, and one
1153 * extra to avoid wrap.
1155 static int sky2_rx_start(struct sky2_port *sky2)
1157 struct sky2_hw *hw = sky2->hw;
1158 struct rx_ring_info *re;
1159 unsigned rxq = rxqaddr[sky2->port];
1160 unsigned i, size, space, thresh;
1162 sky2->rx_put = sky2->rx_next = 0;
1165 /* On PCI express lowering the watermark gives better performance */
1166 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1167 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1169 /* These chips have no ram buffer?
1170 * MAC Rx RAM Read is controlled by hardware */
1171 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1172 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1173 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1174 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1176 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1178 rx_set_checksum(sky2);
1180 /* Space needed for frame data + headers rounded up */
1181 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1183 /* Stopping point for hardware truncation */
1184 thresh = (size - 8) / sizeof(u32);
1186 /* Account for overhead of skb - to avoid order > 0 allocation */
1187 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1188 + sizeof(struct skb_shared_info);
1190 sky2->rx_nfrags = space >> PAGE_SHIFT;
1191 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1193 if (sky2->rx_nfrags != 0) {
1194 /* Compute residue after pages */
1195 space = sky2->rx_nfrags << PAGE_SHIFT;
1202 /* Optimize to handle small packets and headers */
1203 if (size < copybreak)
1205 if (size < ETH_HLEN)
1208 sky2->rx_data_size = size;
1211 for (i = 0; i < sky2->rx_pending; i++) {
1212 re = sky2->rx_ring + i;
1214 re->skb = sky2_rx_alloc(sky2);
1218 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1219 sky2_rx_submit(sky2, re);
1223 * The receiver hangs if it receives frames larger than the
1224 * packet buffer. As a workaround, truncate oversize frames, but
1225 * the register is limited to 9 bits, so if you do frames > 2052
1226 * you better get the MTU right!
1229 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1231 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1232 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1235 /* Tell chip about available buffers */
1236 sky2_rx_update(sky2, rxq);
1239 sky2_rx_clean(sky2);
1243 /* Bring up network interface. */
1244 static int sky2_up(struct net_device *dev)
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 unsigned port = sky2->port;
1250 int cap, err = -ENOMEM;
1251 struct net_device *otherdev = hw->dev[sky2->port^1];
1254 * On dual port PCI-X card, there is an problem where status
1255 * can be received out of order due to split transactions
1257 if (otherdev && netif_running(otherdev) &&
1258 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1259 struct sky2_port *osky2 = netdev_priv(otherdev);
1262 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1263 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1264 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1270 if (netif_msg_ifup(sky2))
1271 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1273 netif_carrier_off(dev);
1275 /* must be power of 2 */
1276 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1278 sizeof(struct sky2_tx_le),
1283 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1287 sky2->tx_prod = sky2->tx_cons = 0;
1289 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1293 memset(sky2->rx_le, 0, RX_LE_BYTES);
1295 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1300 sky2_phy_power(hw, port, 1);
1302 sky2_mac_init(hw, port);
1304 /* Register is number of 4K blocks on internal RAM buffer. */
1305 ramsize = sky2_read8(hw, B2_E_0) * 4;
1306 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1312 rxspace = ramsize / 2;
1314 rxspace = 8 + (2*(ramsize - 16))/3;
1316 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1317 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1319 /* Make sure SyncQ is disabled */
1320 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1324 sky2_qset(hw, txqaddr[port]);
1326 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1327 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1328 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1330 /* Set almost empty threshold */
1331 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1332 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1333 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1335 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1338 err = sky2_rx_start(sky2);
1342 /* Enable interrupts from phy/mac for port */
1343 imask = sky2_read32(hw, B0_IMSK);
1344 imask |= portirq_msk[port];
1345 sky2_write32(hw, B0_IMSK, imask);
1351 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1352 sky2->rx_le, sky2->rx_le_map);
1356 pci_free_consistent(hw->pdev,
1357 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1358 sky2->tx_le, sky2->tx_le_map);
1361 kfree(sky2->tx_ring);
1362 kfree(sky2->rx_ring);
1364 sky2->tx_ring = NULL;
1365 sky2->rx_ring = NULL;
1369 /* Modular subtraction in ring */
1370 static inline int tx_dist(unsigned tail, unsigned head)
1372 return (head - tail) & (TX_RING_SIZE - 1);
1375 /* Number of list elements available for next tx */
1376 static inline int tx_avail(const struct sky2_port *sky2)
1378 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1381 /* Estimate of number of transmit list elements required */
1382 static unsigned tx_le_req(const struct sk_buff *skb)
1386 count = sizeof(dma_addr_t) / sizeof(u32);
1387 count += skb_shinfo(skb)->nr_frags * count;
1389 if (skb_is_gso(skb))
1392 if (skb->ip_summed == CHECKSUM_PARTIAL)
1399 * Put one packet in ring for transmit.
1400 * A single packet can generate multiple list elements, and
1401 * the number of ring elements will probably be less than the number
1402 * of list elements used.
1404 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1406 struct sky2_port *sky2 = netdev_priv(dev);
1407 struct sky2_hw *hw = sky2->hw;
1408 struct sky2_tx_le *le = NULL;
1409 struct tx_ring_info *re;
1416 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1417 return NETDEV_TX_BUSY;
1419 if (unlikely(netif_msg_tx_queued(sky2)))
1420 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1421 dev->name, sky2->tx_prod, skb->len);
1423 len = skb_headlen(skb);
1424 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1425 addr64 = upper_32_bits(mapping);
1427 /* Send high bits if changed or crosses boundary */
1428 if (addr64 != sky2->tx_addr64 ||
1429 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1430 le = get_tx_le(sky2);
1431 le->addr = cpu_to_le32(addr64);
1432 le->opcode = OP_ADDR64 | HW_OWNER;
1433 sky2->tx_addr64 = upper_32_bits(mapping + len);
1436 /* Check for TCP Segmentation Offload */
1437 mss = skb_shinfo(skb)->gso_size;
1439 if (hw->chip_id != CHIP_ID_YUKON_EX)
1440 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1442 if (mss != sky2->tx_last_mss) {
1443 le = get_tx_le(sky2);
1444 le->addr = cpu_to_le32(mss);
1445 if (hw->chip_id == CHIP_ID_YUKON_EX)
1446 le->opcode = OP_MSS | HW_OWNER;
1448 le->opcode = OP_LRGLEN | HW_OWNER;
1449 sky2->tx_last_mss = mss;
1454 #ifdef SKY2_VLAN_TAG_USED
1455 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1456 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1458 le = get_tx_le(sky2);
1460 le->opcode = OP_VLAN|HW_OWNER;
1462 le->opcode |= OP_VLAN;
1463 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1468 /* Handle TCP checksum offload */
1469 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1470 /* On Yukon EX (some versions) encoding change. */
1471 if (hw->chip_id == CHIP_ID_YUKON_EX
1472 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1473 ctrl |= CALSUM; /* auto checksum */
1475 const unsigned offset = skb_transport_offset(skb);
1478 tcpsum = offset << 16; /* sum start */
1479 tcpsum |= offset + skb->csum_offset; /* sum write */
1481 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1482 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1485 if (tcpsum != sky2->tx_tcpsum) {
1486 sky2->tx_tcpsum = tcpsum;
1488 le = get_tx_le(sky2);
1489 le->addr = cpu_to_le32(tcpsum);
1490 le->length = 0; /* initial checksum value */
1491 le->ctrl = 1; /* one packet */
1492 le->opcode = OP_TCPLISW | HW_OWNER;
1497 le = get_tx_le(sky2);
1498 le->addr = cpu_to_le32((u32) mapping);
1499 le->length = cpu_to_le16(len);
1501 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1503 re = tx_le_re(sky2, le);
1505 pci_unmap_addr_set(re, mapaddr, mapping);
1506 pci_unmap_len_set(re, maplen, len);
1508 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1509 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1511 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1512 frag->size, PCI_DMA_TODEVICE);
1513 addr64 = upper_32_bits(mapping);
1514 if (addr64 != sky2->tx_addr64) {
1515 le = get_tx_le(sky2);
1516 le->addr = cpu_to_le32(addr64);
1518 le->opcode = OP_ADDR64 | HW_OWNER;
1519 sky2->tx_addr64 = addr64;
1522 le = get_tx_le(sky2);
1523 le->addr = cpu_to_le32((u32) mapping);
1524 le->length = cpu_to_le16(frag->size);
1526 le->opcode = OP_BUFFER | HW_OWNER;
1528 re = tx_le_re(sky2, le);
1530 pci_unmap_addr_set(re, mapaddr, mapping);
1531 pci_unmap_len_set(re, maplen, frag->size);
1536 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1537 netif_stop_queue(dev);
1539 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1541 dev->trans_start = jiffies;
1542 return NETDEV_TX_OK;
1546 * Free ring elements from starting at tx_cons until "done"
1548 * NB: the hardware will tell us about partial completion of multi-part
1549 * buffers so make sure not to free skb to early.
1551 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1553 struct net_device *dev = sky2->netdev;
1554 struct pci_dev *pdev = sky2->hw->pdev;
1557 BUG_ON(done >= TX_RING_SIZE);
1559 for (idx = sky2->tx_cons; idx != done;
1560 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1561 struct sky2_tx_le *le = sky2->tx_le + idx;
1562 struct tx_ring_info *re = sky2->tx_ring + idx;
1564 switch(le->opcode & ~HW_OWNER) {
1567 pci_unmap_single(pdev,
1568 pci_unmap_addr(re, mapaddr),
1569 pci_unmap_len(re, maplen),
1573 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1574 pci_unmap_len(re, maplen),
1579 if (le->ctrl & EOP) {
1580 if (unlikely(netif_msg_tx_done(sky2)))
1581 printk(KERN_DEBUG "%s: tx done %u\n",
1584 sky2->net_stats.tx_packets++;
1585 sky2->net_stats.tx_bytes += re->skb->len;
1587 dev_kfree_skb_any(re->skb);
1588 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1592 sky2->tx_cons = idx;
1595 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1596 netif_wake_queue(dev);
1599 /* Cleanup all untransmitted buffers, assume transmitter not running */
1600 static void sky2_tx_clean(struct net_device *dev)
1602 struct sky2_port *sky2 = netdev_priv(dev);
1604 netif_tx_lock_bh(dev);
1605 sky2_tx_complete(sky2, sky2->tx_prod);
1606 netif_tx_unlock_bh(dev);
1609 /* Network shutdown */
1610 static int sky2_down(struct net_device *dev)
1612 struct sky2_port *sky2 = netdev_priv(dev);
1613 struct sky2_hw *hw = sky2->hw;
1614 unsigned port = sky2->port;
1618 /* Never really got started! */
1622 if (netif_msg_ifdown(sky2))
1623 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1625 if (netif_carrier_ok(dev) && --hw->active == 0)
1626 del_timer(&hw->watchdog_timer);
1628 /* Stop more packets from being queued */
1629 netif_stop_queue(dev);
1631 /* Disable port IRQ */
1632 imask = sky2_read32(hw, B0_IMSK);
1633 imask &= ~portirq_msk[port];
1634 sky2_write32(hw, B0_IMSK, imask);
1636 sky2_gmac_reset(hw, port);
1638 /* Stop transmitter */
1639 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1640 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1642 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1643 RB_RST_SET | RB_DIS_OP_MD);
1645 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1646 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1647 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1649 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1651 /* Workaround shared GMAC reset */
1652 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1653 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1654 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1656 /* Disable Force Sync bit and Enable Alloc bit */
1657 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1658 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1660 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1661 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1662 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1664 /* Reset the PCI FIFO of the async Tx queue */
1665 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1666 BMU_RST_SET | BMU_FIFO_RST);
1668 /* Reset the Tx prefetch units */
1669 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1672 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1676 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1677 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1679 sky2_phy_power(hw, port, 0);
1681 netif_carrier_off(dev);
1683 /* turn off LED's */
1684 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1686 synchronize_irq(hw->pdev->irq);
1689 sky2_rx_clean(sky2);
1691 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1692 sky2->rx_le, sky2->rx_le_map);
1693 kfree(sky2->rx_ring);
1695 pci_free_consistent(hw->pdev,
1696 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1697 sky2->tx_le, sky2->tx_le_map);
1698 kfree(sky2->tx_ring);
1703 sky2->rx_ring = NULL;
1704 sky2->tx_ring = NULL;
1709 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1711 if (!sky2_is_copper(hw))
1714 if (hw->chip_id == CHIP_ID_YUKON_FE)
1715 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1717 switch (aux & PHY_M_PS_SPEED_MSK) {
1718 case PHY_M_PS_SPEED_1000:
1720 case PHY_M_PS_SPEED_100:
1727 static void sky2_link_up(struct sky2_port *sky2)
1729 struct sky2_hw *hw = sky2->hw;
1730 unsigned port = sky2->port;
1732 static const char *fc_name[] = {
1740 reg = gma_read16(hw, port, GM_GP_CTRL);
1741 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1742 gma_write16(hw, port, GM_GP_CTRL, reg);
1744 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1746 netif_carrier_on(sky2->netdev);
1748 if (hw->active++ == 0)
1749 mod_timer(&hw->watchdog_timer, jiffies + 1);
1752 /* Turn on link LED */
1753 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1754 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1756 if (hw->chip_id == CHIP_ID_YUKON_XL
1757 || hw->chip_id == CHIP_ID_YUKON_EC_U
1758 || hw->chip_id == CHIP_ID_YUKON_EX) {
1759 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1760 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1762 switch(sky2->speed) {
1764 led |= PHY_M_LEDC_INIT_CTRL(7);
1768 led |= PHY_M_LEDC_STA1_CTRL(7);
1772 led |= PHY_M_LEDC_STA0_CTRL(7);
1776 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1777 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1778 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1781 if (netif_msg_link(sky2))
1782 printk(KERN_INFO PFX
1783 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1784 sky2->netdev->name, sky2->speed,
1785 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1786 fc_name[sky2->flow_status]);
1789 static void sky2_link_down(struct sky2_port *sky2)
1791 struct sky2_hw *hw = sky2->hw;
1792 unsigned port = sky2->port;
1795 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1797 reg = gma_read16(hw, port, GM_GP_CTRL);
1798 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1799 gma_write16(hw, port, GM_GP_CTRL, reg);
1801 netif_carrier_off(sky2->netdev);
1803 /* Stop watchdog if both ports are not active */
1804 if (--hw->active == 0)
1805 del_timer(&hw->watchdog_timer);
1808 /* Turn on link LED */
1809 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1811 if (netif_msg_link(sky2))
1812 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1814 sky2_phy_init(hw, port);
1817 static enum flow_control sky2_flow(int rx, int tx)
1820 return tx ? FC_BOTH : FC_RX;
1822 return tx ? FC_TX : FC_NONE;
1825 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1827 struct sky2_hw *hw = sky2->hw;
1828 unsigned port = sky2->port;
1831 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1832 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1833 if (lpa & PHY_M_AN_RF) {
1834 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1838 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1839 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1840 sky2->netdev->name);
1844 sky2->speed = sky2_phy_speed(hw, aux);
1845 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1847 /* Since the pause result bits seem to in different positions on
1848 * different chips. look at registers.
1850 if (!sky2_is_copper(hw)) {
1851 /* Shift for bits in fiber PHY */
1852 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1853 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1855 if (advert & ADVERTISE_1000XPAUSE)
1856 advert |= ADVERTISE_PAUSE_CAP;
1857 if (advert & ADVERTISE_1000XPSE_ASYM)
1858 advert |= ADVERTISE_PAUSE_ASYM;
1859 if (lpa & LPA_1000XPAUSE)
1860 lpa |= LPA_PAUSE_CAP;
1861 if (lpa & LPA_1000XPAUSE_ASYM)
1862 lpa |= LPA_PAUSE_ASYM;
1865 sky2->flow_status = FC_NONE;
1866 if (advert & ADVERTISE_PAUSE_CAP) {
1867 if (lpa & LPA_PAUSE_CAP)
1868 sky2->flow_status = FC_BOTH;
1869 else if (advert & ADVERTISE_PAUSE_ASYM)
1870 sky2->flow_status = FC_RX;
1871 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1872 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1873 sky2->flow_status = FC_TX;
1876 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1877 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1878 sky2->flow_status = FC_NONE;
1880 if (sky2->flow_status & FC_TX)
1881 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1883 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1888 /* Interrupt from PHY */
1889 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1891 struct net_device *dev = hw->dev[port];
1892 struct sky2_port *sky2 = netdev_priv(dev);
1893 u16 istatus, phystat;
1895 if (!netif_running(dev))
1898 spin_lock(&sky2->phy_lock);
1899 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1900 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1902 if (netif_msg_intr(sky2))
1903 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1904 sky2->netdev->name, istatus, phystat);
1906 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1907 if (sky2_autoneg_done(sky2, phystat) == 0)
1912 if (istatus & PHY_M_IS_LSP_CHANGE)
1913 sky2->speed = sky2_phy_speed(hw, phystat);
1915 if (istatus & PHY_M_IS_DUP_CHANGE)
1917 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1919 if (istatus & PHY_M_IS_LST_CHANGE) {
1920 if (phystat & PHY_M_PS_LINK_UP)
1923 sky2_link_down(sky2);
1926 spin_unlock(&sky2->phy_lock);
1929 /* Transmit timeout is only called if we are running, carrier is up
1930 * and tx queue is full (stopped).
1932 static void sky2_tx_timeout(struct net_device *dev)
1934 struct sky2_port *sky2 = netdev_priv(dev);
1935 struct sky2_hw *hw = sky2->hw;
1937 if (netif_msg_timer(sky2))
1938 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1940 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1941 dev->name, sky2->tx_cons, sky2->tx_prod,
1942 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1943 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1945 /* can't restart safely under softirq */
1946 schedule_work(&hw->restart_work);
1949 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1951 struct sky2_port *sky2 = netdev_priv(dev);
1952 struct sky2_hw *hw = sky2->hw;
1953 unsigned port = sky2->port;
1958 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1961 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1964 if (!netif_running(dev)) {
1969 imask = sky2_read32(hw, B0_IMSK);
1970 sky2_write32(hw, B0_IMSK, 0);
1972 dev->trans_start = jiffies; /* prevent tx timeout */
1973 netif_stop_queue(dev);
1974 netif_poll_disable(hw->dev[0]);
1976 synchronize_irq(hw->pdev->irq);
1978 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1979 sky2_set_tx_stfwd(hw, port);
1981 ctl = gma_read16(hw, port, GM_GP_CTRL);
1982 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1984 sky2_rx_clean(sky2);
1988 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1989 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1991 if (dev->mtu > ETH_DATA_LEN)
1992 mode |= GM_SMOD_JUMBO_ENA;
1994 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1996 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1998 err = sky2_rx_start(sky2);
1999 sky2_write32(hw, B0_IMSK, imask);
2004 gma_write16(hw, port, GM_GP_CTRL, ctl);
2006 netif_poll_enable(hw->dev[0]);
2007 netif_wake_queue(dev);
2013 /* For small just reuse existing skb for next receive */
2014 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2015 const struct rx_ring_info *re,
2018 struct sk_buff *skb;
2020 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2022 skb_reserve(skb, 2);
2023 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2024 length, PCI_DMA_FROMDEVICE);
2025 skb_copy_from_linear_data(re->skb, skb->data, length);
2026 skb->ip_summed = re->skb->ip_summed;
2027 skb->csum = re->skb->csum;
2028 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2029 length, PCI_DMA_FROMDEVICE);
2030 re->skb->ip_summed = CHECKSUM_NONE;
2031 skb_put(skb, length);
2036 /* Adjust length of skb with fragments to match received data */
2037 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2038 unsigned int length)
2043 /* put header into skb */
2044 size = min(length, hdr_space);
2049 num_frags = skb_shinfo(skb)->nr_frags;
2050 for (i = 0; i < num_frags; i++) {
2051 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2054 /* don't need this page */
2055 __free_page(frag->page);
2056 --skb_shinfo(skb)->nr_frags;
2058 size = min(length, (unsigned) PAGE_SIZE);
2061 skb->data_len += size;
2062 skb->truesize += size;
2069 /* Normal packet - take skb from ring element and put in a new one */
2070 static struct sk_buff *receive_new(struct sky2_port *sky2,
2071 struct rx_ring_info *re,
2072 unsigned int length)
2074 struct sk_buff *skb, *nskb;
2075 unsigned hdr_space = sky2->rx_data_size;
2077 /* Don't be tricky about reusing pages (yet) */
2078 nskb = sky2_rx_alloc(sky2);
2079 if (unlikely(!nskb))
2083 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2085 prefetch(skb->data);
2087 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2089 if (skb_shinfo(skb)->nr_frags)
2090 skb_put_frags(skb, hdr_space, length);
2092 skb_put(skb, length);
2097 * Receive one packet.
2098 * For larger packets, get new buffer.
2100 static struct sk_buff *sky2_receive(struct net_device *dev,
2101 u16 length, u32 status)
2103 struct sky2_port *sky2 = netdev_priv(dev);
2104 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2105 struct sk_buff *skb = NULL;
2106 u16 count = (status & GMR_FS_LEN) >> 16;
2108 #ifdef SKY2_VLAN_TAG_USED
2109 /* Account for vlan tag */
2110 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2114 if (unlikely(netif_msg_rx_status(sky2)))
2115 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2116 dev->name, sky2->rx_next, status, length);
2118 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2119 prefetch(sky2->rx_ring + sky2->rx_next);
2121 if (status & GMR_FS_ANY_ERR)
2124 if (!(status & GMR_FS_RX_OK))
2127 /* if length reported by DMA does not match PHY, packet was truncated */
2128 if (length != count)
2131 if (length < copybreak)
2132 skb = receive_copy(sky2, re, length);
2134 skb = receive_new(sky2, re, length);
2136 sky2_rx_submit(sky2, re);
2141 /* Truncation of overlength packets
2142 causes PHY length to not match MAC length */
2143 ++sky2->net_stats.rx_length_errors;
2144 if (netif_msg_rx_err(sky2) && net_ratelimit())
2145 pr_info(PFX "%s: rx length mismatch: length %d status %#x\n",
2146 dev->name, length, status);
2150 ++sky2->net_stats.rx_errors;
2151 if (status & GMR_FS_RX_FF_OV) {
2152 sky2->net_stats.rx_over_errors++;
2156 if (netif_msg_rx_err(sky2) && net_ratelimit())
2157 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2158 dev->name, status, length);
2160 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2161 sky2->net_stats.rx_length_errors++;
2162 if (status & GMR_FS_FRAGMENT)
2163 sky2->net_stats.rx_frame_errors++;
2164 if (status & GMR_FS_CRC_ERR)
2165 sky2->net_stats.rx_crc_errors++;
2170 /* Transmit complete */
2171 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2173 struct sky2_port *sky2 = netdev_priv(dev);
2175 if (netif_running(dev)) {
2177 sky2_tx_complete(sky2, last);
2178 netif_tx_unlock(dev);
2182 /* Process status response ring */
2183 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2186 unsigned rx[2] = { 0, 0 };
2187 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2191 while (hw->st_idx != hwidx) {
2192 struct sky2_port *sky2;
2193 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2194 unsigned port = le->css & CSS_LINK_BIT;
2195 struct net_device *dev;
2196 struct sk_buff *skb;
2200 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2202 dev = hw->dev[port];
2203 sky2 = netdev_priv(dev);
2204 length = le16_to_cpu(le->length);
2205 status = le32_to_cpu(le->status);
2207 switch (le->opcode & ~HW_OWNER) {
2210 skb = sky2_receive(dev, length, status);
2211 if (unlikely(!skb)) {
2212 sky2->net_stats.rx_dropped++;
2216 /* This chip reports checksum status differently */
2217 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2218 if (sky2->rx_csum &&
2219 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2220 (le->css & CSS_TCPUDPCSOK))
2221 skb->ip_summed = CHECKSUM_UNNECESSARY;
2223 skb->ip_summed = CHECKSUM_NONE;
2226 skb->protocol = eth_type_trans(skb, dev);
2227 sky2->net_stats.rx_packets++;
2228 sky2->net_stats.rx_bytes += skb->len;
2229 dev->last_rx = jiffies;
2231 #ifdef SKY2_VLAN_TAG_USED
2232 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2233 vlan_hwaccel_receive_skb(skb,
2235 be16_to_cpu(sky2->rx_tag));
2238 netif_receive_skb(skb);
2240 /* Stop after net poll weight */
2241 if (++work_done >= to_do)
2245 #ifdef SKY2_VLAN_TAG_USED
2247 sky2->rx_tag = length;
2251 sky2->rx_tag = length;
2258 if (hw->chip_id == CHIP_ID_YUKON_EX)
2261 /* Both checksum counters are programmed to start at
2262 * the same offset, so unless there is a problem they
2263 * should match. This failure is an early indication that
2264 * hardware receive checksumming won't work.
2266 if (likely(status >> 16 == (status & 0xffff))) {
2267 skb = sky2->rx_ring[sky2->rx_next].skb;
2268 skb->ip_summed = CHECKSUM_COMPLETE;
2269 skb->csum = status & 0xffff;
2271 printk(KERN_NOTICE PFX "%s: hardware receive "
2272 "checksum problem (status = %#x)\n",
2275 sky2_write32(sky2->hw,
2276 Q_ADDR(rxqaddr[port], Q_CSR),
2282 /* TX index reports status for both ports */
2283 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2284 sky2_tx_done(hw->dev[0], status & 0xfff);
2286 sky2_tx_done(hw->dev[1],
2287 ((status >> 24) & 0xff)
2288 | (u16)(length & 0xf) << 8);
2292 if (net_ratelimit())
2293 printk(KERN_WARNING PFX
2294 "unknown status opcode 0x%x\n", le->opcode);
2298 /* Fully processed status ring so clear irq */
2299 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2303 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2306 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2311 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2313 struct net_device *dev = hw->dev[port];
2315 if (net_ratelimit())
2316 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2319 if (status & Y2_IS_PAR_RD1) {
2320 if (net_ratelimit())
2321 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2324 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2327 if (status & Y2_IS_PAR_WR1) {
2328 if (net_ratelimit())
2329 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2332 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2335 if (status & Y2_IS_PAR_MAC1) {
2336 if (net_ratelimit())
2337 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2338 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2341 if (status & Y2_IS_PAR_RX1) {
2342 if (net_ratelimit())
2343 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2344 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2347 if (status & Y2_IS_TCP_TXA1) {
2348 if (net_ratelimit())
2349 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2351 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2355 static void sky2_hw_intr(struct sky2_hw *hw)
2357 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2359 if (status & Y2_IS_TIST_OV)
2360 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2362 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2365 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2366 if (net_ratelimit())
2367 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2370 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2371 sky2_pci_write16(hw, PCI_STATUS,
2372 pci_err | PCI_STATUS_ERROR_BITS);
2373 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2376 if (status & Y2_IS_PCI_EXP) {
2377 /* PCI-Express uncorrectable Error occurred */
2380 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2382 if (net_ratelimit())
2383 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2386 /* clear the interrupt */
2387 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2388 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2390 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2392 if (pex_err & PEX_FATAL_ERRORS) {
2393 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2394 hwmsk &= ~Y2_IS_PCI_EXP;
2395 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2399 if (status & Y2_HWE_L1_MASK)
2400 sky2_hw_error(hw, 0, status);
2402 if (status & Y2_HWE_L1_MASK)
2403 sky2_hw_error(hw, 1, status);
2406 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2408 struct net_device *dev = hw->dev[port];
2409 struct sky2_port *sky2 = netdev_priv(dev);
2410 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2412 if (netif_msg_intr(sky2))
2413 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2416 if (status & GM_IS_RX_CO_OV)
2417 gma_read16(hw, port, GM_RX_IRQ_SRC);
2419 if (status & GM_IS_TX_CO_OV)
2420 gma_read16(hw, port, GM_TX_IRQ_SRC);
2422 if (status & GM_IS_RX_FF_OR) {
2423 ++sky2->net_stats.rx_fifo_errors;
2424 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2427 if (status & GM_IS_TX_FF_UR) {
2428 ++sky2->net_stats.tx_fifo_errors;
2429 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2433 /* This should never happen it is a bug. */
2434 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2435 u16 q, unsigned ring_size)
2437 struct net_device *dev = hw->dev[port];
2438 struct sky2_port *sky2 = netdev_priv(dev);
2440 const u64 *le = (q == Q_R1 || q == Q_R2)
2441 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2443 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2444 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2445 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2446 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2448 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2451 /* Check for lost IRQ once a second */
2452 static void sky2_watchdog(unsigned long arg)
2454 struct sky2_hw *hw = (struct sky2_hw *) arg;
2456 if (sky2_read32(hw, B0_ISRC)) {
2457 struct net_device *dev = hw->dev[0];
2459 if (__netif_rx_schedule_prep(dev))
2460 __netif_rx_schedule(dev);
2464 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2467 /* Hardware/software error handling */
2468 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2470 if (net_ratelimit())
2471 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2473 if (status & Y2_IS_HW_ERR)
2476 if (status & Y2_IS_IRQ_MAC1)
2477 sky2_mac_intr(hw, 0);
2479 if (status & Y2_IS_IRQ_MAC2)
2480 sky2_mac_intr(hw, 1);
2482 if (status & Y2_IS_CHK_RX1)
2483 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2485 if (status & Y2_IS_CHK_RX2)
2486 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2488 if (status & Y2_IS_CHK_TXA1)
2489 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2491 if (status & Y2_IS_CHK_TXA2)
2492 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2495 static int sky2_poll(struct net_device *dev0, int *budget)
2497 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2499 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2501 if (unlikely(status & Y2_IS_ERROR))
2502 sky2_err_intr(hw, status);
2504 if (status & Y2_IS_IRQ_PHY1)
2505 sky2_phy_intr(hw, 0);
2507 if (status & Y2_IS_IRQ_PHY2)
2508 sky2_phy_intr(hw, 1);
2510 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2511 *budget -= work_done;
2512 dev0->quota -= work_done;
2515 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
2518 /* Bug/Errata workaround?
2519 * Need to kick the TX irq moderation timer.
2521 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2522 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2523 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2525 netif_rx_complete(dev0);
2527 sky2_read32(hw, B0_Y2_SP_LISR);
2531 static irqreturn_t sky2_intr(int irq, void *dev_id)
2533 struct sky2_hw *hw = dev_id;
2534 struct net_device *dev0 = hw->dev[0];
2537 /* Reading this mask interrupts as side effect */
2538 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2539 if (status == 0 || status == ~0)
2542 prefetch(&hw->st_le[hw->st_idx]);
2543 if (likely(__netif_rx_schedule_prep(dev0)))
2544 __netif_rx_schedule(dev0);
2549 #ifdef CONFIG_NET_POLL_CONTROLLER
2550 static void sky2_netpoll(struct net_device *dev)
2552 struct sky2_port *sky2 = netdev_priv(dev);
2553 struct net_device *dev0 = sky2->hw->dev[0];
2555 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2556 __netif_rx_schedule(dev0);
2560 /* Chip internal frequency for clock calculations */
2561 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2563 switch (hw->chip_id) {
2564 case CHIP_ID_YUKON_EC:
2565 case CHIP_ID_YUKON_EC_U:
2566 case CHIP_ID_YUKON_EX:
2567 return 125; /* 125 Mhz */
2568 case CHIP_ID_YUKON_FE:
2569 return 100; /* 100 Mhz */
2570 default: /* YUKON_XL */
2571 return 156; /* 156 Mhz */
2575 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2577 return sky2_mhz(hw) * us;
2580 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2582 return clk / sky2_mhz(hw);
2586 static int __devinit sky2_init(struct sky2_hw *hw)
2590 /* Enable all clocks */
2591 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2593 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2595 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2596 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2597 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2602 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2604 /* This rev is really old, and requires untested workarounds */
2605 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2606 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2607 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2608 hw->chip_id, hw->chip_rev);
2612 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2614 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2615 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2616 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2623 static void sky2_reset(struct sky2_hw *hw)
2629 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2630 status = sky2_read16(hw, HCU_CCSR);
2631 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2632 HCU_CCSR_UC_STATE_MSK);
2633 sky2_write16(hw, HCU_CCSR, status);
2635 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2636 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2639 sky2_write8(hw, B0_CTST, CS_RST_SET);
2640 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2642 /* clear PCI errors, if any */
2643 status = sky2_pci_read16(hw, PCI_STATUS);
2645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2646 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2649 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2651 /* clear any PEX errors */
2652 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2653 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2658 for (i = 0; i < hw->ports; i++) {
2659 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2660 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2662 if (hw->chip_id == CHIP_ID_YUKON_EX)
2663 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2664 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2668 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2670 /* Clear I2C IRQ noise */
2671 sky2_write32(hw, B2_I2C_IRQ, 1);
2673 /* turn off hardware timer (unused) */
2674 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2675 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2677 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2679 /* Turn off descriptor polling */
2680 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2682 /* Turn off receive timestamp */
2683 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2684 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2686 /* enable the Tx Arbiters */
2687 for (i = 0; i < hw->ports; i++)
2688 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2690 /* Initialize ram interface */
2691 for (i = 0; i < hw->ports; i++) {
2692 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2694 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2695 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2696 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2697 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2698 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2699 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2700 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2701 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2702 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2703 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2704 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2705 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2708 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2710 for (i = 0; i < hw->ports; i++)
2711 sky2_gmac_reset(hw, i);
2713 memset(hw->st_le, 0, STATUS_LE_BYTES);
2716 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2717 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2719 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2720 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2722 /* Set the list last index */
2723 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2725 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2726 sky2_write8(hw, STAT_FIFO_WM, 16);
2728 /* set Status-FIFO ISR watermark */
2729 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2730 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2732 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2734 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2735 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2736 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2738 /* enable status unit */
2739 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2741 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2742 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2743 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2746 static void sky2_restart(struct work_struct *work)
2748 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2749 struct net_device *dev;
2753 sky2_write32(hw, B0_IMSK, 0);
2754 sky2_read32(hw, B0_IMSK);
2756 netif_poll_disable(hw->dev[0]);
2758 for (i = 0; i < hw->ports; i++) {
2760 if (netif_running(dev))
2765 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2766 netif_poll_enable(hw->dev[0]);
2768 for (i = 0; i < hw->ports; i++) {
2770 if (netif_running(dev)) {
2773 printk(KERN_INFO PFX "%s: could not restart %d\n",
2783 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2785 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2788 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2790 const struct sky2_port *sky2 = netdev_priv(dev);
2792 wol->supported = sky2_wol_supported(sky2->hw);
2793 wol->wolopts = sky2->wol;
2796 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2798 struct sky2_port *sky2 = netdev_priv(dev);
2799 struct sky2_hw *hw = sky2->hw;
2801 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2804 sky2->wol = wol->wolopts;
2806 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
2807 sky2_write32(hw, B0_CTST, sky2->wol
2808 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2810 if (!netif_running(dev))
2811 sky2_wol_init(sky2);
2815 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2817 if (sky2_is_copper(hw)) {
2818 u32 modes = SUPPORTED_10baseT_Half
2819 | SUPPORTED_10baseT_Full
2820 | SUPPORTED_100baseT_Half
2821 | SUPPORTED_100baseT_Full
2822 | SUPPORTED_Autoneg | SUPPORTED_TP;
2824 if (hw->chip_id != CHIP_ID_YUKON_FE)
2825 modes |= SUPPORTED_1000baseT_Half
2826 | SUPPORTED_1000baseT_Full;
2829 return SUPPORTED_1000baseT_Half
2830 | SUPPORTED_1000baseT_Full
2835 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2837 struct sky2_port *sky2 = netdev_priv(dev);
2838 struct sky2_hw *hw = sky2->hw;
2840 ecmd->transceiver = XCVR_INTERNAL;
2841 ecmd->supported = sky2_supported_modes(hw);
2842 ecmd->phy_address = PHY_ADDR_MARV;
2843 if (sky2_is_copper(hw)) {
2844 ecmd->port = PORT_TP;
2845 ecmd->speed = sky2->speed;
2847 ecmd->speed = SPEED_1000;
2848 ecmd->port = PORT_FIBRE;
2851 ecmd->advertising = sky2->advertising;
2852 ecmd->autoneg = sky2->autoneg;
2853 ecmd->duplex = sky2->duplex;
2857 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2859 struct sky2_port *sky2 = netdev_priv(dev);
2860 const struct sky2_hw *hw = sky2->hw;
2861 u32 supported = sky2_supported_modes(hw);
2863 if (ecmd->autoneg == AUTONEG_ENABLE) {
2864 ecmd->advertising = supported;
2870 switch (ecmd->speed) {
2872 if (ecmd->duplex == DUPLEX_FULL)
2873 setting = SUPPORTED_1000baseT_Full;
2874 else if (ecmd->duplex == DUPLEX_HALF)
2875 setting = SUPPORTED_1000baseT_Half;
2880 if (ecmd->duplex == DUPLEX_FULL)
2881 setting = SUPPORTED_100baseT_Full;
2882 else if (ecmd->duplex == DUPLEX_HALF)
2883 setting = SUPPORTED_100baseT_Half;
2889 if (ecmd->duplex == DUPLEX_FULL)
2890 setting = SUPPORTED_10baseT_Full;
2891 else if (ecmd->duplex == DUPLEX_HALF)
2892 setting = SUPPORTED_10baseT_Half;
2900 if ((setting & supported) == 0)
2903 sky2->speed = ecmd->speed;
2904 sky2->duplex = ecmd->duplex;
2907 sky2->autoneg = ecmd->autoneg;
2908 sky2->advertising = ecmd->advertising;
2910 if (netif_running(dev)) {
2911 sky2_phy_reinit(sky2);
2912 sky2_set_multicast(dev);
2918 static void sky2_get_drvinfo(struct net_device *dev,
2919 struct ethtool_drvinfo *info)
2921 struct sky2_port *sky2 = netdev_priv(dev);
2923 strcpy(info->driver, DRV_NAME);
2924 strcpy(info->version, DRV_VERSION);
2925 strcpy(info->fw_version, "N/A");
2926 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2929 static const struct sky2_stat {
2930 char name[ETH_GSTRING_LEN];
2933 { "tx_bytes", GM_TXO_OK_HI },
2934 { "rx_bytes", GM_RXO_OK_HI },
2935 { "tx_broadcast", GM_TXF_BC_OK },
2936 { "rx_broadcast", GM_RXF_BC_OK },
2937 { "tx_multicast", GM_TXF_MC_OK },
2938 { "rx_multicast", GM_RXF_MC_OK },
2939 { "tx_unicast", GM_TXF_UC_OK },
2940 { "rx_unicast", GM_RXF_UC_OK },
2941 { "tx_mac_pause", GM_TXF_MPAUSE },
2942 { "rx_mac_pause", GM_RXF_MPAUSE },
2943 { "collisions", GM_TXF_COL },
2944 { "late_collision",GM_TXF_LAT_COL },
2945 { "aborted", GM_TXF_ABO_COL },
2946 { "single_collisions", GM_TXF_SNG_COL },
2947 { "multi_collisions", GM_TXF_MUL_COL },
2949 { "rx_short", GM_RXF_SHT },
2950 { "rx_runt", GM_RXE_FRAG },
2951 { "rx_64_byte_packets", GM_RXF_64B },
2952 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2953 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2954 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2955 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2956 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2957 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2958 { "rx_too_long", GM_RXF_LNG_ERR },
2959 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2960 { "rx_jabber", GM_RXF_JAB_PKT },
2961 { "rx_fcs_error", GM_RXF_FCS_ERR },
2963 { "tx_64_byte_packets", GM_TXF_64B },
2964 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2965 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2966 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2967 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2968 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2969 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2970 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2973 static u32 sky2_get_rx_csum(struct net_device *dev)
2975 struct sky2_port *sky2 = netdev_priv(dev);
2977 return sky2->rx_csum;
2980 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2982 struct sky2_port *sky2 = netdev_priv(dev);
2984 sky2->rx_csum = data;
2986 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2987 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2992 static u32 sky2_get_msglevel(struct net_device *netdev)
2994 struct sky2_port *sky2 = netdev_priv(netdev);
2995 return sky2->msg_enable;
2998 static int sky2_nway_reset(struct net_device *dev)
3000 struct sky2_port *sky2 = netdev_priv(dev);
3002 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3005 sky2_phy_reinit(sky2);
3006 sky2_set_multicast(dev);
3011 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3013 struct sky2_hw *hw = sky2->hw;
3014 unsigned port = sky2->port;
3017 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3018 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3019 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3020 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3022 for (i = 2; i < count; i++)
3023 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3026 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3028 struct sky2_port *sky2 = netdev_priv(netdev);
3029 sky2->msg_enable = value;
3032 static int sky2_get_stats_count(struct net_device *dev)
3034 return ARRAY_SIZE(sky2_stats);
3037 static void sky2_get_ethtool_stats(struct net_device *dev,
3038 struct ethtool_stats *stats, u64 * data)
3040 struct sky2_port *sky2 = netdev_priv(dev);
3042 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3045 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3049 switch (stringset) {
3051 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3052 memcpy(data + i * ETH_GSTRING_LEN,
3053 sky2_stats[i].name, ETH_GSTRING_LEN);
3058 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3060 struct sky2_port *sky2 = netdev_priv(dev);
3061 return &sky2->net_stats;
3064 static int sky2_set_mac_address(struct net_device *dev, void *p)
3066 struct sky2_port *sky2 = netdev_priv(dev);
3067 struct sky2_hw *hw = sky2->hw;
3068 unsigned port = sky2->port;
3069 const struct sockaddr *addr = p;
3071 if (!is_valid_ether_addr(addr->sa_data))
3072 return -EADDRNOTAVAIL;
3074 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3075 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3076 dev->dev_addr, ETH_ALEN);
3077 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3078 dev->dev_addr, ETH_ALEN);
3080 /* virtual address for data */
3081 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3083 /* physical address: used for pause frames */
3084 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3089 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3093 bit = ether_crc(ETH_ALEN, addr) & 63;
3094 filter[bit >> 3] |= 1 << (bit & 7);
3097 static void sky2_set_multicast(struct net_device *dev)
3099 struct sky2_port *sky2 = netdev_priv(dev);
3100 struct sky2_hw *hw = sky2->hw;
3101 unsigned port = sky2->port;
3102 struct dev_mc_list *list = dev->mc_list;
3106 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3108 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3109 memset(filter, 0, sizeof(filter));
3111 reg = gma_read16(hw, port, GM_RX_CTRL);
3112 reg |= GM_RXCR_UCF_ENA;
3114 if (dev->flags & IFF_PROMISC) /* promiscuous */
3115 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3116 else if (dev->flags & IFF_ALLMULTI)
3117 memset(filter, 0xff, sizeof(filter));
3118 else if (dev->mc_count == 0 && !rx_pause)
3119 reg &= ~GM_RXCR_MCF_ENA;
3122 reg |= GM_RXCR_MCF_ENA;
3125 sky2_add_filter(filter, pause_mc_addr);
3127 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3128 sky2_add_filter(filter, list->dmi_addr);
3131 gma_write16(hw, port, GM_MC_ADDR_H1,
3132 (u16) filter[0] | ((u16) filter[1] << 8));
3133 gma_write16(hw, port, GM_MC_ADDR_H2,
3134 (u16) filter[2] | ((u16) filter[3] << 8));
3135 gma_write16(hw, port, GM_MC_ADDR_H3,
3136 (u16) filter[4] | ((u16) filter[5] << 8));
3137 gma_write16(hw, port, GM_MC_ADDR_H4,
3138 (u16) filter[6] | ((u16) filter[7] << 8));
3140 gma_write16(hw, port, GM_RX_CTRL, reg);
3143 /* Can have one global because blinking is controlled by
3144 * ethtool and that is always under RTNL mutex
3146 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3150 switch (hw->chip_id) {
3151 case CHIP_ID_YUKON_XL:
3152 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3153 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3154 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3155 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3156 PHY_M_LEDC_INIT_CTRL(7) |
3157 PHY_M_LEDC_STA1_CTRL(7) |
3158 PHY_M_LEDC_STA0_CTRL(7))
3161 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3165 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3166 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3167 on ? PHY_M_LED_ALL : 0);
3171 /* blink LED's for finding board */
3172 static int sky2_phys_id(struct net_device *dev, u32 data)
3174 struct sky2_port *sky2 = netdev_priv(dev);
3175 struct sky2_hw *hw = sky2->hw;
3176 unsigned port = sky2->port;
3177 u16 ledctrl, ledover = 0;
3182 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3183 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3187 /* save initial values */
3188 spin_lock_bh(&sky2->phy_lock);
3189 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3190 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3191 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3192 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3193 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3195 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3196 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3200 while (!interrupted && ms > 0) {
3201 sky2_led(hw, port, onoff);
3204 spin_unlock_bh(&sky2->phy_lock);
3205 interrupted = msleep_interruptible(250);
3206 spin_lock_bh(&sky2->phy_lock);
3211 /* resume regularly scheduled programming */
3212 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3213 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3214 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3215 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3216 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3218 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3219 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3221 spin_unlock_bh(&sky2->phy_lock);
3226 static void sky2_get_pauseparam(struct net_device *dev,
3227 struct ethtool_pauseparam *ecmd)
3229 struct sky2_port *sky2 = netdev_priv(dev);
3231 switch (sky2->flow_mode) {
3233 ecmd->tx_pause = ecmd->rx_pause = 0;
3236 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3239 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3242 ecmd->tx_pause = ecmd->rx_pause = 1;
3245 ecmd->autoneg = sky2->autoneg;
3248 static int sky2_set_pauseparam(struct net_device *dev,
3249 struct ethtool_pauseparam *ecmd)
3251 struct sky2_port *sky2 = netdev_priv(dev);
3253 sky2->autoneg = ecmd->autoneg;
3254 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3256 if (netif_running(dev))
3257 sky2_phy_reinit(sky2);
3262 static int sky2_get_coalesce(struct net_device *dev,
3263 struct ethtool_coalesce *ecmd)
3265 struct sky2_port *sky2 = netdev_priv(dev);
3266 struct sky2_hw *hw = sky2->hw;
3268 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3269 ecmd->tx_coalesce_usecs = 0;
3271 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3272 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3274 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3276 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3277 ecmd->rx_coalesce_usecs = 0;
3279 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3280 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3282 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3284 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3285 ecmd->rx_coalesce_usecs_irq = 0;
3287 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3288 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3291 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3296 /* Note: this affect both ports */
3297 static int sky2_set_coalesce(struct net_device *dev,
3298 struct ethtool_coalesce *ecmd)
3300 struct sky2_port *sky2 = netdev_priv(dev);
3301 struct sky2_hw *hw = sky2->hw;
3302 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3304 if (ecmd->tx_coalesce_usecs > tmax ||
3305 ecmd->rx_coalesce_usecs > tmax ||
3306 ecmd->rx_coalesce_usecs_irq > tmax)
3309 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3311 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3313 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3316 if (ecmd->tx_coalesce_usecs == 0)
3317 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3319 sky2_write32(hw, STAT_TX_TIMER_INI,
3320 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3321 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3323 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3325 if (ecmd->rx_coalesce_usecs == 0)
3326 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3328 sky2_write32(hw, STAT_LEV_TIMER_INI,
3329 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3330 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3332 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3334 if (ecmd->rx_coalesce_usecs_irq == 0)
3335 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3337 sky2_write32(hw, STAT_ISR_TIMER_INI,
3338 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3339 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3341 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3345 static void sky2_get_ringparam(struct net_device *dev,
3346 struct ethtool_ringparam *ering)
3348 struct sky2_port *sky2 = netdev_priv(dev);
3350 ering->rx_max_pending = RX_MAX_PENDING;
3351 ering->rx_mini_max_pending = 0;
3352 ering->rx_jumbo_max_pending = 0;
3353 ering->tx_max_pending = TX_RING_SIZE - 1;
3355 ering->rx_pending = sky2->rx_pending;
3356 ering->rx_mini_pending = 0;
3357 ering->rx_jumbo_pending = 0;
3358 ering->tx_pending = sky2->tx_pending;
3361 static int sky2_set_ringparam(struct net_device *dev,
3362 struct ethtool_ringparam *ering)
3364 struct sky2_port *sky2 = netdev_priv(dev);
3367 if (ering->rx_pending > RX_MAX_PENDING ||
3368 ering->rx_pending < 8 ||
3369 ering->tx_pending < MAX_SKB_TX_LE ||
3370 ering->tx_pending > TX_RING_SIZE - 1)
3373 if (netif_running(dev))
3376 sky2->rx_pending = ering->rx_pending;
3377 sky2->tx_pending = ering->tx_pending;
3379 if (netif_running(dev)) {
3384 sky2_set_multicast(dev);
3390 static int sky2_get_regs_len(struct net_device *dev)
3396 * Returns copy of control register region
3397 * Note: ethtool_get_regs always provides full size (16k) buffer
3399 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3402 const struct sky2_port *sky2 = netdev_priv(dev);
3403 const void __iomem *io = sky2->hw->regs;
3406 memset(p, 0, regs->len);
3408 memcpy_fromio(p, io, B3_RAM_ADDR);
3410 /* skip diagnostic ram region */
3411 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3413 /* copy GMAC registers */
3414 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3415 if (sky2->hw->ports > 1)
3416 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3420 /* In order to do Jumbo packets on these chips, need to turn off the
3421 * transmit store/forward. Therefore checksum offload won't work.
3423 static int no_tx_offload(struct net_device *dev)
3425 const struct sky2_port *sky2 = netdev_priv(dev);
3426 const struct sky2_hw *hw = sky2->hw;
3428 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3431 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3433 if (data && no_tx_offload(dev))
3436 return ethtool_op_set_tx_csum(dev, data);
3440 static int sky2_set_tso(struct net_device *dev, u32 data)
3442 if (data && no_tx_offload(dev))
3445 return ethtool_op_set_tso(dev, data);
3448 static int sky2_get_eeprom_len(struct net_device *dev)
3450 struct sky2_port *sky2 = netdev_priv(dev);
3453 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3454 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3457 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3459 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3461 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3463 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3466 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3468 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3469 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3472 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3475 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3478 struct sky2_port *sky2 = netdev_priv(dev);
3479 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3480 int length = eeprom->len;
3481 u16 offset = eeprom->offset;
3486 eeprom->magic = SKY2_EEPROM_MAGIC;
3488 while (length > 0) {
3489 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3490 int n = min_t(int, length, sizeof(val));
3492 memcpy(data, &val, n);
3500 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3503 struct sky2_port *sky2 = netdev_priv(dev);
3504 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3505 int length = eeprom->len;
3506 u16 offset = eeprom->offset;
3511 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3514 while (length > 0) {
3516 int n = min_t(int, length, sizeof(val));
3518 if (n < sizeof(val))
3519 val = sky2_vpd_read(sky2->hw, cap, offset);
3520 memcpy(&val, data, n);
3522 sky2_vpd_write(sky2->hw, cap, offset, val);
3532 static const struct ethtool_ops sky2_ethtool_ops = {
3533 .get_settings = sky2_get_settings,
3534 .set_settings = sky2_set_settings,
3535 .get_drvinfo = sky2_get_drvinfo,
3536 .get_wol = sky2_get_wol,
3537 .set_wol = sky2_set_wol,
3538 .get_msglevel = sky2_get_msglevel,
3539 .set_msglevel = sky2_set_msglevel,
3540 .nway_reset = sky2_nway_reset,
3541 .get_regs_len = sky2_get_regs_len,
3542 .get_regs = sky2_get_regs,
3543 .get_link = ethtool_op_get_link,
3544 .get_eeprom_len = sky2_get_eeprom_len,
3545 .get_eeprom = sky2_get_eeprom,
3546 .set_eeprom = sky2_set_eeprom,
3547 .get_sg = ethtool_op_get_sg,
3548 .set_sg = ethtool_op_set_sg,
3549 .get_tx_csum = ethtool_op_get_tx_csum,
3550 .set_tx_csum = sky2_set_tx_csum,
3551 .get_tso = ethtool_op_get_tso,
3552 .set_tso = sky2_set_tso,
3553 .get_rx_csum = sky2_get_rx_csum,
3554 .set_rx_csum = sky2_set_rx_csum,
3555 .get_strings = sky2_get_strings,
3556 .get_coalesce = sky2_get_coalesce,
3557 .set_coalesce = sky2_set_coalesce,
3558 .get_ringparam = sky2_get_ringparam,
3559 .set_ringparam = sky2_set_ringparam,
3560 .get_pauseparam = sky2_get_pauseparam,
3561 .set_pauseparam = sky2_set_pauseparam,
3562 .phys_id = sky2_phys_id,
3563 .get_stats_count = sky2_get_stats_count,
3564 .get_ethtool_stats = sky2_get_ethtool_stats,
3567 #ifdef CONFIG_SKY2_DEBUG
3569 static struct dentry *sky2_debug;
3571 static int sky2_debug_show(struct seq_file *seq, void *v)
3573 struct net_device *dev = seq->private;
3574 const struct sky2_port *sky2 = netdev_priv(dev);
3575 const struct sky2_hw *hw = sky2->hw;
3576 unsigned port = sky2->port;
3580 if (!netif_running(dev))
3583 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3584 sky2_read32(hw, B0_ISRC),
3585 sky2_read32(hw, B0_IMSK),
3586 sky2_read32(hw, B0_Y2_SP_ICR));
3588 netif_poll_disable(hw->dev[0]);
3589 last = sky2_read16(hw, STAT_PUT_IDX);
3591 if (hw->st_idx == last)
3592 seq_puts(seq, "Status ring (empty)\n");
3594 seq_puts(seq, "Status ring\n");
3595 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3596 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3597 const struct sky2_status_le *le = hw->st_le + idx;
3598 seq_printf(seq, "[%d] %#x %d %#x\n",
3599 idx, le->opcode, le->length, le->status);
3601 seq_puts(seq, "\n");
3604 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3605 sky2->tx_cons, sky2->tx_prod,
3606 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3607 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3609 /* Dump contents of tx ring */
3611 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3612 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3613 const struct sky2_tx_le *le = sky2->tx_le + idx;
3614 u32 a = le32_to_cpu(le->addr);
3617 seq_printf(seq, "%u:", idx);
3620 switch(le->opcode & ~HW_OWNER) {
3622 seq_printf(seq, " %#x:", a);
3625 seq_printf(seq, " mtu=%d", a);
3628 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3631 seq_printf(seq, " csum=%#x", a);
3634 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3637 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3640 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3643 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3644 a, le16_to_cpu(le->length));
3647 if (le->ctrl & EOP) {
3648 seq_putc(seq, '\n');
3653 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3654 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3655 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3656 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3658 netif_poll_enable(hw->dev[0]);
3662 static int sky2_debug_open(struct inode *inode, struct file *file)
3664 return single_open(file, sky2_debug_show, inode->i_private);
3667 static const struct file_operations sky2_debug_fops = {
3668 .owner = THIS_MODULE,
3669 .open = sky2_debug_open,
3671 .llseek = seq_lseek,
3672 .release = single_release,
3676 * Use network device events to create/remove/rename
3677 * debugfs file entries
3679 static int sky2_device_event(struct notifier_block *unused,
3680 unsigned long event, void *ptr)
3682 struct net_device *dev = ptr;
3684 if (dev->open == sky2_up) {
3685 struct sky2_port *sky2 = netdev_priv(dev);
3688 case NETDEV_CHANGENAME:
3689 if (!netif_running(dev))
3693 case NETDEV_GOING_DOWN:
3694 if (sky2->debugfs) {
3695 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3697 debugfs_remove(sky2->debugfs);
3698 sky2->debugfs = NULL;
3701 if (event != NETDEV_CHANGENAME)
3703 /* fallthrough for changename */
3707 d = debugfs_create_file(dev->name, S_IRUGO,
3710 if (d == NULL || IS_ERR(d))
3711 printk(KERN_INFO PFX
3712 "%s: debugfs create failed\n",
3724 static struct notifier_block sky2_notifier = {
3725 .notifier_call = sky2_device_event,
3729 static __init void sky2_debug_init(void)
3733 ent = debugfs_create_dir("sky2", NULL);
3734 if (!ent || IS_ERR(ent))
3738 register_netdevice_notifier(&sky2_notifier);
3741 static __exit void sky2_debug_cleanup(void)
3744 unregister_netdevice_notifier(&sky2_notifier);
3745 debugfs_remove(sky2_debug);
3751 #define sky2_debug_init()
3752 #define sky2_debug_cleanup()
3756 /* Initialize network device */
3757 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3759 int highmem, int wol)
3761 struct sky2_port *sky2;
3762 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3765 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3769 SET_MODULE_OWNER(dev);
3770 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3771 dev->irq = hw->pdev->irq;
3772 dev->open = sky2_up;
3773 dev->stop = sky2_down;
3774 dev->do_ioctl = sky2_ioctl;
3775 dev->hard_start_xmit = sky2_xmit_frame;
3776 dev->get_stats = sky2_get_stats;
3777 dev->set_multicast_list = sky2_set_multicast;
3778 dev->set_mac_address = sky2_set_mac_address;
3779 dev->change_mtu = sky2_change_mtu;
3780 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3781 dev->tx_timeout = sky2_tx_timeout;
3782 dev->watchdog_timeo = TX_WATCHDOG;
3784 dev->poll = sky2_poll;
3785 dev->weight = NAPI_WEIGHT;
3786 #ifdef CONFIG_NET_POLL_CONTROLLER
3787 /* Network console (only works on port 0)
3788 * because netpoll makes assumptions about NAPI
3791 dev->poll_controller = sky2_netpoll;
3794 sky2 = netdev_priv(dev);
3797 sky2->msg_enable = netif_msg_init(debug, default_msg);
3799 /* Auto speed and flow control */
3800 sky2->autoneg = AUTONEG_ENABLE;
3801 sky2->flow_mode = FC_BOTH;
3805 sky2->advertising = sky2_supported_modes(hw);
3809 spin_lock_init(&sky2->phy_lock);
3810 sky2->tx_pending = TX_DEF_PENDING;
3811 sky2->rx_pending = RX_DEF_PENDING;
3813 hw->dev[port] = dev;
3817 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3819 dev->features |= NETIF_F_HIGHDMA;
3821 #ifdef SKY2_VLAN_TAG_USED
3822 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3823 dev->vlan_rx_register = sky2_vlan_rx_register;
3826 /* read the mac address */
3827 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3828 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3833 static void __devinit sky2_show_addr(struct net_device *dev)
3835 const struct sky2_port *sky2 = netdev_priv(dev);
3837 if (netif_msg_probe(sky2))
3838 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3840 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3841 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3844 /* Handle software interrupt used during MSI test */
3845 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3847 struct sky2_hw *hw = dev_id;
3848 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3853 if (status & Y2_IS_IRQ_SW) {
3855 wake_up(&hw->msi_wait);
3856 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3858 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3863 /* Test interrupt path by forcing a a software IRQ */
3864 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3866 struct pci_dev *pdev = hw->pdev;
3869 init_waitqueue_head (&hw->msi_wait);
3871 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3873 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3875 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3879 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3880 sky2_read8(hw, B0_CTST);
3882 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3885 /* MSI test failed, go back to INTx mode */
3886 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3887 "switching to INTx mode.\n");
3890 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3893 sky2_write32(hw, B0_IMSK, 0);
3894 sky2_read32(hw, B0_IMSK);
3896 free_irq(pdev->irq, hw);
3901 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3903 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3908 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3910 return value & PCI_PM_CTRL_PME_ENABLE;
3913 static int __devinit sky2_probe(struct pci_dev *pdev,
3914 const struct pci_device_id *ent)
3916 struct net_device *dev;
3918 int err, using_dac = 0, wol_default;
3920 err = pci_enable_device(pdev);
3922 dev_err(&pdev->dev, "cannot enable PCI device\n");
3926 err = pci_request_regions(pdev, DRV_NAME);
3928 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3929 goto err_out_disable;
3932 pci_set_master(pdev);
3934 if (sizeof(dma_addr_t) > sizeof(u32) &&
3935 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3937 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3939 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3940 "for consistent allocations\n");
3941 goto err_out_free_regions;
3944 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3946 dev_err(&pdev->dev, "no usable DMA configuration\n");
3947 goto err_out_free_regions;
3951 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3954 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3956 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3957 goto err_out_free_regions;
3962 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3964 dev_err(&pdev->dev, "cannot map device registers\n");
3965 goto err_out_free_hw;
3969 /* The sk98lin vendor driver uses hardware byte swapping but
3970 * this driver uses software swapping.
3974 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3975 reg &= ~PCI_REV_DESC;
3976 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3980 /* ring for status responses */
3981 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3984 goto err_out_iounmap;
3986 err = sky2_init(hw);
3988 goto err_out_iounmap;
3990 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3991 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3992 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3993 hw->chip_id, hw->chip_rev);
3997 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4000 goto err_out_free_pci;
4003 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4004 err = sky2_test_msi(hw);
4005 if (err == -EOPNOTSUPP)
4006 pci_disable_msi(pdev);
4008 goto err_out_free_netdev;
4011 err = register_netdev(dev);
4013 dev_err(&pdev->dev, "cannot register net device\n");
4014 goto err_out_free_netdev;
4017 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4020 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4021 goto err_out_unregister;
4023 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4025 sky2_show_addr(dev);
4027 if (hw->ports > 1) {
4028 struct net_device *dev1;
4030 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4032 dev_warn(&pdev->dev, "allocation for second device failed\n");
4033 else if ((err = register_netdev(dev1))) {
4034 dev_warn(&pdev->dev,
4035 "register of second port failed (%d)\n", err);
4039 sky2_show_addr(dev1);
4042 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4043 INIT_WORK(&hw->restart_work, sky2_restart);
4045 pci_set_drvdata(pdev, hw);
4051 pci_disable_msi(pdev);
4052 unregister_netdev(dev);
4053 err_out_free_netdev:
4056 sky2_write8(hw, B0_CTST, CS_RST_SET);
4057 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4062 err_out_free_regions:
4063 pci_release_regions(pdev);
4065 pci_disable_device(pdev);
4067 pci_set_drvdata(pdev, NULL);
4071 static void __devexit sky2_remove(struct pci_dev *pdev)
4073 struct sky2_hw *hw = pci_get_drvdata(pdev);
4074 struct net_device *dev0, *dev1;
4079 del_timer_sync(&hw->watchdog_timer);
4081 flush_scheduled_work();
4083 sky2_write32(hw, B0_IMSK, 0);
4084 synchronize_irq(hw->pdev->irq);
4089 unregister_netdev(dev1);
4090 unregister_netdev(dev0);
4094 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4095 sky2_write8(hw, B0_CTST, CS_RST_SET);
4096 sky2_read8(hw, B0_CTST);
4098 free_irq(pdev->irq, hw);
4100 pci_disable_msi(pdev);
4101 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4102 pci_release_regions(pdev);
4103 pci_disable_device(pdev);
4111 pci_set_drvdata(pdev, NULL);
4115 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4117 struct sky2_hw *hw = pci_get_drvdata(pdev);
4123 netif_poll_disable(hw->dev[0]);
4125 for (i = 0; i < hw->ports; i++) {
4126 struct net_device *dev = hw->dev[i];
4127 struct sky2_port *sky2 = netdev_priv(dev);
4129 if (netif_running(dev))
4133 sky2_wol_init(sky2);
4138 sky2_write32(hw, B0_IMSK, 0);
4141 pci_save_state(pdev);
4142 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4143 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4148 static int sky2_resume(struct pci_dev *pdev)
4150 struct sky2_hw *hw = pci_get_drvdata(pdev);
4156 err = pci_set_power_state(pdev, PCI_D0);
4160 err = pci_restore_state(pdev);
4164 pci_enable_wake(pdev, PCI_D0, 0);
4166 /* Re-enable all clocks */
4167 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4168 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4172 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4174 for (i = 0; i < hw->ports; i++) {
4175 struct net_device *dev = hw->dev[i];
4176 if (netif_running(dev)) {
4179 printk(KERN_ERR PFX "%s: could not up: %d\n",
4185 sky2_set_multicast(dev);
4189 netif_poll_enable(hw->dev[0]);
4193 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4194 pci_disable_device(pdev);
4199 static void sky2_shutdown(struct pci_dev *pdev)
4201 struct sky2_hw *hw = pci_get_drvdata(pdev);
4207 netif_poll_disable(hw->dev[0]);
4209 for (i = 0; i < hw->ports; i++) {
4210 struct net_device *dev = hw->dev[i];
4211 struct sky2_port *sky2 = netdev_priv(dev);
4215 sky2_wol_init(sky2);
4222 pci_enable_wake(pdev, PCI_D3hot, wol);
4223 pci_enable_wake(pdev, PCI_D3cold, wol);
4225 pci_disable_device(pdev);
4226 pci_set_power_state(pdev, PCI_D3hot);
4230 static struct pci_driver sky2_driver = {
4232 .id_table = sky2_id_table,
4233 .probe = sky2_probe,
4234 .remove = __devexit_p(sky2_remove),
4236 .suspend = sky2_suspend,
4237 .resume = sky2_resume,
4239 .shutdown = sky2_shutdown,
4242 static int __init sky2_init_module(void)
4245 return pci_register_driver(&sky2_driver);
4248 static void __exit sky2_cleanup_module(void)
4250 pci_unregister_driver(&sky2_driver);
4251 sky2_debug_cleanup();
4254 module_init(sky2_init_module);
4255 module_exit(sky2_cleanup_module);
4257 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4258 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4259 MODULE_LICENSE("GPL");
4260 MODULE_VERSION(DRV_VERSION);