2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static int idle_timeout = 100;
103 module_param(idle_timeout, int, 0);
104 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
106 static const struct pci_device_id sky2_id_table[] = {
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
140 MODULE_DEVICE_TABLE(pci, sky2_id_table);
142 /* Avoid conditionals by using array */
143 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
145 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
147 /* This driver supports yukon2 chipset only */
148 static const char *yukon2_name[] = {
150 "EC Ultra", /* 0xb4 */
151 "Extreme", /* 0xb5 */
156 /* Access to external PHY */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165 for (i = 0; i < PHY_RETRIES; i++) {
166 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
171 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
175 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
179 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
180 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
182 for (i = 0; i < PHY_RETRIES; i++) {
183 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
184 *val = gma_read16(hw, port, GM_SMI_DATA);
194 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
198 if (__gm_phy_read(hw, port, reg, &v) != 0)
199 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
204 static void sky2_power_on(struct sky2_hw *hw)
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw, B0_POWER_CTRL,
208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
210 /* disable Core Clock Division, */
211 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
214 /* enable bits are inverted */
215 sky2_write8(hw, B2_Y2_CLK_GATE,
216 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
217 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
218 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
220 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
222 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
225 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
226 /* set all bits to 0 except bits 15..12 and 8 */
227 reg &= P_ASPM_CONTROL_MSK;
228 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
230 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
231 /* set all bits to 0 except bits 28 & 27 */
232 reg &= P_CTL_TIM_VMAIN_AV_MSK;
233 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
235 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
237 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
238 reg = sky2_read32(hw, B2_GP_IO);
239 reg |= GLB_GPIO_STAT_RACE_DIS;
240 sky2_write32(hw, B2_GP_IO, reg);
244 static void sky2_power_aux(struct sky2_hw *hw)
246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 /* enable bits are inverted */
250 sky2_write8(hw, B2_Y2_CLK_GATE,
251 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
252 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
253 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255 /* switch power to VAUX */
256 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
257 sky2_write8(hw, B0_POWER_CTRL,
258 (PC_VAUX_ENA | PC_VCC_ENA |
259 PC_VAUX_ON | PC_VCC_OFF));
262 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
266 /* disable all GMAC IRQ's */
267 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
268 /* disable PHY IRQs */
269 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
271 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
272 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
274 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
276 reg = gma_read16(hw, port, GM_RX_CTRL);
277 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
278 gma_write16(hw, port, GM_RX_CTRL, reg);
281 /* flow control to advertise bits */
282 static const u16 copper_fc_adv[] = {
284 [FC_TX] = PHY_M_AN_ASP,
285 [FC_RX] = PHY_M_AN_PC,
286 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
289 /* flow control to advertise bits when using 1000BaseX */
290 static const u16 fiber_fc_adv[] = {
291 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
292 [FC_TX] = PHY_M_P_ASYM_MD_X,
293 [FC_RX] = PHY_M_P_SYM_MD_X,
294 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
297 /* flow control to GMA disable bits */
298 static const u16 gm_fc_disable[] = {
299 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
300 [FC_TX] = GM_GPCR_FC_RX_DIS,
301 [FC_RX] = GM_GPCR_FC_TX_DIS,
306 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
308 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
309 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
311 if (sky2->autoneg == AUTONEG_ENABLE
312 && !(hw->chip_id == CHIP_ID_YUKON_XL
313 || hw->chip_id == CHIP_ID_YUKON_EC_U
314 || hw->chip_id == CHIP_ID_YUKON_EX)) {
315 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
317 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
319 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
321 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
322 if (hw->chip_id == CHIP_ID_YUKON_EC)
323 /* set downshift counter to 3x and enable downshift */
324 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
326 /* set master & slave downshift counter to 1x */
327 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
333 if (sky2_is_copper(hw)) {
334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
344 /* downshift on PHY 88E1112 and 88E1149 is changed */
345 if (sky2->autoneg == AUTONEG_ENABLE
346 && (hw->chip_id == CHIP_ID_YUKON_XL
347 || hw->chip_id == CHIP_ID_YUKON_EC_U
348 || hw->chip_id == CHIP_ID_YUKON_EX)) {
349 /* set downshift counter to 3x and enable downshift */
350 ctrl &= ~PHY_M_PC_DSC_MSK;
351 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
355 /* workaround for deviation #4.88 (CRC errors) */
356 /* disable Automatic Crossover */
358 ctrl &= ~PHY_M_PC_MDIX_MSK;
361 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
363 /* special setup for PHY 88E1112 Fiber */
364 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
365 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
367 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
369 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
370 ctrl &= ~PHY_M_MAC_MD_MSK;
371 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
372 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
374 if (hw->pmd_type == 'P') {
375 /* select page 1 to access Fiber registers */
376 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
378 /* for SFP-module set SIGDET polarity to low */
379 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
380 ctrl |= PHY_M_FIB_SIGD_POL;
381 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
384 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
392 if (sky2->autoneg == AUTONEG_ENABLE) {
393 if (sky2_is_copper(hw)) {
394 if (sky2->advertising & ADVERTISED_1000baseT_Full)
395 ct1000 |= PHY_M_1000C_AFD;
396 if (sky2->advertising & ADVERTISED_1000baseT_Half)
397 ct1000 |= PHY_M_1000C_AHD;
398 if (sky2->advertising & ADVERTISED_100baseT_Full)
399 adv |= PHY_M_AN_100_FD;
400 if (sky2->advertising & ADVERTISED_100baseT_Half)
401 adv |= PHY_M_AN_100_HD;
402 if (sky2->advertising & ADVERTISED_10baseT_Full)
403 adv |= PHY_M_AN_10_FD;
404 if (sky2->advertising & ADVERTISED_10baseT_Half)
405 adv |= PHY_M_AN_10_HD;
407 adv |= copper_fc_adv[sky2->flow_mode];
408 } else { /* special defines for FIBER (88E1040S only) */
409 if (sky2->advertising & ADVERTISED_1000baseT_Full)
410 adv |= PHY_M_AN_1000X_AFD;
411 if (sky2->advertising & ADVERTISED_1000baseT_Half)
412 adv |= PHY_M_AN_1000X_AHD;
414 adv |= fiber_fc_adv[sky2->flow_mode];
417 /* Restart Auto-negotiation */
418 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
420 /* forced speed/duplex settings */
421 ct1000 = PHY_M_1000C_MSE;
423 /* Disable auto update for duplex flow control and speed */
424 reg |= GM_GPCR_AU_ALL_DIS;
426 switch (sky2->speed) {
428 ctrl |= PHY_CT_SP1000;
429 reg |= GM_GPCR_SPEED_1000;
432 ctrl |= PHY_CT_SP100;
433 reg |= GM_GPCR_SPEED_100;
437 if (sky2->duplex == DUPLEX_FULL) {
438 reg |= GM_GPCR_DUP_FULL;
439 ctrl |= PHY_CT_DUP_MD;
440 } else if (sky2->speed < SPEED_1000)
441 sky2->flow_mode = FC_NONE;
444 reg |= gm_fc_disable[sky2->flow_mode];
446 /* Forward pause packets to GMAC? */
447 if (sky2->flow_mode & FC_RX)
448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
450 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
453 gma_write16(hw, port, GM_GP_CTRL, reg);
455 if (hw->chip_id != CHIP_ID_YUKON_FE)
456 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
458 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
459 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
461 /* Setup Phy LED's */
462 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
465 switch (hw->chip_id) {
466 case CHIP_ID_YUKON_FE:
467 /* on 88E3082 these bits are at 11..9 (shifted left) */
468 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
470 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
472 /* delete ACT LED control bits */
473 ctrl &= ~PHY_M_FELP_LED1_MSK;
474 /* change ACT LED control to blink mode */
475 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
476 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
479 case CHIP_ID_YUKON_XL:
480 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
482 /* select page 3 to access LED control register */
483 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
485 /* set LED Function Control register */
486 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
487 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
488 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
489 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
490 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
492 /* set Polarity Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
494 (PHY_M_POLC_LS1_P_MIX(4) |
495 PHY_M_POLC_IS0_P_MIX(4) |
496 PHY_M_POLC_LOS_CTRL(2) |
497 PHY_M_POLC_INIT_CTRL(2) |
498 PHY_M_POLC_STA1_CTRL(2) |
499 PHY_M_POLC_STA0_CTRL(2)));
501 /* restore page register */
502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
505 case CHIP_ID_YUKON_EC_U:
506 case CHIP_ID_YUKON_EX:
507 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
509 /* select page 3 to access LED control register */
510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
512 /* set LED Function Control register */
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
514 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
515 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
516 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
517 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
519 /* set Blink Rate in LED Timer Control Register */
520 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
521 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
522 /* restore page register */
523 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
527 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
528 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
529 /* turn off the Rx LED (LED_RX) */
530 ledover &= ~PHY_M_LED_MO_RX;
533 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
534 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
535 /* apply fixes in PHY AFE */
536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
538 /* increase differential signal amplitude in 10BASE-T */
539 gm_phy_write(hw, port, 0x18, 0xaa99);
540 gm_phy_write(hw, port, 0x17, 0x2011);
542 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
543 gm_phy_write(hw, port, 0x18, 0xa204);
544 gm_phy_write(hw, port, 0x17, 0x2002);
546 /* set page register to 0 */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
548 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
549 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
551 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
552 /* turn on 100 Mbps LED (LED_LINK100) */
553 ledover |= PHY_M_LED_MO_100;
557 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
561 /* Enable phy interrupt on auto-negotiation complete (or link up) */
562 if (sky2->autoneg == AUTONEG_ENABLE)
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
565 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
568 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
571 static const u32 phy_power[]
572 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
574 /* looks like this XL is back asswards .. */
575 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
578 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
579 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
581 /* Turn off phy power saving */
582 reg1 &= ~phy_power[port];
584 reg1 |= phy_power[port];
586 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
587 sky2_pci_read32(hw, PCI_DEV_REG1);
588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
592 /* Force a renegotiation */
593 static void sky2_phy_reinit(struct sky2_port *sky2)
595 spin_lock_bh(&sky2->phy_lock);
596 sky2_phy_init(sky2->hw, sky2->port);
597 spin_unlock_bh(&sky2->phy_lock);
600 /* Put device in state to listen for Wake On Lan */
601 static void sky2_wol_init(struct sky2_port *sky2)
603 struct sky2_hw *hw = sky2->hw;
604 unsigned port = sky2->port;
605 enum flow_control save_mode;
609 /* Bring hardware out of reset */
610 sky2_write16(hw, B0_CTST, CS_RST_CLR);
611 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
613 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
614 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
617 * sky2_reset will re-enable on resume
619 save_mode = sky2->flow_mode;
620 ctrl = sky2->advertising;
622 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
623 sky2->flow_mode = FC_NONE;
624 sky2_phy_power(hw, port, 1);
625 sky2_phy_reinit(sky2);
627 sky2->flow_mode = save_mode;
628 sky2->advertising = ctrl;
630 /* Set GMAC to no flow control and auto update for speed/duplex */
631 gma_write16(hw, port, GM_GP_CTRL,
632 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
633 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
635 /* Set WOL address */
636 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
637 sky2->netdev->dev_addr, ETH_ALEN);
639 /* Turn on appropriate WOL control bits */
640 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
642 if (sky2->wol & WAKE_PHY)
643 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
645 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
647 if (sky2->wol & WAKE_MAGIC)
648 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
650 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
652 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
653 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
655 /* Turn on legacy PCI-Express PME mode */
656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
657 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
658 reg1 |= PCI_Y2_PME_LEGACY;
659 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
660 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
663 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
667 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
669 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
670 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
672 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
674 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
675 /* set Tx GMAC FIFO Almost Empty Threshold */
676 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
677 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
679 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
680 TX_JUMBO_ENA | TX_STFW_DIS);
682 /* Can't do offload because of lack of store/forward */
683 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
686 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
687 TX_JUMBO_DIS | TX_STFW_ENA);
691 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
693 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
696 const u8 *addr = hw->dev[port]->dev_addr;
698 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
699 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
701 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
703 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
704 /* WA DEV_472 -- looks like crossed wires on port 2 */
705 /* clear GMAC 1 Control reset */
706 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
708 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
709 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
710 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
711 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
712 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
715 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
717 /* Enable Transmit FIFO Underrun */
718 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
720 spin_lock_bh(&sky2->phy_lock);
721 sky2_phy_init(hw, port);
722 spin_unlock_bh(&sky2->phy_lock);
725 reg = gma_read16(hw, port, GM_PHY_ADDR);
726 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
728 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
729 gma_read16(hw, port, i);
730 gma_write16(hw, port, GM_PHY_ADDR, reg);
732 /* transmit control */
733 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
735 /* receive control reg: unicast + multicast + no FCS */
736 gma_write16(hw, port, GM_RX_CTRL,
737 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
739 /* transmit flow control */
740 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
742 /* transmit parameter */
743 gma_write16(hw, port, GM_TX_PARAM,
744 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
745 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
746 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
747 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
749 /* serial mode register */
750 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
751 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
753 if (hw->dev[port]->mtu > ETH_DATA_LEN)
754 reg |= GM_SMOD_JUMBO_ENA;
756 gma_write16(hw, port, GM_SERIAL_MODE, reg);
758 /* virtual address for data */
759 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
761 /* physical address: used for pause frames */
762 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
764 /* ignore counter overflows */
765 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
766 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
767 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
769 /* Configure Rx MAC FIFO */
770 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
771 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
772 if (hw->chip_id == CHIP_ID_YUKON_EX)
773 reg |= GMF_RX_OVER_ON;
775 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
777 /* Flush Rx MAC FIFO on any flow control or error */
778 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
780 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
781 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
783 /* Configure Tx MAC FIFO */
784 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
785 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
787 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
788 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
789 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
791 sky2_set_tx_stfwd(hw, port);
796 /* Assign Ram Buffer allocation to queue */
797 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
801 /* convert from K bytes to qwords used for hw register */
804 end = start + space - 1;
806 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
807 sky2_write32(hw, RB_ADDR(q, RB_START), start);
808 sky2_write32(hw, RB_ADDR(q, RB_END), end);
809 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
810 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
812 if (q == Q_R1 || q == Q_R2) {
813 u32 tp = space - space/4;
815 /* On receive queue's set the thresholds
816 * give receiver priority when > 3/4 full
817 * send pause when down to 2K
819 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
820 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
823 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
824 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
826 /* Enable store & forward on Tx queue's because
827 * Tx FIFO is only 1K on Yukon
829 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
832 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
833 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
836 /* Setup Bus Memory Interface */
837 static void sky2_qset(struct sky2_hw *hw, u16 q)
839 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
840 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
841 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
842 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
845 /* Setup prefetch unit registers. This is the interface between
846 * hardware and driver list elements
848 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
851 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
852 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
853 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
854 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
855 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
856 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
858 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
861 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
863 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
865 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
870 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
871 struct sky2_tx_le *le)
873 return sky2->tx_ring + (le - sky2->tx_le);
876 /* Update chip's next pointer */
877 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
879 /* Make sure write' to descriptors are complete before we tell hardware */
881 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
883 /* Synchronize I/O on since next processor may write to tail */
888 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
890 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
891 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
896 /* Return high part of DMA address (could be 32 or 64 bit) */
897 static inline u32 high32(dma_addr_t a)
899 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
902 /* Build description to hardware for one receive segment */
903 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
904 dma_addr_t map, unsigned len)
906 struct sky2_rx_le *le;
907 u32 hi = high32(map);
909 if (sky2->rx_addr64 != hi) {
910 le = sky2_next_rx(sky2);
911 le->addr = cpu_to_le32(hi);
912 le->opcode = OP_ADDR64 | HW_OWNER;
913 sky2->rx_addr64 = high32(map + len);
916 le = sky2_next_rx(sky2);
917 le->addr = cpu_to_le32((u32) map);
918 le->length = cpu_to_le16(len);
919 le->opcode = op | HW_OWNER;
922 /* Build description to hardware for one possibly fragmented skb */
923 static void sky2_rx_submit(struct sky2_port *sky2,
924 const struct rx_ring_info *re)
928 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
930 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
931 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
935 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
938 struct sk_buff *skb = re->skb;
941 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
942 pci_unmap_len_set(re, data_size, size);
944 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
945 re->frag_addr[i] = pci_map_page(pdev,
946 skb_shinfo(skb)->frags[i].page,
947 skb_shinfo(skb)->frags[i].page_offset,
948 skb_shinfo(skb)->frags[i].size,
952 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
954 struct sk_buff *skb = re->skb;
957 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
960 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
961 pci_unmap_page(pdev, re->frag_addr[i],
962 skb_shinfo(skb)->frags[i].size,
966 /* Tell chip where to start receive checksum.
967 * Actually has two checksums, but set both same to avoid possible byte
970 static void rx_set_checksum(struct sky2_port *sky2)
972 struct sky2_rx_le *le;
974 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
975 le = sky2_next_rx(sky2);
976 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
978 le->opcode = OP_TCPSTART | HW_OWNER;
980 sky2_write32(sky2->hw,
981 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
982 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
988 * The RX Stop command will not work for Yukon-2 if the BMU does not
989 * reach the end of packet and since we can't make sure that we have
990 * incoming data, we must reset the BMU while it is not doing a DMA
991 * transfer. Since it is possible that the RX path is still active,
992 * the RX RAM buffer will be stopped first, so any possible incoming
993 * data will not trigger a DMA. After the RAM buffer is stopped, the
994 * BMU is polled until any DMA in progress is ended and only then it
997 static void sky2_rx_stop(struct sky2_port *sky2)
999 struct sky2_hw *hw = sky2->hw;
1000 unsigned rxq = rxqaddr[sky2->port];
1003 /* disable the RAM Buffer receive queue */
1004 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1006 for (i = 0; i < 0xffff; i++)
1007 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1008 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1011 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1012 sky2->netdev->name);
1014 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1016 /* reset the Rx prefetch unit */
1017 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1021 /* Clean out receive buffer area, assumes receiver hardware stopped */
1022 static void sky2_rx_clean(struct sky2_port *sky2)
1026 memset(sky2->rx_le, 0, RX_LE_BYTES);
1027 for (i = 0; i < sky2->rx_pending; i++) {
1028 struct rx_ring_info *re = sky2->rx_ring + i;
1031 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1038 /* Basic MII support */
1039 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1041 struct mii_ioctl_data *data = if_mii(ifr);
1042 struct sky2_port *sky2 = netdev_priv(dev);
1043 struct sky2_hw *hw = sky2->hw;
1044 int err = -EOPNOTSUPP;
1046 if (!netif_running(dev))
1047 return -ENODEV; /* Phy still in reset */
1051 data->phy_id = PHY_ADDR_MARV;
1057 spin_lock_bh(&sky2->phy_lock);
1058 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1059 spin_unlock_bh(&sky2->phy_lock);
1061 data->val_out = val;
1066 if (!capable(CAP_NET_ADMIN))
1069 spin_lock_bh(&sky2->phy_lock);
1070 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1072 spin_unlock_bh(&sky2->phy_lock);
1078 #ifdef SKY2_VLAN_TAG_USED
1079 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1081 struct sky2_port *sky2 = netdev_priv(dev);
1082 struct sky2_hw *hw = sky2->hw;
1083 u16 port = sky2->port;
1085 netif_tx_lock_bh(dev);
1086 netif_poll_disable(sky2->hw->dev[0]);
1090 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1092 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1095 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1097 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1101 netif_poll_enable(sky2->hw->dev[0]);
1102 netif_tx_unlock_bh(dev);
1107 * Allocate an skb for receiving. If the MTU is large enough
1108 * make the skb non-linear with a fragment list of pages.
1110 * It appears the hardware has a bug in the FIFO logic that
1111 * cause it to hang if the FIFO gets overrun and the receive buffer
1112 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1113 * aligned except if slab debugging is enabled.
1115 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1117 struct sk_buff *skb;
1121 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1125 p = (unsigned long) skb->data;
1126 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1128 for (i = 0; i < sky2->rx_nfrags; i++) {
1129 struct page *page = alloc_page(GFP_ATOMIC);
1133 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1143 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1145 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1149 * Allocate and setup receiver buffer pool.
1150 * Normal case this ends up creating one list element for skb
1151 * in the receive ring. Worst case if using large MTU and each
1152 * allocation falls on a different 64 bit region, that results
1153 * in 6 list elements per ring entry.
1154 * One element is used for checksum enable/disable, and one
1155 * extra to avoid wrap.
1157 static int sky2_rx_start(struct sky2_port *sky2)
1159 struct sky2_hw *hw = sky2->hw;
1160 struct rx_ring_info *re;
1161 unsigned rxq = rxqaddr[sky2->port];
1162 unsigned i, size, space, thresh;
1164 sky2->rx_put = sky2->rx_next = 0;
1167 /* On PCI express lowering the watermark gives better performance */
1168 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1169 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1171 /* These chips have no ram buffer?
1172 * MAC Rx RAM Read is controlled by hardware */
1173 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1174 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1175 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1176 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1178 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1180 rx_set_checksum(sky2);
1182 /* Space needed for frame data + headers rounded up */
1183 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1185 /* Stopping point for hardware truncation */
1186 thresh = (size - 8) / sizeof(u32);
1188 /* Account for overhead of skb - to avoid order > 0 allocation */
1189 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1190 + sizeof(struct skb_shared_info);
1192 sky2->rx_nfrags = space >> PAGE_SHIFT;
1193 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1195 if (sky2->rx_nfrags != 0) {
1196 /* Compute residue after pages */
1197 space = sky2->rx_nfrags << PAGE_SHIFT;
1204 /* Optimize to handle small packets and headers */
1205 if (size < copybreak)
1207 if (size < ETH_HLEN)
1210 sky2->rx_data_size = size;
1213 for (i = 0; i < sky2->rx_pending; i++) {
1214 re = sky2->rx_ring + i;
1216 re->skb = sky2_rx_alloc(sky2);
1220 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1221 sky2_rx_submit(sky2, re);
1225 * The receiver hangs if it receives frames larger than the
1226 * packet buffer. As a workaround, truncate oversize frames, but
1227 * the register is limited to 9 bits, so if you do frames > 2052
1228 * you better get the MTU right!
1231 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1233 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1234 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1237 /* Tell chip about available buffers */
1238 sky2_rx_update(sky2, rxq);
1241 sky2_rx_clean(sky2);
1245 /* Bring up network interface. */
1246 static int sky2_up(struct net_device *dev)
1248 struct sky2_port *sky2 = netdev_priv(dev);
1249 struct sky2_hw *hw = sky2->hw;
1250 unsigned port = sky2->port;
1252 int cap, err = -ENOMEM;
1253 struct net_device *otherdev = hw->dev[sky2->port^1];
1256 * On dual port PCI-X card, there is an problem where status
1257 * can be received out of order due to split transactions
1259 if (otherdev && netif_running(otherdev) &&
1260 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1261 struct sky2_port *osky2 = netdev_priv(otherdev);
1264 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1265 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1266 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1272 if (netif_msg_ifup(sky2))
1273 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1275 netif_carrier_off(dev);
1277 /* must be power of 2 */
1278 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1280 sizeof(struct sky2_tx_le),
1285 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1289 sky2->tx_prod = sky2->tx_cons = 0;
1291 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1295 memset(sky2->rx_le, 0, RX_LE_BYTES);
1297 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1302 sky2_phy_power(hw, port, 1);
1304 sky2_mac_init(hw, port);
1306 /* Register is number of 4K blocks on internal RAM buffer. */
1307 ramsize = sky2_read8(hw, B2_E_0) * 4;
1308 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1314 rxspace = ramsize / 2;
1316 rxspace = 8 + (2*(ramsize - 16))/3;
1318 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1319 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1321 /* Make sure SyncQ is disabled */
1322 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1326 sky2_qset(hw, txqaddr[port]);
1328 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1329 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1330 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1332 /* Set almost empty threshold */
1333 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1334 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1335 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1337 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1340 err = sky2_rx_start(sky2);
1344 /* Enable interrupts from phy/mac for port */
1345 imask = sky2_read32(hw, B0_IMSK);
1346 imask |= portirq_msk[port];
1347 sky2_write32(hw, B0_IMSK, imask);
1353 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1354 sky2->rx_le, sky2->rx_le_map);
1358 pci_free_consistent(hw->pdev,
1359 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1360 sky2->tx_le, sky2->tx_le_map);
1363 kfree(sky2->tx_ring);
1364 kfree(sky2->rx_ring);
1366 sky2->tx_ring = NULL;
1367 sky2->rx_ring = NULL;
1371 /* Modular subtraction in ring */
1372 static inline int tx_dist(unsigned tail, unsigned head)
1374 return (head - tail) & (TX_RING_SIZE - 1);
1377 /* Number of list elements available for next tx */
1378 static inline int tx_avail(const struct sky2_port *sky2)
1380 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1383 /* Estimate of number of transmit list elements required */
1384 static unsigned tx_le_req(const struct sk_buff *skb)
1388 count = sizeof(dma_addr_t) / sizeof(u32);
1389 count += skb_shinfo(skb)->nr_frags * count;
1391 if (skb_is_gso(skb))
1394 if (skb->ip_summed == CHECKSUM_PARTIAL)
1401 * Put one packet in ring for transmit.
1402 * A single packet can generate multiple list elements, and
1403 * the number of ring elements will probably be less than the number
1404 * of list elements used.
1406 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1408 struct sky2_port *sky2 = netdev_priv(dev);
1409 struct sky2_hw *hw = sky2->hw;
1410 struct sky2_tx_le *le = NULL;
1411 struct tx_ring_info *re;
1418 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1419 return NETDEV_TX_BUSY;
1421 if (unlikely(netif_msg_tx_queued(sky2)))
1422 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1423 dev->name, sky2->tx_prod, skb->len);
1425 len = skb_headlen(skb);
1426 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1427 addr64 = high32(mapping);
1429 /* Send high bits if changed or crosses boundary */
1430 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1431 le = get_tx_le(sky2);
1432 le->addr = cpu_to_le32(addr64);
1433 le->opcode = OP_ADDR64 | HW_OWNER;
1434 sky2->tx_addr64 = high32(mapping + len);
1437 /* Check for TCP Segmentation Offload */
1438 mss = skb_shinfo(skb)->gso_size;
1440 if (hw->chip_id != CHIP_ID_YUKON_EX)
1441 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1443 if (mss != sky2->tx_last_mss) {
1444 le = get_tx_le(sky2);
1445 le->addr = cpu_to_le32(mss);
1446 if (hw->chip_id == CHIP_ID_YUKON_EX)
1447 le->opcode = OP_MSS | HW_OWNER;
1449 le->opcode = OP_LRGLEN | HW_OWNER;
1450 sky2->tx_last_mss = mss;
1455 #ifdef SKY2_VLAN_TAG_USED
1456 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1457 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1459 le = get_tx_le(sky2);
1461 le->opcode = OP_VLAN|HW_OWNER;
1463 le->opcode |= OP_VLAN;
1464 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1469 /* Handle TCP checksum offload */
1470 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1471 /* On Yukon EX (some versions) encoding change. */
1472 if (hw->chip_id == CHIP_ID_YUKON_EX
1473 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1474 ctrl |= CALSUM; /* auto checksum */
1476 const unsigned offset = skb_transport_offset(skb);
1479 tcpsum = offset << 16; /* sum start */
1480 tcpsum |= offset + skb->csum_offset; /* sum write */
1482 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1483 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1486 if (tcpsum != sky2->tx_tcpsum) {
1487 sky2->tx_tcpsum = tcpsum;
1489 le = get_tx_le(sky2);
1490 le->addr = cpu_to_le32(tcpsum);
1491 le->length = 0; /* initial checksum value */
1492 le->ctrl = 1; /* one packet */
1493 le->opcode = OP_TCPLISW | HW_OWNER;
1498 le = get_tx_le(sky2);
1499 le->addr = cpu_to_le32((u32) mapping);
1500 le->length = cpu_to_le16(len);
1502 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1504 re = tx_le_re(sky2, le);
1506 pci_unmap_addr_set(re, mapaddr, mapping);
1507 pci_unmap_len_set(re, maplen, len);
1509 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1510 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1512 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1513 frag->size, PCI_DMA_TODEVICE);
1514 addr64 = high32(mapping);
1515 if (addr64 != sky2->tx_addr64) {
1516 le = get_tx_le(sky2);
1517 le->addr = cpu_to_le32(addr64);
1519 le->opcode = OP_ADDR64 | HW_OWNER;
1520 sky2->tx_addr64 = addr64;
1523 le = get_tx_le(sky2);
1524 le->addr = cpu_to_le32((u32) mapping);
1525 le->length = cpu_to_le16(frag->size);
1527 le->opcode = OP_BUFFER | HW_OWNER;
1529 re = tx_le_re(sky2, le);
1531 pci_unmap_addr_set(re, mapaddr, mapping);
1532 pci_unmap_len_set(re, maplen, frag->size);
1537 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1538 netif_stop_queue(dev);
1540 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1542 dev->trans_start = jiffies;
1543 return NETDEV_TX_OK;
1547 * Free ring elements from starting at tx_cons until "done"
1549 * NB: the hardware will tell us about partial completion of multi-part
1550 * buffers so make sure not to free skb to early.
1552 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1554 struct net_device *dev = sky2->netdev;
1555 struct pci_dev *pdev = sky2->hw->pdev;
1558 BUG_ON(done >= TX_RING_SIZE);
1560 for (idx = sky2->tx_cons; idx != done;
1561 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1562 struct sky2_tx_le *le = sky2->tx_le + idx;
1563 struct tx_ring_info *re = sky2->tx_ring + idx;
1565 switch(le->opcode & ~HW_OWNER) {
1568 pci_unmap_single(pdev,
1569 pci_unmap_addr(re, mapaddr),
1570 pci_unmap_len(re, maplen),
1574 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1575 pci_unmap_len(re, maplen),
1580 if (le->ctrl & EOP) {
1581 if (unlikely(netif_msg_tx_done(sky2)))
1582 printk(KERN_DEBUG "%s: tx done %u\n",
1585 sky2->net_stats.tx_packets++;
1586 sky2->net_stats.tx_bytes += re->skb->len;
1588 dev_kfree_skb_any(re->skb);
1589 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1593 sky2->tx_cons = idx;
1596 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1597 netif_wake_queue(dev);
1600 /* Cleanup all untransmitted buffers, assume transmitter not running */
1601 static void sky2_tx_clean(struct net_device *dev)
1603 struct sky2_port *sky2 = netdev_priv(dev);
1605 netif_tx_lock_bh(dev);
1606 sky2_tx_complete(sky2, sky2->tx_prod);
1607 netif_tx_unlock_bh(dev);
1610 /* Network shutdown */
1611 static int sky2_down(struct net_device *dev)
1613 struct sky2_port *sky2 = netdev_priv(dev);
1614 struct sky2_hw *hw = sky2->hw;
1615 unsigned port = sky2->port;
1619 /* Never really got started! */
1623 if (netif_msg_ifdown(sky2))
1624 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1626 /* Stop more packets from being queued */
1627 netif_stop_queue(dev);
1629 /* Disable port IRQ */
1630 imask = sky2_read32(hw, B0_IMSK);
1631 imask &= ~portirq_msk[port];
1632 sky2_write32(hw, B0_IMSK, imask);
1634 sky2_gmac_reset(hw, port);
1636 /* Stop transmitter */
1637 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1638 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1640 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1641 RB_RST_SET | RB_DIS_OP_MD);
1643 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1644 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1645 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1647 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1649 /* Workaround shared GMAC reset */
1650 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1651 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1652 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1654 /* Disable Force Sync bit and Enable Alloc bit */
1655 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1656 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1658 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1659 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1660 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1662 /* Reset the PCI FIFO of the async Tx queue */
1663 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1664 BMU_RST_SET | BMU_FIFO_RST);
1666 /* Reset the Tx prefetch units */
1667 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1670 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1674 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1675 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1677 sky2_phy_power(hw, port, 0);
1679 netif_carrier_off(dev);
1681 /* turn off LED's */
1682 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1684 synchronize_irq(hw->pdev->irq);
1687 sky2_rx_clean(sky2);
1689 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1690 sky2->rx_le, sky2->rx_le_map);
1691 kfree(sky2->rx_ring);
1693 pci_free_consistent(hw->pdev,
1694 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1695 sky2->tx_le, sky2->tx_le_map);
1696 kfree(sky2->tx_ring);
1701 sky2->rx_ring = NULL;
1702 sky2->tx_ring = NULL;
1707 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1709 if (!sky2_is_copper(hw))
1712 if (hw->chip_id == CHIP_ID_YUKON_FE)
1713 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1715 switch (aux & PHY_M_PS_SPEED_MSK) {
1716 case PHY_M_PS_SPEED_1000:
1718 case PHY_M_PS_SPEED_100:
1725 static void sky2_link_up(struct sky2_port *sky2)
1727 struct sky2_hw *hw = sky2->hw;
1728 unsigned port = sky2->port;
1730 static const char *fc_name[] = {
1738 reg = gma_read16(hw, port, GM_GP_CTRL);
1739 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1740 gma_write16(hw, port, GM_GP_CTRL, reg);
1742 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1744 netif_carrier_on(sky2->netdev);
1746 /* Turn on link LED */
1747 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1748 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1750 if (hw->chip_id == CHIP_ID_YUKON_XL
1751 || hw->chip_id == CHIP_ID_YUKON_EC_U
1752 || hw->chip_id == CHIP_ID_YUKON_EX) {
1753 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1754 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1756 switch(sky2->speed) {
1758 led |= PHY_M_LEDC_INIT_CTRL(7);
1762 led |= PHY_M_LEDC_STA1_CTRL(7);
1766 led |= PHY_M_LEDC_STA0_CTRL(7);
1770 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1771 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1772 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1775 if (netif_msg_link(sky2))
1776 printk(KERN_INFO PFX
1777 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1778 sky2->netdev->name, sky2->speed,
1779 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1780 fc_name[sky2->flow_status]);
1783 static void sky2_link_down(struct sky2_port *sky2)
1785 struct sky2_hw *hw = sky2->hw;
1786 unsigned port = sky2->port;
1789 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1791 reg = gma_read16(hw, port, GM_GP_CTRL);
1792 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1793 gma_write16(hw, port, GM_GP_CTRL, reg);
1795 netif_carrier_off(sky2->netdev);
1797 /* Turn on link LED */
1798 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1800 if (netif_msg_link(sky2))
1801 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1803 sky2_phy_init(hw, port);
1806 static enum flow_control sky2_flow(int rx, int tx)
1809 return tx ? FC_BOTH : FC_RX;
1811 return tx ? FC_TX : FC_NONE;
1814 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1816 struct sky2_hw *hw = sky2->hw;
1817 unsigned port = sky2->port;
1820 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1821 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1822 if (lpa & PHY_M_AN_RF) {
1823 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1827 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1828 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1829 sky2->netdev->name);
1833 sky2->speed = sky2_phy_speed(hw, aux);
1834 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1836 /* Since the pause result bits seem to in different positions on
1837 * different chips. look at registers.
1839 if (!sky2_is_copper(hw)) {
1840 /* Shift for bits in fiber PHY */
1841 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1842 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1844 if (advert & ADVERTISE_1000XPAUSE)
1845 advert |= ADVERTISE_PAUSE_CAP;
1846 if (advert & ADVERTISE_1000XPSE_ASYM)
1847 advert |= ADVERTISE_PAUSE_ASYM;
1848 if (lpa & LPA_1000XPAUSE)
1849 lpa |= LPA_PAUSE_CAP;
1850 if (lpa & LPA_1000XPAUSE_ASYM)
1851 lpa |= LPA_PAUSE_ASYM;
1854 sky2->flow_status = FC_NONE;
1855 if (advert & ADVERTISE_PAUSE_CAP) {
1856 if (lpa & LPA_PAUSE_CAP)
1857 sky2->flow_status = FC_BOTH;
1858 else if (advert & ADVERTISE_PAUSE_ASYM)
1859 sky2->flow_status = FC_RX;
1860 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1861 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1862 sky2->flow_status = FC_TX;
1865 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1866 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1867 sky2->flow_status = FC_NONE;
1869 if (sky2->flow_status & FC_TX)
1870 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1872 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1877 /* Interrupt from PHY */
1878 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1880 struct net_device *dev = hw->dev[port];
1881 struct sky2_port *sky2 = netdev_priv(dev);
1882 u16 istatus, phystat;
1884 if (!netif_running(dev))
1887 spin_lock(&sky2->phy_lock);
1888 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1889 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1891 if (netif_msg_intr(sky2))
1892 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1893 sky2->netdev->name, istatus, phystat);
1895 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1896 if (sky2_autoneg_done(sky2, phystat) == 0)
1901 if (istatus & PHY_M_IS_LSP_CHANGE)
1902 sky2->speed = sky2_phy_speed(hw, phystat);
1904 if (istatus & PHY_M_IS_DUP_CHANGE)
1906 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1908 if (istatus & PHY_M_IS_LST_CHANGE) {
1909 if (phystat & PHY_M_PS_LINK_UP)
1912 sky2_link_down(sky2);
1915 spin_unlock(&sky2->phy_lock);
1918 /* Transmit timeout is only called if we are running, carrier is up
1919 * and tx queue is full (stopped).
1921 static void sky2_tx_timeout(struct net_device *dev)
1923 struct sky2_port *sky2 = netdev_priv(dev);
1924 struct sky2_hw *hw = sky2->hw;
1926 if (netif_msg_timer(sky2))
1927 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1929 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1930 dev->name, sky2->tx_cons, sky2->tx_prod,
1931 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1932 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1934 /* can't restart safely under softirq */
1935 schedule_work(&hw->restart_work);
1938 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1940 struct sky2_port *sky2 = netdev_priv(dev);
1941 struct sky2_hw *hw = sky2->hw;
1942 unsigned port = sky2->port;
1947 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1950 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1953 if (!netif_running(dev)) {
1958 imask = sky2_read32(hw, B0_IMSK);
1959 sky2_write32(hw, B0_IMSK, 0);
1961 dev->trans_start = jiffies; /* prevent tx timeout */
1962 netif_stop_queue(dev);
1963 netif_poll_disable(hw->dev[0]);
1965 synchronize_irq(hw->pdev->irq);
1967 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1968 sky2_set_tx_stfwd(hw, port);
1970 ctl = gma_read16(hw, port, GM_GP_CTRL);
1971 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1973 sky2_rx_clean(sky2);
1977 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1978 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1980 if (dev->mtu > ETH_DATA_LEN)
1981 mode |= GM_SMOD_JUMBO_ENA;
1983 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1985 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1987 err = sky2_rx_start(sky2);
1988 sky2_write32(hw, B0_IMSK, imask);
1993 gma_write16(hw, port, GM_GP_CTRL, ctl);
1995 netif_poll_enable(hw->dev[0]);
1996 netif_wake_queue(dev);
2002 /* For small just reuse existing skb for next receive */
2003 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2004 const struct rx_ring_info *re,
2007 struct sk_buff *skb;
2009 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2011 skb_reserve(skb, 2);
2012 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2013 length, PCI_DMA_FROMDEVICE);
2014 skb_copy_from_linear_data(re->skb, skb->data, length);
2015 skb->ip_summed = re->skb->ip_summed;
2016 skb->csum = re->skb->csum;
2017 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2018 length, PCI_DMA_FROMDEVICE);
2019 re->skb->ip_summed = CHECKSUM_NONE;
2020 skb_put(skb, length);
2025 /* Adjust length of skb with fragments to match received data */
2026 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2027 unsigned int length)
2032 /* put header into skb */
2033 size = min(length, hdr_space);
2038 num_frags = skb_shinfo(skb)->nr_frags;
2039 for (i = 0; i < num_frags; i++) {
2040 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2043 /* don't need this page */
2044 __free_page(frag->page);
2045 --skb_shinfo(skb)->nr_frags;
2047 size = min(length, (unsigned) PAGE_SIZE);
2050 skb->data_len += size;
2051 skb->truesize += size;
2058 /* Normal packet - take skb from ring element and put in a new one */
2059 static struct sk_buff *receive_new(struct sky2_port *sky2,
2060 struct rx_ring_info *re,
2061 unsigned int length)
2063 struct sk_buff *skb, *nskb;
2064 unsigned hdr_space = sky2->rx_data_size;
2066 pr_debug(PFX "receive new length=%d\n", length);
2068 /* Don't be tricky about reusing pages (yet) */
2069 nskb = sky2_rx_alloc(sky2);
2070 if (unlikely(!nskb))
2074 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2076 prefetch(skb->data);
2078 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2080 if (skb_shinfo(skb)->nr_frags)
2081 skb_put_frags(skb, hdr_space, length);
2083 skb_put(skb, length);
2088 * Receive one packet.
2089 * For larger packets, get new buffer.
2091 static struct sk_buff *sky2_receive(struct net_device *dev,
2092 u16 length, u32 status)
2094 struct sky2_port *sky2 = netdev_priv(dev);
2095 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2096 struct sk_buff *skb = NULL;
2098 if (unlikely(netif_msg_rx_status(sky2)))
2099 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2100 dev->name, sky2->rx_next, status, length);
2102 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2103 prefetch(sky2->rx_ring + sky2->rx_next);
2105 if (status & GMR_FS_ANY_ERR)
2108 if (!(status & GMR_FS_RX_OK))
2111 if (status >> 16 != length)
2114 if (length < copybreak)
2115 skb = receive_copy(sky2, re, length);
2117 skb = receive_new(sky2, re, length);
2119 sky2_rx_submit(sky2, re);
2124 /* Truncation of overlength packets
2125 causes PHY length to not match MAC length */
2126 ++sky2->net_stats.rx_length_errors;
2129 ++sky2->net_stats.rx_errors;
2130 if (status & GMR_FS_RX_FF_OV) {
2131 sky2->net_stats.rx_over_errors++;
2135 if (netif_msg_rx_err(sky2) && net_ratelimit())
2136 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2137 dev->name, status, length);
2139 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2140 sky2->net_stats.rx_length_errors++;
2141 if (status & GMR_FS_FRAGMENT)
2142 sky2->net_stats.rx_frame_errors++;
2143 if (status & GMR_FS_CRC_ERR)
2144 sky2->net_stats.rx_crc_errors++;
2149 /* Transmit complete */
2150 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2152 struct sky2_port *sky2 = netdev_priv(dev);
2154 if (netif_running(dev)) {
2156 sky2_tx_complete(sky2, last);
2157 netif_tx_unlock(dev);
2161 /* Process status response ring */
2162 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2165 unsigned rx[2] = { 0, 0 };
2166 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2170 while (hw->st_idx != hwidx) {
2171 struct sky2_port *sky2;
2172 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2173 unsigned port = le->css & CSS_LINK_BIT;
2174 struct net_device *dev;
2175 struct sk_buff *skb;
2179 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2181 dev = hw->dev[port];
2182 sky2 = netdev_priv(dev);
2183 length = le16_to_cpu(le->length);
2184 status = le32_to_cpu(le->status);
2186 switch (le->opcode & ~HW_OWNER) {
2189 skb = sky2_receive(dev, length, status);
2190 if (unlikely(!skb)) {
2191 sky2->net_stats.rx_dropped++;
2195 /* This chip reports checksum status differently */
2196 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2197 if (sky2->rx_csum &&
2198 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2199 (le->css & CSS_TCPUDPCSOK))
2200 skb->ip_summed = CHECKSUM_UNNECESSARY;
2202 skb->ip_summed = CHECKSUM_NONE;
2205 skb->protocol = eth_type_trans(skb, dev);
2206 sky2->net_stats.rx_packets++;
2207 sky2->net_stats.rx_bytes += skb->len;
2208 dev->last_rx = jiffies;
2210 #ifdef SKY2_VLAN_TAG_USED
2211 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2212 vlan_hwaccel_receive_skb(skb,
2214 be16_to_cpu(sky2->rx_tag));
2217 netif_receive_skb(skb);
2219 /* Stop after net poll weight */
2220 if (++work_done >= to_do)
2224 #ifdef SKY2_VLAN_TAG_USED
2226 sky2->rx_tag = length;
2230 sky2->rx_tag = length;
2237 if (hw->chip_id == CHIP_ID_YUKON_EX)
2240 /* Both checksum counters are programmed to start at
2241 * the same offset, so unless there is a problem they
2242 * should match. This failure is an early indication that
2243 * hardware receive checksumming won't work.
2245 if (likely(status >> 16 == (status & 0xffff))) {
2246 skb = sky2->rx_ring[sky2->rx_next].skb;
2247 skb->ip_summed = CHECKSUM_COMPLETE;
2248 skb->csum = status & 0xffff;
2250 printk(KERN_NOTICE PFX "%s: hardware receive "
2251 "checksum problem (status = %#x)\n",
2254 sky2_write32(sky2->hw,
2255 Q_ADDR(rxqaddr[port], Q_CSR),
2261 /* TX index reports status for both ports */
2262 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2263 sky2_tx_done(hw->dev[0], status & 0xfff);
2265 sky2_tx_done(hw->dev[1],
2266 ((status >> 24) & 0xff)
2267 | (u16)(length & 0xf) << 8);
2271 if (net_ratelimit())
2272 printk(KERN_WARNING PFX
2273 "unknown status opcode 0x%x\n", le->opcode);
2277 /* Fully processed status ring so clear irq */
2278 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2282 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2285 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2290 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2292 struct net_device *dev = hw->dev[port];
2294 if (net_ratelimit())
2295 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2298 if (status & Y2_IS_PAR_RD1) {
2299 if (net_ratelimit())
2300 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2303 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2306 if (status & Y2_IS_PAR_WR1) {
2307 if (net_ratelimit())
2308 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2311 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2314 if (status & Y2_IS_PAR_MAC1) {
2315 if (net_ratelimit())
2316 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2317 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2320 if (status & Y2_IS_PAR_RX1) {
2321 if (net_ratelimit())
2322 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2323 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2326 if (status & Y2_IS_TCP_TXA1) {
2327 if (net_ratelimit())
2328 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2330 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2334 static void sky2_hw_intr(struct sky2_hw *hw)
2336 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2338 if (status & Y2_IS_TIST_OV)
2339 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2341 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2344 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2345 if (net_ratelimit())
2346 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2349 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2350 sky2_pci_write16(hw, PCI_STATUS,
2351 pci_err | PCI_STATUS_ERROR_BITS);
2352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2355 if (status & Y2_IS_PCI_EXP) {
2356 /* PCI-Express uncorrectable Error occurred */
2359 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2361 if (net_ratelimit())
2362 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2365 /* clear the interrupt */
2366 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2367 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2369 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2371 if (pex_err & PEX_FATAL_ERRORS) {
2372 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2373 hwmsk &= ~Y2_IS_PCI_EXP;
2374 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2378 if (status & Y2_HWE_L1_MASK)
2379 sky2_hw_error(hw, 0, status);
2381 if (status & Y2_HWE_L1_MASK)
2382 sky2_hw_error(hw, 1, status);
2385 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2387 struct net_device *dev = hw->dev[port];
2388 struct sky2_port *sky2 = netdev_priv(dev);
2389 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2391 if (netif_msg_intr(sky2))
2392 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2395 if (status & GM_IS_RX_CO_OV)
2396 gma_read16(hw, port, GM_RX_IRQ_SRC);
2398 if (status & GM_IS_TX_CO_OV)
2399 gma_read16(hw, port, GM_TX_IRQ_SRC);
2401 if (status & GM_IS_RX_FF_OR) {
2402 ++sky2->net_stats.rx_fifo_errors;
2403 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2406 if (status & GM_IS_TX_FF_UR) {
2407 ++sky2->net_stats.tx_fifo_errors;
2408 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2412 /* This should never happen it is a bug. */
2413 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2414 u16 q, unsigned ring_size)
2416 struct net_device *dev = hw->dev[port];
2417 struct sky2_port *sky2 = netdev_priv(dev);
2419 const u64 *le = (q == Q_R1 || q == Q_R2)
2420 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2422 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2423 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2424 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2425 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2427 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2430 /* If idle then force a fake soft NAPI poll once a second
2431 * to work around cases where sharing an edge triggered interrupt.
2433 static inline void sky2_idle_start(struct sky2_hw *hw)
2435 if (idle_timeout > 0)
2436 mod_timer(&hw->idle_timer,
2437 jiffies + msecs_to_jiffies(idle_timeout));
2440 static void sky2_idle(unsigned long arg)
2442 struct sky2_hw *hw = (struct sky2_hw *) arg;
2443 struct net_device *dev = hw->dev[0];
2445 if (__netif_rx_schedule_prep(dev))
2446 __netif_rx_schedule(dev);
2448 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2451 /* Hardware/software error handling */
2452 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2454 if (net_ratelimit())
2455 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2457 if (status & Y2_IS_HW_ERR)
2460 if (status & Y2_IS_IRQ_MAC1)
2461 sky2_mac_intr(hw, 0);
2463 if (status & Y2_IS_IRQ_MAC2)
2464 sky2_mac_intr(hw, 1);
2466 if (status & Y2_IS_CHK_RX1)
2467 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2469 if (status & Y2_IS_CHK_RX2)
2470 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2472 if (status & Y2_IS_CHK_TXA1)
2473 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2475 if (status & Y2_IS_CHK_TXA2)
2476 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2479 static int sky2_poll(struct net_device *dev0, int *budget)
2481 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2483 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2485 if (unlikely(status & Y2_IS_ERROR))
2486 sky2_err_intr(hw, status);
2488 if (status & Y2_IS_IRQ_PHY1)
2489 sky2_phy_intr(hw, 0);
2491 if (status & Y2_IS_IRQ_PHY2)
2492 sky2_phy_intr(hw, 1);
2494 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2495 *budget -= work_done;
2496 dev0->quota -= work_done;
2499 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
2502 /* Bug/Errata workaround?
2503 * Need to kick the TX irq moderation timer.
2505 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2506 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2507 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2509 netif_rx_complete(dev0);
2511 sky2_read32(hw, B0_Y2_SP_LISR);
2515 static irqreturn_t sky2_intr(int irq, void *dev_id)
2517 struct sky2_hw *hw = dev_id;
2518 struct net_device *dev0 = hw->dev[0];
2521 /* Reading this mask interrupts as side effect */
2522 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2523 if (status == 0 || status == ~0)
2526 prefetch(&hw->st_le[hw->st_idx]);
2527 if (likely(__netif_rx_schedule_prep(dev0)))
2528 __netif_rx_schedule(dev0);
2533 #ifdef CONFIG_NET_POLL_CONTROLLER
2534 static void sky2_netpoll(struct net_device *dev)
2536 struct sky2_port *sky2 = netdev_priv(dev);
2537 struct net_device *dev0 = sky2->hw->dev[0];
2539 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2540 __netif_rx_schedule(dev0);
2544 /* Chip internal frequency for clock calculations */
2545 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2547 switch (hw->chip_id) {
2548 case CHIP_ID_YUKON_EC:
2549 case CHIP_ID_YUKON_EC_U:
2550 case CHIP_ID_YUKON_EX:
2551 return 125; /* 125 Mhz */
2552 case CHIP_ID_YUKON_FE:
2553 return 100; /* 100 Mhz */
2554 default: /* YUKON_XL */
2555 return 156; /* 156 Mhz */
2559 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2561 return sky2_mhz(hw) * us;
2564 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2566 return clk / sky2_mhz(hw);
2570 static int __devinit sky2_init(struct sky2_hw *hw)
2574 /* Enable all clocks */
2575 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2577 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2579 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2580 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2581 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2586 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2588 /* This rev is really old, and requires untested workarounds */
2589 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2590 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2591 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2592 hw->chip_id, hw->chip_rev);
2596 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2598 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2599 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2600 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2607 static void sky2_reset(struct sky2_hw *hw)
2613 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2614 status = sky2_read16(hw, HCU_CCSR);
2615 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2616 HCU_CCSR_UC_STATE_MSK);
2617 sky2_write16(hw, HCU_CCSR, status);
2619 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2620 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2623 sky2_write8(hw, B0_CTST, CS_RST_SET);
2624 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2626 /* clear PCI errors, if any */
2627 status = sky2_pci_read16(hw, PCI_STATUS);
2629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2630 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2633 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2635 /* clear any PEX errors */
2636 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2637 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2642 for (i = 0; i < hw->ports; i++) {
2643 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2644 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2646 if (hw->chip_id == CHIP_ID_YUKON_EX)
2647 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2648 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2652 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2654 /* Clear I2C IRQ noise */
2655 sky2_write32(hw, B2_I2C_IRQ, 1);
2657 /* turn off hardware timer (unused) */
2658 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2659 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2661 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2663 /* Turn off descriptor polling */
2664 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2666 /* Turn off receive timestamp */
2667 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2668 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2670 /* enable the Tx Arbiters */
2671 for (i = 0; i < hw->ports; i++)
2672 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2674 /* Initialize ram interface */
2675 for (i = 0; i < hw->ports; i++) {
2676 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2684 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2685 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2686 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2687 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2688 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2689 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2692 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2694 for (i = 0; i < hw->ports; i++)
2695 sky2_gmac_reset(hw, i);
2697 memset(hw->st_le, 0, STATUS_LE_BYTES);
2700 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2701 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2703 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2704 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2706 /* Set the list last index */
2707 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2709 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2710 sky2_write8(hw, STAT_FIFO_WM, 16);
2712 /* set Status-FIFO ISR watermark */
2713 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2714 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2716 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2718 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2719 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2720 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2722 /* enable status unit */
2723 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2725 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2726 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2727 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2730 static void sky2_restart(struct work_struct *work)
2732 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2733 struct net_device *dev;
2736 dev_dbg(&hw->pdev->dev, "restarting\n");
2738 del_timer_sync(&hw->idle_timer);
2741 sky2_write32(hw, B0_IMSK, 0);
2742 sky2_read32(hw, B0_IMSK);
2744 netif_poll_disable(hw->dev[0]);
2746 for (i = 0; i < hw->ports; i++) {
2748 if (netif_running(dev))
2753 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2754 netif_poll_enable(hw->dev[0]);
2756 for (i = 0; i < hw->ports; i++) {
2758 if (netif_running(dev)) {
2761 printk(KERN_INFO PFX "%s: could not restart %d\n",
2768 sky2_idle_start(hw);
2773 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2775 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2778 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2780 const struct sky2_port *sky2 = netdev_priv(dev);
2782 wol->supported = sky2_wol_supported(sky2->hw);
2783 wol->wolopts = sky2->wol;
2786 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2788 struct sky2_port *sky2 = netdev_priv(dev);
2789 struct sky2_hw *hw = sky2->hw;
2791 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2794 sky2->wol = wol->wolopts;
2796 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
2797 sky2_write32(hw, B0_CTST, sky2->wol
2798 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2800 if (!netif_running(dev))
2801 sky2_wol_init(sky2);
2805 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2807 if (sky2_is_copper(hw)) {
2808 u32 modes = SUPPORTED_10baseT_Half
2809 | SUPPORTED_10baseT_Full
2810 | SUPPORTED_100baseT_Half
2811 | SUPPORTED_100baseT_Full
2812 | SUPPORTED_Autoneg | SUPPORTED_TP;
2814 if (hw->chip_id != CHIP_ID_YUKON_FE)
2815 modes |= SUPPORTED_1000baseT_Half
2816 | SUPPORTED_1000baseT_Full;
2819 return SUPPORTED_1000baseT_Half
2820 | SUPPORTED_1000baseT_Full
2825 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2827 struct sky2_port *sky2 = netdev_priv(dev);
2828 struct sky2_hw *hw = sky2->hw;
2830 ecmd->transceiver = XCVR_INTERNAL;
2831 ecmd->supported = sky2_supported_modes(hw);
2832 ecmd->phy_address = PHY_ADDR_MARV;
2833 if (sky2_is_copper(hw)) {
2834 ecmd->supported = SUPPORTED_10baseT_Half
2835 | SUPPORTED_10baseT_Full
2836 | SUPPORTED_100baseT_Half
2837 | SUPPORTED_100baseT_Full
2838 | SUPPORTED_1000baseT_Half
2839 | SUPPORTED_1000baseT_Full
2840 | SUPPORTED_Autoneg | SUPPORTED_TP;
2841 ecmd->port = PORT_TP;
2842 ecmd->speed = sky2->speed;
2844 ecmd->speed = SPEED_1000;
2845 ecmd->port = PORT_FIBRE;
2848 ecmd->advertising = sky2->advertising;
2849 ecmd->autoneg = sky2->autoneg;
2850 ecmd->duplex = sky2->duplex;
2854 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2856 struct sky2_port *sky2 = netdev_priv(dev);
2857 const struct sky2_hw *hw = sky2->hw;
2858 u32 supported = sky2_supported_modes(hw);
2860 if (ecmd->autoneg == AUTONEG_ENABLE) {
2861 ecmd->advertising = supported;
2867 switch (ecmd->speed) {
2869 if (ecmd->duplex == DUPLEX_FULL)
2870 setting = SUPPORTED_1000baseT_Full;
2871 else if (ecmd->duplex == DUPLEX_HALF)
2872 setting = SUPPORTED_1000baseT_Half;
2877 if (ecmd->duplex == DUPLEX_FULL)
2878 setting = SUPPORTED_100baseT_Full;
2879 else if (ecmd->duplex == DUPLEX_HALF)
2880 setting = SUPPORTED_100baseT_Half;
2886 if (ecmd->duplex == DUPLEX_FULL)
2887 setting = SUPPORTED_10baseT_Full;
2888 else if (ecmd->duplex == DUPLEX_HALF)
2889 setting = SUPPORTED_10baseT_Half;
2897 if ((setting & supported) == 0)
2900 sky2->speed = ecmd->speed;
2901 sky2->duplex = ecmd->duplex;
2904 sky2->autoneg = ecmd->autoneg;
2905 sky2->advertising = ecmd->advertising;
2907 if (netif_running(dev))
2908 sky2_phy_reinit(sky2);
2913 static void sky2_get_drvinfo(struct net_device *dev,
2914 struct ethtool_drvinfo *info)
2916 struct sky2_port *sky2 = netdev_priv(dev);
2918 strcpy(info->driver, DRV_NAME);
2919 strcpy(info->version, DRV_VERSION);
2920 strcpy(info->fw_version, "N/A");
2921 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2924 static const struct sky2_stat {
2925 char name[ETH_GSTRING_LEN];
2928 { "tx_bytes", GM_TXO_OK_HI },
2929 { "rx_bytes", GM_RXO_OK_HI },
2930 { "tx_broadcast", GM_TXF_BC_OK },
2931 { "rx_broadcast", GM_RXF_BC_OK },
2932 { "tx_multicast", GM_TXF_MC_OK },
2933 { "rx_multicast", GM_RXF_MC_OK },
2934 { "tx_unicast", GM_TXF_UC_OK },
2935 { "rx_unicast", GM_RXF_UC_OK },
2936 { "tx_mac_pause", GM_TXF_MPAUSE },
2937 { "rx_mac_pause", GM_RXF_MPAUSE },
2938 { "collisions", GM_TXF_COL },
2939 { "late_collision",GM_TXF_LAT_COL },
2940 { "aborted", GM_TXF_ABO_COL },
2941 { "single_collisions", GM_TXF_SNG_COL },
2942 { "multi_collisions", GM_TXF_MUL_COL },
2944 { "rx_short", GM_RXF_SHT },
2945 { "rx_runt", GM_RXE_FRAG },
2946 { "rx_64_byte_packets", GM_RXF_64B },
2947 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2948 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2949 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2950 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2951 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2952 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2953 { "rx_too_long", GM_RXF_LNG_ERR },
2954 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2955 { "rx_jabber", GM_RXF_JAB_PKT },
2956 { "rx_fcs_error", GM_RXF_FCS_ERR },
2958 { "tx_64_byte_packets", GM_TXF_64B },
2959 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2960 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2961 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2962 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2963 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2964 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2965 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2968 static u32 sky2_get_rx_csum(struct net_device *dev)
2970 struct sky2_port *sky2 = netdev_priv(dev);
2972 return sky2->rx_csum;
2975 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2977 struct sky2_port *sky2 = netdev_priv(dev);
2979 sky2->rx_csum = data;
2981 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2982 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2987 static u32 sky2_get_msglevel(struct net_device *netdev)
2989 struct sky2_port *sky2 = netdev_priv(netdev);
2990 return sky2->msg_enable;
2993 static int sky2_nway_reset(struct net_device *dev)
2995 struct sky2_port *sky2 = netdev_priv(dev);
2997 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3000 sky2_phy_reinit(sky2);
3005 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3007 struct sky2_hw *hw = sky2->hw;
3008 unsigned port = sky2->port;
3011 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3012 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3013 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3014 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3016 for (i = 2; i < count; i++)
3017 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3020 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3022 struct sky2_port *sky2 = netdev_priv(netdev);
3023 sky2->msg_enable = value;
3026 static int sky2_get_stats_count(struct net_device *dev)
3028 return ARRAY_SIZE(sky2_stats);
3031 static void sky2_get_ethtool_stats(struct net_device *dev,
3032 struct ethtool_stats *stats, u64 * data)
3034 struct sky2_port *sky2 = netdev_priv(dev);
3036 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3039 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3043 switch (stringset) {
3045 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3046 memcpy(data + i * ETH_GSTRING_LEN,
3047 sky2_stats[i].name, ETH_GSTRING_LEN);
3052 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3054 struct sky2_port *sky2 = netdev_priv(dev);
3055 return &sky2->net_stats;
3058 static int sky2_set_mac_address(struct net_device *dev, void *p)
3060 struct sky2_port *sky2 = netdev_priv(dev);
3061 struct sky2_hw *hw = sky2->hw;
3062 unsigned port = sky2->port;
3063 const struct sockaddr *addr = p;
3065 if (!is_valid_ether_addr(addr->sa_data))
3066 return -EADDRNOTAVAIL;
3068 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3069 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3070 dev->dev_addr, ETH_ALEN);
3071 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3072 dev->dev_addr, ETH_ALEN);
3074 /* virtual address for data */
3075 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3077 /* physical address: used for pause frames */
3078 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3083 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3087 bit = ether_crc(ETH_ALEN, addr) & 63;
3088 filter[bit >> 3] |= 1 << (bit & 7);
3091 static void sky2_set_multicast(struct net_device *dev)
3093 struct sky2_port *sky2 = netdev_priv(dev);
3094 struct sky2_hw *hw = sky2->hw;
3095 unsigned port = sky2->port;
3096 struct dev_mc_list *list = dev->mc_list;
3100 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3102 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3103 memset(filter, 0, sizeof(filter));
3105 reg = gma_read16(hw, port, GM_RX_CTRL);
3106 reg |= GM_RXCR_UCF_ENA;
3108 if (dev->flags & IFF_PROMISC) /* promiscuous */
3109 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3110 else if (dev->flags & IFF_ALLMULTI)
3111 memset(filter, 0xff, sizeof(filter));
3112 else if (dev->mc_count == 0 && !rx_pause)
3113 reg &= ~GM_RXCR_MCF_ENA;
3116 reg |= GM_RXCR_MCF_ENA;
3119 sky2_add_filter(filter, pause_mc_addr);
3121 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3122 sky2_add_filter(filter, list->dmi_addr);
3125 gma_write16(hw, port, GM_MC_ADDR_H1,
3126 (u16) filter[0] | ((u16) filter[1] << 8));
3127 gma_write16(hw, port, GM_MC_ADDR_H2,
3128 (u16) filter[2] | ((u16) filter[3] << 8));
3129 gma_write16(hw, port, GM_MC_ADDR_H3,
3130 (u16) filter[4] | ((u16) filter[5] << 8));
3131 gma_write16(hw, port, GM_MC_ADDR_H4,
3132 (u16) filter[6] | ((u16) filter[7] << 8));
3134 gma_write16(hw, port, GM_RX_CTRL, reg);
3137 /* Can have one global because blinking is controlled by
3138 * ethtool and that is always under RTNL mutex
3140 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3144 switch (hw->chip_id) {
3145 case CHIP_ID_YUKON_XL:
3146 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3147 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3148 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3149 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3150 PHY_M_LEDC_INIT_CTRL(7) |
3151 PHY_M_LEDC_STA1_CTRL(7) |
3152 PHY_M_LEDC_STA0_CTRL(7))
3155 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3159 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3160 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3161 on ? PHY_M_LED_ALL : 0);
3165 /* blink LED's for finding board */
3166 static int sky2_phys_id(struct net_device *dev, u32 data)
3168 struct sky2_port *sky2 = netdev_priv(dev);
3169 struct sky2_hw *hw = sky2->hw;
3170 unsigned port = sky2->port;
3171 u16 ledctrl, ledover = 0;
3176 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3177 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3181 /* save initial values */
3182 spin_lock_bh(&sky2->phy_lock);
3183 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3184 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3185 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3186 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3187 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3189 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3190 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3194 while (!interrupted && ms > 0) {
3195 sky2_led(hw, port, onoff);
3198 spin_unlock_bh(&sky2->phy_lock);
3199 interrupted = msleep_interruptible(250);
3200 spin_lock_bh(&sky2->phy_lock);
3205 /* resume regularly scheduled programming */
3206 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3207 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3208 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3209 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3210 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3212 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3213 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3215 spin_unlock_bh(&sky2->phy_lock);
3220 static void sky2_get_pauseparam(struct net_device *dev,
3221 struct ethtool_pauseparam *ecmd)
3223 struct sky2_port *sky2 = netdev_priv(dev);
3225 switch (sky2->flow_mode) {
3227 ecmd->tx_pause = ecmd->rx_pause = 0;
3230 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3233 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3236 ecmd->tx_pause = ecmd->rx_pause = 1;
3239 ecmd->autoneg = sky2->autoneg;
3242 static int sky2_set_pauseparam(struct net_device *dev,
3243 struct ethtool_pauseparam *ecmd)
3245 struct sky2_port *sky2 = netdev_priv(dev);
3247 sky2->autoneg = ecmd->autoneg;
3248 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3250 if (netif_running(dev))
3251 sky2_phy_reinit(sky2);
3256 static int sky2_get_coalesce(struct net_device *dev,
3257 struct ethtool_coalesce *ecmd)
3259 struct sky2_port *sky2 = netdev_priv(dev);
3260 struct sky2_hw *hw = sky2->hw;
3262 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3263 ecmd->tx_coalesce_usecs = 0;
3265 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3266 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3268 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3270 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3271 ecmd->rx_coalesce_usecs = 0;
3273 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3274 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3276 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3278 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3279 ecmd->rx_coalesce_usecs_irq = 0;
3281 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3282 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3285 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3290 /* Note: this affect both ports */
3291 static int sky2_set_coalesce(struct net_device *dev,
3292 struct ethtool_coalesce *ecmd)
3294 struct sky2_port *sky2 = netdev_priv(dev);
3295 struct sky2_hw *hw = sky2->hw;
3296 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3298 if (ecmd->tx_coalesce_usecs > tmax ||
3299 ecmd->rx_coalesce_usecs > tmax ||
3300 ecmd->rx_coalesce_usecs_irq > tmax)
3303 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3305 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3307 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3310 if (ecmd->tx_coalesce_usecs == 0)
3311 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3313 sky2_write32(hw, STAT_TX_TIMER_INI,
3314 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3315 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3317 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3319 if (ecmd->rx_coalesce_usecs == 0)
3320 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3322 sky2_write32(hw, STAT_LEV_TIMER_INI,
3323 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3324 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3326 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3328 if (ecmd->rx_coalesce_usecs_irq == 0)
3329 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3331 sky2_write32(hw, STAT_ISR_TIMER_INI,
3332 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3333 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3335 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3339 static void sky2_get_ringparam(struct net_device *dev,
3340 struct ethtool_ringparam *ering)
3342 struct sky2_port *sky2 = netdev_priv(dev);
3344 ering->rx_max_pending = RX_MAX_PENDING;
3345 ering->rx_mini_max_pending = 0;
3346 ering->rx_jumbo_max_pending = 0;
3347 ering->tx_max_pending = TX_RING_SIZE - 1;
3349 ering->rx_pending = sky2->rx_pending;
3350 ering->rx_mini_pending = 0;
3351 ering->rx_jumbo_pending = 0;
3352 ering->tx_pending = sky2->tx_pending;
3355 static int sky2_set_ringparam(struct net_device *dev,
3356 struct ethtool_ringparam *ering)
3358 struct sky2_port *sky2 = netdev_priv(dev);
3361 if (ering->rx_pending > RX_MAX_PENDING ||
3362 ering->rx_pending < 8 ||
3363 ering->tx_pending < MAX_SKB_TX_LE ||
3364 ering->tx_pending > TX_RING_SIZE - 1)
3367 if (netif_running(dev))
3370 sky2->rx_pending = ering->rx_pending;
3371 sky2->tx_pending = ering->tx_pending;
3373 if (netif_running(dev)) {
3378 sky2_set_multicast(dev);
3384 static int sky2_get_regs_len(struct net_device *dev)
3390 * Returns copy of control register region
3391 * Note: ethtool_get_regs always provides full size (16k) buffer
3393 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3396 const struct sky2_port *sky2 = netdev_priv(dev);
3397 const void __iomem *io = sky2->hw->regs;
3400 memset(p, 0, regs->len);
3402 memcpy_fromio(p, io, B3_RAM_ADDR);
3404 /* skip diagnostic ram region */
3405 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3407 /* copy GMAC registers */
3408 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3409 if (sky2->hw->ports > 1)
3410 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3414 /* In order to do Jumbo packets on these chips, need to turn off the
3415 * transmit store/forward. Therefore checksum offload won't work.
3417 static int no_tx_offload(struct net_device *dev)
3419 const struct sky2_port *sky2 = netdev_priv(dev);
3420 const struct sky2_hw *hw = sky2->hw;
3422 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3425 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3427 if (data && no_tx_offload(dev))
3430 return ethtool_op_set_tx_csum(dev, data);
3434 static int sky2_set_tso(struct net_device *dev, u32 data)
3436 if (data && no_tx_offload(dev))
3439 return ethtool_op_set_tso(dev, data);
3442 static int sky2_get_eeprom_len(struct net_device *dev)
3444 struct sky2_port *sky2 = netdev_priv(dev);
3447 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3448 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3451 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3453 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3455 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3457 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3460 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3462 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3463 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3466 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3469 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3472 struct sky2_port *sky2 = netdev_priv(dev);
3473 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3474 int length = eeprom->len;
3475 u16 offset = eeprom->offset;
3480 eeprom->magic = SKY2_EEPROM_MAGIC;
3482 while (length > 0) {
3483 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3484 int n = min_t(int, length, sizeof(val));
3486 memcpy(data, &val, n);
3494 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3497 struct sky2_port *sky2 = netdev_priv(dev);
3498 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3499 int length = eeprom->len;
3500 u16 offset = eeprom->offset;
3505 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3508 while (length > 0) {
3510 int n = min_t(int, length, sizeof(val));
3512 if (n < sizeof(val))
3513 val = sky2_vpd_read(sky2->hw, cap, offset);
3514 memcpy(&val, data, n);
3516 sky2_vpd_write(sky2->hw, cap, offset, val);
3526 static const struct ethtool_ops sky2_ethtool_ops = {
3527 .get_settings = sky2_get_settings,
3528 .set_settings = sky2_set_settings,
3529 .get_drvinfo = sky2_get_drvinfo,
3530 .get_wol = sky2_get_wol,
3531 .set_wol = sky2_set_wol,
3532 .get_msglevel = sky2_get_msglevel,
3533 .set_msglevel = sky2_set_msglevel,
3534 .nway_reset = sky2_nway_reset,
3535 .get_regs_len = sky2_get_regs_len,
3536 .get_regs = sky2_get_regs,
3537 .get_link = ethtool_op_get_link,
3538 .get_eeprom_len = sky2_get_eeprom_len,
3539 .get_eeprom = sky2_get_eeprom,
3540 .set_eeprom = sky2_set_eeprom,
3541 .get_sg = ethtool_op_get_sg,
3542 .set_sg = ethtool_op_set_sg,
3543 .get_tx_csum = ethtool_op_get_tx_csum,
3544 .set_tx_csum = sky2_set_tx_csum,
3545 .get_tso = ethtool_op_get_tso,
3546 .set_tso = sky2_set_tso,
3547 .get_rx_csum = sky2_get_rx_csum,
3548 .set_rx_csum = sky2_set_rx_csum,
3549 .get_strings = sky2_get_strings,
3550 .get_coalesce = sky2_get_coalesce,
3551 .set_coalesce = sky2_set_coalesce,
3552 .get_ringparam = sky2_get_ringparam,
3553 .set_ringparam = sky2_set_ringparam,
3554 .get_pauseparam = sky2_get_pauseparam,
3555 .set_pauseparam = sky2_set_pauseparam,
3556 .phys_id = sky2_phys_id,
3557 .get_stats_count = sky2_get_stats_count,
3558 .get_ethtool_stats = sky2_get_ethtool_stats,
3559 .get_perm_addr = ethtool_op_get_perm_addr,
3562 #ifdef CONFIG_SKY2_DEBUG
3564 static struct dentry *sky2_debug;
3566 static int sky2_debug_show(struct seq_file *seq, void *v)
3568 struct net_device *dev = seq->private;
3569 const struct sky2_port *sky2 = netdev_priv(dev);
3570 const struct sky2_hw *hw = sky2->hw;
3571 unsigned port = sky2->port;
3575 if (!netif_running(dev))
3578 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3579 sky2_read32(hw, B0_ISRC),
3580 sky2_read32(hw, B0_IMSK),
3581 sky2_read32(hw, B0_Y2_SP_ICR));
3583 netif_poll_disable(hw->dev[0]);
3584 last = sky2_read16(hw, STAT_PUT_IDX);
3586 if (hw->st_idx == last)
3587 seq_puts(seq, "Status ring (empty)\n");
3589 seq_puts(seq, "Status ring\n");
3590 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3591 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3592 const struct sky2_status_le *le = hw->st_le + idx;
3593 seq_printf(seq, "[%d] %#x %d %#x\n",
3594 idx, le->opcode, le->length, le->status);
3596 seq_puts(seq, "\n");
3599 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3600 sky2->tx_cons, sky2->tx_prod,
3601 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3602 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3604 /* Dump contents of tx ring */
3606 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3607 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3608 const struct sky2_tx_le *le = sky2->tx_le + idx;
3609 u32 a = le32_to_cpu(le->addr);
3612 seq_printf(seq, "%u:", idx);
3615 switch(le->opcode & ~HW_OWNER) {
3617 seq_printf(seq, " %#x:", a);
3620 seq_printf(seq, " mtu=%d", a);
3623 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3626 seq_printf(seq, " csum=%#x", a);
3629 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3632 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3635 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3638 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3639 a, le16_to_cpu(le->length));
3642 if (le->ctrl & EOP) {
3643 seq_putc(seq, '\n');
3648 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3649 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3650 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3651 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3653 netif_poll_enable(hw->dev[0]);
3657 static int sky2_debug_open(struct inode *inode, struct file *file)
3659 return single_open(file, sky2_debug_show, inode->i_private);
3662 static const struct file_operations sky2_debug_fops = {
3663 .owner = THIS_MODULE,
3664 .open = sky2_debug_open,
3666 .llseek = seq_lseek,
3667 .release = single_release,
3671 * Use network device events to create/remove/rename
3672 * debugfs file entries
3674 static int sky2_device_event(struct notifier_block *unused,
3675 unsigned long event, void *ptr)
3677 struct net_device *dev = ptr;
3679 if (dev->open == sky2_up) {
3680 struct sky2_port *sky2 = netdev_priv(dev);
3683 case NETDEV_CHANGENAME:
3684 if (!netif_running(dev))
3688 case NETDEV_GOING_DOWN:
3689 if (sky2->debugfs) {
3690 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3692 debugfs_remove(sky2->debugfs);
3693 sky2->debugfs = NULL;
3696 if (event != NETDEV_CHANGENAME)
3698 /* fallthrough for changename */
3702 d = debugfs_create_file(dev->name, S_IRUGO,
3705 if (d == NULL || IS_ERR(d))
3706 printk(KERN_INFO PFX
3707 "%s: debugfs create failed\n",
3719 static struct notifier_block sky2_notifier = {
3720 .notifier_call = sky2_device_event,
3724 static __init void sky2_debug_init(void)
3728 ent = debugfs_create_dir("sky2", NULL);
3729 if (!ent || IS_ERR(ent))
3733 register_netdevice_notifier(&sky2_notifier);
3736 static __exit void sky2_debug_cleanup(void)
3739 unregister_netdevice_notifier(&sky2_notifier);
3740 debugfs_remove(sky2_debug);
3746 #define sky2_debug_init()
3747 #define sky2_debug_cleanup()
3751 /* Initialize network device */
3752 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3754 int highmem, int wol)
3756 struct sky2_port *sky2;
3757 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3760 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3764 SET_MODULE_OWNER(dev);
3765 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3766 dev->irq = hw->pdev->irq;
3767 dev->open = sky2_up;
3768 dev->stop = sky2_down;
3769 dev->do_ioctl = sky2_ioctl;
3770 dev->hard_start_xmit = sky2_xmit_frame;
3771 dev->get_stats = sky2_get_stats;
3772 dev->set_multicast_list = sky2_set_multicast;
3773 dev->set_mac_address = sky2_set_mac_address;
3774 dev->change_mtu = sky2_change_mtu;
3775 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3776 dev->tx_timeout = sky2_tx_timeout;
3777 dev->watchdog_timeo = TX_WATCHDOG;
3779 dev->poll = sky2_poll;
3780 dev->weight = NAPI_WEIGHT;
3781 #ifdef CONFIG_NET_POLL_CONTROLLER
3782 /* Network console (only works on port 0)
3783 * because netpoll makes assumptions about NAPI
3786 dev->poll_controller = sky2_netpoll;
3789 sky2 = netdev_priv(dev);
3792 sky2->msg_enable = netif_msg_init(debug, default_msg);
3794 /* Auto speed and flow control */
3795 sky2->autoneg = AUTONEG_ENABLE;
3796 sky2->flow_mode = FC_BOTH;
3800 sky2->advertising = sky2_supported_modes(hw);
3804 spin_lock_init(&sky2->phy_lock);
3805 sky2->tx_pending = TX_DEF_PENDING;
3806 sky2->rx_pending = RX_DEF_PENDING;
3808 hw->dev[port] = dev;
3812 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3814 dev->features |= NETIF_F_HIGHDMA;
3816 #ifdef SKY2_VLAN_TAG_USED
3817 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3818 dev->vlan_rx_register = sky2_vlan_rx_register;
3821 /* read the mac address */
3822 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3823 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3828 static void __devinit sky2_show_addr(struct net_device *dev)
3830 const struct sky2_port *sky2 = netdev_priv(dev);
3832 if (netif_msg_probe(sky2))
3833 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3835 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3836 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3839 /* Handle software interrupt used during MSI test */
3840 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3842 struct sky2_hw *hw = dev_id;
3843 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3848 if (status & Y2_IS_IRQ_SW) {
3850 wake_up(&hw->msi_wait);
3851 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3853 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3858 /* Test interrupt path by forcing a a software IRQ */
3859 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3861 struct pci_dev *pdev = hw->pdev;
3864 init_waitqueue_head (&hw->msi_wait);
3866 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3868 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3870 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3874 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3875 sky2_read8(hw, B0_CTST);
3877 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3880 /* MSI test failed, go back to INTx mode */
3881 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3882 "switching to INTx mode.\n");
3885 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3888 sky2_write32(hw, B0_IMSK, 0);
3889 sky2_read32(hw, B0_IMSK);
3891 free_irq(pdev->irq, hw);
3896 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3898 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3903 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3905 return value & PCI_PM_CTRL_PME_ENABLE;
3908 static int __devinit sky2_probe(struct pci_dev *pdev,
3909 const struct pci_device_id *ent)
3911 struct net_device *dev;
3913 int err, using_dac = 0, wol_default;
3915 err = pci_enable_device(pdev);
3917 dev_err(&pdev->dev, "cannot enable PCI device\n");
3921 err = pci_request_regions(pdev, DRV_NAME);
3923 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3924 goto err_out_disable;
3927 pci_set_master(pdev);
3929 if (sizeof(dma_addr_t) > sizeof(u32) &&
3930 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3932 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3934 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3935 "for consistent allocations\n");
3936 goto err_out_free_regions;
3939 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3941 dev_err(&pdev->dev, "no usable DMA configuration\n");
3942 goto err_out_free_regions;
3946 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3949 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3951 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3952 goto err_out_free_regions;
3957 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3959 dev_err(&pdev->dev, "cannot map device registers\n");
3960 goto err_out_free_hw;
3964 /* The sk98lin vendor driver uses hardware byte swapping but
3965 * this driver uses software swapping.
3969 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3970 reg &= ~PCI_REV_DESC;
3971 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3975 /* ring for status responses */
3976 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3979 goto err_out_iounmap;
3981 err = sky2_init(hw);
3983 goto err_out_iounmap;
3985 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3986 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3987 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3988 hw->chip_id, hw->chip_rev);
3992 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3995 goto err_out_free_pci;
3998 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3999 err = sky2_test_msi(hw);
4000 if (err == -EOPNOTSUPP)
4001 pci_disable_msi(pdev);
4003 goto err_out_free_netdev;
4006 err = register_netdev(dev);
4008 dev_err(&pdev->dev, "cannot register net device\n");
4009 goto err_out_free_netdev;
4012 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4015 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4016 goto err_out_unregister;
4018 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4020 sky2_show_addr(dev);
4022 if (hw->ports > 1) {
4023 struct net_device *dev1;
4025 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4027 dev_warn(&pdev->dev, "allocation for second device failed\n");
4028 else if ((err = register_netdev(dev1))) {
4029 dev_warn(&pdev->dev,
4030 "register of second port failed (%d)\n", err);
4034 sky2_show_addr(dev1);
4037 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
4038 INIT_WORK(&hw->restart_work, sky2_restart);
4040 sky2_idle_start(hw);
4042 pci_set_drvdata(pdev, hw);
4048 pci_disable_msi(pdev);
4049 unregister_netdev(dev);
4050 err_out_free_netdev:
4053 sky2_write8(hw, B0_CTST, CS_RST_SET);
4054 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4059 err_out_free_regions:
4060 pci_release_regions(pdev);
4062 pci_disable_device(pdev);
4064 pci_set_drvdata(pdev, NULL);
4068 static void __devexit sky2_remove(struct pci_dev *pdev)
4070 struct sky2_hw *hw = pci_get_drvdata(pdev);
4071 struct net_device *dev0, *dev1;
4076 del_timer_sync(&hw->idle_timer);
4078 flush_scheduled_work();
4080 sky2_write32(hw, B0_IMSK, 0);
4081 synchronize_irq(hw->pdev->irq);
4086 unregister_netdev(dev1);
4087 unregister_netdev(dev0);
4091 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4092 sky2_write8(hw, B0_CTST, CS_RST_SET);
4093 sky2_read8(hw, B0_CTST);
4095 free_irq(pdev->irq, hw);
4097 pci_disable_msi(pdev);
4098 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4099 pci_release_regions(pdev);
4100 pci_disable_device(pdev);
4108 pci_set_drvdata(pdev, NULL);
4112 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4114 struct sky2_hw *hw = pci_get_drvdata(pdev);
4120 del_timer_sync(&hw->idle_timer);
4121 netif_poll_disable(hw->dev[0]);
4123 for (i = 0; i < hw->ports; i++) {
4124 struct net_device *dev = hw->dev[i];
4125 struct sky2_port *sky2 = netdev_priv(dev);
4127 if (netif_running(dev))
4131 sky2_wol_init(sky2);
4136 sky2_write32(hw, B0_IMSK, 0);
4139 pci_save_state(pdev);
4140 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4141 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4146 static int sky2_resume(struct pci_dev *pdev)
4148 struct sky2_hw *hw = pci_get_drvdata(pdev);
4154 err = pci_set_power_state(pdev, PCI_D0);
4158 err = pci_restore_state(pdev);
4162 pci_enable_wake(pdev, PCI_D0, 0);
4164 /* Re-enable all clocks */
4165 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4166 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4170 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4172 for (i = 0; i < hw->ports; i++) {
4173 struct net_device *dev = hw->dev[i];
4174 if (netif_running(dev)) {
4177 printk(KERN_ERR PFX "%s: could not up: %d\n",
4185 netif_poll_enable(hw->dev[0]);
4186 sky2_idle_start(hw);
4189 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4190 pci_disable_device(pdev);
4195 static void sky2_shutdown(struct pci_dev *pdev)
4197 struct sky2_hw *hw = pci_get_drvdata(pdev);
4203 del_timer_sync(&hw->idle_timer);
4204 netif_poll_disable(hw->dev[0]);
4206 for (i = 0; i < hw->ports; i++) {
4207 struct net_device *dev = hw->dev[i];
4208 struct sky2_port *sky2 = netdev_priv(dev);
4212 sky2_wol_init(sky2);
4219 pci_enable_wake(pdev, PCI_D3hot, wol);
4220 pci_enable_wake(pdev, PCI_D3cold, wol);
4222 pci_disable_device(pdev);
4223 pci_set_power_state(pdev, PCI_D3hot);
4227 static struct pci_driver sky2_driver = {
4229 .id_table = sky2_id_table,
4230 .probe = sky2_probe,
4231 .remove = __devexit_p(sky2_remove),
4233 .suspend = sky2_suspend,
4234 .resume = sky2_resume,
4236 .shutdown = sky2_shutdown,
4239 static int __init sky2_init_module(void)
4242 return pci_register_driver(&sky2_driver);
4245 static void __exit sky2_cleanup_module(void)
4247 pci_unregister_driver(&sky2_driver);
4248 sky2_debug_cleanup();
4251 module_init(sky2_init_module);
4252 module_exit(sky2_cleanup_module);
4254 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4255 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4256 MODULE_LICENSE("GPL");
4257 MODULE_VERSION(DRV_VERSION);