1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
33 ---------------------------------------------------------------------------*/
39 * Define your architecture specific bus configuration parameters here.
42 #if defined(CONFIG_ARCH_LUBBOCK)
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
58 #elif defined(CONFIG_BFIN)
60 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
62 # if defined (CONFIG_BFIN561_EZKIT)
63 #define SMC_CAN_USE_8BIT 0
64 #define SMC_CAN_USE_16BIT 1
65 #define SMC_CAN_USE_32BIT 1
66 #define SMC_IO_SHIFT 0
68 #define SMC_USE_BFIN_DMA 0
71 #define SMC_inw(a, r) readw((a) + (r))
72 #define SMC_outw(v, a, r) writew(v, (a) + (r))
73 #define SMC_inl(a, r) readl((a) + (r))
74 #define SMC_outl(v, a, r) writel(v, (a) + (r))
75 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
76 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
78 #define SMC_CAN_USE_8BIT 0
79 #define SMC_CAN_USE_16BIT 1
80 #define SMC_CAN_USE_32BIT 0
81 #define SMC_IO_SHIFT 0
83 #define SMC_USE_BFIN_DMA 0
86 #define SMC_inw(a, r) readw((a) + (r))
87 #define SMC_outw(v, a, r) writew(v, (a) + (r))
88 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
89 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
91 /* check if the mac in reg is valid */
92 #define SMC_GET_MAC_ADDR(addr) \
95 __v = SMC_inw(ioaddr, ADDR0_REG); \
96 addr[0] = __v; addr[1] = __v >> 8; \
97 __v = SMC_inw(ioaddr, ADDR1_REG); \
98 addr[2] = __v; addr[3] = __v >> 8; \
99 __v = SMC_inw(ioaddr, ADDR2_REG); \
100 addr[4] = __v; addr[5] = __v >> 8; \
101 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
102 random_ether_addr(addr); \
105 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
107 /* We can only do 16-bit reads and writes in the static memory space. */
108 #define SMC_CAN_USE_8BIT 0
109 #define SMC_CAN_USE_16BIT 1
110 #define SMC_CAN_USE_32BIT 0
113 #define SMC_IO_SHIFT 0
115 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
116 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
117 #define SMC_insw(a, r, p, l) \
119 unsigned long __port = (a) + (r); \
120 u16 *__p = (u16 *)(p); \
122 insw(__port, __p, __l); \
124 *__p = swab16(*__p); \
129 #define SMC_outsw(a, r, p, l) \
131 unsigned long __port = (a) + (r); \
132 u16 *__p = (u16 *)(p); \
135 /* Believe it or not, the swab isn't needed. */ \
136 outw( /* swab16 */ (*__p++), __port); \
140 #define SMC_IRQ_FLAGS (0)
142 #elif defined(CONFIG_SA1100_PLEB)
143 /* We can only do 16-bit reads and writes in the static memory space. */
144 #define SMC_CAN_USE_8BIT 1
145 #define SMC_CAN_USE_16BIT 1
146 #define SMC_CAN_USE_32BIT 0
147 #define SMC_IO_SHIFT 0
150 #define SMC_inb(a, r) readb((a) + (r))
151 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
152 #define SMC_inw(a, r) readw((a) + (r))
153 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
154 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
155 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
156 #define SMC_outw(v, a, r) writew(v, (a) + (r))
157 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
159 #define SMC_IRQ_FLAGS (0)
161 #elif defined(CONFIG_SA1100_ASSABET)
163 #include <asm/arch/neponset.h>
165 /* We can only do 8-bit reads and writes in the static memory space. */
166 #define SMC_CAN_USE_8BIT 1
167 #define SMC_CAN_USE_16BIT 0
168 #define SMC_CAN_USE_32BIT 0
171 /* The first two address lines aren't connected... */
172 #define SMC_IO_SHIFT 2
174 #define SMC_inb(a, r) readb((a) + (r))
175 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
176 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
177 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
179 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
181 #define SMC_CAN_USE_8BIT 0
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 0
184 #define SMC_IO_SHIFT 0
187 #define SMC_inw(a, r) readw((a) + (r))
188 #define SMC_outw(v, a, r) writew(v, (a) + (r))
189 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
190 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
192 #elif defined(CONFIG_ARCH_INNOKOM) || \
193 defined(CONFIG_MACH_MAINSTONE) || \
194 defined(CONFIG_ARCH_PXA_IDP) || \
195 defined(CONFIG_ARCH_RAMSES)
197 #define SMC_CAN_USE_8BIT 1
198 #define SMC_CAN_USE_16BIT 1
199 #define SMC_CAN_USE_32BIT 1
200 #define SMC_IO_SHIFT 0
202 #define SMC_USE_PXA_DMA 1
204 #define SMC_inb(a, r) readb((a) + (r))
205 #define SMC_inw(a, r) readw((a) + (r))
206 #define SMC_inl(a, r) readl((a) + (r))
207 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
208 #define SMC_outl(v, a, r) writel(v, (a) + (r))
209 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
210 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
212 /* We actually can't write halfwords properly if not word aligned */
214 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
217 unsigned int v = val << 16;
218 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
219 writel(v, ioaddr + (reg & ~2));
221 writew(val, ioaddr + reg);
225 #elif defined(CONFIG_ARCH_OMAP)
227 /* We can only do 16-bit reads and writes in the static memory space. */
228 #define SMC_CAN_USE_8BIT 0
229 #define SMC_CAN_USE_16BIT 1
230 #define SMC_CAN_USE_32BIT 0
231 #define SMC_IO_SHIFT 0
234 #define SMC_inw(a, r) readw((a) + (r))
235 #define SMC_outw(v, a, r) writew(v, (a) + (r))
236 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
237 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
239 #include <asm/mach-types.h>
240 #include <asm/arch/cpu.h>
242 #ifdef CONFIG_ARCH_OMAP1
243 #define SMC_IRQ_FLAGS ((machine_is_omap_innovator() || \
244 machine_is_omap_osk()) \
245 ? IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING)
247 #define SMC_IRQ_FLAGS (machine_is_omap_apollon() \
248 ? IRQF_TRIGGER_RISING : IRQF_TRIGGER_LOW)
251 #elif defined(CONFIG_SH_SH4202_MICRODEV)
253 #define SMC_CAN_USE_8BIT 0
254 #define SMC_CAN_USE_16BIT 1
255 #define SMC_CAN_USE_32BIT 0
257 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
258 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
259 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
260 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
261 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
262 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
263 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
264 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
265 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
266 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
268 #define SMC_IRQ_FLAGS (0)
270 #elif defined(CONFIG_ISA)
272 #define SMC_CAN_USE_8BIT 1
273 #define SMC_CAN_USE_16BIT 1
274 #define SMC_CAN_USE_32BIT 0
276 #define SMC_inb(a, r) inb((a) + (r))
277 #define SMC_inw(a, r) inw((a) + (r))
278 #define SMC_outb(v, a, r) outb(v, (a) + (r))
279 #define SMC_outw(v, a, r) outw(v, (a) + (r))
280 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
281 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
283 #elif defined(CONFIG_M32R)
285 #define SMC_CAN_USE_8BIT 0
286 #define SMC_CAN_USE_16BIT 1
287 #define SMC_CAN_USE_32BIT 0
289 #define SMC_inb(a, r) inb(((u32)a) + (r))
290 #define SMC_inw(a, r) inw(((u32)a) + (r))
291 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
292 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
293 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
294 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
296 #define SMC_IRQ_FLAGS (0)
298 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
299 #define RPC_LSB_DEFAULT RPC_LED_100_10
301 #elif defined(CONFIG_MACH_LPD79520) \
302 || defined(CONFIG_MACH_LPD7A400) \
303 || defined(CONFIG_MACH_LPD7A404)
305 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
306 * way that the CPU handles chip selects and the way that the SMC chip
307 * expects the chip select to operate. Refer to
308 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
309 * IOBARRIER is a byte, in order that we read the least-common
310 * denominator. It would be wasteful to read 32 bits from an 8-bit
313 * There is no explicit protection against interrupts intervening
314 * between the writew and the IOBARRIER. In SMC ISR there is a
315 * preamble that performs an IOBARRIER in the extremely unlikely event
316 * that the driver interrupts itself between a writew to the chip an
317 * the IOBARRIER that follows *and* the cache is large enough that the
318 * first off-chip access while handing the interrupt is to the SMC
319 * chip. Other devices in the same address space as the SMC chip must
320 * be aware of the potential for trouble and perform a similar
321 * IOBARRIER on entry to their ISR.
324 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
326 #define SMC_CAN_USE_8BIT 0
327 #define SMC_CAN_USE_16BIT 1
328 #define SMC_CAN_USE_32BIT 0
330 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
332 #define SMC_inw(a,r)\
333 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
334 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
336 #define SMC_insw LPD7_SMC_insw
337 static inline void LPD7_SMC_insw (unsigned char* a, int r,
338 unsigned char* p, int l)
340 unsigned short* ps = (unsigned short*) p;
342 *ps++ = readw (a + r);
347 #define SMC_outsw LPD7_SMC_outsw
348 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
349 unsigned char* p, int l)
351 unsigned short* ps = (unsigned short*) p;
353 writew (*ps++, a + r);
358 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
360 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
361 #define RPC_LSB_DEFAULT RPC_LED_100_10
363 #elif defined(CONFIG_SOC_AU1X00)
367 /* We can only do 16-bit reads and writes in the static memory space. */
368 #define SMC_CAN_USE_8BIT 0
369 #define SMC_CAN_USE_16BIT 1
370 #define SMC_CAN_USE_32BIT 0
371 #define SMC_IO_SHIFT 0
374 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
375 #define SMC_insw(a, r, p, l) \
377 unsigned long _a = (unsigned long)((a) + (r)); \
379 u16 *_p = (u16 *)(p); \
381 *_p++ = au_readw(_a); \
383 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
384 #define SMC_outsw(a, r, p, l) \
386 unsigned long _a = (unsigned long)((a) + (r)); \
388 const u16 *_p = (const u16 *)(p); \
390 au_writew(*_p++ , _a); \
393 #define SMC_IRQ_FLAGS (0)
395 #elif defined(CONFIG_ARCH_VERSATILE)
397 #define SMC_CAN_USE_8BIT 1
398 #define SMC_CAN_USE_16BIT 1
399 #define SMC_CAN_USE_32BIT 1
402 #define SMC_inb(a, r) readb((a) + (r))
403 #define SMC_inw(a, r) readw((a) + (r))
404 #define SMC_inl(a, r) readl((a) + (r))
405 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
406 #define SMC_outw(v, a, r) writew(v, (a) + (r))
407 #define SMC_outl(v, a, r) writel(v, (a) + (r))
408 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
409 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
411 #define SMC_IRQ_FLAGS (0)
415 #define SMC_CAN_USE_8BIT 1
416 #define SMC_CAN_USE_16BIT 1
417 #define SMC_CAN_USE_32BIT 1
420 #define SMC_inb(a, r) readb((a) + (r))
421 #define SMC_inw(a, r) readw((a) + (r))
422 #define SMC_inl(a, r) readl((a) + (r))
423 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
424 #define SMC_outw(v, a, r) writew(v, (a) + (r))
425 #define SMC_outl(v, a, r) writel(v, (a) + (r))
426 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
427 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
429 #define RPC_LSA_DEFAULT RPC_LED_100_10
430 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
434 #ifdef SMC_USE_PXA_DMA
436 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
437 * always happening in irq context so no need to worry about races. TX is
438 * different and probably not worth it for that reason, and not as critical
439 * as RX which can overrun memory and lose packets.
441 #include <linux/dma-mapping.h>
443 #include <asm/arch/pxa-regs.h>
447 #define SMC_insl(a, r, p, l) \
448 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
450 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
451 u_char *buf, int len)
455 /* fallback if no DMA available */
456 if (dma == (unsigned char)-1) {
457 readsl(ioaddr + reg, buf, len);
461 /* 64 bit alignment is required for memory to memory DMA */
463 *((u32 *)buf) = SMC_inl(ioaddr, reg);
469 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
470 DCSR(dma) = DCSR_NODESC;
472 DSADR(dma) = physaddr + reg;
473 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
474 DCMD_WIDTH4 | (DCMD_LENGTH & len));
475 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
476 while (!(DCSR(dma) & DCSR_STOPSTATE))
479 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
485 #define SMC_insw(a, r, p, l) \
486 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
488 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
489 u_char *buf, int len)
493 /* fallback if no DMA available */
494 if (dma == (unsigned char)-1) {
495 readsw(ioaddr + reg, buf, len);
499 /* 64 bit alignment is required for memory to memory DMA */
500 while ((long)buf & 6) {
501 *((u16 *)buf) = SMC_inw(ioaddr, reg);
507 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
508 DCSR(dma) = DCSR_NODESC;
510 DSADR(dma) = physaddr + reg;
511 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
512 DCMD_WIDTH2 | (DCMD_LENGTH & len));
513 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
514 while (!(DCSR(dma) & DCSR_STOPSTATE))
517 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
522 smc_pxa_dma_irq(int dma, void *dummy)
526 #endif /* SMC_USE_PXA_DMA */
530 * Everything a particular hardware setup needs should have been defined
531 * at this point. Add stubs for the undefined cases, mainly to avoid
532 * compilation warnings since they'll be optimized away, or to prevent buggy
536 #if ! SMC_CAN_USE_32BIT
537 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
538 #define SMC_outl(x, ioaddr, reg) BUG()
539 #define SMC_insl(a, r, p, l) BUG()
540 #define SMC_outsl(a, r, p, l) BUG()
543 #if !defined(SMC_insl) || !defined(SMC_outsl)
544 #define SMC_insl(a, r, p, l) BUG()
545 #define SMC_outsl(a, r, p, l) BUG()
548 #if ! SMC_CAN_USE_16BIT
551 * Any 16-bit access is performed with two 8-bit accesses if the hardware
552 * can't do it directly. Most registers are 16-bit so those are mandatory.
554 #define SMC_outw(x, ioaddr, reg) \
556 unsigned int __val16 = (x); \
557 SMC_outb( __val16, ioaddr, reg ); \
558 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
560 #define SMC_inw(ioaddr, reg) \
562 unsigned int __val16; \
563 __val16 = SMC_inb( ioaddr, reg ); \
564 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
568 #define SMC_insw(a, r, p, l) BUG()
569 #define SMC_outsw(a, r, p, l) BUG()
573 #if !defined(SMC_insw) || !defined(SMC_outsw)
574 #define SMC_insw(a, r, p, l) BUG()
575 #define SMC_outsw(a, r, p, l) BUG()
578 #if ! SMC_CAN_USE_8BIT
579 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
580 #define SMC_outb(x, ioaddr, reg) BUG()
581 #define SMC_insb(a, r, p, l) BUG()
582 #define SMC_outsb(a, r, p, l) BUG()
585 #if !defined(SMC_insb) || !defined(SMC_outsb)
586 #define SMC_insb(a, r, p, l) BUG()
587 #define SMC_outsb(a, r, p, l) BUG()
590 #ifndef SMC_CAN_USE_DATACS
591 #define SMC_CAN_USE_DATACS 0
595 #define SMC_IO_SHIFT 0
598 #ifndef SMC_IRQ_FLAGS
599 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
602 #ifndef SMC_INTERRUPT_PREAMBLE
603 #define SMC_INTERRUPT_PREAMBLE
607 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
608 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
609 #define SMC_DATA_EXTENT (4)
612 . Bank Select Register:
614 . yyyy yyyy 0000 00xx
616 . yyyy yyyy = 0x33, for identification purposes.
618 #define BANK_SELECT (14 << SMC_IO_SHIFT)
621 // Transmit Control Register
623 #define TCR_REG SMC_REG(0x0000, 0)
624 #define TCR_ENABLE 0x0001 // When 1 we can transmit
625 #define TCR_LOOP 0x0002 // Controls output pin LBK
626 #define TCR_FORCOL 0x0004 // When 1 will force a collision
627 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
628 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
629 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
630 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
631 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
632 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
633 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
635 #define TCR_CLEAR 0 /* do NOTHING */
636 /* the default settings for the TCR register : */
637 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
640 // EPH Status Register
642 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
643 #define ES_TX_SUC 0x0001 // Last TX was successful
644 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
645 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
646 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
647 #define ES_16COL 0x0010 // 16 Collisions Reached
648 #define ES_SQET 0x0020 // Signal Quality Error Test
649 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
650 #define ES_TXDEFR 0x0080 // Transmit Deferred
651 #define ES_LATCOL 0x0200 // Late collision detected on last tx
652 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
653 #define ES_EXC_DEF 0x0800 // Excessive Deferral
654 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
655 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
656 #define ES_TXUNRN 0x8000 // Tx Underrun
659 // Receive Control Register
661 #define RCR_REG SMC_REG(0x0004, 0)
662 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
663 #define RCR_PRMS 0x0002 // Enable promiscuous mode
664 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
665 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
666 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
667 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
668 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
669 #define RCR_SOFTRST 0x8000 // resets the chip
671 /* the normal settings for the RCR register : */
672 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
673 #define RCR_CLEAR 0x0 // set it to a base state
678 #define COUNTER_REG SMC_REG(0x0006, 0)
681 // Memory Information Register
683 #define MIR_REG SMC_REG(0x0008, 0)
686 // Receive/Phy Control Register
688 #define RPC_REG SMC_REG(0x000A, 0)
689 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
690 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
691 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
692 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
693 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
694 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
695 #define RPC_LED_RES (0x01) // LED = Reserved
696 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
697 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
698 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
699 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
700 #define RPC_LED_TX (0x06) // LED = TX packet occurred
701 #define RPC_LED_RX (0x07) // LED = RX packet occurred
703 #ifndef RPC_LSA_DEFAULT
704 #define RPC_LSA_DEFAULT RPC_LED_100
706 #ifndef RPC_LSB_DEFAULT
707 #define RPC_LSB_DEFAULT RPC_LED_FD
710 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
713 /* Bank 0 0x0C is reserved */
715 // Bank Select Register
717 #define BSR_REG 0x000E
722 #define CONFIG_REG SMC_REG(0x0000, 1)
723 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
724 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
725 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
726 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
728 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
729 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
732 // Base Address Register
734 #define BASE_REG SMC_REG(0x0002, 1)
737 // Individual Address Registers
739 #define ADDR0_REG SMC_REG(0x0004, 1)
740 #define ADDR1_REG SMC_REG(0x0006, 1)
741 #define ADDR2_REG SMC_REG(0x0008, 1)
744 // General Purpose Register
746 #define GP_REG SMC_REG(0x000A, 1)
751 #define CTL_REG SMC_REG(0x000C, 1)
752 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
753 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
754 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
755 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
756 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
757 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
758 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
759 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
762 // MMU Command Register
764 #define MMU_CMD_REG SMC_REG(0x0000, 2)
765 #define MC_BUSY 1 // When 1 the last release has not completed
766 #define MC_NOP (0<<5) // No Op
767 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
768 #define MC_RESET (2<<5) // Reset MMU to initial state
769 #define MC_REMOVE (3<<5) // Remove the current rx packet
770 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
771 #define MC_FREEPKT (5<<5) // Release packet in PNR register
772 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
773 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
776 // Packet Number Register
778 #define PN_REG SMC_REG(0x0002, 2)
781 // Allocation Result Register
783 #define AR_REG SMC_REG(0x0003, 2)
784 #define AR_FAILED 0x80 // Alocation Failed
787 // TX FIFO Ports Register
789 #define TXFIFO_REG SMC_REG(0x0004, 2)
790 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
792 // RX FIFO Ports Register
794 #define RXFIFO_REG SMC_REG(0x0005, 2)
795 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
797 #define FIFO_REG SMC_REG(0x0004, 2)
801 #define PTR_REG SMC_REG(0x0006, 2)
802 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
803 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
804 #define PTR_READ 0x2000 // When 1 the operation is a read
809 #define DATA_REG SMC_REG(0x0008, 2)
812 // Interrupt Status/Acknowledge Register
814 #define INT_REG SMC_REG(0x000C, 2)
817 // Interrupt Mask Register
819 #define IM_REG SMC_REG(0x000D, 2)
820 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
821 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
822 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
823 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
824 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
825 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
826 #define IM_TX_INT 0x02 // Transmit Interrupt
827 #define IM_RCV_INT 0x01 // Receive Interrupt
830 // Multicast Table Registers
832 #define MCAST_REG1 SMC_REG(0x0000, 3)
833 #define MCAST_REG2 SMC_REG(0x0002, 3)
834 #define MCAST_REG3 SMC_REG(0x0004, 3)
835 #define MCAST_REG4 SMC_REG(0x0006, 3)
838 // Management Interface Register (MII)
840 #define MII_REG SMC_REG(0x0008, 3)
841 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
842 #define MII_MDOE 0x0008 // MII Output Enable
843 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
844 #define MII_MDI 0x0002 // MII Input, pin MDI
845 #define MII_MDO 0x0001 // MII Output, pin MDO
850 /* ( hi: chip id low: rev # ) */
851 #define REV_REG SMC_REG(0x000A, 3)
854 // Early RCV Register
856 /* this is NOT on SMC9192 */
857 #define ERCV_REG SMC_REG(0x000C, 3)
858 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
859 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
864 #define EXT_REG SMC_REG(0x0000, 7)
872 #define CHIP_91100FD 8
873 #define CHIP_91111FD 9
875 static const char * chip_ids[ 16 ] = {
877 /* 3 */ "SMC91C90/91C92",
882 /* 8 */ "SMC91C100FD",
883 /* 9 */ "SMC91C11xFD",
889 . Receive status bits
891 #define RS_ALGNERR 0x8000
892 #define RS_BRODCAST 0x4000
893 #define RS_BADCRC 0x2000
894 #define RS_ODDFRAME 0x1000
895 #define RS_TOOLONG 0x0800
896 #define RS_TOOSHORT 0x0400
897 #define RS_MULTICAST 0x0001
898 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
903 * LAN83C183 == LAN91C111 Internal PHY
905 #define PHY_LAN83C183 0x0016f840
906 #define PHY_LAN83C180 0x02821c50
909 * PHY Register Addresses (LAN91C111 Internal PHY)
911 * Generic PHY registers can be found in <linux/mii.h>
913 * These phy registers are specific to our on-board phy.
916 // PHY Configuration Register 1
917 #define PHY_CFG1_REG 0x10
918 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
919 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
920 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
921 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
922 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
923 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
924 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
925 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
926 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
927 #define PHY_CFG1_TLVL_MASK 0x003C
928 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
931 // PHY Configuration Register 2
932 #define PHY_CFG2_REG 0x11
933 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
934 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
935 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
936 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
938 // PHY Status Output (and Interrupt status) Register
939 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
940 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
941 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
942 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
943 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
944 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
945 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
946 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
947 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
948 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
949 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
951 // PHY Interrupt/Status Mask Register
952 #define PHY_MASK_REG 0x13 // Interrupt Mask
953 // Uses the same bit definitions as PHY_INT_REG
957 * SMC91C96 ethernet config and status registers.
958 * These are in the "attribute" space.
961 #define ECOR_RESET 0x80
962 #define ECOR_LEVEL_IRQ 0x40
963 #define ECOR_WR_ATTRIB 0x04
964 #define ECOR_ENABLE 0x01
967 #define ECSR_IOIS8 0x20
968 #define ECSR_PWRDWN 0x04
969 #define ECSR_INT 0x02
971 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
975 * Macros to abstract register access according to the data bus
976 * capabilities. Please use those and not the in/out primitives.
977 * Note: the following macros do *not* select the bank -- this must
978 * be done separately as needed in the main code. The SMC_REG() macro
979 * only uses the bank argument for debugging purposes (when enabled).
981 * Note: despite inline functions being safer, everything leading to this
982 * should preferably be macros to let BUG() display the line number in
983 * the core source code since we're interested in the top call site
984 * not in any inline function location.
988 #define SMC_REG(reg, bank) \
990 int __b = SMC_CURRENT_BANK(); \
991 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
992 printk( "%s: bank reg screwed (0x%04x)\n", \
999 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1003 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1004 * aligned to a 32 bit boundary. I tell you that does exist!
1005 * Fortunately the affected register accesses can be easily worked around
1006 * since we can write zeroes to the preceeding 16 bits without adverse
1007 * effects and use a 32-bit access.
1009 * Enforce it on any 32-bit capable setup for now.
1011 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1013 #define SMC_GET_PN() \
1014 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1015 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1017 #define SMC_SET_PN(x) \
1019 if (SMC_MUST_ALIGN_WRITE) \
1020 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1021 else if (SMC_CAN_USE_8BIT) \
1022 SMC_outb(x, ioaddr, PN_REG); \
1024 SMC_outw(x, ioaddr, PN_REG); \
1027 #define SMC_GET_AR() \
1028 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1029 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1031 #define SMC_GET_TXFIFO() \
1032 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1033 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1035 #define SMC_GET_RXFIFO() \
1036 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1037 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1039 #define SMC_GET_INT() \
1040 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1041 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1043 #define SMC_ACK_INT(x) \
1045 if (SMC_CAN_USE_8BIT) \
1046 SMC_outb(x, ioaddr, INT_REG); \
1048 unsigned long __flags; \
1050 local_irq_save(__flags); \
1051 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1052 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1053 local_irq_restore(__flags); \
1057 #define SMC_GET_INT_MASK() \
1058 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1059 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1061 #define SMC_SET_INT_MASK(x) \
1063 if (SMC_CAN_USE_8BIT) \
1064 SMC_outb(x, ioaddr, IM_REG); \
1066 SMC_outw((x) << 8, ioaddr, INT_REG); \
1069 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1071 #define SMC_SELECT_BANK(x) \
1073 if (SMC_MUST_ALIGN_WRITE) \
1074 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1076 SMC_outw(x, ioaddr, BANK_SELECT); \
1079 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1081 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1083 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1085 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1087 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1089 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1091 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1093 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1095 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1097 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1099 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1101 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1103 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1105 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1107 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1109 #define SMC_SET_PTR(x) \
1111 if (SMC_MUST_ALIGN_WRITE) \
1112 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1114 SMC_outw(x, ioaddr, PTR_REG); \
1117 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1119 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1121 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1123 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1125 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1127 #define SMC_SET_RPC(x) \
1129 if (SMC_MUST_ALIGN_WRITE) \
1130 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1132 SMC_outw(x, ioaddr, RPC_REG); \
1135 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1137 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1139 #ifndef SMC_GET_MAC_ADDR
1140 #define SMC_GET_MAC_ADDR(addr) \
1143 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1144 addr[0] = __v; addr[1] = __v >> 8; \
1145 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1146 addr[2] = __v; addr[3] = __v >> 8; \
1147 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1148 addr[4] = __v; addr[5] = __v >> 8; \
1152 #define SMC_SET_MAC_ADDR(addr) \
1154 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1155 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1156 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1159 #define SMC_SET_MCAST(x) \
1161 const unsigned char *mt = (x); \
1162 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1163 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1164 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1165 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1168 #define SMC_PUT_PKT_HDR(status, length) \
1170 if (SMC_CAN_USE_32BIT) \
1171 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1173 SMC_outw(status, ioaddr, DATA_REG); \
1174 SMC_outw(length, ioaddr, DATA_REG); \
1178 #define SMC_GET_PKT_HDR(status, length) \
1180 if (SMC_CAN_USE_32BIT) { \
1181 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1182 (status) = __val & 0xffff; \
1183 (length) = __val >> 16; \
1185 (status) = SMC_inw(ioaddr, DATA_REG); \
1186 (length) = SMC_inw(ioaddr, DATA_REG); \
1190 #define SMC_PUSH_DATA(p, l) \
1192 if (SMC_CAN_USE_32BIT) { \
1193 void *__ptr = (p); \
1195 void __iomem *__ioaddr = ioaddr; \
1196 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1198 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1201 if (SMC_CAN_USE_DATACS && lp->datacs) \
1202 __ioaddr = lp->datacs; \
1203 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1205 __ptr += (__len & ~3); \
1206 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1208 } else if (SMC_CAN_USE_16BIT) \
1209 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1210 else if (SMC_CAN_USE_8BIT) \
1211 SMC_outsb(ioaddr, DATA_REG, p, l); \
1214 #define SMC_PULL_DATA(p, l) \
1216 if (SMC_CAN_USE_32BIT) { \
1217 void *__ptr = (p); \
1219 void __iomem *__ioaddr = ioaddr; \
1220 if ((unsigned long)__ptr & 2) { \
1222 * We want 32bit alignment here. \
1223 * Since some buses perform a full \
1224 * 32bit fetch even for 16bit data \
1225 * we can't use SMC_inw() here. \
1226 * Back both source (on-chip) and \
1227 * destination pointers of 2 bytes. \
1228 * This is possible since the call to \
1229 * SMC_GET_PKT_HDR() already advanced \
1230 * the source pointer of 4 bytes, and \
1231 * the skb_reserve(skb, 2) advanced \
1232 * the destination pointer of 2 bytes. \
1236 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1238 if (SMC_CAN_USE_DATACS && lp->datacs) \
1239 __ioaddr = lp->datacs; \
1241 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1242 } else if (SMC_CAN_USE_16BIT) \
1243 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1244 else if (SMC_CAN_USE_8BIT) \
1245 SMC_insb(ioaddr, DATA_REG, p, l); \
1248 #endif /* _SMC91X_H_ */