drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43
  44 #include <net/checksum.h>
  45 #include <net/ip.h>
  46
  47 #include <asm/system.h>
  48 #include <asm/io.h>
  49 #include <asm/byteorder.h>
  50 #include <asm/uaccess.h>
  51
  52 #ifdef CONFIG_SPARC
  53 #include <asm/idprom.h>
  54 #include <asm/prom.h>
  55 #endif
  56
  57 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  58 #define TG3_VLAN_TAG_USED 1
  59 #else
  60 #define TG3_VLAN_TAG_USED 0
  61 #endif
  62
  63 #define TG3_TSO_SUPPORT 1
  64
  65 #include "tg3.h"
  66
  67 #define DRV_MODULE_NAME         "tg3"
  68 #define PFX DRV_MODULE_NAME     ": "
  69 #define DRV_MODULE_VERSION      "3.93"
  70 #define DRV_MODULE_RELDATE      "May 22, 2008"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_RING_SIZE                512
 100 #define TG3_DEF_RX_RING_PENDING         200
 101 #define TG3_RX_JUMBO_RING_SIZE          256
 102 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 103
 104 /* Do not place this n-ring entries value into the tp struct itself,
 105  * we really want to expose these constants to GCC so that modulo et
 106  * al.  operations are done with shifts and masks instead of with
 107  * hw multiply/modulo instructions.  Another solution would be to
 108  * replace things like '% foo' with '& (foo - 1)'.
 109  */
 110 #define TG3_RX_RCB_RING_SIZE(tp)        \
 111         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 112
 113 #define TG3_TX_RING_SIZE                512
 114 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 115
 116 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_RING_SIZE)
 118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_JUMBO_RING_SIZE)
 120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 121                                    TG3_RX_RCB_RING_SIZE(tp))
 122 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 123                                  TG3_TX_RING_SIZE)
 124 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 125
 126 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 127 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 128
 129 /* minimum number of free TX descriptors required to wake up TX process */
 130 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 131
 132 /* number of ETHTOOL_GSTATS u64's */
 133 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 134
 135 #define TG3_NUM_TEST            6
 136
 137 static char version[] __devinitdata =
 138         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 139
 140 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 141 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 142 MODULE_LICENSE("GPL");
 143 MODULE_VERSION(DRV_MODULE_VERSION);
 144
 145 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 146 module_param(tg3_debug, int, 0);
 147 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 148
 149 static struct pci_device_id tg3_pci_tbl[] = {
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 216         {}
 217 };
 218
 219 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 220
 221 static const struct {
 222         const char string[ETH_GSTRING_LEN];
 223 } ethtool_stats_keys[TG3_NUM_STATS] = {
 224         { "rx_octets" },
 225         { "rx_fragments" },
 226         { "rx_ucast_packets" },
 227         { "rx_mcast_packets" },
 228         { "rx_bcast_packets" },
 229         { "rx_fcs_errors" },
 230         { "rx_align_errors" },
 231         { "rx_xon_pause_rcvd" },
 232         { "rx_xoff_pause_rcvd" },
 233         { "rx_mac_ctrl_rcvd" },
 234         { "rx_xoff_entered" },
 235         { "rx_frame_too_long_errors" },
 236         { "rx_jabbers" },
 237         { "rx_undersize_packets" },
 238         { "rx_in_length_errors" },
 239         { "rx_out_length_errors" },
 240         { "rx_64_or_less_octet_packets" },
 241         { "rx_65_to_127_octet_packets" },
 242         { "rx_128_to_255_octet_packets" },
 243         { "rx_256_to_511_octet_packets" },
 244         { "rx_512_to_1023_octet_packets" },
 245         { "rx_1024_to_1522_octet_packets" },
 246         { "rx_1523_to_2047_octet_packets" },
 247         { "rx_2048_to_4095_octet_packets" },
 248         { "rx_4096_to_8191_octet_packets" },
 249         { "rx_8192_to_9022_octet_packets" },
 250
 251         { "tx_octets" },
 252         { "tx_collisions" },
 253
 254         { "tx_xon_sent" },
 255         { "tx_xoff_sent" },
 256         { "tx_flow_control" },
 257         { "tx_mac_errors" },
 258         { "tx_single_collisions" },
 259         { "tx_mult_collisions" },
 260         { "tx_deferred" },
 261         { "tx_excessive_collisions" },
 262         { "tx_late_collisions" },
 263         { "tx_collide_2times" },
 264         { "tx_collide_3times" },
 265         { "tx_collide_4times" },
 266         { "tx_collide_5times" },
 267         { "tx_collide_6times" },
 268         { "tx_collide_7times" },
 269         { "tx_collide_8times" },
 270         { "tx_collide_9times" },
 271         { "tx_collide_10times" },
 272         { "tx_collide_11times" },
 273         { "tx_collide_12times" },
 274         { "tx_collide_13times" },
 275         { "tx_collide_14times" },
 276         { "tx_collide_15times" },
 277         { "tx_ucast_packets" },
 278         { "tx_mcast_packets" },
 279         { "tx_bcast_packets" },
 280         { "tx_carrier_sense_errors" },
 281         { "tx_discards" },
 282         { "tx_errors" },
 283
 284         { "dma_writeq_full" },
 285         { "dma_write_prioq_full" },
 286         { "rxbds_empty" },
 287         { "rx_discards" },
 288         { "rx_errors" },
 289         { "rx_threshold_hit" },
 290
 291         { "dma_readq_full" },
 292         { "dma_read_prioq_full" },
 293         { "tx_comp_queue_full" },
 294
 295         { "ring_set_send_prod_index" },
 296         { "ring_status_update" },
 297         { "nic_irqs" },
 298         { "nic_avoided_irqs" },
 299         { "nic_tx_threshold_hit" }
 300 };
 301
 302 static const struct {
 303         const char string[ETH_GSTRING_LEN];
 304 } ethtool_test_keys[TG3_NUM_TEST] = {
 305         { "nvram test     (online) " },
 306         { "link test      (online) " },
 307         { "register test  (offline)" },
 308         { "memory test    (offline)" },
 309         { "loopback test  (offline)" },
 310         { "interrupt test (offline)" },
 311 };
 312
 313 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 314 {
 315         writel(val, tp->regs + off);
 316 }
 317
 318 static u32 tg3_read32(struct tg3 *tp, u32 off)
 319 {
 320         return (readl(tp->regs + off));
 321 }
 322
 323 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 324 {
 325         writel(val, tp->aperegs + off);
 326 }
 327
 328 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 329 {
 330         return (readl(tp->aperegs + off));
 331 }
 332
 333 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 334 {
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&tp->indirect_lock, flags);
 338         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 339         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 340         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 341 }
 342
 343 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         writel(val, tp->regs + off);
 346         readl(tp->regs + off);
 347 }
 348
 349 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 350 {
 351         unsigned long flags;
 352         u32 val;
 353
 354         spin_lock_irqsave(&tp->indirect_lock, flags);
 355         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 356         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 357         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 358         return val;
 359 }
 360
 361 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         unsigned long flags;
 364
 365         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 366                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 367                                        TG3_64BIT_REG_LOW, val);
 368                 return;
 369         }
 370         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 371                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 372                                        TG3_64BIT_REG_LOW, val);
 373                 return;
 374         }
 375
 376         spin_lock_irqsave(&tp->indirect_lock, flags);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 378         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 379         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 380
 381         /* In indirect mode when disabling interrupts, we also need
 382          * to clear the interrupt bit in the GRC local ctrl register.
 383          */
 384         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 385             (val == 0x1)) {
 386                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 387                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 388         }
 389 }
 390
 391 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 392 {
 393         unsigned long flags;
 394         u32 val;
 395
 396         spin_lock_irqsave(&tp->indirect_lock, flags);
 397         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 398         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 399         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 400         return val;
 401 }
 402
 403 /* usec_wait specifies the wait time in usec when writing to certain registers
 404  * where it is unsafe to read back the register without some delay.
 405  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 406  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 407  */
 408 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 409 {
 410         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 411             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 412                 /* Non-posted methods */
 413                 tp->write32(tp, off, val);
 414         else {
 415                 /* Posted method */
 416                 tg3_write32(tp, off, val);
 417                 if (usec_wait)
 418                         udelay(usec_wait);
 419                 tp->read32(tp, off);
 420         }
 421         /* Wait again after the read for the posted method to guarantee that
 422          * the wait time is met.
 423          */
 424         if (usec_wait)
 425                 udelay(usec_wait);
 426 }
 427
 428 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 429 {
 430         tp->write32_mbox(tp, off, val);
 431         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 432             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 433                 tp->read32_mbox(tp, off);
 434 }
 435
 436 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 437 {
 438         void __iomem *mbox = tp->regs + off;
 439         writel(val, mbox);
 440         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 441                 writel(val, mbox);
 442         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 443                 readl(mbox);
 444 }
 445
 446 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 447 {
 448         return (readl(tp->regs + off + GRCMBOX_BASE));
 449 }
 450
 451 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 452 {
 453         writel(val, tp->regs + off + GRCMBOX_BASE);
 454 }
 455
 456 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 457 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 458 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 459 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 460 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 461
 462 #define tw32(reg,val)           tp->write32(tp, reg, val)
 463 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 464 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 465 #define tr32(reg)               tp->read32(tp, reg)
 466
 467 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 468 {
 469         unsigned long flags;
 470
 471         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 472             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 473                 return;
 474
 475         spin_lock_irqsave(&tp->indirect_lock, flags);
 476         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 477                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 478                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 479
 480                 /* Always leave this as zero. */
 481                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 482         } else {
 483                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 484                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 485
 486                 /* Always leave this as zero. */
 487                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 488         }
 489         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 490 }
 491
 492 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 493 {
 494         unsigned long flags;
 495
 496         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 497             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 498                 *val = 0;
 499                 return;
 500         }
 501
 502         spin_lock_irqsave(&tp->indirect_lock, flags);
 503         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 505                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 506
 507                 /* Always leave this as zero. */
 508                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 509         } else {
 510                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 511                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 512
 513                 /* Always leave this as zero. */
 514                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 515         }
 516         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 517 }
 518
 519 static void tg3_ape_lock_init(struct tg3 *tp)
 520 {
 521         int i;
 522
 523         /* Make sure the driver hasn't any stale locks. */
 524         for (i = 0; i < 8; i++)
 525                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 526                                 APE_LOCK_GRANT_DRIVER);
 527 }
 528
 529 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 530 {
 531         int i, off;
 532         int ret = 0;
 533         u32 status;
 534
 535         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 536                 return 0;
 537
 538         switch (locknum) {
 539                 case TG3_APE_LOCK_GRC:
 540                 case TG3_APE_LOCK_MEM:
 541                         break;
 542                 default:
 543                         return -EINVAL;
 544         }
 545
 546         off = 4 * locknum;
 547
 548         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 549
 550         /* Wait for up to 1 millisecond to acquire lock. */
 551         for (i = 0; i < 100; i++) {
 552                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 553                 if (status == APE_LOCK_GRANT_DRIVER)
 554                         break;
 555                 udelay(10);
 556         }
 557
 558         if (status != APE_LOCK_GRANT_DRIVER) {
 559                 /* Revoke the lock request. */
 560                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 561                                 APE_LOCK_GRANT_DRIVER);
 562
 563                 ret = -EBUSY;
 564         }
 565
 566         return ret;
 567 }
 568
 569 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 570 {
 571         int off;
 572
 573         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 574                 return;
 575
 576         switch (locknum) {
 577                 case TG3_APE_LOCK_GRC:
 578                 case TG3_APE_LOCK_MEM:
 579                         break;
 580                 default:
 581                         return;
 582         }
 583
 584         off = 4 * locknum;
 585         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 586 }
 587
 588 static void tg3_disable_ints(struct tg3 *tp)
 589 {
 590         tw32(TG3PCI_MISC_HOST_CTRL,
 591              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 592         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 593 }
 594
 595 static inline void tg3_cond_int(struct tg3 *tp)
 596 {
 597         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 598             (tp->hw_status->status & SD_STATUS_UPDATED))
 599                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 600         else
 601                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 602                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 603 }
 604
 605 static void tg3_enable_ints(struct tg3 *tp)
 606 {
 607         tp->irq_sync = 0;
 608         wmb();
 609
 610         tw32(TG3PCI_MISC_HOST_CTRL,
 611              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 612         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 613                        (tp->last_tag << 24));
 614         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 615                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 616                                (tp->last_tag << 24));
 617         tg3_cond_int(tp);
 618 }
 619
 620 static inline unsigned int tg3_has_work(struct tg3 *tp)
 621 {
 622         struct tg3_hw_status *sblk = tp->hw_status;
 623         unsigned int work_exists = 0;
 624
 625         /* check for phy events */
 626         if (!(tp->tg3_flags &
 627               (TG3_FLAG_USE_LINKCHG_REG |
 628                TG3_FLAG_POLL_SERDES))) {
 629                 if (sblk->status & SD_STATUS_LINK_CHG)
 630                         work_exists = 1;
 631         }
 632         /* check for RX/TX work to do */
 633         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 634             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 635                 work_exists = 1;
 636
 637         return work_exists;
 638 }
 639
 640 /* tg3_restart_ints
 641  *  similar to tg3_enable_ints, but it accurately determines whether there
 642  *  is new work pending and can return without flushing the PIO write
 643  *  which reenables interrupts
 644  */
 645 static void tg3_restart_ints(struct tg3 *tp)
 646 {
 647         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 648                      tp->last_tag << 24);
 649         mmiowb();
 650
 651         /* When doing tagged status, this work check is unnecessary.
 652          * The last_tag we write above tells the chip which piece of
 653          * work we've completed.
 654          */
 655         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 656             tg3_has_work(tp))
 657                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 658                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 659 }
 660
 661 static inline void tg3_netif_stop(struct tg3 *tp)
 662 {
 663         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 664         napi_disable(&tp->napi);
 665         netif_tx_disable(tp->dev);
 666 }
 667
 668 static inline void tg3_netif_start(struct tg3 *tp)
 669 {
 670         netif_wake_queue(tp->dev);
 671         /* NOTE: unconditional netif_wake_queue is only appropriate
 672          * so long as all callers are assured to have free tx slots
 673          * (such as after tg3_init_hw)
 674          */
 675         napi_enable(&tp->napi);
 676         tp->hw_status->status |= SD_STATUS_UPDATED;
 677         tg3_enable_ints(tp);
 678 }
 679
 680 static void tg3_switch_clocks(struct tg3 *tp)
 681 {
 682         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 683         u32 orig_clock_ctrl;
 684
 685         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 686             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 687                 return;
 688
 689         orig_clock_ctrl = clock_ctrl;
 690         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 691                        CLOCK_CTRL_CLKRUN_OENABLE |
 692                        0x1f);
 693         tp->pci_clock_ctrl = clock_ctrl;
 694
 695         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 696                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 697                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 698                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 699                 }
 700         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 701                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 702                             clock_ctrl |
 703                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 704                             40);
 705                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 706                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 707                             40);
 708         }
 709         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 710 }
 711
 712 #define PHY_BUSY_LOOPS  5000
 713
 714 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 715 {
 716         u32 frame_val;
 717         unsigned int loops;
 718         int ret;
 719
 720         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 721                 tw32_f(MAC_MI_MODE,
 722                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 723                 udelay(80);
 724         }
 725
 726         *val = 0x0;
 727
 728         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 729                       MI_COM_PHY_ADDR_MASK);
 730         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 731                       MI_COM_REG_ADDR_MASK);
 732         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 733
 734         tw32_f(MAC_MI_COM, frame_val);
 735
 736         loops = PHY_BUSY_LOOPS;
 737         while (loops != 0) {
 738                 udelay(10);
 739                 frame_val = tr32(MAC_MI_COM);
 740
 741                 if ((frame_val & MI_COM_BUSY) == 0) {
 742                         udelay(5);
 743                         frame_val = tr32(MAC_MI_COM);
 744                         break;
 745                 }
 746                 loops -= 1;
 747         }
 748
 749         ret = -EBUSY;
 750         if (loops != 0) {
 751                 *val = frame_val & MI_COM_DATA_MASK;
 752                 ret = 0;
 753         }
 754
 755         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 756                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 757                 udelay(80);
 758         }
 759
 760         return ret;
 761 }
 762
 763 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 764 {
 765         u32 frame_val;
 766         unsigned int loops;
 767         int ret;
 768
 769         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 770             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 771                 return 0;
 772
 773         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 774                 tw32_f(MAC_MI_MODE,
 775                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 776                 udelay(80);
 777         }
 778
 779         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 780                       MI_COM_PHY_ADDR_MASK);
 781         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 782                       MI_COM_REG_ADDR_MASK);
 783         frame_val |= (val & MI_COM_DATA_MASK);
 784         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 785
 786         tw32_f(MAC_MI_COM, frame_val);
 787
 788         loops = PHY_BUSY_LOOPS;
 789         while (loops != 0) {
 790                 udelay(10);
 791                 frame_val = tr32(MAC_MI_COM);
 792                 if ((frame_val & MI_COM_BUSY) == 0) {
 793                         udelay(5);
 794                         frame_val = tr32(MAC_MI_COM);
 795                         break;
 796                 }
 797                 loops -= 1;
 798         }
 799
 800         ret = -EBUSY;
 801         if (loops != 0)
 802                 ret = 0;
 803
 804         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 805                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 806                 udelay(80);
 807         }
 808
 809         return ret;
 810 }
 811
 812 static int tg3_bmcr_reset(struct tg3 *tp)
 813 {
 814         u32 phy_control;
 815         int limit, err;
 816
 817         /* OK, reset it, and poll the BMCR_RESET bit until it
 818          * clears or we time out.
 819          */
 820         phy_control = BMCR_RESET;
 821         err = tg3_writephy(tp, MII_BMCR, phy_control);
 822         if (err != 0)
 823                 return -EBUSY;
 824
 825         limit = 5000;
 826         while (limit--) {
 827                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 828                 if (err != 0)
 829                         return -EBUSY;
 830
 831                 if ((phy_control & BMCR_RESET) == 0) {
 832                         udelay(40);
 833                         break;
 834                 }
 835                 udelay(10);
 836         }
 837         if (limit <= 0)
 838                 return -EBUSY;
 839
 840         return 0;
 841 }
 842
 843 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 844 {
 845         struct tg3 *tp = (struct tg3 *)bp->priv;
 846         u32 val;
 847
 848         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 849                 return -EAGAIN;
 850
 851         if (tg3_readphy(tp, reg, &val))
 852                 return -EIO;
 853
 854         return val;
 855 }
 856
 857 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 858 {
 859         struct tg3 *tp = (struct tg3 *)bp->priv;
 860
 861         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 862                 return -EAGAIN;
 863
 864         if (tg3_writephy(tp, reg, val))
 865                 return -EIO;
 866
 867         return 0;
 868 }
 869
 870 static int tg3_mdio_reset(struct mii_bus *bp)
 871 {
 872         return 0;
 873 }
 874
 875 static void tg3_mdio_config(struct tg3 *tp)
 876 {
 877         u32 val;
 878
 879         if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
 880             PHY_INTERFACE_MODE_RGMII)
 881                 return;
 882
 883         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
 884                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
 885         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 886                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 887                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 888                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 889                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 890         }
 891         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
 892
 893         val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
 894         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 895                 val |= MAC_PHYCFG2_INBAND_ENABLE;
 896         tw32(MAC_PHYCFG2, val);
 897
 898         val = tr32(MAC_EXT_RGMII_MODE);
 899         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 900                  MAC_RGMII_MODE_RX_QUALITY |
 901                  MAC_RGMII_MODE_RX_ACTIVITY |
 902                  MAC_RGMII_MODE_RX_ENG_DET |
 903                  MAC_RGMII_MODE_TX_ENABLE |
 904                  MAC_RGMII_MODE_TX_LOWPWR |
 905                  MAC_RGMII_MODE_TX_RESET);
 906         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 907                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 908                         val |= MAC_RGMII_MODE_RX_INT_B |
 909                                MAC_RGMII_MODE_RX_QUALITY |
 910                                MAC_RGMII_MODE_RX_ACTIVITY |
 911                                MAC_RGMII_MODE_RX_ENG_DET;
 912                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 913                         val |= MAC_RGMII_MODE_TX_ENABLE |
 914                                MAC_RGMII_MODE_TX_LOWPWR |
 915                                MAC_RGMII_MODE_TX_RESET;
 916         }
 917         tw32(MAC_EXT_RGMII_MODE, val);
 918 }
 919
 920 static void tg3_mdio_start(struct tg3 *tp)
 921 {
 922         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 923                 mutex_lock(&tp->mdio_bus.mdio_lock);
 924                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 925                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 926         }
 927
 928         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 929         tw32_f(MAC_MI_MODE, tp->mi_mode);
 930         udelay(80);
 931
 932         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
 933                 tg3_mdio_config(tp);
 934 }
 935
 936 static void tg3_mdio_stop(struct tg3 *tp)
 937 {
 938         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 939                 mutex_lock(&tp->mdio_bus.mdio_lock);
 940                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 941                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 942         }
 943 }
 944
 945 static int tg3_mdio_init(struct tg3 *tp)
 946 {
 947         int i;
 948         u32 reg;
 949         struct phy_device *phydev;
 950         struct mii_bus *mdio_bus = &tp->mdio_bus;
 951
 952         tg3_mdio_start(tp);
 953
 954         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
 955             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
 956                 return 0;
 957
 958         memset(mdio_bus, 0, sizeof(*mdio_bus));
 959
 960         mdio_bus->name     = "tg3 mdio bus";
 961         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
 962                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
 963         mdio_bus->priv     = tp;
 964         mdio_bus->dev      = &tp->pdev->dev;
 965         mdio_bus->read     = &tg3_mdio_read;
 966         mdio_bus->write    = &tg3_mdio_write;
 967         mdio_bus->reset    = &tg3_mdio_reset;
 968         mdio_bus->phy_mask = ~(1 << PHY_ADDR);
 969         mdio_bus->irq      = &tp->mdio_irq[0];
 970
 971         for (i = 0; i < PHY_MAX_ADDR; i++)
 972                 mdio_bus->irq[i] = PHY_POLL;
 973
 974         /* The bus registration will look for all the PHYs on the mdio bus.
 975          * Unfortunately, it does not ensure the PHY is powered up before
 976          * accessing the PHY ID registers.  A chip reset is the
 977          * quickest way to bring the device back to an operational state..
 978          */
 979         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
 980                 tg3_bmcr_reset(tp);
 981
 982         i = mdiobus_register(mdio_bus);
 983         if (i) {
 984                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
 985                         tp->dev->name, i);
 986                 return i;
 987         }
 988
 989         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
 990
 991         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
 992
 993         switch (phydev->phy_id) {
 994         case TG3_PHY_ID_BCM50610:
 995                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
 997                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
 998                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 999                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1001                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1002                 break;
1003         case TG3_PHY_ID_BCMAC131:
1004                 phydev->interface = PHY_INTERFACE_MODE_MII;
1005                 break;
1006         }
1007
1008         tg3_mdio_config(tp);
1009
1010         return 0;
1011 }
1012
1013 static void tg3_mdio_fini(struct tg3 *tp)
1014 {
1015         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1016                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1017                 mdiobus_unregister(&tp->mdio_bus);
1018                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1019         }
1020 }
1021
1022 /* tp->lock is held. */
1023 static void tg3_wait_for_event_ack(struct tg3 *tp)
1024 {
1025         int i;
1026
1027         /* Wait for up to 2.5 milliseconds */
1028         for (i = 0; i < 250000; i++) {
1029                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1030                         break;
1031                 udelay(10);
1032         }
1033 }
1034
1035 /* tp->lock is held. */
1036 static void tg3_ump_link_report(struct tg3 *tp)
1037 {
1038         u32 reg;
1039         u32 val;
1040
1041         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1042             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1043                 return;
1044
1045         tg3_wait_for_event_ack(tp);
1046
1047         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1048
1049         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1050
1051         val = 0;
1052         if (!tg3_readphy(tp, MII_BMCR, &reg))
1053                 val = reg << 16;
1054         if (!tg3_readphy(tp, MII_BMSR, &reg))
1055                 val |= (reg & 0xffff);
1056         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1057
1058         val = 0;
1059         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1060                 val = reg << 16;
1061         if (!tg3_readphy(tp, MII_LPA, &reg))
1062                 val |= (reg & 0xffff);
1063         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1064
1065         val = 0;
1066         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1067                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1068                         val = reg << 16;
1069                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1070                         val |= (reg & 0xffff);
1071         }
1072         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1073
1074         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1075                 val = reg << 16;
1076         else
1077                 val = 0;
1078         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1079
1080         val = tr32(GRC_RX_CPU_EVENT);
1081         val |= GRC_RX_CPU_DRIVER_EVENT;
1082         tw32_f(GRC_RX_CPU_EVENT, val);
1083 }
1084
1085 static void tg3_link_report(struct tg3 *tp)
1086 {
1087         if (!netif_carrier_ok(tp->dev)) {
1088                 if (netif_msg_link(tp))
1089                         printk(KERN_INFO PFX "%s: Link is down.\n",
1090                                tp->dev->name);
1091                 tg3_ump_link_report(tp);
1092         } else if (netif_msg_link(tp)) {
1093                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1094                        tp->dev->name,
1095                        (tp->link_config.active_speed == SPEED_1000 ?
1096                         1000 :
1097                         (tp->link_config.active_speed == SPEED_100 ?
1098                          100 : 10)),
1099                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1100                         "full" : "half"));
1101
1102                 printk(KERN_INFO PFX
1103                        "%s: Flow control is %s for TX and %s for RX.\n",
1104                        tp->dev->name,
1105                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1106                        "on" : "off",
1107                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1108                        "on" : "off");
1109                 tg3_ump_link_report(tp);
1110         }
1111 }
1112
1113 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1114 {
1115         u16 miireg;
1116
1117         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1118                 miireg = ADVERTISE_PAUSE_CAP;
1119         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1120                 miireg = ADVERTISE_PAUSE_ASYM;
1121         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1122                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1123         else
1124                 miireg = 0;
1125
1126         return miireg;
1127 }
1128
1129 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1130 {
1131         u16 miireg;
1132
1133         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1134                 miireg = ADVERTISE_1000XPAUSE;
1135         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1136                 miireg = ADVERTISE_1000XPSE_ASYM;
1137         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1138                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1139         else
1140                 miireg = 0;
1141
1142         return miireg;
1143 }
1144
1145 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1146 {
1147         u8 cap = 0;
1148
1149         if (lcladv & ADVERTISE_PAUSE_CAP) {
1150                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1151                         if (rmtadv & LPA_PAUSE_CAP)
1152                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1153                         else if (rmtadv & LPA_PAUSE_ASYM)
1154                                 cap = TG3_FLOW_CTRL_RX;
1155                 } else {
1156                         if (rmtadv & LPA_PAUSE_CAP)
1157                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1158                 }
1159         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1160                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1161                         cap = TG3_FLOW_CTRL_TX;
1162         }
1163
1164         return cap;
1165 }
1166
1167 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1168 {
1169         u8 cap = 0;
1170
1171         if (lcladv & ADVERTISE_1000XPAUSE) {
1172                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1173                         if (rmtadv & LPA_1000XPAUSE)
1174                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1175                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1176                                 cap = TG3_FLOW_CTRL_RX;
1177                 } else {
1178                         if (rmtadv & LPA_1000XPAUSE)
1179                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1180                 }
1181         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1182                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1183                         cap = TG3_FLOW_CTRL_TX;
1184         }
1185
1186         return cap;
1187 }
1188
1189 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1190 {
1191         u8 autoneg;
1192         u8 flowctrl = 0;
1193         u32 old_rx_mode = tp->rx_mode;
1194         u32 old_tx_mode = tp->tx_mode;
1195
1196         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1197                 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1198         else
1199                 autoneg = tp->link_config.autoneg;
1200
1201         if (autoneg == AUTONEG_ENABLE &&
1202             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1203                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1204                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1205                 else
1206                         flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1207         } else
1208                 flowctrl = tp->link_config.flowctrl;
1209
1210         tp->link_config.active_flowctrl = flowctrl;
1211
1212         if (flowctrl & TG3_FLOW_CTRL_RX)
1213                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1214         else
1215                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1216
1217         if (old_rx_mode != tp->rx_mode)
1218                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1219
1220         if (flowctrl & TG3_FLOW_CTRL_TX)
1221                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1222         else
1223                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1224
1225         if (old_tx_mode != tp->tx_mode)
1226                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1227 }
1228
1229 static void tg3_adjust_link(struct net_device *dev)
1230 {
1231         u8 oldflowctrl, linkmesg = 0;
1232         u32 mac_mode, lcl_adv, rmt_adv;
1233         struct tg3 *tp = netdev_priv(dev);
1234         struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1235
1236         spin_lock(&tp->lock);
1237
1238         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1239                                     MAC_MODE_HALF_DUPLEX);
1240
1241         oldflowctrl = tp->link_config.active_flowctrl;
1242
1243         if (phydev->link) {
1244                 lcl_adv = 0;
1245                 rmt_adv = 0;
1246
1247                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1248                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1249                 else
1250                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1251
1252                 if (phydev->duplex == DUPLEX_HALF)
1253                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1254                 else {
1255                         lcl_adv = tg3_advert_flowctrl_1000T(
1256                                   tp->link_config.flowctrl);
1257
1258                         if (phydev->pause)
1259                                 rmt_adv = LPA_PAUSE_CAP;
1260                         if (phydev->asym_pause)
1261                                 rmt_adv |= LPA_PAUSE_ASYM;
1262                 }
1263
1264                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1265         } else
1266                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1267
1268         if (mac_mode != tp->mac_mode) {
1269                 tp->mac_mode = mac_mode;
1270                 tw32_f(MAC_MODE, tp->mac_mode);
1271                 udelay(40);
1272         }
1273
1274         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1275                 tw32(MAC_TX_LENGTHS,
1276                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1277                       (6 << TX_LENGTHS_IPG_SHIFT) |
1278                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1279         else
1280                 tw32(MAC_TX_LENGTHS,
1281                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1282                       (6 << TX_LENGTHS_IPG_SHIFT) |
1283                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1284
1285         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1286             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1287             phydev->speed != tp->link_config.active_speed ||
1288             phydev->duplex != tp->link_config.active_duplex ||
1289             oldflowctrl != tp->link_config.active_flowctrl)
1290             linkmesg = 1;
1291
1292         tp->link_config.active_speed = phydev->speed;
1293         tp->link_config.active_duplex = phydev->duplex;
1294
1295         spin_unlock(&tp->lock);
1296
1297         if (linkmesg)
1298                 tg3_link_report(tp);
1299 }
1300
1301 static int tg3_phy_init(struct tg3 *tp)
1302 {
1303         struct phy_device *phydev;
1304
1305         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1306                 return 0;
1307
1308         /* Bring the PHY back to a known state. */
1309         tg3_bmcr_reset(tp);
1310
1311         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1312
1313         /* Attach the MAC to the PHY. */
1314         phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1315                              phydev->dev_flags, phydev->interface);
1316         if (IS_ERR(phydev)) {
1317                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1318                 return PTR_ERR(phydev);
1319         }
1320
1321         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1322
1323         /* Mask with MAC supported features. */
1324         phydev->supported &= (PHY_GBIT_FEATURES |
1325                               SUPPORTED_Pause |
1326                               SUPPORTED_Asym_Pause);
1327
1328         phydev->advertising = phydev->supported;
1329
1330         printk(KERN_INFO
1331                "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1332                tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1333
1334         return 0;
1335 }
1336
1337 static void tg3_phy_start(struct tg3 *tp)
1338 {
1339         struct phy_device *phydev;
1340
1341         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1342                 return;
1343
1344         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1345
1346         if (tp->link_config.phy_is_low_power) {
1347                 tp->link_config.phy_is_low_power = 0;
1348                 phydev->speed = tp->link_config.orig_speed;
1349                 phydev->duplex = tp->link_config.orig_duplex;
1350                 phydev->autoneg = tp->link_config.orig_autoneg;
1351                 phydev->advertising = tp->link_config.orig_advertising;
1352         }
1353
1354         phy_start(phydev);
1355
1356         phy_start_aneg(phydev);
1357 }
1358
1359 static void tg3_phy_stop(struct tg3 *tp)
1360 {
1361         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1362                 return;
1363
1364         phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1365 }
1366
1367 static void tg3_phy_fini(struct tg3 *tp)
1368 {
1369         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1370                 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1371                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1372         }
1373 }
1374
1375 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1376 {
1377         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1378         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1379 }
1380
1381 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1382 {
1383         u32 phy;
1384
1385         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1386             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1387                 return;
1388
1389         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1390                 u32 ephy;
1391
1392                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1393                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1394                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1395                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1396                                 if (enable)
1397                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1398                                 else
1399                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1400                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1401                         }
1402                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1403                 }
1404         } else {
1405                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1406                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1407                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1408                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1409                         if (enable)
1410                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1411                         else
1412                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1413                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1414                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1415                 }
1416         }
1417 }
1418
1419 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1420 {
1421         u32 val;
1422
1423         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1424                 return;
1425
1426         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1427             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1428                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1429                              (val | (1 << 15) | (1 << 4)));
1430 }
1431
1432 static void tg3_phy_apply_otp(struct tg3 *tp)
1433 {
1434         u32 otp, phy;
1435
1436         if (!tp->phy_otp)
1437                 return;
1438
1439         otp = tp->phy_otp;
1440
1441         /* Enable SM_DSP clock and tx 6dB coding. */
1442         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1443               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1444               MII_TG3_AUXCTL_ACTL_TX_6DB;
1445         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1446
1447         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1448         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1449         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1450
1451         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1452               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1453         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1454
1455         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1456         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1457         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1458
1459         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1460         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1461
1462         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1463         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1464
1465         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1466               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1467         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1468
1469         /* Turn off SM_DSP clock. */
1470         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1471               MII_TG3_AUXCTL_ACTL_TX_6DB;
1472         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1473 }
1474
1475 static int tg3_wait_macro_done(struct tg3 *tp)
1476 {
1477         int limit = 100;
1478
1479         while (limit--) {
1480                 u32 tmp32;
1481
1482                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1483                         if ((tmp32 & 0x1000) == 0)
1484                                 break;
1485                 }
1486         }
1487         if (limit <= 0)
1488                 return -EBUSY;
1489
1490         return 0;
1491 }
1492
1493 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1494 {
1495         static const u32 test_pat[4][6] = {
1496         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1497         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1498         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1499         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1500         };
1501         int chan;
1502
1503         for (chan = 0; chan < 4; chan++) {
1504                 int i;
1505
1506                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1507                              (chan * 0x2000) | 0x0200);
1508                 tg3_writephy(tp, 0x16, 0x0002);
1509
1510                 for (i = 0; i < 6; i++)
1511                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1512                                      test_pat[chan][i]);
1513
1514                 tg3_writephy(tp, 0x16, 0x0202);
1515                 if (tg3_wait_macro_done(tp)) {
1516                         *resetp = 1;
1517                         return -EBUSY;
1518                 }
1519
1520                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1521                              (chan * 0x2000) | 0x0200);
1522                 tg3_writephy(tp, 0x16, 0x0082);
1523                 if (tg3_wait_macro_done(tp)) {
1524                         *resetp = 1;
1525                         return -EBUSY;
1526                 }
1527
1528                 tg3_writephy(tp, 0x16, 0x0802);
1529                 if (tg3_wait_macro_done(tp)) {
1530                         *resetp = 1;
1531                         return -EBUSY;
1532                 }
1533
1534                 for (i = 0; i < 6; i += 2) {
1535                         u32 low, high;
1536
1537                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1538                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1539                             tg3_wait_macro_done(tp)) {
1540                                 *resetp = 1;
1541                                 return -EBUSY;
1542                         }
1543                         low &= 0x7fff;
1544                         high &= 0x000f;
1545                         if (low != test_pat[chan][i] ||
1546                             high != test_pat[chan][i+1]) {
1547                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1548                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1549                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1550
1551                                 return -EBUSY;
1552                         }
1553                 }
1554         }
1555
1556         return 0;
1557 }
1558
1559 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1560 {
1561         int chan;
1562
1563         for (chan = 0; chan < 4; chan++) {
1564                 int i;
1565
1566                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1567                              (chan * 0x2000) | 0x0200);
1568                 tg3_writephy(tp, 0x16, 0x0002);
1569                 for (i = 0; i < 6; i++)
1570                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1571                 tg3_writephy(tp, 0x16, 0x0202);
1572                 if (tg3_wait_macro_done(tp))
1573                         return -EBUSY;
1574         }
1575
1576         return 0;
1577 }
1578
1579 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1580 {
1581         u32 reg32, phy9_orig;
1582         int retries, do_phy_reset, err;
1583
1584         retries = 10;
1585         do_phy_reset = 1;
1586         do {
1587                 if (do_phy_reset) {
1588                         err = tg3_bmcr_reset(tp);
1589                         if (err)
1590                                 return err;
1591                         do_phy_reset = 0;
1592                 }
1593
1594                 /* Disable transmitter and interrupt.  */
1595                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1596                         continue;
1597
1598                 reg32 |= 0x3000;
1599                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1600
1601                 /* Set full-duplex, 1000 mbps.  */
1602                 tg3_writephy(tp, MII_BMCR,
1603                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1604
1605                 /* Set to master mode.  */
1606                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1607                         continue;
1608
1609                 tg3_writephy(tp, MII_TG3_CTRL,
1610                              (MII_TG3_CTRL_AS_MASTER |
1611                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1612
1613                 /* Enable SM_DSP_CLOCK and 6dB.  */
1614                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1615
1616                 /* Block the PHY control access.  */
1617                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1618                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1619
1620                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1621                 if (!err)
1622                         break;
1623         } while (--retries);
1624
1625         err = tg3_phy_reset_chanpat(tp);
1626         if (err)
1627                 return err;
1628
1629         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1630         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1631
1632         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1633         tg3_writephy(tp, 0x16, 0x0000);
1634
1635         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1636             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1637                 /* Set Extended packet length bit for jumbo frames */
1638                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1639         }
1640         else {
1641                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1642         }
1643
1644         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1645
1646         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1647                 reg32 &= ~0x3000;
1648                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1649         } else if (!err)
1650                 err = -EBUSY;
1651
1652         return err;
1653 }
1654
1655 /* This will reset the tigon3 PHY if there is no valid
1656  * link unless the FORCE argument is non-zero.
1657  */
1658 static int tg3_phy_reset(struct tg3 *tp)
1659 {
1660         u32 cpmuctrl;
1661         u32 phy_status;
1662         int err;
1663
1664         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1665                 u32 val;
1666
1667                 val = tr32(GRC_MISC_CFG);
1668                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1669                 udelay(40);
1670         }
1671         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1672         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1673         if (err != 0)
1674                 return -EBUSY;
1675
1676         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1677                 netif_carrier_off(tp->dev);
1678                 tg3_link_report(tp);
1679         }
1680
1681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1682             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1683             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1684                 err = tg3_phy_reset_5703_4_5(tp);
1685                 if (err)
1686                         return err;
1687                 goto out;
1688         }
1689
1690         cpmuctrl = 0;
1691         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1692             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1693                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1694                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1695                         tw32(TG3_CPMU_CTRL,
1696                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1697         }
1698
1699         err = tg3_bmcr_reset(tp);
1700         if (err)
1701                 return err;
1702
1703         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1704                 u32 phy;
1705
1706                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1707                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1708
1709                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1710         }
1711
1712         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1713                 u32 val;
1714
1715                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1716                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1717                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1718                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1719                         udelay(40);
1720                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1721                 }
1722
1723                 /* Disable GPHY autopowerdown. */
1724                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1725                              MII_TG3_MISC_SHDW_WREN |
1726                              MII_TG3_MISC_SHDW_APD_SEL |
1727                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1728         }
1729
1730         tg3_phy_apply_otp(tp);
1731
1732 out:
1733         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1734                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1736                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1737                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1738                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1739                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1740         }
1741         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1742                 tg3_writephy(tp, 0x1c, 0x8d68);
1743                 tg3_writephy(tp, 0x1c, 0x8d68);
1744         }
1745         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1746                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1747                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1748                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1749                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1750                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1751                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1752                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1753                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1754         }
1755         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1756                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1757                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1758                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1759                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1760                         tg3_writephy(tp, MII_TG3_TEST1,
1761                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1762                 } else
1763                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1764                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1765         }
1766         /* Set Extended packet length bit (bit 14) on all chips that */
1767         /* support jumbo frames */
1768         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1769                 /* Cannot do read-modify-write on 5401 */
1770                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1771         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1772                 u32 phy_reg;
1773
1774                 /* Set bit 14 with read-modify-write to preserve other bits */
1775                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1776                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1777                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1778         }
1779
1780         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1781          * jumbo frames transmission.
1782          */
1783         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1784                 u32 phy_reg;
1785
1786                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1787                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1788                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1789         }
1790
1791         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1792                 /* adjust output voltage */
1793                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1794         }
1795
1796         tg3_phy_toggle_automdix(tp, 1);
1797         tg3_phy_set_wirespeed(tp);
1798         return 0;
1799 }
1800
1801 static void tg3_frob_aux_power(struct tg3 *tp)
1802 {
1803         struct tg3 *tp_peer = tp;
1804
1805         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1806                 return;
1807
1808         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1809             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1810                 struct net_device *dev_peer;
1811
1812                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1813                 /* remove_one() may have been run on the peer. */
1814                 if (!dev_peer)
1815                         tp_peer = tp;
1816                 else
1817                         tp_peer = netdev_priv(dev_peer);
1818         }
1819
1820         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1821             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1822             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1823             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1824                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1825                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1826                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1827                                     (GRC_LCLCTRL_GPIO_OE0 |
1828                                      GRC_LCLCTRL_GPIO_OE1 |
1829                                      GRC_LCLCTRL_GPIO_OE2 |
1830                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1831                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1832                                     100);
1833                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1834                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1835                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1836                                              GRC_LCLCTRL_GPIO_OE1 |
1837                                              GRC_LCLCTRL_GPIO_OE2 |
1838                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1839                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1840                                              tp->grc_local_ctrl;
1841                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1842
1843                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1844                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1845
1846                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1847                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1848                 } else {
1849                         u32 no_gpio2;
1850                         u32 grc_local_ctrl = 0;
1851
1852                         if (tp_peer != tp &&
1853                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1854                                 return;
1855
1856                         /* Workaround to prevent overdrawing Amps. */
1857                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1858                             ASIC_REV_5714) {
1859                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1860                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1861                                             grc_local_ctrl, 100);
1862                         }
1863
1864                         /* On 5753 and variants, GPIO2 cannot be used. */
1865                         no_gpio2 = tp->nic_sram_data_cfg &
1866                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1867
1868                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1869                                          GRC_LCLCTRL_GPIO_OE1 |
1870                                          GRC_LCLCTRL_GPIO_OE2 |
1871                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1872                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1873                         if (no_gpio2) {
1874                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1875                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1876                         }
1877                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1878                                                     grc_local_ctrl, 100);
1879
1880                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1881
1882                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1883                                                     grc_local_ctrl, 100);
1884
1885                         if (!no_gpio2) {
1886                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1887                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1888                                             grc_local_ctrl, 100);
1889                         }
1890                 }
1891         } else {
1892                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1893                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1894                         if (tp_peer != tp &&
1895                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1896                                 return;
1897
1898                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1899                                     (GRC_LCLCTRL_GPIO_OE1 |
1900                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1901
1902                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1903                                     GRC_LCLCTRL_GPIO_OE1, 100);
1904
1905                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1906                                     (GRC_LCLCTRL_GPIO_OE1 |
1907                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1908                 }
1909         }
1910 }
1911
1912 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1913 {
1914         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1915                 return 1;
1916         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1917                 if (speed != SPEED_10)
1918                         return 1;
1919         } else if (speed == SPEED_10)
1920                 return 1;
1921
1922         return 0;
1923 }
1924
1925 static int tg3_setup_phy(struct tg3 *, int);
1926
1927 #define RESET_KIND_SHUTDOWN     0
1928 #define RESET_KIND_INIT         1
1929 #define RESET_KIND_SUSPEND      2
1930
1931 static void tg3_write_sig_post_reset(struct tg3 *, int);
1932 static int tg3_halt_cpu(struct tg3 *, u32);
1933 static int tg3_nvram_lock(struct tg3 *);
1934 static void tg3_nvram_unlock(struct tg3 *);
1935
1936 static void tg3_power_down_phy(struct tg3 *tp)
1937 {
1938         u32 val;
1939
1940         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1941                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1942                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1943                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1944
1945                         sg_dig_ctrl |=
1946                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1947                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1948                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1949                 }
1950                 return;
1951         }
1952
1953         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1954                 tg3_bmcr_reset(tp);
1955                 val = tr32(GRC_MISC_CFG);
1956                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1957                 udelay(40);
1958                 return;
1959         } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1960                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1961                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1962                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1963         }
1964
1965         /* The PHY should not be powered down on some chips because
1966          * of bugs.
1967          */
1968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1969             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1970             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1971              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1972                 return;
1973
1974         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1975                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1976                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1977                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1978                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1979         }
1980
1981         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1982 }
1983
1984 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1985 {
1986         u32 misc_host_ctrl;
1987
1988         /* Make sure register accesses (indirect or otherwise)
1989          * will function correctly.
1990          */
1991         pci_write_config_dword(tp->pdev,
1992                                TG3PCI_MISC_HOST_CTRL,
1993                                tp->misc_host_ctrl);
1994
1995         switch (state) {
1996         case PCI_D0:
1997                 pci_enable_wake(tp->pdev, state, false);
1998                 pci_set_power_state(tp->pdev, PCI_D0);
1999
2000                 /* Switch out of Vaux if it is a NIC */
2001                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2002                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2003
2004                 return 0;
2005
2006         case PCI_D1:
2007         case PCI_D2:
2008         case PCI_D3hot:
2009                 break;
2010
2011         default:
2012                 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2013                         tp->dev->name, state);
2014                 return -EINVAL;
2015         }
2016         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2017         tw32(TG3PCI_MISC_HOST_CTRL,
2018              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2019
2020         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2021                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2022                     !tp->link_config.phy_is_low_power) {
2023                         struct phy_device *phydev;
2024                         u32 advertising;
2025
2026                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2027
2028                         tp->link_config.phy_is_low_power = 1;
2029
2030                         tp->link_config.orig_speed = phydev->speed;
2031                         tp->link_config.orig_duplex = phydev->duplex;
2032                         tp->link_config.orig_autoneg = phydev->autoneg;
2033                         tp->link_config.orig_advertising = phydev->advertising;
2034
2035                         advertising = ADVERTISED_TP |
2036                                       ADVERTISED_Pause |
2037                                       ADVERTISED_Autoneg |
2038                                       ADVERTISED_10baseT_Half;
2039
2040                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2041                             (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2042                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2043                                         advertising |=
2044                                                 ADVERTISED_100baseT_Half |
2045                                                 ADVERTISED_100baseT_Full |
2046                                                 ADVERTISED_10baseT_Full;
2047                                 else
2048                                         advertising |= ADVERTISED_10baseT_Full;
2049                         }
2050
2051                         phydev->advertising = advertising;
2052
2053                         phy_start_aneg(phydev);
2054                 }
2055         } else {
2056                 if (tp->link_config.phy_is_low_power == 0) {
2057                         tp->link_config.phy_is_low_power = 1;
2058                         tp->link_config.orig_speed = tp->link_config.speed;
2059                         tp->link_config.orig_duplex = tp->link_config.duplex;
2060                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2061                 }
2062
2063                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2064                         tp->link_config.speed = SPEED_10;
2065                         tp->link_config.duplex = DUPLEX_HALF;
2066                         tp->link_config.autoneg = AUTONEG_ENABLE;
2067                         tg3_setup_phy(tp, 0);
2068                 }
2069         }
2070
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2072                 u32 val;
2073
2074                 val = tr32(GRC_VCPU_EXT_CTRL);
2075                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2076         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2077                 int i;
2078                 u32 val;
2079
2080                 for (i = 0; i < 200; i++) {
2081                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2082                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2083                                 break;
2084                         msleep(1);
2085                 }
2086         }
2087         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2088                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2089                                                      WOL_DRV_STATE_SHUTDOWN |
2090                                                      WOL_DRV_WOL |
2091                                                      WOL_SET_MAGIC_PKT);
2092
2093         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2094                 u32 mac_mode;
2095
2096                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2097                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2098                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2099                                 udelay(40);
2100                         }
2101
2102                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2103                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2104                         else
2105                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2106
2107                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2108                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2109                             ASIC_REV_5700) {
2110                                 u32 speed = (tp->tg3_flags &
2111                                              TG3_FLAG_WOL_SPEED_100MB) ?
2112                                              SPEED_100 : SPEED_10;
2113                                 if (tg3_5700_link_polarity(tp, speed))
2114                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2115                                 else
2116                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2117                         }
2118                 } else {
2119                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2120                 }
2121
2122                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2123                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2124
2125                 if (pci_pme_capable(tp->pdev, state) &&
2126                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE))
2127                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2128
2129                 tw32_f(MAC_MODE, mac_mode);
2130                 udelay(100);
2131
2132                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2133                 udelay(10);
2134         }
2135
2136         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2137             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2138              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2139                 u32 base_val;
2140
2141                 base_val = tp->pci_clock_ctrl;
2142                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2143                              CLOCK_CTRL_TXCLK_DISABLE);
2144
2145                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2146                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2147         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2148                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2149                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2150                 /* do nothing */
2151         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2152                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2153                 u32 newbits1, newbits2;
2154
2155                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2156                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2157                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2158                                     CLOCK_CTRL_TXCLK_DISABLE |
2159                                     CLOCK_CTRL_ALTCLK);
2160                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2161                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2162                         newbits1 = CLOCK_CTRL_625_CORE;
2163                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2164                 } else {
2165                         newbits1 = CLOCK_CTRL_ALTCLK;
2166                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2167                 }
2168
2169                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2170                             40);
2171
2172                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2173                             40);
2174
2175                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2176                         u32 newbits3;
2177
2178                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2179                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2180                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2181                                             CLOCK_CTRL_TXCLK_DISABLE |
2182                                             CLOCK_CTRL_44MHZ_CORE);
2183                         } else {
2184                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2185                         }
2186
2187                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2188                                     tp->pci_clock_ctrl | newbits3, 40);
2189                 }
2190         }
2191
2192         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2193             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2194             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2195                 tg3_power_down_phy(tp);
2196
2197         tg3_frob_aux_power(tp);
2198
2199         /* Workaround for unstable PLL clock */
2200         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2201             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2202                 u32 val = tr32(0x7d00);
2203
2204                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2205                 tw32(0x7d00, val);
2206                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2207                         int err;
2208
2209                         err = tg3_nvram_lock(tp);
2210                         tg3_halt_cpu(tp, RX_CPU_BASE);
2211                         if (!err)
2212                                 tg3_nvram_unlock(tp);
2213                 }
2214         }
2215
2216         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2217
2218         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
2219                 pci_enable_wake(tp->pdev, state, true);
2220
2221         /* Finally, set the new power state. */
2222         pci_set_power_state(tp->pdev, state);
2223
2224         return 0;
2225 }
2226
2227 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2228 {
2229         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2230         case MII_TG3_AUX_STAT_10HALF:
2231                 *speed = SPEED_10;
2232                 *duplex = DUPLEX_HALF;
2233                 break;
2234
2235         case MII_TG3_AUX_STAT_10FULL:
2236                 *speed = SPEED_10;
2237                 *duplex = DUPLEX_FULL;
2238                 break;
2239
2240         case MII_TG3_AUX_STAT_100HALF:
2241                 *speed = SPEED_100;
2242                 *duplex = DUPLEX_HALF;
2243                 break;
2244
2245         case MII_TG3_AUX_STAT_100FULL:
2246                 *speed = SPEED_100;
2247                 *duplex = DUPLEX_FULL;
2248                 break;
2249
2250         case MII_TG3_AUX_STAT_1000HALF:
2251                 *speed = SPEED_1000;
2252                 *duplex = DUPLEX_HALF;
2253                 break;
2254
2255         case MII_TG3_AUX_STAT_1000FULL:
2256                 *speed = SPEED_1000;
2257                 *duplex = DUPLEX_FULL;
2258                 break;
2259
2260         default:
2261                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2262                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2263                                  SPEED_10;
2264                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2265                                   DUPLEX_HALF;
2266                         break;
2267                 }
2268                 *speed = SPEED_INVALID;
2269                 *duplex = DUPLEX_INVALID;
2270                 break;
2271         }
2272 }
2273
2274 static void tg3_phy_copper_begin(struct tg3 *tp)
2275 {
2276         u32 new_adv;
2277         int i;
2278
2279         if (tp->link_config.phy_is_low_power) {
2280                 /* Entering low power mode.  Disable gigabit and
2281                  * 100baseT advertisements.
2282                  */
2283                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2284
2285                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2286                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2287                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2288                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2289
2290                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2291         } else if (tp->link_config.speed == SPEED_INVALID) {
2292                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2293                         tp->link_config.advertising &=
2294                                 ~(ADVERTISED_1000baseT_Half |
2295                                   ADVERTISED_1000baseT_Full);
2296
2297                 new_adv = ADVERTISE_CSMA;
2298                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2299                         new_adv |= ADVERTISE_10HALF;
2300                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2301                         new_adv |= ADVERTISE_10FULL;
2302                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2303                         new_adv |= ADVERTISE_100HALF;
2304                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2305                         new_adv |= ADVERTISE_100FULL;
2306
2307                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2308
2309                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2310
2311                 if (tp->link_config.advertising &
2312                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2313                         new_adv = 0;
2314                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2315                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2316                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2317                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2318                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2319                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2320                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2321                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2322                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2323                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2324                 } else {
2325                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2326                 }
2327         } else {
2328                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2329                 new_adv |= ADVERTISE_CSMA;
2330
2331                 /* Asking for a specific link mode. */
2332                 if (tp->link_config.speed == SPEED_1000) {
2333                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2334
2335                         if (tp->link_config.duplex == DUPLEX_FULL)
2336                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2337                         else
2338                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2339                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2340                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2341                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2342                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2343                 } else {
2344                         if (tp->link_config.speed == SPEED_100) {
2345                                 if (tp->link_config.duplex == DUPLEX_FULL)
2346                                         new_adv |= ADVERTISE_100FULL;
2347                                 else
2348                                         new_adv |= ADVERTISE_100HALF;
2349                         } else {
2350                                 if (tp->link_config.duplex == DUPLEX_FULL)
2351                                         new_adv |= ADVERTISE_10FULL;
2352                                 else
2353                                         new_adv |= ADVERTISE_10HALF;
2354                         }
2355                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2356
2357                         new_adv = 0;
2358                 }
2359
2360                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2361         }
2362
2363         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2364             tp->link_config.speed != SPEED_INVALID) {
2365                 u32 bmcr, orig_bmcr;
2366
2367                 tp->link_config.active_speed = tp->link_config.speed;
2368                 tp->link_config.active_duplex = tp->link_config.duplex;
2369
2370                 bmcr = 0;
2371                 switch (tp->link_config.speed) {
2372                 default:
2373                 case SPEED_10:
2374                         break;
2375
2376                 case SPEED_100:
2377                         bmcr |= BMCR_SPEED100;
2378                         break;
2379
2380                 case SPEED_1000:
2381                         bmcr |= TG3_BMCR_SPEED1000;
2382                         break;
2383                 }
2384
2385                 if (tp->link_config.duplex == DUPLEX_FULL)
2386                         bmcr |= BMCR_FULLDPLX;
2387
2388                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2389                     (bmcr != orig_bmcr)) {
2390                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2391                         for (i = 0; i < 1500; i++) {
2392                                 u32 tmp;
2393
2394                                 udelay(10);
2395                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2396                                     tg3_readphy(tp, MII_BMSR, &tmp))
2397                                         continue;
2398                                 if (!(tmp & BMSR_LSTATUS)) {
2399                                         udelay(40);
2400                                         break;
2401                                 }
2402                         }
2403                         tg3_writephy(tp, MII_BMCR, bmcr);
2404                         udelay(40);
2405                 }
2406         } else {
2407                 tg3_writephy(tp, MII_BMCR,
2408                              BMCR_ANENABLE | BMCR_ANRESTART);
2409         }
2410 }
2411
2412 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2413 {
2414         int err;
2415
2416         /* Turn off tap power management. */
2417         /* Set Extended packet length bit */
2418         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2419
2420         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2421         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2422
2423         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2424         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2425
2426         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2427         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2428
2429         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2430         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2431
2432         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2433         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2434
2435         udelay(40);
2436
2437         return err;
2438 }
2439
2440 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2441 {
2442         u32 adv_reg, all_mask = 0;
2443
2444         if (mask & ADVERTISED_10baseT_Half)
2445                 all_mask |= ADVERTISE_10HALF;
2446         if (mask & ADVERTISED_10baseT_Full)
2447                 all_mask |= ADVERTISE_10FULL;
2448         if (mask & ADVERTISED_100baseT_Half)
2449                 all_mask |= ADVERTISE_100HALF;
2450         if (mask & ADVERTISED_100baseT_Full)
2451                 all_mask |= ADVERTISE_100FULL;
2452
2453         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2454                 return 0;
2455
2456         if ((adv_reg & all_mask) != all_mask)
2457                 return 0;
2458         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2459                 u32 tg3_ctrl;
2460
2461                 all_mask = 0;
2462                 if (mask & ADVERTISED_1000baseT_Half)
2463                         all_mask |= ADVERTISE_1000HALF;
2464                 if (mask & ADVERTISED_1000baseT_Full)
2465                         all_mask |= ADVERTISE_1000FULL;
2466
2467                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2468                         return 0;
2469
2470                 if ((tg3_ctrl & all_mask) != all_mask)
2471                         return 0;
2472         }
2473         return 1;
2474 }
2475
2476 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2477 {
2478         u32 curadv, reqadv;
2479
2480         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2481                 return 1;
2482
2483         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2484         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2485
2486         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2487                 if (curadv != reqadv)
2488                         return 0;
2489
2490                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2491                         tg3_readphy(tp, MII_LPA, rmtadv);
2492         } else {
2493                 /* Reprogram the advertisement register, even if it
2494                  * does not affect the current link.  If the link
2495                  * gets renegotiated in the future, we can save an
2496                  * additional renegotiation cycle by advertising
2497                  * it correctly in the first place.
2498                  */
2499                 if (curadv != reqadv) {
2500                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2501                                      ADVERTISE_PAUSE_ASYM);
2502                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2503                 }
2504         }
2505
2506         return 1;
2507 }
2508
2509 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2510 {
2511         int current_link_up;
2512         u32 bmsr, dummy;
2513         u32 lcl_adv, rmt_adv;
2514         u16 current_speed;
2515         u8 current_duplex;
2516         int i, err;
2517
2518         tw32(MAC_EVENT, 0);
2519
2520         tw32_f(MAC_STATUS,
2521              (MAC_STATUS_SYNC_CHANGED |
2522               MAC_STATUS_CFG_CHANGED |
2523               MAC_STATUS_MI_COMPLETION |
2524               MAC_STATUS_LNKSTATE_CHANGED));
2525         udelay(40);
2526
2527         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2528                 tw32_f(MAC_MI_MODE,
2529                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2530                 udelay(80);
2531         }
2532
2533         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2534
2535         /* Some third-party PHYs need to be reset on link going
2536          * down.
2537          */
2538         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2539              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2540              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2541             netif_carrier_ok(tp->dev)) {
2542                 tg3_readphy(tp, MII_BMSR, &bmsr);
2543                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2544                     !(bmsr & BMSR_LSTATUS))
2545                         force_reset = 1;
2546         }
2547         if (force_reset)
2548                 tg3_phy_reset(tp);
2549
2550         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2551                 tg3_readphy(tp, MII_BMSR, &bmsr);
2552                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2553                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2554                         bmsr = 0;
2555
2556                 if (!(bmsr & BMSR_LSTATUS)) {
2557                         err = tg3_init_5401phy_dsp(tp);
2558                         if (err)
2559                                 return err;
2560
2561                         tg3_readphy(tp, MII_BMSR, &bmsr);
2562                         for (i = 0; i < 1000; i++) {
2563                                 udelay(10);
2564                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2565                                     (bmsr & BMSR_LSTATUS)) {
2566                                         udelay(40);
2567                                         break;
2568                                 }
2569                         }
2570
2571                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2572                             !(bmsr & BMSR_LSTATUS) &&
2573                             tp->link_config.active_speed == SPEED_1000) {
2574                                 err = tg3_phy_reset(tp);
2575                                 if (!err)
2576                                         err = tg3_init_5401phy_dsp(tp);
2577                                 if (err)
2578                                         return err;
2579                         }
2580                 }
2581         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2582                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2583                 /* 5701 {A0,B0} CRC bug workaround */
2584                 tg3_writephy(tp, 0x15, 0x0a75);
2585                 tg3_writephy(tp, 0x1c, 0x8c68);
2586                 tg3_writephy(tp, 0x1c, 0x8d68);
2587                 tg3_writephy(tp, 0x1c, 0x8c68);
2588         }
2589
2590         /* Clear pending interrupts... */
2591         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2592         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2593
2594         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2595                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2596         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2597                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2598
2599         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2600             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2601                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2602                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2603                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2604                 else
2605                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2606         }
2607
2608         current_link_up = 0;
2609         current_speed = SPEED_INVALID;
2610         current_duplex = DUPLEX_INVALID;
2611
2612         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2613                 u32 val;
2614
2615                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2616                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2617                 if (!(val & (1 << 10))) {
2618                         val |= (1 << 10);
2619                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2620                         goto relink;
2621                 }
2622         }
2623
2624         bmsr = 0;
2625         for (i = 0; i < 100; i++) {
2626                 tg3_readphy(tp, MII_BMSR, &bmsr);
2627                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2628                     (bmsr & BMSR_LSTATUS))
2629                         break;
2630                 udelay(40);
2631         }
2632
2633         if (bmsr & BMSR_LSTATUS) {
2634                 u32 aux_stat, bmcr;
2635
2636                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2637                 for (i = 0; i < 2000; i++) {
2638                         udelay(10);
2639                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2640                             aux_stat)
2641                                 break;
2642                 }
2643
2644                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2645                                              &current_speed,
2646                                              &current_duplex);
2647
2648                 bmcr = 0;
2649                 for (i = 0; i < 200; i++) {
2650                         tg3_readphy(tp, MII_BMCR, &bmcr);
2651                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2652                                 continue;
2653                         if (bmcr && bmcr != 0x7fff)
2654                                 break;
2655                         udelay(10);
2656                 }
2657
2658                 lcl_adv = 0;
2659                 rmt_adv = 0;
2660
2661                 tp->link_config.active_speed = current_speed;
2662                 tp->link_config.active_duplex = current_duplex;
2663
2664                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2665                         if ((bmcr & BMCR_ANENABLE) &&
2666                             tg3_copper_is_advertising_all(tp,
2667                                                 tp->link_config.advertising)) {
2668                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2669                                                                   &rmt_adv))
2670                                         current_link_up = 1;
2671                         }
2672                 } else {
2673                         if (!(bmcr & BMCR_ANENABLE) &&
2674                             tp->link_config.speed == current_speed &&
2675                             tp->link_config.duplex == current_duplex &&
2676                             tp->link_config.flowctrl ==
2677                             tp->link_config.active_flowctrl) {
2678                                 current_link_up = 1;
2679                         }
2680                 }
2681
2682                 if (current_link_up == 1 &&
2683                     tp->link_config.active_duplex == DUPLEX_FULL)
2684                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2685         }
2686
2687 relink:
2688         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2689                 u32 tmp;
2690
2691                 tg3_phy_copper_begin(tp);
2692
2693                 tg3_readphy(tp, MII_BMSR, &tmp);
2694                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2695                     (tmp & BMSR_LSTATUS))
2696                         current_link_up = 1;
2697         }
2698
2699         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2700         if (current_link_up == 1) {
2701                 if (tp->link_config.active_speed == SPEED_100 ||
2702                     tp->link_config.active_speed == SPEED_10)
2703                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2704                 else
2705                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2706         } else
2707                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2708
2709         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2710         if (tp->link_config.active_duplex == DUPLEX_HALF)
2711                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2712
2713         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2714                 if (current_link_up == 1 &&
2715                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2716                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2717                 else
2718                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2719         }
2720
2721         /* ??? Without this setting Netgear GA302T PHY does not
2722          * ??? send/receive packets...
2723          */
2724         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2725             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2726                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2727                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2728                 udelay(80);
2729         }
2730
2731         tw32_f(MAC_MODE, tp->mac_mode);
2732         udelay(40);
2733
2734         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2735                 /* Polled via timer. */
2736                 tw32_f(MAC_EVENT, 0);
2737         } else {
2738                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2739         }
2740         udelay(40);
2741
2742         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2743             current_link_up == 1 &&
2744             tp->link_config.active_speed == SPEED_1000 &&
2745             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2746              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2747                 udelay(120);
2748                 tw32_f(MAC_STATUS,
2749                      (MAC_STATUS_SYNC_CHANGED |
2750                       MAC_STATUS_CFG_CHANGED));
2751                 udelay(40);
2752                 tg3_write_mem(tp,
2753                               NIC_SRAM_FIRMWARE_MBOX,
2754                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2755         }
2756
2757         if (current_link_up != netif_carrier_ok(tp->dev)) {
2758                 if (current_link_up)
2759                         netif_carrier_on(tp->dev);
2760                 else
2761                         netif_carrier_off(tp->dev);
2762                 tg3_link_report(tp);
2763         }
2764
2765         return 0;
2766 }
2767
2768 struct tg3_fiber_aneginfo {
2769         int state;
2770 #define ANEG_STATE_UNKNOWN              0
2771 #define ANEG_STATE_AN_ENABLE            1
2772 #define ANEG_STATE_RESTART_INIT         2
2773 #define ANEG_STATE_RESTART              3
2774 #define ANEG_STATE_DISABLE_LINK_OK      4
2775 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2776 #define ANEG_STATE_ABILITY_DETECT       6
2777 #define ANEG_STATE_ACK_DETECT_INIT      7
2778 #define ANEG_STATE_ACK_DETECT           8
2779 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2780 #define ANEG_STATE_COMPLETE_ACK         10
2781 #define ANEG_STATE_IDLE_DETECT_INIT     11
2782 #define ANEG_STATE_IDLE_DETECT          12
2783 #define ANEG_STATE_LINK_OK              13
2784 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2785 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2786
2787         u32 flags;
2788 #define MR_AN_ENABLE            0x00000001
2789 #define MR_RESTART_AN           0x00000002
2790 #define MR_AN_COMPLETE          0x00000004
2791 #define MR_PAGE_RX              0x00000008
2792 #define MR_NP_LOADED            0x00000010
2793 #define MR_TOGGLE_TX            0x00000020
2794 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2795 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2796 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2797 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2798 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2799 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2800 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2801 #define MR_TOGGLE_RX            0x00002000
2802 #define MR_NP_RX                0x00004000
2803
2804 #define MR_LINK_OK              0x80000000
2805
2806         unsigned long link_time, cur_time;
2807
2808         u32 ability_match_cfg;
2809         int ability_match_count;
2810
2811         char ability_match, idle_match, ack_match;
2812
2813         u32 txconfig, rxconfig;
2814 #define ANEG_CFG_NP             0x00000080
2815 #define ANEG_CFG_ACK            0x00000040
2816 #define ANEG_CFG_RF2            0x00000020
2817 #define ANEG_CFG_RF1            0x00000010
2818 #define ANEG_CFG_PS2            0x00000001
2819 #define ANEG_CFG_PS1            0x00008000
2820 #define ANEG_CFG_HD             0x00004000
2821 #define ANEG_CFG_FD             0x00002000
2822 #define ANEG_CFG_INVAL          0x00001f06
2823
2824 };
2825 #define ANEG_OK         0
2826 #define ANEG_DONE       1
2827 #define ANEG_TIMER_ENAB 2
2828 #define ANEG_FAILED     -1
2829
2830 #define ANEG_STATE_SETTLE_TIME  10000
2831
2832 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2833                                    struct tg3_fiber_aneginfo *ap)
2834 {
2835         u16 flowctrl;
2836         unsigned long delta;
2837         u32 rx_cfg_reg;
2838         int ret;
2839
2840         if (ap->state == ANEG_STATE_UNKNOWN) {
2841                 ap->rxconfig = 0;
2842                 ap->link_time = 0;
2843                 ap->cur_time = 0;
2844                 ap->ability_match_cfg = 0;
2845                 ap->ability_match_count = 0;
2846                 ap->ability_match = 0;
2847                 ap->idle_match = 0;
2848                 ap->ack_match = 0;
2849         }
2850         ap->cur_time++;
2851
2852         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2853                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2854
2855                 if (rx_cfg_reg != ap->ability_match_cfg) {
2856                         ap->ability_match_cfg = rx_cfg_reg;
2857                         ap->ability_match = 0;
2858                         ap->ability_match_count = 0;
2859                 } else {
2860                         if (++ap->ability_match_count > 1) {
2861                                 ap->ability_match = 1;
2862                                 ap->ability_match_cfg = rx_cfg_reg;
2863                         }
2864                 }
2865                 if (rx_cfg_reg & ANEG_CFG_ACK)
2866                         ap->ack_match = 1;
2867                 else
2868                         ap->ack_match = 0;
2869
2870                 ap->idle_match = 0;
2871         } else {
2872                 ap->idle_match = 1;
2873                 ap->ability_match_cfg = 0;
2874                 ap->ability_match_count = 0;
2875                 ap->ability_match = 0;
2876                 ap->ack_match = 0;
2877
2878                 rx_cfg_reg = 0;
2879         }
2880
2881         ap->rxconfig = rx_cfg_reg;
2882         ret = ANEG_OK;
2883
2884         switch(ap->state) {
2885         case ANEG_STATE_UNKNOWN:
2886                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2887                         ap->state = ANEG_STATE_AN_ENABLE;
2888
2889                 /* fallthru */
2890         case ANEG_STATE_AN_ENABLE:
2891                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2892                 if (ap->flags & MR_AN_ENABLE) {
2893                         ap->link_time = 0;
2894                         ap->cur_time = 0;
2895                         ap->ability_match_cfg = 0;
2896                         ap->ability_match_count = 0;
2897                         ap->ability_match = 0;
2898                         ap->idle_match = 0;
2899                         ap->ack_match = 0;
2900
2901                         ap->state = ANEG_STATE_RESTART_INIT;
2902                 } else {
2903                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2904                 }
2905                 break;
2906
2907         case ANEG_STATE_RESTART_INIT:
2908                 ap->link_time = ap->cur_time;
2909                 ap->flags &= ~(MR_NP_LOADED);
2910                 ap->txconfig = 0;
2911                 tw32(MAC_TX_AUTO_NEG, 0);
2912                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2913                 tw32_f(MAC_MODE, tp->mac_mode);
2914                 udelay(40);
2915
2916                 ret = ANEG_TIMER_ENAB;
2917                 ap->state = ANEG_STATE_RESTART;
2918
2919                 /* fallthru */
2920         case ANEG_STATE_RESTART:
2921                 delta = ap->cur_time - ap->link_time;
2922                 if (delta > ANEG_STATE_SETTLE_TIME) {
2923                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2924                 } else {
2925                         ret = ANEG_TIMER_ENAB;
2926                 }
2927                 break;
2928
2929         case ANEG_STATE_DISABLE_LINK_OK:
2930                 ret = ANEG_DONE;
2931                 break;
2932
2933         case ANEG_STATE_ABILITY_DETECT_INIT:
2934                 ap->flags &= ~(MR_TOGGLE_TX);
2935                 ap->txconfig = ANEG_CFG_FD;
2936                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2937                 if (flowctrl & ADVERTISE_1000XPAUSE)
2938                         ap->txconfig |= ANEG_CFG_PS1;
2939                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2940                         ap->txconfig |= ANEG_CFG_PS2;
2941                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2942                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2943                 tw32_f(MAC_MODE, tp->mac_mode);
2944                 udelay(40);
2945
2946                 ap->state = ANEG_STATE_ABILITY_DETECT;
2947                 break;
2948
2949         case ANEG_STATE_ABILITY_DETECT:
2950                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2951                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2952                 }
2953                 break;
2954
2955         case ANEG_STATE_ACK_DETECT_INIT:
2956                 ap->txconfig |= ANEG_CFG_ACK;
2957                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2958                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2959                 tw32_f(MAC_MODE, tp->mac_mode);
2960                 udelay(40);
2961
2962                 ap->state = ANEG_STATE_ACK_DETECT;
2963
2964                 /* fallthru */
2965         case ANEG_STATE_ACK_DETECT:
2966                 if (ap->ack_match != 0) {
2967                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2968                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2969                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2970                         } else {
2971                                 ap->state = ANEG_STATE_AN_ENABLE;
2972                         }
2973                 } else if (ap->ability_match != 0 &&
2974                            ap->rxconfig == 0) {
2975                         ap->state = ANEG_STATE_AN_ENABLE;
2976                 }
2977                 break;
2978
2979         case ANEG_STATE_COMPLETE_ACK_INIT:
2980                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2981                         ret = ANEG_FAILED;
2982                         break;
2983                 }
2984                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2985                                MR_LP_ADV_HALF_DUPLEX |
2986                                MR_LP_ADV_SYM_PAUSE |
2987                                MR_LP_ADV_ASYM_PAUSE |
2988                                MR_LP_ADV_REMOTE_FAULT1 |
2989                                MR_LP_ADV_REMOTE_FAULT2 |
2990                                MR_LP_ADV_NEXT_PAGE |
2991                                MR_TOGGLE_RX |
2992                                MR_NP_RX);
2993                 if (ap->rxconfig & ANEG_CFG_FD)
2994                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2995                 if (ap->rxconfig & ANEG_CFG_HD)
2996                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2997                 if (ap->rxconfig & ANEG_CFG_PS1)
2998                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2999                 if (ap->rxconfig & ANEG_CFG_PS2)
3000                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3001                 if (ap->rxconfig & ANEG_CFG_RF1)
3002                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3003                 if (ap->rxconfig & ANEG_CFG_RF2)
3004                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3005                 if (ap->rxconfig & ANEG_CFG_NP)
3006                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3007
3008                 ap->link_time = ap->cur_time;
3009
3010                 ap->flags ^= (MR_TOGGLE_TX);
3011                 if (ap->rxconfig & 0x0008)
3012                         ap->flags |= MR_TOGGLE_RX;
3013                 if (ap->rxconfig & ANEG_CFG_NP)
3014                         ap->flags |= MR_NP_RX;
3015                 ap->flags |= MR_PAGE_RX;
3016
3017                 ap->state = ANEG_STATE_COMPLETE_ACK;
3018                 ret = ANEG_TIMER_ENAB;
3019                 break;
3020
3021         case ANEG_STATE_COMPLETE_ACK:
3022                 if (ap->ability_match != 0 &&
3023                     ap->rxconfig == 0) {
3024                         ap->state = ANEG_STATE_AN_ENABLE;
3025                         break;
3026                 }
3027                 delta = ap->cur_time - ap->link_time;
3028                 if (delta > ANEG_STATE_SETTLE_TIME) {
3029                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3030                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3031                         } else {
3032                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3033                                     !(ap->flags & MR_NP_RX)) {
3034                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3035                                 } else {
3036                                         ret = ANEG_FAILED;
3037                                 }
3038                         }
3039                 }
3040                 break;
3041
3042         case ANEG_STATE_IDLE_DETECT_INIT:
3043                 ap->link_time = ap->cur_time;
3044                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3045                 tw32_f(MAC_MODE, tp->mac_mode);
3046                 udelay(40);
3047
3048                 ap->state = ANEG_STATE_IDLE_DETECT;
3049                 ret = ANEG_TIMER_ENAB;
3050                 break;
3051
3052         case ANEG_STATE_IDLE_DETECT:
3053                 if (ap->ability_match != 0 &&
3054                     ap->rxconfig == 0) {
3055                         ap->state = ANEG_STATE_AN_ENABLE;
3056                         break;
3057                 }
3058                 delta = ap->cur_time - ap->link_time;
3059                 if (delta > ANEG_STATE_SETTLE_TIME) {
3060                         /* XXX another gem from the Broadcom driver :( */
3061                         ap->state = ANEG_STATE_LINK_OK;
3062                 }
3063                 break;
3064
3065         case ANEG_STATE_LINK_OK:
3066                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3067                 ret = ANEG_DONE;
3068                 break;
3069
3070         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3071                 /* ??? unimplemented */
3072                 break;
3073
3074         case ANEG_STATE_NEXT_PAGE_WAIT:
3075                 /* ??? unimplemented */
3076                 break;
3077
3078         default:
3079                 ret = ANEG_FAILED;
3080                 break;
3081         }
3082
3083         return ret;
3084 }
3085
3086 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3087 {
3088         int res = 0;
3089         struct tg3_fiber_aneginfo aninfo;
3090         int status = ANEG_FAILED;
3091         unsigned int tick;
3092         u32 tmp;
3093
3094         tw32_f(MAC_TX_AUTO_NEG, 0);
3095
3096         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3097         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3098         udelay(40);
3099
3100         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3101         udelay(40);
3102
3103         memset(&aninfo, 0, sizeof(aninfo));
3104         aninfo.flags |= MR_AN_ENABLE;
3105         aninfo.state = ANEG_STATE_UNKNOWN;
3106         aninfo.cur_time = 0;
3107         tick = 0;
3108         while (++tick < 195000) {
3109                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3110                 if (status == ANEG_DONE || status == ANEG_FAILED)
3111                         break;
3112
3113                 udelay(1);
3114         }
3115
3116         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3117         tw32_f(MAC_MODE, tp->mac_mode);
3118         udelay(40);
3119
3120         *txflags = aninfo.txconfig;
3121         *rxflags = aninfo.flags;
3122
3123         if (status == ANEG_DONE &&
3124             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3125                              MR_LP_ADV_FULL_DUPLEX)))
3126                 res = 1;
3127
3128         return res;
3129 }
3130
3131 static void tg3_init_bcm8002(struct tg3 *tp)
3132 {
3133         u32 mac_status = tr32(MAC_STATUS);
3134         int i;
3135
3136         /* Reset when initting first time or we have a link. */
3137         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3138             !(mac_status & MAC_STATUS_PCS_SYNCED))
3139                 return;
3140
3141         /* Set PLL lock range. */
3142         tg3_writephy(tp, 0x16, 0x8007);
3143
3144         /* SW reset */
3145         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3146
3147         /* Wait for reset to complete. */
3148         /* XXX schedule_timeout() ... */
3149         for (i = 0; i < 500; i++)
3150                 udelay(10);
3151
3152         /* Config mode; select PMA/Ch 1 regs. */
3153         tg3_writephy(tp, 0x10, 0x8411);
3154
3155         /* Enable auto-lock and comdet, select txclk for tx. */
3156         tg3_writephy(tp, 0x11, 0x0a10);
3157
3158         tg3_writephy(tp, 0x18, 0x00a0);
3159         tg3_writephy(tp, 0x16, 0x41ff);
3160
3161         /* Assert and deassert POR. */
3162         tg3_writephy(tp, 0x13, 0x0400);
3163         udelay(40);
3164         tg3_writephy(tp, 0x13, 0x0000);
3165
3166         tg3_writephy(tp, 0x11, 0x0a50);
3167         udelay(40);
3168         tg3_writephy(tp, 0x11, 0x0a10);
3169
3170         /* Wait for signal to stabilize */
3171         /* XXX schedule_timeout() ... */
3172         for (i = 0; i < 15000; i++)
3173                 udelay(10);
3174
3175         /* Deselect the channel register so we can read the PHYID
3176          * later.
3177          */
3178         tg3_writephy(tp, 0x10, 0x8011);
3179 }
3180
3181 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3182 {
3183         u16 flowctrl;
3184         u32 sg_dig_ctrl, sg_dig_status;
3185         u32 serdes_cfg, expected_sg_dig_ctrl;
3186         int workaround, port_a;
3187         int current_link_up;
3188
3189         serdes_cfg = 0;
3190         expected_sg_dig_ctrl = 0;
3191         workaround = 0;
3192         port_a = 1;
3193         current_link_up = 0;
3194
3195         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3196             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3197                 workaround = 1;
3198                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3199                         port_a = 0;
3200
3201                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3202                 /* preserve bits 20-23 for voltage regulator */
3203                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3204         }
3205
3206         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3207
3208         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3209                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3210                         if (workaround) {
3211                                 u32 val = serdes_cfg;
3212
3213                                 if (port_a)
3214                                         val |= 0xc010000;
3215                                 else
3216                                         val |= 0x4010000;
3217                                 tw32_f(MAC_SERDES_CFG, val);
3218                         }
3219
3220                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3221                 }
3222                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3223                         tg3_setup_flow_control(tp, 0, 0);
3224                         current_link_up = 1;
3225                 }
3226                 goto out;
3227         }
3228
3229         /* Want auto-negotiation.  */
3230         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3231
3232         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3233         if (flowctrl & ADVERTISE_1000XPAUSE)
3234                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3235         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3236                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3237
3238         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3239                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3240                     tp->serdes_counter &&
3241                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3242                                     MAC_STATUS_RCVD_CFG)) ==
3243                      MAC_STATUS_PCS_SYNCED)) {
3244                         tp->serdes_counter--;
3245                         current_link_up = 1;
3246                         goto out;
3247                 }
3248 restart_autoneg:
3249                 if (workaround)
3250                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3251                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3252                 udelay(5);
3253                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3254
3255                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3256                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3257         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3258                                  MAC_STATUS_SIGNAL_DET)) {
3259                 sg_dig_status = tr32(SG_DIG_STATUS);
3260                 mac_status = tr32(MAC_STATUS);
3261
3262                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3263                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3264                         u32 local_adv = 0, remote_adv = 0;
3265
3266                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3267                                 local_adv |= ADVERTISE_1000XPAUSE;
3268                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3269                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3270
3271                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3272                                 remote_adv |= LPA_1000XPAUSE;
3273                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3274                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3275
3276                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3277                         current_link_up = 1;
3278                         tp->serdes_counter = 0;
3279                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3280                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3281                         if (tp->serdes_counter)
3282                                 tp->serdes_counter--;
3283                         else {
3284                                 if (workaround) {
3285                                         u32 val = serdes_cfg;
3286
3287                                         if (port_a)
3288                                                 val |= 0xc010000;
3289                                         else
3290                                                 val |= 0x4010000;
3291
3292                                         tw32_f(MAC_SERDES_CFG, val);
3293                                 }
3294
3295                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3296                                 udelay(40);
3297
3298                                 /* Link parallel detection - link is up */
3299                                 /* only if we have PCS_SYNC and not */
3300                                 /* receiving config code words */
3301                                 mac_status = tr32(MAC_STATUS);
3302                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3303                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3304                                         tg3_setup_flow_control(tp, 0, 0);
3305                                         current_link_up = 1;
3306                                         tp->tg3_flags2 |=
3307                                                 TG3_FLG2_PARALLEL_DETECT;
3308                                         tp->serdes_counter =
3309                                                 SERDES_PARALLEL_DET_TIMEOUT;
3310                                 } else
3311                                         goto restart_autoneg;
3312                         }
3313                 }
3314         } else {
3315                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3316                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3317         }
3318
3319 out:
3320         return current_link_up;
3321 }
3322
3323 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3324 {
3325         int current_link_up = 0;
3326
3327         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3328                 goto out;
3329
3330         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3331                 u32 txflags, rxflags;
3332                 int i;
3333
3334                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3335                         u32 local_adv = 0, remote_adv = 0;
3336
3337                         if (txflags & ANEG_CFG_PS1)
3338                                 local_adv |= ADVERTISE_1000XPAUSE;
3339                         if (txflags & ANEG_CFG_PS2)
3340                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3341
3342                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3343                                 remote_adv |= LPA_1000XPAUSE;
3344                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3345                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3346
3347                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3348
3349                         current_link_up = 1;
3350                 }
3351                 for (i = 0; i < 30; i++) {
3352                         udelay(20);
3353                         tw32_f(MAC_STATUS,
3354                                (MAC_STATUS_SYNC_CHANGED |
3355                                 MAC_STATUS_CFG_CHANGED));
3356                         udelay(40);
3357                         if ((tr32(MAC_STATUS) &
3358                              (MAC_STATUS_SYNC_CHANGED |
3359                               MAC_STATUS_CFG_CHANGED)) == 0)
3360                                 break;
3361                 }
3362
3363                 mac_status = tr32(MAC_STATUS);
3364                 if (current_link_up == 0 &&
3365                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3366                     !(mac_status & MAC_STATUS_RCVD_CFG))
3367                         current_link_up = 1;
3368         } else {
3369                 tg3_setup_flow_control(tp, 0, 0);
3370
3371                 /* Forcing 1000FD link up. */
3372                 current_link_up = 1;
3373
3374                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3375                 udelay(40);
3376
3377                 tw32_f(MAC_MODE, tp->mac_mode);
3378                 udelay(40);
3379         }
3380
3381 out:
3382         return current_link_up;
3383 }
3384
3385 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3386 {
3387         u32 orig_pause_cfg;
3388         u16 orig_active_speed;
3389         u8 orig_active_duplex;
3390         u32 mac_status;
3391         int current_link_up;
3392         int i;
3393
3394         orig_pause_cfg = tp->link_config.active_flowctrl;
3395         orig_active_speed = tp->link_config.active_speed;
3396         orig_active_duplex = tp->link_config.active_duplex;
3397
3398         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3399             netif_carrier_ok(tp->dev) &&
3400             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3401                 mac_status = tr32(MAC_STATUS);
3402                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3403                                MAC_STATUS_SIGNAL_DET |
3404                                MAC_STATUS_CFG_CHANGED |
3405                                MAC_STATUS_RCVD_CFG);
3406                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3407                                    MAC_STATUS_SIGNAL_DET)) {
3408                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3409                                             MAC_STATUS_CFG_CHANGED));
3410                         return 0;
3411                 }
3412         }
3413
3414         tw32_f(MAC_TX_AUTO_NEG, 0);
3415
3416         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3417         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3418         tw32_f(MAC_MODE, tp->mac_mode);
3419         udelay(40);
3420
3421         if (tp->phy_id == PHY_ID_BCM8002)
3422                 tg3_init_bcm8002(tp);
3423
3424         /* Enable link change event even when serdes polling.  */
3425         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3426         udelay(40);
3427
3428         current_link_up = 0;
3429         mac_status = tr32(MAC_STATUS);
3430
3431         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3432                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3433         else
3434                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3435
3436         tp->hw_status->status =
3437                 (SD_STATUS_UPDATED |
3438                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3439
3440         for (i = 0; i < 100; i++) {
3441                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3442                                     MAC_STATUS_CFG_CHANGED));
3443                 udelay(5);
3444                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3445                                          MAC_STATUS_CFG_CHANGED |
3446                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3447                         break;
3448         }
3449
3450         mac_status = tr32(MAC_STATUS);
3451         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3452                 current_link_up = 0;
3453                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3454                     tp->serdes_counter == 0) {
3455                         tw32_f(MAC_MODE, (tp->mac_mode |
3456                                           MAC_MODE_SEND_CONFIGS));
3457                         udelay(1);
3458                         tw32_f(MAC_MODE, tp->mac_mode);
3459                 }
3460         }
3461
3462         if (current_link_up == 1) {
3463                 tp->link_config.active_speed = SPEED_1000;
3464                 tp->link_config.active_duplex = DUPLEX_FULL;
3465                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3466                                     LED_CTRL_LNKLED_OVERRIDE |
3467                                     LED_CTRL_1000MBPS_ON));
3468         } else {
3469                 tp->link_config.active_speed = SPEED_INVALID;
3470                 tp->link_config.active_duplex = DUPLEX_INVALID;
3471                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3472                                     LED_CTRL_LNKLED_OVERRIDE |
3473                                     LED_CTRL_TRAFFIC_OVERRIDE));
3474         }
3475
3476         if (current_link_up != netif_carrier_ok(tp->dev)) {
3477                 if (current_link_up)
3478                         netif_carrier_on(tp->dev);
3479                 else
3480                         netif_carrier_off(tp->dev);
3481                 tg3_link_report(tp);
3482         } else {
3483                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3484                 if (orig_pause_cfg != now_pause_cfg ||
3485                     orig_active_speed != tp->link_config.active_speed ||
3486                     orig_active_duplex != tp->link_config.active_duplex)
3487                         tg3_link_report(tp);
3488         }
3489
3490         return 0;
3491 }
3492
3493 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3494 {
3495         int current_link_up, err = 0;
3496         u32 bmsr, bmcr;
3497         u16 current_speed;
3498         u8 current_duplex;
3499         u32 local_adv, remote_adv;
3500
3501         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3502         tw32_f(MAC_MODE, tp->mac_mode);
3503         udelay(40);
3504
3505         tw32(MAC_EVENT, 0);
3506
3507         tw32_f(MAC_STATUS,
3508              (MAC_STATUS_SYNC_CHANGED |
3509               MAC_STATUS_CFG_CHANGED |
3510               MAC_STATUS_MI_COMPLETION |
3511               MAC_STATUS_LNKSTATE_CHANGED));
3512         udelay(40);
3513
3514         if (force_reset)
3515                 tg3_phy_reset(tp);
3516
3517         current_link_up = 0;
3518         current_speed = SPEED_INVALID;
3519         current_duplex = DUPLEX_INVALID;
3520
3521         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3522         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3523         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3524                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3525                         bmsr |= BMSR_LSTATUS;
3526                 else
3527                         bmsr &= ~BMSR_LSTATUS;
3528         }
3529
3530         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3531
3532         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3533             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3534                 /* do nothing, just check for link up at the end */
3535         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3536                 u32 adv, new_adv;
3537
3538                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3539                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3540                                   ADVERTISE_1000XPAUSE |
3541                                   ADVERTISE_1000XPSE_ASYM |
3542                                   ADVERTISE_SLCT);
3543
3544                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3545
3546                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3547                         new_adv |= ADVERTISE_1000XHALF;
3548                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3549                         new_adv |= ADVERTISE_1000XFULL;
3550
3551                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3552                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3553                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3554                         tg3_writephy(tp, MII_BMCR, bmcr);
3555
3556                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3557                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3558                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3559
3560                         return err;
3561                 }
3562         } else {
3563                 u32 new_bmcr;
3564
3565                 bmcr &= ~BMCR_SPEED1000;
3566                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3567
3568                 if (tp->link_config.duplex == DUPLEX_FULL)
3569                         new_bmcr |= BMCR_FULLDPLX;
3570
3571                 if (new_bmcr != bmcr) {
3572                         /* BMCR_SPEED1000 is a reserved bit that needs
3573                          * to be set on write.
3574                          */
3575                         new_bmcr |= BMCR_SPEED1000;
3576
3577                         /* Force a linkdown */
3578                         if (netif_carrier_ok(tp->dev)) {
3579                                 u32 adv;
3580
3581                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3582                                 adv &= ~(ADVERTISE_1000XFULL |
3583                                          ADVERTISE_1000XHALF |
3584                                          ADVERTISE_SLCT);
3585                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3586                                 tg3_writephy(tp, MII_BMCR, bmcr |
3587                                                            BMCR_ANRESTART |
3588                                                            BMCR_ANENABLE);
3589                                 udelay(10);
3590                                 netif_carrier_off(tp->dev);
3591                         }
3592                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3593                         bmcr = new_bmcr;
3594                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3595                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3596                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3597                             ASIC_REV_5714) {
3598                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3599                                         bmsr |= BMSR_LSTATUS;
3600                                 else
3601                                         bmsr &= ~BMSR_LSTATUS;
3602                         }
3603                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3604                 }
3605         }
3606
3607         if (bmsr & BMSR_LSTATUS) {
3608                 current_speed = SPEED_1000;
3609                 current_link_up = 1;
3610                 if (bmcr & BMCR_FULLDPLX)
3611                         current_duplex = DUPLEX_FULL;
3612                 else
3613                         current_duplex = DUPLEX_HALF;
3614
3615                 local_adv = 0;
3616                 remote_adv = 0;
3617
3618                 if (bmcr & BMCR_ANENABLE) {
3619                         u32 common;
3620
3621                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3622                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3623                         common = local_adv & remote_adv;
3624                         if (common & (ADVERTISE_1000XHALF |
3625                                       ADVERTISE_1000XFULL)) {
3626                                 if (common & ADVERTISE_1000XFULL)
3627                                         current_duplex = DUPLEX_FULL;
3628                                 else
3629                                         current_duplex = DUPLEX_HALF;
3630                         }
3631                         else
3632                                 current_link_up = 0;
3633                 }
3634         }
3635
3636         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3637                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3638
3639         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3640         if (tp->link_config.active_duplex == DUPLEX_HALF)
3641                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3642
3643         tw32_f(MAC_MODE, tp->mac_mode);
3644         udelay(40);
3645
3646         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3647
3648         tp->link_config.active_speed = current_speed;
3649         tp->link_config.active_duplex = current_duplex;
3650
3651         if (current_link_up != netif_carrier_ok(tp->dev)) {
3652                 if (current_link_up)
3653                         netif_carrier_on(tp->dev);
3654                 else {
3655                         netif_carrier_off(tp->dev);
3656                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3657                 }
3658                 tg3_link_report(tp);
3659         }
3660         return err;
3661 }
3662
3663 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3664 {
3665         if (tp->serdes_counter) {
3666                 /* Give autoneg time to complete. */
3667                 tp->serdes_counter--;
3668                 return;
3669         }
3670         if (!netif_carrier_ok(tp->dev) &&
3671             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3672                 u32 bmcr;
3673
3674                 tg3_readphy(tp, MII_BMCR, &bmcr);
3675                 if (bmcr & BMCR_ANENABLE) {
3676                         u32 phy1, phy2;
3677
3678                         /* Select shadow register 0x1f */
3679                         tg3_writephy(tp, 0x1c, 0x7c00);
3680                         tg3_readphy(tp, 0x1c, &phy1);
3681
3682                         /* Select expansion interrupt status register */
3683                         tg3_writephy(tp, 0x17, 0x0f01);
3684                         tg3_readphy(tp, 0x15, &phy2);
3685                         tg3_readphy(tp, 0x15, &phy2);
3686
3687                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3688                                 /* We have signal detect and not receiving
3689                                  * config code words, link is up by parallel
3690                                  * detection.
3691                                  */
3692
3693                                 bmcr &= ~BMCR_ANENABLE;
3694                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3695                                 tg3_writephy(tp, MII_BMCR, bmcr);
3696                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3697                         }
3698                 }
3699         }
3700         else if (netif_carrier_ok(tp->dev) &&
3701                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3702                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3703                 u32 phy2;
3704
3705                 /* Select expansion interrupt status register */
3706                 tg3_writephy(tp, 0x17, 0x0f01);
3707                 tg3_readphy(tp, 0x15, &phy2);
3708                 if (phy2 & 0x20) {
3709                         u32 bmcr;
3710
3711                         /* Config code words received, turn on autoneg. */
3712                         tg3_readphy(tp, MII_BMCR, &bmcr);
3713                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3714
3715                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3716
3717                 }
3718         }
3719 }
3720
3721 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3722 {
3723         int err;
3724
3725         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3726                 err = tg3_setup_fiber_phy(tp, force_reset);
3727         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3728                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3729         } else {
3730                 err = tg3_setup_copper_phy(tp, force_reset);
3731         }
3732
3733         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3734             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3735                 u32 val, scale;
3736
3737                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3738                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3739                         scale = 65;
3740                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3741                         scale = 6;
3742                 else
3743                         scale = 12;
3744
3745                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3746                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3747                 tw32(GRC_MISC_CFG, val);
3748         }
3749
3750         if (tp->link_config.active_speed == SPEED_1000 &&
3751             tp->link_config.active_duplex == DUPLEX_HALF)
3752                 tw32(MAC_TX_LENGTHS,
3753                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3754                       (6 << TX_LENGTHS_IPG_SHIFT) |
3755                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3756         else
3757                 tw32(MAC_TX_LENGTHS,
3758                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3759                       (6 << TX_LENGTHS_IPG_SHIFT) |
3760                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3761
3762         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3763                 if (netif_carrier_ok(tp->dev)) {
3764                         tw32(HOSTCC_STAT_COAL_TICKS,
3765                              tp->coal.stats_block_coalesce_usecs);
3766                 } else {
3767                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3768                 }
3769         }
3770
3771         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3772                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3773                 if (!netif_carrier_ok(tp->dev))
3774                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3775                               tp->pwrmgmt_thresh;
3776                 else
3777                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3778                 tw32(PCIE_PWR_MGMT_THRESH, val);
3779         }
3780
3781         return err;
3782 }
3783
3784 /* This is called whenever we suspect that the system chipset is re-
3785  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3786  * is bogus tx completions. We try to recover by setting the
3787  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3788  * in the workqueue.
3789  */
3790 static void tg3_tx_recover(struct tg3 *tp)
3791 {
3792         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3793                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3794
3795         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3796                "mapped I/O cycles to the network device, attempting to "
3797                "recover. Please report the problem to the driver maintainer "
3798                "and include system chipset information.\n", tp->dev->name);
3799
3800         spin_lock(&tp->lock);
3801         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3802         spin_unlock(&tp->lock);
3803 }
3804
3805 static inline u32 tg3_tx_avail(struct tg3 *tp)
3806 {
3807         smp_mb();
3808         return (tp->tx_pending -
3809                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3810 }
3811
3812 /* Tigon3 never reports partial packet sends.  So we do not
3813  * need special logic to handle SKBs that have not had all
3814  * of their frags sent yet, like SunGEM does.
3815  */
3816 static void tg3_tx(struct tg3 *tp)
3817 {
3818         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3819         u32 sw_idx = tp->tx_cons;
3820
3821         while (sw_idx != hw_idx) {
3822                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3823                 struct sk_buff *skb = ri->skb;
3824                 int i, tx_bug = 0;
3825
3826                 if (unlikely(skb == NULL)) {
3827                         tg3_tx_recover(tp);
3828                         return;
3829                 }
3830
3831                 pci_unmap_single(tp->pdev,
3832                                  pci_unmap_addr(ri, mapping),
3833                                  skb_headlen(skb),
3834                                  PCI_DMA_TODEVICE);
3835
3836                 ri->skb = NULL;
3837
3838                 sw_idx = NEXT_TX(sw_idx);
3839
3840                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3841                         ri = &tp->tx_buffers[sw_idx];
3842                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3843                                 tx_bug = 1;
3844
3845                         pci_unmap_page(tp->pdev,
3846                                        pci_unmap_addr(ri, mapping),
3847                                        skb_shinfo(skb)->frags[i].size,
3848                                        PCI_DMA_TODEVICE);
3849
3850                         sw_idx = NEXT_TX(sw_idx);
3851                 }
3852
3853                 dev_kfree_skb(skb);
3854
3855                 if (unlikely(tx_bug)) {
3856                         tg3_tx_recover(tp);
3857                         return;
3858                 }
3859         }
3860
3861         tp->tx_cons = sw_idx;
3862
3863         /* Need to make the tx_cons update visible to tg3_start_xmit()
3864          * before checking for netif_queue_stopped().  Without the
3865          * memory barrier, there is a small possibility that tg3_start_xmit()
3866          * will miss it and cause the queue to be stopped forever.
3867          */
3868         smp_mb();
3869
3870         if (unlikely(netif_queue_stopped(tp->dev) &&
3871                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3872                 netif_tx_lock(tp->dev);
3873                 if (netif_queue_stopped(tp->dev) &&
3874                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3875                         netif_wake_queue(tp->dev);
3876                 netif_tx_unlock(tp->dev);
3877         }
3878 }
3879
3880 /* Returns size of skb allocated or < 0 on error.
3881  *
3882  * We only need to fill in the address because the other members
3883  * of the RX descriptor are invariant, see tg3_init_rings.
3884  *
3885  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3886  * posting buffers we only dirty the first cache line of the RX
3887  * descriptor (containing the address).  Whereas for the RX status
3888  * buffers the cpu only reads the last cacheline of the RX descriptor
3889  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3890  */
3891 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3892                             int src_idx, u32 dest_idx_unmasked)
3893 {
3894         struct tg3_rx_buffer_desc *desc;
3895         struct ring_info *map, *src_map;
3896         struct sk_buff *skb;
3897         dma_addr_t mapping;
3898         int skb_size, dest_idx;
3899
3900         src_map = NULL;
3901         switch (opaque_key) {
3902         case RXD_OPAQUE_RING_STD:
3903                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3904                 desc = &tp->rx_std[dest_idx];
3905                 map = &tp->rx_std_buffers[dest_idx];
3906                 if (src_idx >= 0)
3907                         src_map = &tp->rx_std_buffers[src_idx];
3908                 skb_size = tp->rx_pkt_buf_sz;
3909                 break;
3910
3911         case RXD_OPAQUE_RING_JUMBO:
3912                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3913                 desc = &tp->rx_jumbo[dest_idx];
3914                 map = &tp->rx_jumbo_buffers[dest_idx];
3915                 if (src_idx >= 0)
3916                         src_map = &tp->rx_jumbo_buffers[src_idx];
3917                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3918                 break;
3919
3920         default:
3921                 return -EINVAL;
3922         }
3923
3924         /* Do not overwrite any of the map or rp information
3925          * until we are sure we can commit to a new buffer.
3926          *
3927          * Callers depend upon this behavior and assume that
3928          * we leave everything unchanged if we fail.
3929          */
3930         skb = netdev_alloc_skb(tp->dev, skb_size);
3931         if (skb == NULL)
3932                 return -ENOMEM;
3933
3934         skb_reserve(skb, tp->rx_offset);
3935
3936         mapping = pci_map_single(tp->pdev, skb->data,
3937                                  skb_size - tp->rx_offset,
3938                                  PCI_DMA_FROMDEVICE);
3939
3940         map->skb = skb;
3941         pci_unmap_addr_set(map, mapping, mapping);
3942
3943         if (src_map != NULL)
3944                 src_map->skb = NULL;
3945
3946         desc->addr_hi = ((u64)mapping >> 32);
3947         desc->addr_lo = ((u64)mapping & 0xffffffff);
3948
3949         return skb_size;
3950 }
3951
3952 /* We only need to move over in the address because the other
3953  * members of the RX descriptor are invariant.  See notes above
3954  * tg3_alloc_rx_skb for full details.
3955  */
3956 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3957                            int src_idx, u32 dest_idx_unmasked)
3958 {
3959         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3960         struct ring_info *src_map, *dest_map;
3961         int dest_idx;
3962
3963         switch (opaque_key) {
3964         case RXD_OPAQUE_RING_STD:
3965                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3966                 dest_desc = &tp->rx_std[dest_idx];
3967                 dest_map = &tp->rx_std_buffers[dest_idx];
3968                 src_desc = &tp->rx_std[src_idx];
3969                 src_map = &tp->rx_std_buffers[src_idx];
3970                 break;
3971
3972         case RXD_OPAQUE_RING_JUMBO:
3973                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3974                 dest_desc = &tp->rx_jumbo[dest_idx];
3975                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3976                 src_desc = &tp->rx_jumbo[src_idx];
3977                 src_map = &tp->rx_jumbo_buffers[src_idx];
3978                 break;
3979
3980         default:
3981                 return;
3982         }
3983
3984         dest_map->skb = src_map->skb;
3985         pci_unmap_addr_set(dest_map, mapping,
3986                            pci_unmap_addr(src_map, mapping));
3987         dest_desc->addr_hi = src_desc->addr_hi;
3988         dest_desc->addr_lo = src_desc->addr_lo;
3989
3990         src_map->skb = NULL;
3991 }
3992
3993 #if TG3_VLAN_TAG_USED
3994 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3995 {
3996         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3997 }
3998 #endif
3999
4000 /* The RX ring scheme is composed of multiple rings which post fresh
4001  * buffers to the chip, and one special ring the chip uses to report
4002  * status back to the host.
4003  *
4004  * The special ring reports the status of received packets to the
4005  * host.  The chip does not write into the original descriptor the
4006  * RX buffer was obtained from.  The chip simply takes the original
4007  * descriptor as provided by the host, updates the status and length
4008  * field, then writes this into the next status ring entry.
4009  *
4010  * Each ring the host uses to post buffers to the chip is described
4011  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4012  * it is first placed into the on-chip ram.  When the packet's length
4013  * is known, it walks down the TG3_BDINFO entries to select the ring.
4014  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4015  * which is within the range of the new packet's length is chosen.
4016  *
4017  * The "separate ring for rx status" scheme may sound queer, but it makes
4018  * sense from a cache coherency perspective.  If only the host writes
4019  * to the buffer post rings, and only the chip writes to the rx status
4020  * rings, then cache lines never move beyond shared-modified state.
4021  * If both the host and chip were to write into the same ring, cache line
4022  * eviction could occur since both entities want it in an exclusive state.
4023  */
4024 static int tg3_rx(struct tg3 *tp, int budget)
4025 {
4026         u32 work_mask, rx_std_posted = 0;
4027         u32 sw_idx = tp->rx_rcb_ptr;
4028         u16 hw_idx;
4029         int received;
4030
4031         hw_idx = tp->hw_status->idx[0].rx_producer;
4032         /*
4033          * We need to order the read of hw_idx and the read of
4034          * the opaque cookie.
4035          */
4036         rmb();
4037         work_mask = 0;
4038         received = 0;
4039         while (sw_idx != hw_idx && budget > 0) {
4040                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4041                 unsigned int len;
4042                 struct sk_buff *skb;
4043                 dma_addr_t dma_addr;
4044                 u32 opaque_key, desc_idx, *post_ptr;
4045
4046                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4047                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4048                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4049                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4050                                                   mapping);
4051                         skb = tp->rx_std_buffers[desc_idx].skb;
4052                         post_ptr = &tp->rx_std_ptr;
4053                         rx_std_posted++;
4054                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4055                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4056                                                   mapping);
4057                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4058                         post_ptr = &tp->rx_jumbo_ptr;
4059                 }
4060                 else {
4061                         goto next_pkt_nopost;
4062                 }
4063
4064                 work_mask |= opaque_key;
4065
4066                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4067                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4068                 drop_it:
4069                         tg3_recycle_rx(tp, opaque_key,
4070                                        desc_idx, *post_ptr);
4071                 drop_it_no_recycle:
4072                         /* Other statistics kept track of by card. */
4073                         tp->net_stats.rx_dropped++;
4074                         goto next_pkt;
4075                 }
4076
4077                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4078
4079                 if (len > RX_COPY_THRESHOLD
4080                         && tp->rx_offset == 2
4081                         /* rx_offset != 2 iff this is a 5701 card running
4082                          * in PCI-X mode [see tg3_get_invariants()] */
4083                 ) {
4084                         int skb_size;
4085
4086                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4087                                                     desc_idx, *post_ptr);
4088                         if (skb_size < 0)
4089                                 goto drop_it;
4090
4091                         pci_unmap_single(tp->pdev, dma_addr,
4092                                          skb_size - tp->rx_offset,
4093                                          PCI_DMA_FROMDEVICE);
4094
4095                         skb_put(skb, len);
4096                 } else {
4097                         struct sk_buff *copy_skb;
4098
4099                         tg3_recycle_rx(tp, opaque_key,
4100                                        desc_idx, *post_ptr);
4101
4102                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4103                         if (copy_skb == NULL)
4104                                 goto drop_it_no_recycle;
4105
4106                         skb_reserve(copy_skb, 2);
4107                         skb_put(copy_skb, len);
4108                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4109                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4110                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4111
4112                         /* We'll reuse the original ring buffer. */
4113                         skb = copy_skb;
4114                 }
4115
4116                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4117                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4118                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4119                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4120                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4121                 else
4122                         skb->ip_summed = CHECKSUM_NONE;
4123
4124                 skb->protocol = eth_type_trans(skb, tp->dev);
4125 #if TG3_VLAN_TAG_USED
4126                 if (tp->vlgrp != NULL &&
4127                     desc->type_flags & RXD_FLAG_VLAN) {
4128                         tg3_vlan_rx(tp, skb,
4129                                     desc->err_vlan & RXD_VLAN_MASK);
4130                 } else
4131 #endif
4132                         netif_receive_skb(skb);
4133
4134                 tp->dev->last_rx = jiffies;
4135                 received++;
4136                 budget--;
4137
4138 next_pkt:
4139                 (*post_ptr)++;
4140
4141                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4142                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4143
4144                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4145                                      TG3_64BIT_REG_LOW, idx);
4146                         work_mask &= ~RXD_OPAQUE_RING_STD;
4147                         rx_std_posted = 0;
4148                 }
4149 next_pkt_nopost:
4150                 sw_idx++;
4151                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4152
4153                 /* Refresh hw_idx to see if there is new work */
4154                 if (sw_idx == hw_idx) {
4155                         hw_idx = tp->hw_status->idx[0].rx_producer;
4156                         rmb();
4157                 }
4158         }
4159
4160         /* ACK the status ring. */
4161         tp->rx_rcb_ptr = sw_idx;
4162         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4163
4164         /* Refill RX ring(s). */
4165         if (work_mask & RXD_OPAQUE_RING_STD) {
4166                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4167                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4168                              sw_idx);
4169         }
4170         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4171                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4172                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4173                              sw_idx);
4174         }
4175         mmiowb();
4176
4177         return received;
4178 }
4179
4180 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4181 {
4182         struct tg3_hw_status *sblk = tp->hw_status;
4183
4184         /* handle link change and other phy events */
4185         if (!(tp->tg3_flags &
4186               (TG3_FLAG_USE_LINKCHG_REG |
4187                TG3_FLAG_POLL_SERDES))) {
4188                 if (sblk->status & SD_STATUS_LINK_CHG) {
4189                         sblk->status = SD_STATUS_UPDATED |
4190                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4191                         spin_lock(&tp->lock);
4192                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4193                                 tw32_f(MAC_STATUS,
4194                                      (MAC_STATUS_SYNC_CHANGED |
4195                                       MAC_STATUS_CFG_CHANGED |
4196                                       MAC_STATUS_MI_COMPLETION |
4197                                       MAC_STATUS_LNKSTATE_CHANGED));
4198                                 udelay(40);
4199                         } else
4200                                 tg3_setup_phy(tp, 0);
4201                         spin_unlock(&tp->lock);
4202                 }
4203         }
4204
4205         /* run TX completion thread */
4206         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4207                 tg3_tx(tp);
4208                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4209                         return work_done;
4210         }
4211
4212         /* run RX thread, within the bounds set by NAPI.
4213          * All RX "locking" is done by ensuring outside
4214          * code synchronizes with tg3->napi.poll()
4215          */
4216         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4217                 work_done += tg3_rx(tp, budget - work_done);
4218
4219         return work_done;
4220 }
4221
4222 static int tg3_poll(struct napi_struct *napi, int budget)
4223 {
4224         struct tg3 *tp = container_of(napi, struct tg3, napi);
4225         int work_done = 0;
4226         struct tg3_hw_status *sblk = tp->hw_status;
4227
4228         while (1) {
4229                 work_done = tg3_poll_work(tp, work_done, budget);
4230
4231                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4232                         goto tx_recovery;
4233
4234                 if (unlikely(work_done >= budget))
4235                         break;
4236
4237                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4238                         /* tp->last_tag is used in tg3_restart_ints() below
4239                          * to tell the hw how much work has been processed,
4240                          * so we must read it before checking for more work.
4241                          */
4242                         tp->last_tag = sblk->status_tag;
4243                         rmb();
4244                 } else
4245                         sblk->status &= ~SD_STATUS_UPDATED;
4246
4247                 if (likely(!tg3_has_work(tp))) {
4248                         netif_rx_complete(tp->dev, napi);
4249                         tg3_restart_ints(tp);
4250                         break;
4251                 }
4252         }
4253
4254         return work_done;
4255
4256 tx_recovery:
4257         /* work_done is guaranteed to be less than budget. */
4258         netif_rx_complete(tp->dev, napi);
4259         schedule_work(&tp->reset_task);
4260         return work_done;
4261 }
4262
4263 static void tg3_irq_quiesce(struct tg3 *tp)
4264 {
4265         BUG_ON(tp->irq_sync);
4266
4267         tp->irq_sync = 1;
4268         smp_mb();
4269
4270         synchronize_irq(tp->pdev->irq);
4271 }
4272
4273 static inline int tg3_irq_sync(struct tg3 *tp)
4274 {
4275         return tp->irq_sync;
4276 }
4277
4278 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4279  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4280  * with as well.  Most of the time, this is not necessary except when
4281  * shutting down the device.
4282  */
4283 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4284 {
4285         spin_lock_bh(&tp->lock);
4286         if (irq_sync)
4287                 tg3_irq_quiesce(tp);
4288 }
4289
4290 static inline void tg3_full_unlock(struct tg3 *tp)
4291 {
4292         spin_unlock_bh(&tp->lock);
4293 }
4294
4295 /* One-shot MSI handler - Chip automatically disables interrupt
4296  * after sending MSI so driver doesn't have to do it.
4297  */
4298 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4299 {
4300         struct net_device *dev = dev_id;
4301         struct tg3 *tp = netdev_priv(dev);
4302
4303         prefetch(tp->hw_status);
4304         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4305
4306         if (likely(!tg3_irq_sync(tp)))
4307                 netif_rx_schedule(dev, &tp->napi);
4308
4309         return IRQ_HANDLED;
4310 }
4311
4312 /* MSI ISR - No need to check for interrupt sharing and no need to
4313  * flush status block and interrupt mailbox. PCI ordering rules
4314  * guarantee that MSI will arrive after the status block.
4315  */
4316 static irqreturn_t tg3_msi(int irq, void *dev_id)
4317 {
4318         struct net_device *dev = dev_id;
4319         struct tg3 *tp = netdev_priv(dev);
4320
4321         prefetch(tp->hw_status);
4322         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4323         /*
4324          * Writing any value to intr-mbox-0 clears PCI INTA# and
4325          * chip-internal interrupt pending events.
4326          * Writing non-zero to intr-mbox-0 additional tells the
4327          * NIC to stop sending us irqs, engaging "in-intr-handler"
4328          * event coalescing.
4329          */
4330         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4331         if (likely(!tg3_irq_sync(tp)))
4332                 netif_rx_schedule(dev, &tp->napi);
4333
4334         return IRQ_RETVAL(1);
4335 }
4336
4337 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4338 {
4339         struct net_device *dev = dev_id;
4340         struct tg3 *tp = netdev_priv(dev);
4341         struct tg3_hw_status *sblk = tp->hw_status;
4342         unsigned int handled = 1;
4343
4344         /* In INTx mode, it is possible for the interrupt to arrive at
4345          * the CPU before the status block posted prior to the interrupt.
4346          * Reading the PCI State register will confirm whether the
4347          * interrupt is ours and will flush the status block.
4348          */
4349         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4350                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4351                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4352                         handled = 0;
4353                         goto out;
4354                 }
4355         }
4356
4357         /*
4358          * Writing any value to intr-mbox-0 clears PCI INTA# and
4359          * chip-internal interrupt pending events.
4360          * Writing non-zero to intr-mbox-0 additional tells the
4361          * NIC to stop sending us irqs, engaging "in-intr-handler"
4362          * event coalescing.
4363          *
4364          * Flush the mailbox to de-assert the IRQ immediately to prevent
4365          * spurious interrupts.  The flush impacts performance but
4366          * excessive spurious interrupts can be worse in some cases.
4367          */
4368         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4369         if (tg3_irq_sync(tp))
4370                 goto out;
4371         sblk->status &= ~SD_STATUS_UPDATED;
4372         if (likely(tg3_has_work(tp))) {
4373                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4374                 netif_rx_schedule(dev, &tp->napi);
4375         } else {
4376                 /* No work, shared interrupt perhaps?  re-enable
4377                  * interrupts, and flush that PCI write
4378                  */
4379                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4380                                0x00000000);
4381         }
4382 out:
4383         return IRQ_RETVAL(handled);
4384 }
4385
4386 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4387 {
4388         struct net_device *dev = dev_id;
4389         struct tg3 *tp = netdev_priv(dev);
4390         struct tg3_hw_status *sblk = tp->hw_status;
4391         unsigned int handled = 1;
4392
4393         /* In INTx mode, it is possible for the interrupt to arrive at
4394          * the CPU before the status block posted prior to the interrupt.
4395          * Reading the PCI State register will confirm whether the
4396          * interrupt is ours and will flush the status block.
4397          */
4398         if (unlikely(sblk->status_tag == tp->last_tag)) {
4399                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4400                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4401                         handled = 0;
4402                         goto out;
4403                 }
4404         }
4405
4406         /*
4407          * writing any value to intr-mbox-0 clears PCI INTA# and
4408          * chip-internal interrupt pending events.
4409          * writing non-zero to intr-mbox-0 additional tells the
4410          * NIC to stop sending us irqs, engaging "in-intr-handler"
4411          * event coalescing.
4412          *
4413          * Flush the mailbox to de-assert the IRQ immediately to prevent
4414          * spurious interrupts.  The flush impacts performance but
4415          * excessive spurious interrupts can be worse in some cases.
4416          */
4417         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4418         if (tg3_irq_sync(tp))
4419                 goto out;
4420         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4421                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4422                 /* Update last_tag to mark that this status has been
4423                  * seen. Because interrupt may be shared, we may be
4424                  * racing with tg3_poll(), so only update last_tag
4425                  * if tg3_poll() is not scheduled.
4426                  */
4427                 tp->last_tag = sblk->status_tag;
4428                 __netif_rx_schedule(dev, &tp->napi);
4429         }
4430 out:
4431         return IRQ_RETVAL(handled);
4432 }
4433
4434 /* ISR for interrupt test */
4435 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4436 {
4437         struct net_device *dev = dev_id;
4438         struct tg3 *tp = netdev_priv(dev);
4439         struct tg3_hw_status *sblk = tp->hw_status;
4440
4441         if ((sblk->status & SD_STATUS_UPDATED) ||
4442             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4443                 tg3_disable_ints(tp);
4444                 return IRQ_RETVAL(1);
4445         }
4446         return IRQ_RETVAL(0);
4447 }
4448
4449 static int tg3_init_hw(struct tg3 *, int);
4450 static int tg3_halt(struct tg3 *, int, int);
4451
4452 /* Restart hardware after configuration changes, self-test, etc.
4453  * Invoked with tp->lock held.
4454  */
4455 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4456         __releases(tp->lock)
4457         __acquires(tp->lock)
4458 {
4459         int err;
4460
4461         err = tg3_init_hw(tp, reset_phy);
4462         if (err) {
4463                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4464                        "aborting.\n", tp->dev->name);
4465                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4466                 tg3_full_unlock(tp);
4467                 del_timer_sync(&tp->timer);
4468                 tp->irq_sync = 0;
4469                 napi_enable(&tp->napi);
4470                 dev_close(tp->dev);
4471                 tg3_full_lock(tp, 0);
4472         }
4473         return err;
4474 }
4475
4476 #ifdef CONFIG_NET_POLL_CONTROLLER
4477 static void tg3_poll_controller(struct net_device *dev)
4478 {
4479         struct tg3 *tp = netdev_priv(dev);
4480
4481         tg3_interrupt(tp->pdev->irq, dev);
4482 }
4483 #endif
4484
4485 static void tg3_reset_task(struct work_struct *work)
4486 {
4487         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4488         int err;
4489         unsigned int restart_timer;
4490
4491         tg3_full_lock(tp, 0);
4492
4493         if (!netif_running(tp->dev)) {
4494                 tg3_full_unlock(tp);
4495                 return;
4496         }
4497
4498         tg3_full_unlock(tp);
4499
4500         tg3_phy_stop(tp);
4501
4502         tg3_netif_stop(tp);
4503
4504         tg3_full_lock(tp, 1);
4505
4506         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4507         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4508
4509         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4510                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4511                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4512                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4513                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4514         }
4515
4516         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4517         err = tg3_init_hw(tp, 1);
4518         if (err)
4519                 goto out;
4520
4521         tg3_netif_start(tp);
4522
4523         if (restart_timer)
4524                 mod_timer(&tp->timer, jiffies + 1);
4525
4526 out:
4527         tg3_full_unlock(tp);
4528
4529         if (!err)
4530                 tg3_phy_start(tp);
4531 }
4532
4533 static void tg3_dump_short_state(struct tg3 *tp)
4534 {
4535         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4536                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4537         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4538                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4539 }
4540
4541 static void tg3_tx_timeout(struct net_device *dev)
4542 {
4543         struct tg3 *tp = netdev_priv(dev);
4544
4545         if (netif_msg_tx_err(tp)) {
4546                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4547                        dev->name);
4548                 tg3_dump_short_state(tp);
4549         }
4550
4551         schedule_work(&tp->reset_task);
4552 }
4553
4554 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4555 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4556 {
4557         u32 base = (u32) mapping & 0xffffffff;
4558
4559         return ((base > 0xffffdcc0) &&
4560                 (base + len + 8 < base));
4561 }
4562
4563 /* Test for DMA addresses > 40-bit */
4564 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4565                                           int len)
4566 {
4567 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4568         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4569                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4570         return 0;
4571 #else
4572         return 0;
4573 #endif
4574 }
4575
4576 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4577
4578 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4579 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4580                                        u32 last_plus_one, u32 *start,
4581                                        u32 base_flags, u32 mss)
4582 {
4583         struct sk_buff *new_skb;
4584         dma_addr_t new_addr = 0;
4585         u32 entry = *start;
4586         int i, ret = 0;
4587
4588         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4589                 new_skb = skb_copy(skb, GFP_ATOMIC);
4590         else {
4591                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4592
4593                 new_skb = skb_copy_expand(skb,
4594                                           skb_headroom(skb) + more_headroom,
4595                                           skb_tailroom(skb), GFP_ATOMIC);
4596         }
4597
4598         if (!new_skb) {
4599                 ret = -1;
4600         } else {
4601                 /* New SKB is guaranteed to be linear. */
4602                 entry = *start;
4603                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4604                                           PCI_DMA_TODEVICE);
4605                 /* Make sure new skb does not cross any 4G boundaries.
4606                  * Drop the packet if it does.
4607                  */
4608                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4609                         ret = -1;
4610                         dev_kfree_skb(new_skb);
4611                         new_skb = NULL;
4612                 } else {
4613                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4614                                     base_flags, 1 | (mss << 1));
4615                         *start = NEXT_TX(entry);
4616                 }
4617         }
4618
4619         /* Now clean up the sw ring entries. */
4620         i = 0;
4621         while (entry != last_plus_one) {
4622                 int len;
4623
4624                 if (i == 0)
4625                         len = skb_headlen(skb);
4626                 else
4627                         len = skb_shinfo(skb)->frags[i-1].size;
4628                 pci_unmap_single(tp->pdev,
4629                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4630                                  len, PCI_DMA_TODEVICE);
4631                 if (i == 0) {
4632                         tp->tx_buffers[entry].skb = new_skb;
4633                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4634                 } else {
4635                         tp->tx_buffers[entry].skb = NULL;
4636                 }
4637                 entry = NEXT_TX(entry);
4638                 i++;
4639         }
4640
4641         dev_kfree_skb(skb);
4642
4643         return ret;
4644 }
4645
4646 static void tg3_set_txd(struct tg3 *tp, int entry,
4647                         dma_addr_t mapping, int len, u32 flags,
4648                         u32 mss_and_is_end)
4649 {
4650         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4651         int is_end = (mss_and_is_end & 0x1);
4652         u32 mss = (mss_and_is_end >> 1);
4653         u32 vlan_tag = 0;
4654
4655         if (is_end)
4656                 flags |= TXD_FLAG_END;
4657         if (flags & TXD_FLAG_VLAN) {
4658                 vlan_tag = flags >> 16;
4659                 flags &= 0xffff;
4660         }
4661         vlan_tag |= (mss << TXD_MSS_SHIFT);
4662
4663         txd->addr_hi = ((u64) mapping >> 32);
4664         txd->addr_lo = ((u64) mapping & 0xffffffff);
4665         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4666         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4667 }
4668
4669 /* hard_start_xmit for devices that don't have any bugs and
4670  * support TG3_FLG2_HW_TSO_2 only.
4671  */
4672 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4673 {
4674         struct tg3 *tp = netdev_priv(dev);
4675         dma_addr_t mapping;
4676         u32 len, entry, base_flags, mss;
4677
4678         len = skb_headlen(skb);
4679
4680         /* We are running in BH disabled context with netif_tx_lock
4681          * and TX reclaim runs via tp->napi.poll inside of a software
4682          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4683          * no IRQ context deadlocks to worry about either.  Rejoice!
4684          */
4685         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4686                 if (!netif_queue_stopped(dev)) {
4687                         netif_stop_queue(dev);
4688
4689                         /* This is a hard error, log it. */
4690                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4691                                "queue awake!\n", dev->name);
4692                 }
4693                 return NETDEV_TX_BUSY;
4694         }
4695
4696         entry = tp->tx_prod;
4697         base_flags = 0;
4698         mss = 0;
4699         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4700                 int tcp_opt_len, ip_tcp_len;
4701
4702                 if (skb_header_cloned(skb) &&
4703                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4704                         dev_kfree_skb(skb);
4705                         goto out_unlock;
4706                 }
4707
4708                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4709                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4710                 else {
4711                         struct iphdr *iph = ip_hdr(skb);
4712
4713                         tcp_opt_len = tcp_optlen(skb);
4714                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4715
4716                         iph->check = 0;
4717                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4718                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4719                 }
4720
4721                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4722                                TXD_FLAG_CPU_POST_DMA);
4723
4724                 tcp_hdr(skb)->check = 0;
4725
4726         }
4727         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4728                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4729 #if TG3_VLAN_TAG_USED
4730         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4731                 base_flags |= (TXD_FLAG_VLAN |
4732                                (vlan_tx_tag_get(skb) << 16));
4733 #endif
4734
4735         /* Queue skb data, a.k.a. the main skb fragment. */
4736         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4737
4738         tp->tx_buffers[entry].skb = skb;
4739         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4740
4741         tg3_set_txd(tp, entry, mapping, len, base_flags,
4742                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4743
4744         entry = NEXT_TX(entry);
4745
4746         /* Now loop through additional data fragments, and queue them. */
4747         if (skb_shinfo(skb)->nr_frags > 0) {
4748                 unsigned int i, last;
4749
4750                 last = skb_shinfo(skb)->nr_frags - 1;
4751                 for (i = 0; i <= last; i++) {
4752                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4753
4754                         len = frag->size;
4755                         mapping = pci_map_page(tp->pdev,
4756                                                frag->page,
4757                                                frag->page_offset,
4758                                                len, PCI_DMA_TODEVICE);
4759
4760                         tp->tx_buffers[entry].skb = NULL;
4761                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4762
4763                         tg3_set_txd(tp, entry, mapping, len,
4764                                     base_flags, (i == last) | (mss << 1));
4765
4766                         entry = NEXT_TX(entry);
4767                 }
4768         }
4769
4770         /* Packets are ready, update Tx producer idx local and on card. */
4771         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4772
4773         tp->tx_prod = entry;
4774         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4775                 netif_stop_queue(dev);
4776                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4777                         netif_wake_queue(tp->dev);
4778         }
4779
4780 out_unlock:
4781         mmiowb();
4782
4783         dev->trans_start = jiffies;
4784
4785         return NETDEV_TX_OK;
4786 }
4787
4788 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4789
4790 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4791  * TSO header is greater than 80 bytes.
4792  */
4793 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4794 {
4795         struct sk_buff *segs, *nskb;
4796
4797         /* Estimate the number of fragments in the worst case */
4798         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4799                 netif_stop_queue(tp->dev);
4800                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4801                         return NETDEV_TX_BUSY;
4802
4803                 netif_wake_queue(tp->dev);
4804         }
4805
4806         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4807         if (IS_ERR(segs))
4808                 goto tg3_tso_bug_end;
4809
4810         do {
4811                 nskb = segs;
4812                 segs = segs->next;
4813                 nskb->next = NULL;
4814                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4815         } while (segs);
4816
4817 tg3_tso_bug_end:
4818         dev_kfree_skb(skb);
4819
4820         return NETDEV_TX_OK;
4821 }
4822
4823 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4824  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4825  */
4826 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4827 {
4828         struct tg3 *tp = netdev_priv(dev);
4829         dma_addr_t mapping;
4830         u32 len, entry, base_flags, mss;
4831         int would_hit_hwbug;
4832
4833         len = skb_headlen(skb);
4834
4835         /* We are running in BH disabled context with netif_tx_lock
4836          * and TX reclaim runs via tp->napi.poll inside of a software
4837          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4838          * no IRQ context deadlocks to worry about either.  Rejoice!
4839          */
4840         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4841                 if (!netif_queue_stopped(dev)) {
4842                         netif_stop_queue(dev);
4843
4844                         /* This is a hard error, log it. */
4845                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4846                                "queue awake!\n", dev->name);
4847                 }
4848                 return NETDEV_TX_BUSY;
4849         }
4850
4851         entry = tp->tx_prod;
4852         base_flags = 0;
4853         if (skb->ip_summed == CHECKSUM_PARTIAL)
4854                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4855         mss = 0;
4856         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4857                 struct iphdr *iph;
4858                 int tcp_opt_len, ip_tcp_len, hdr_len;
4859
4860                 if (skb_header_cloned(skb) &&
4861                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4862                         dev_kfree_skb(skb);
4863                         goto out_unlock;
4864                 }
4865
4866                 tcp_opt_len = tcp_optlen(skb);
4867                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4868
4869                 hdr_len = ip_tcp_len + tcp_opt_len;
4870                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4871                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4872                         return (tg3_tso_bug(tp, skb));
4873
4874                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4875                                TXD_FLAG_CPU_POST_DMA);
4876
4877                 iph = ip_hdr(skb);
4878                 iph->check = 0;
4879                 iph->tot_len = htons(mss + hdr_len);
4880                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4881                         tcp_hdr(skb)->check = 0;
4882                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4883                 } else
4884                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4885                                                                  iph->daddr, 0,
4886                                                                  IPPROTO_TCP,
4887                                                                  0);
4888
4889                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4890                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4891                         if (tcp_opt_len || iph->ihl > 5) {
4892                                 int tsflags;
4893
4894                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4895                                 mss |= (tsflags << 11);
4896                         }
4897                 } else {
4898                         if (tcp_opt_len || iph->ihl > 5) {
4899                                 int tsflags;
4900
4901                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4902                                 base_flags |= tsflags << 12;
4903                         }
4904                 }
4905         }
4906 #if TG3_VLAN_TAG_USED
4907         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4908                 base_flags |= (TXD_FLAG_VLAN |
4909                                (vlan_tx_tag_get(skb) << 16));
4910 #endif
4911
4912         /* Queue skb data, a.k.a. the main skb fragment. */
4913         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4914
4915         tp->tx_buffers[entry].skb = skb;
4916         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4917
4918         would_hit_hwbug = 0;
4919
4920         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4921                 would_hit_hwbug = 1;
4922         else if (tg3_4g_overflow_test(mapping, len))
4923                 would_hit_hwbug = 1;
4924
4925         tg3_set_txd(tp, entry, mapping, len, base_flags,
4926                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4927
4928         entry = NEXT_TX(entry);
4929
4930         /* Now loop through additional data fragments, and queue them. */
4931         if (skb_shinfo(skb)->nr_frags > 0) {
4932                 unsigned int i, last;
4933
4934                 last = skb_shinfo(skb)->nr_frags - 1;
4935                 for (i = 0; i <= last; i++) {
4936                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4937
4938                         len = frag->size;
4939                         mapping = pci_map_page(tp->pdev,
4940                                                frag->page,
4941                                                frag->page_offset,
4942                                                len, PCI_DMA_TODEVICE);
4943
4944                         tp->tx_buffers[entry].skb = NULL;
4945                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4946
4947                         if (tg3_4g_overflow_test(mapping, len))
4948                                 would_hit_hwbug = 1;
4949
4950                         if (tg3_40bit_overflow_test(tp, mapping, len))
4951                                 would_hit_hwbug = 1;
4952
4953                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4954                                 tg3_set_txd(tp, entry, mapping, len,
4955                                             base_flags, (i == last)|(mss << 1));
4956                         else
4957                                 tg3_set_txd(tp, entry, mapping, len,
4958                                             base_flags, (i == last));
4959
4960                         entry = NEXT_TX(entry);
4961                 }
4962         }
4963
4964         if (would_hit_hwbug) {
4965                 u32 last_plus_one = entry;
4966                 u32 start;
4967
4968                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4969                 start &= (TG3_TX_RING_SIZE - 1);
4970
4971                 /* If the workaround fails due to memory/mapping
4972                  * failure, silently drop this packet.
4973                  */
4974                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4975                                                 &start, base_flags, mss))
4976                         goto out_unlock;
4977
4978                 entry = start;
4979         }
4980
4981         /* Packets are ready, update Tx producer idx local and on card. */
4982         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4983
4984         tp->tx_prod = entry;
4985         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4986                 netif_stop_queue(dev);
4987                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4988                         netif_wake_queue(tp->dev);
4989         }
4990
4991 out_unlock:
4992         mmiowb();
4993
4994         dev->trans_start = jiffies;
4995
4996         return NETDEV_TX_OK;
4997 }
4998
4999 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5000                                int new_mtu)
5001 {
5002         dev->mtu = new_mtu;
5003
5004         if (new_mtu > ETH_DATA_LEN) {
5005                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5006                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5007                         ethtool_op_set_tso(dev, 0);
5008                 }
5009                 else
5010                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5011         } else {
5012                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5013                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5014                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5015         }
5016 }
5017
5018 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5019 {
5020         struct tg3 *tp = netdev_priv(dev);
5021         int err;
5022
5023         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5024                 return -EINVAL;
5025
5026         if (!netif_running(dev)) {
5027                 /* We'll just catch it later when the
5028                  * device is up'd.
5029                  */
5030                 tg3_set_mtu(dev, tp, new_mtu);
5031                 return 0;
5032         }
5033
5034         tg3_phy_stop(tp);
5035
5036         tg3_netif_stop(tp);
5037
5038         tg3_full_lock(tp, 1);
5039
5040         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5041
5042         tg3_set_mtu(dev, tp, new_mtu);
5043
5044         err = tg3_restart_hw(tp, 0);
5045
5046         if (!err)
5047                 tg3_netif_start(tp);
5048
5049         tg3_full_unlock(tp);
5050
5051         if (!err)
5052                 tg3_phy_start(tp);
5053
5054         return err;
5055 }
5056
5057 /* Free up pending packets in all rx/tx rings.
5058  *
5059  * The chip has been shut down and the driver detached from
5060  * the networking, so no interrupts or new tx packets will
5061  * end up in the driver.  tp->{tx,}lock is not held and we are not
5062  * in an interrupt context and thus may sleep.
5063  */
5064 static void tg3_free_rings(struct tg3 *tp)
5065 {
5066         struct ring_info *rxp;
5067         int i;
5068
5069         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5070                 rxp = &tp->rx_std_buffers[i];
5071
5072                 if (rxp->skb == NULL)
5073                         continue;
5074                 pci_unmap_single(tp->pdev,
5075                                  pci_unmap_addr(rxp, mapping),
5076                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5077                                  PCI_DMA_FROMDEVICE);
5078                 dev_kfree_skb_any(rxp->skb);
5079                 rxp->skb = NULL;
5080         }
5081
5082         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5083                 rxp = &tp->rx_jumbo_buffers[i];
5084
5085                 if (rxp->skb == NULL)
5086                         continue;
5087                 pci_unmap_single(tp->pdev,
5088                                  pci_unmap_addr(rxp, mapping),
5089                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5090                                  PCI_DMA_FROMDEVICE);
5091                 dev_kfree_skb_any(rxp->skb);
5092                 rxp->skb = NULL;
5093         }
5094
5095         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5096                 struct tx_ring_info *txp;
5097                 struct sk_buff *skb;
5098                 int j;
5099
5100                 txp = &tp->tx_buffers[i];
5101                 skb = txp->skb;
5102
5103                 if (skb == NULL) {
5104                         i++;
5105                         continue;
5106                 }
5107
5108                 pci_unmap_single(tp->pdev,
5109                                  pci_unmap_addr(txp, mapping),
5110                                  skb_headlen(skb),
5111                                  PCI_DMA_TODEVICE);
5112                 txp->skb = NULL;
5113
5114                 i++;
5115
5116                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5117                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5118                         pci_unmap_page(tp->pdev,
5119                                        pci_unmap_addr(txp, mapping),
5120                                        skb_shinfo(skb)->frags[j].size,
5121                                        PCI_DMA_TODEVICE);
5122                         i++;
5123                 }
5124
5125                 dev_kfree_skb_any(skb);
5126         }
5127 }
5128
5129 /* Initialize tx/rx rings for packet processing.
5130  *
5131  * The chip has been shut down and the driver detached from
5132  * the networking, so no interrupts or new tx packets will
5133  * end up in the driver.  tp->{tx,}lock are held and thus
5134  * we may not sleep.
5135  */
5136 static int tg3_init_rings(struct tg3 *tp)
5137 {
5138         u32 i;
5139
5140         /* Free up all the SKBs. */
5141         tg3_free_rings(tp);
5142
5143         /* Zero out all descriptors. */
5144         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5145         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5146         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5147         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5148
5149         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5150         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5151             (tp->dev->mtu > ETH_DATA_LEN))
5152                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5153
5154         /* Initialize invariants of the rings, we only set this
5155          * stuff once.  This works because the card does not
5156          * write into the rx buffer posting rings.
5157          */
5158         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5159                 struct tg3_rx_buffer_desc *rxd;
5160
5161                 rxd = &tp->rx_std[i];
5162                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5163                         << RXD_LEN_SHIFT;
5164                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5165                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5166                                (i << RXD_OPAQUE_INDEX_SHIFT));
5167         }
5168
5169         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5170                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5171                         struct tg3_rx_buffer_desc *rxd;
5172
5173                         rxd = &tp->rx_jumbo[i];
5174                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5175                                 << RXD_LEN_SHIFT;
5176                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5177                                 RXD_FLAG_JUMBO;
5178                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5179                                (i << RXD_OPAQUE_INDEX_SHIFT));
5180                 }
5181         }
5182
5183         /* Now allocate fresh SKBs for each rx ring. */
5184         for (i = 0; i < tp->rx_pending; i++) {
5185                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5186                         printk(KERN_WARNING PFX
5187                                "%s: Using a smaller RX standard ring, "
5188                                "only %d out of %d buffers were allocated "
5189                                "successfully.\n",
5190                                tp->dev->name, i, tp->rx_pending);
5191                         if (i == 0)
5192                                 return -ENOMEM;
5193                         tp->rx_pending = i;
5194                         break;
5195                 }
5196         }
5197
5198         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5199                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5200                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5201                                              -1, i) < 0) {
5202                                 printk(KERN_WARNING PFX
5203                                        "%s: Using a smaller RX jumbo ring, "
5204                                        "only %d out of %d buffers were "
5205                                        "allocated successfully.\n",
5206                                        tp->dev->name, i, tp->rx_jumbo_pending);
5207                                 if (i == 0) {
5208                                         tg3_free_rings(tp);
5209                                         return -ENOMEM;
5210                                 }
5211                                 tp->rx_jumbo_pending = i;
5212                                 break;
5213                         }
5214                 }
5215         }
5216         return 0;
5217 }
5218
5219 /*
5220  * Must not be invoked with interrupt sources disabled and
5221  * the hardware shutdown down.
5222  */
5223 static void tg3_free_consistent(struct tg3 *tp)
5224 {
5225         kfree(tp->rx_std_buffers);
5226         tp->rx_std_buffers = NULL;
5227         if (tp->rx_std) {
5228                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5229                                     tp->rx_std, tp->rx_std_mapping);
5230                 tp->rx_std = NULL;
5231         }
5232         if (tp->rx_jumbo) {
5233                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5234                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5235                 tp->rx_jumbo = NULL;
5236         }
5237         if (tp->rx_rcb) {
5238                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5239                                     tp->rx_rcb, tp->rx_rcb_mapping);
5240                 tp->rx_rcb = NULL;
5241         }
5242         if (tp->tx_ring) {
5243                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5244                         tp->tx_ring, tp->tx_desc_mapping);
5245                 tp->tx_ring = NULL;
5246         }
5247         if (tp->hw_status) {
5248                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5249                                     tp->hw_status, tp->status_mapping);
5250                 tp->hw_status = NULL;
5251         }
5252         if (tp->hw_stats) {
5253                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5254                                     tp->hw_stats, tp->stats_mapping);
5255                 tp->hw_stats = NULL;
5256         }
5257 }
5258
5259 /*
5260  * Must not be invoked with interrupt sources disabled and
5261  * the hardware shutdown down.  Can sleep.
5262  */
5263 static int tg3_alloc_consistent(struct tg3 *tp)
5264 {
5265         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5266                                       (TG3_RX_RING_SIZE +
5267                                        TG3_RX_JUMBO_RING_SIZE)) +
5268                                      (sizeof(struct tx_ring_info) *
5269                                       TG3_TX_RING_SIZE),
5270                                      GFP_KERNEL);
5271         if (!tp->rx_std_buffers)
5272                 return -ENOMEM;
5273
5274         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5275         tp->tx_buffers = (struct tx_ring_info *)
5276                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5277
5278         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5279                                           &tp->rx_std_mapping);
5280         if (!tp->rx_std)
5281                 goto err_out;
5282
5283         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5284                                             &tp->rx_jumbo_mapping);
5285
5286         if (!tp->rx_jumbo)
5287                 goto err_out;
5288
5289         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5290                                           &tp->rx_rcb_mapping);
5291         if (!tp->rx_rcb)
5292                 goto err_out;
5293
5294         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5295                                            &tp->tx_desc_mapping);
5296         if (!tp->tx_ring)
5297                 goto err_out;
5298
5299         tp->hw_status = pci_alloc_consistent(tp->pdev,
5300                                              TG3_HW_STATUS_SIZE,
5301                                              &tp->status_mapping);
5302         if (!tp->hw_status)
5303                 goto err_out;
5304
5305         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5306                                             sizeof(struct tg3_hw_stats),
5307                                             &tp->stats_mapping);
5308         if (!tp->hw_stats)
5309                 goto err_out;
5310
5311         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5312         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5313
5314         return 0;
5315
5316 err_out:
5317         tg3_free_consistent(tp);
5318         return -ENOMEM;
5319 }
5320
5321 #define MAX_WAIT_CNT 1000
5322
5323 /* To stop a block, clear the enable bit and poll till it
5324  * clears.  tp->lock is held.
5325  */
5326 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5327 {
5328         unsigned int i;
5329         u32 val;
5330
5331         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5332                 switch (ofs) {
5333                 case RCVLSC_MODE:
5334                 case DMAC_MODE:
5335                 case MBFREE_MODE:
5336                 case BUFMGR_MODE:
5337                 case MEMARB_MODE:
5338                         /* We can't enable/disable these bits of the
5339                          * 5705/5750, just say success.
5340                          */
5341                         return 0;
5342
5343                 default:
5344                         break;
5345                 }
5346         }
5347
5348         val = tr32(ofs);
5349         val &= ~enable_bit;
5350         tw32_f(ofs, val);
5351
5352         for (i = 0; i < MAX_WAIT_CNT; i++) {
5353                 udelay(100);
5354                 val = tr32(ofs);
5355                 if ((val & enable_bit) == 0)
5356                         break;
5357         }
5358
5359         if (i == MAX_WAIT_CNT && !silent) {
5360                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5361                        "ofs=%lx enable_bit=%x\n",
5362                        ofs, enable_bit);
5363                 return -ENODEV;
5364         }
5365
5366         return 0;
5367 }
5368
5369 /* tp->lock is held. */
5370 static int tg3_abort_hw(struct tg3 *tp, int silent)
5371 {
5372         int i, err;
5373
5374         tg3_disable_ints(tp);
5375
5376         tp->rx_mode &= ~RX_MODE_ENABLE;
5377         tw32_f(MAC_RX_MODE, tp->rx_mode);
5378         udelay(10);
5379
5380         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5381         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5382         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5383         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5384         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5385         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5386
5387         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5388         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5389         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5390         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5391         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5392         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5393         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5394
5395         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5396         tw32_f(MAC_MODE, tp->mac_mode);
5397         udelay(40);
5398
5399         tp->tx_mode &= ~TX_MODE_ENABLE;
5400         tw32_f(MAC_TX_MODE, tp->tx_mode);
5401
5402         for (i = 0; i < MAX_WAIT_CNT; i++) {
5403                 udelay(100);
5404                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5405                         break;
5406         }
5407         if (i >= MAX_WAIT_CNT) {
5408                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5409                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5410                        tp->dev->name, tr32(MAC_TX_MODE));
5411                 err |= -ENODEV;
5412         }
5413
5414         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5415         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5416         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5417
5418         tw32(FTQ_RESET, 0xffffffff);
5419         tw32(FTQ_RESET, 0x00000000);
5420
5421         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5422         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5423
5424         if (tp->hw_status)
5425                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5426         if (tp->hw_stats)
5427                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5428
5429         return err;
5430 }
5431
5432 /* tp->lock is held. */
5433 static int tg3_nvram_lock(struct tg3 *tp)
5434 {
5435         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5436                 int i;
5437
5438                 if (tp->nvram_lock_cnt == 0) {
5439                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5440                         for (i = 0; i < 8000; i++) {
5441                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5442                                         break;
5443                                 udelay(20);
5444                         }
5445                         if (i == 8000) {
5446                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5447                                 return -ENODEV;
5448                         }
5449                 }
5450                 tp->nvram_lock_cnt++;
5451         }
5452         return 0;
5453 }
5454
5455 /* tp->lock is held. */
5456 static void tg3_nvram_unlock(struct tg3 *tp)
5457 {
5458         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5459                 if (tp->nvram_lock_cnt > 0)
5460                         tp->nvram_lock_cnt--;
5461                 if (tp->nvram_lock_cnt == 0)
5462                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5463         }
5464 }
5465
5466 /* tp->lock is held. */
5467 static void tg3_enable_nvram_access(struct tg3 *tp)
5468 {
5469         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5470             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5471                 u32 nvaccess = tr32(NVRAM_ACCESS);
5472
5473                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5474         }
5475 }
5476
5477 /* tp->lock is held. */
5478 static void tg3_disable_nvram_access(struct tg3 *tp)
5479 {
5480         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5481             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5482                 u32 nvaccess = tr32(NVRAM_ACCESS);
5483
5484                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5485         }
5486 }
5487
5488 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5489 {
5490         int i;
5491         u32 apedata;
5492
5493         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5494         if (apedata != APE_SEG_SIG_MAGIC)
5495                 return;
5496
5497         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5498         if (!(apedata & APE_FW_STATUS_READY))
5499                 return;
5500
5501         /* Wait for up to 1 millisecond for APE to service previous event. */
5502         for (i = 0; i < 10; i++) {
5503                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5504                         return;
5505
5506                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5507
5508                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5509                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5510                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5511
5512                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5513
5514                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5515                         break;
5516
5517                 udelay(100);
5518         }
5519
5520         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5521                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5522 }
5523
5524 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5525 {
5526         u32 event;
5527         u32 apedata;
5528
5529         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5530                 return;
5531
5532         switch (kind) {
5533                 case RESET_KIND_INIT:
5534                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5535                                         APE_HOST_SEG_SIG_MAGIC);
5536                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5537                                         APE_HOST_SEG_LEN_MAGIC);
5538                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5539                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5540                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5541                                         APE_HOST_DRIVER_ID_MAGIC);
5542                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5543                                         APE_HOST_BEHAV_NO_PHYLOCK);
5544
5545                         event = APE_EVENT_STATUS_STATE_START;
5546                         break;
5547                 case RESET_KIND_SHUTDOWN:
5548                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5549                         break;
5550                 case RESET_KIND_SUSPEND:
5551                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5552                         break;
5553                 default:
5554                         return;
5555         }
5556
5557         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5558
5559         tg3_ape_send_event(tp, event);
5560 }
5561
5562 /* tp->lock is held. */
5563 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5564 {
5565         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5566                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5567
5568         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5569                 switch (kind) {
5570                 case RESET_KIND_INIT:
5571                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5572                                       DRV_STATE_START);
5573                         break;
5574
5575                 case RESET_KIND_SHUTDOWN:
5576                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5577                                       DRV_STATE_UNLOAD);
5578                         break;
5579
5580                 case RESET_KIND_SUSPEND:
5581                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5582                                       DRV_STATE_SUSPEND);
5583                         break;
5584
5585                 default:
5586                         break;
5587                 }
5588         }
5589
5590         if (kind == RESET_KIND_INIT ||
5591             kind == RESET_KIND_SUSPEND)
5592                 tg3_ape_driver_state_change(tp, kind);
5593 }
5594
5595 /* tp->lock is held. */
5596 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5597 {
5598         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5599                 switch (kind) {
5600                 case RESET_KIND_INIT:
5601                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5602                                       DRV_STATE_START_DONE);
5603                         break;
5604
5605                 case RESET_KIND_SHUTDOWN:
5606                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5607                                       DRV_STATE_UNLOAD_DONE);
5608                         break;
5609
5610                 default:
5611                         break;
5612                 }
5613         }
5614
5615         if (kind == RESET_KIND_SHUTDOWN)
5616                 tg3_ape_driver_state_change(tp, kind);
5617 }
5618
5619 /* tp->lock is held. */
5620 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5621 {
5622         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5623                 switch (kind) {
5624                 case RESET_KIND_INIT:
5625                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5626                                       DRV_STATE_START);
5627                         break;
5628
5629                 case RESET_KIND_SHUTDOWN:
5630                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5631                                       DRV_STATE_UNLOAD);
5632                         break;
5633
5634                 case RESET_KIND_SUSPEND:
5635                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5636                                       DRV_STATE_SUSPEND);
5637                         break;
5638
5639                 default:
5640                         break;
5641                 }
5642         }
5643 }
5644
5645 static int tg3_poll_fw(struct tg3 *tp)
5646 {
5647         int i;
5648         u32 val;
5649
5650         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5651                 /* Wait up to 20ms for init done. */
5652                 for (i = 0; i < 200; i++) {
5653                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5654                                 return 0;
5655                         udelay(100);
5656                 }
5657                 return -ENODEV;
5658         }
5659
5660         /* Wait for firmware initialization to complete. */
5661         for (i = 0; i < 100000; i++) {
5662                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5663                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5664                         break;
5665                 udelay(10);
5666         }
5667
5668         /* Chip might not be fitted with firmware.  Some Sun onboard
5669          * parts are configured like that.  So don't signal the timeout
5670          * of the above loop as an error, but do report the lack of
5671          * running firmware once.
5672          */
5673         if (i >= 100000 &&
5674             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5675                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5676
5677                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5678                        tp->dev->name);
5679         }
5680
5681         return 0;
5682 }
5683
5684 /* Save PCI command register before chip reset */
5685 static void tg3_save_pci_state(struct tg3 *tp)
5686 {
5687         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5688 }
5689
5690 /* Restore PCI state after chip reset */
5691 static void tg3_restore_pci_state(struct tg3 *tp)
5692 {
5693         u32 val;
5694
5695         /* Re-enable indirect register accesses. */
5696         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5697                                tp->misc_host_ctrl);
5698
5699         /* Set MAX PCI retry to zero. */
5700         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5701         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5702             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5703                 val |= PCISTATE_RETRY_SAME_DMA;
5704         /* Allow reads and writes to the APE register and memory space. */
5705         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5706                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5707                        PCISTATE_ALLOW_APE_SHMEM_WR;
5708         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5709
5710         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5711
5712         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5713                 pcie_set_readrq(tp->pdev, 4096);
5714         else {
5715                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5716                                       tp->pci_cacheline_sz);
5717                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5718                                       tp->pci_lat_timer);
5719         }
5720
5721         /* Make sure PCI-X relaxed ordering bit is clear. */
5722         if (tp->pcix_cap) {
5723                 u16 pcix_cmd;
5724
5725                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5726                                      &pcix_cmd);
5727                 pcix_cmd &= ~PCI_X_CMD_ERO;
5728                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5729                                       pcix_cmd);
5730         }
5731
5732         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5733
5734                 /* Chip reset on 5780 will reset MSI enable bit,
5735                  * so need to restore it.
5736                  */
5737                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5738                         u16 ctrl;
5739
5740                         pci_read_config_word(tp->pdev,
5741                                              tp->msi_cap + PCI_MSI_FLAGS,
5742                                              &ctrl);
5743                         pci_write_config_word(tp->pdev,
5744                                               tp->msi_cap + PCI_MSI_FLAGS,
5745                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5746                         val = tr32(MSGINT_MODE);
5747                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5748                 }
5749         }
5750 }
5751
5752 static void tg3_stop_fw(struct tg3 *);
5753
5754 /* tp->lock is held. */
5755 static int tg3_chip_reset(struct tg3 *tp)
5756 {
5757         u32 val;
5758         void (*write_op)(struct tg3 *, u32, u32);
5759         int err;
5760
5761         tg3_nvram_lock(tp);
5762
5763         tg3_mdio_stop(tp);
5764
5765         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5766
5767         /* No matching tg3_nvram_unlock() after this because
5768          * chip reset below will undo the nvram lock.
5769          */
5770         tp->nvram_lock_cnt = 0;
5771
5772         /* GRC_MISC_CFG core clock reset will clear the memory
5773          * enable bit in PCI register 4 and the MSI enable bit
5774          * on some chips, so we save relevant registers here.
5775          */
5776         tg3_save_pci_state(tp);
5777
5778         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5779             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5780             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5781             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5782             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5783             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5784                 tw32(GRC_FASTBOOT_PC, 0);
5785
5786         /*
5787          * We must avoid the readl() that normally takes place.
5788          * It locks machines, causes machine checks, and other
5789          * fun things.  So, temporarily disable the 5701
5790          * hardware workaround, while we do the reset.
5791          */
5792         write_op = tp->write32;
5793         if (write_op == tg3_write_flush_reg32)
5794                 tp->write32 = tg3_write32;
5795
5796         /* Prevent the irq handler from reading or writing PCI registers
5797          * during chip reset when the memory enable bit in the PCI command
5798          * register may be cleared.  The chip does not generate interrupt
5799          * at this time, but the irq handler may still be called due to irq
5800          * sharing or irqpoll.
5801          */
5802         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5803         if (tp->hw_status) {
5804                 tp->hw_status->status = 0;
5805                 tp->hw_status->status_tag = 0;
5806         }
5807         tp->last_tag = 0;
5808         smp_mb();
5809         synchronize_irq(tp->pdev->irq);
5810
5811         /* do the reset */
5812         val = GRC_MISC_CFG_CORECLK_RESET;
5813
5814         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5815                 if (tr32(0x7e2c) == 0x60) {
5816                         tw32(0x7e2c, 0x20);
5817                 }
5818                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5819                         tw32(GRC_MISC_CFG, (1 << 29));
5820                         val |= (1 << 29);
5821                 }
5822         }
5823
5824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5825                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5826                 tw32(GRC_VCPU_EXT_CTRL,
5827                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5828         }
5829
5830         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5831                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5832         tw32(GRC_MISC_CFG, val);
5833
5834         /* restore 5701 hardware bug workaround write method */
5835         tp->write32 = write_op;
5836
5837         /* Unfortunately, we have to delay before the PCI read back.
5838          * Some 575X chips even will not respond to a PCI cfg access
5839          * when the reset command is given to the chip.
5840          *
5841          * How do these hardware designers expect things to work
5842          * properly if the PCI write is posted for a long period
5843          * of time?  It is always necessary to have some method by
5844          * which a register read back can occur to push the write
5845          * out which does the reset.
5846          *
5847          * For most tg3 variants the trick below was working.
5848          * Ho hum...
5849          */
5850         udelay(120);
5851
5852         /* Flush PCI posted writes.  The normal MMIO registers
5853          * are inaccessible at this time so this is the only
5854          * way to make this reliably (actually, this is no longer
5855          * the case, see above).  I tried to use indirect
5856          * register read/write but this upset some 5701 variants.
5857          */
5858         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5859
5860         udelay(120);
5861
5862         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5863                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5864                         int i;
5865                         u32 cfg_val;
5866
5867                         /* Wait for link training to complete.  */
5868                         for (i = 0; i < 5000; i++)
5869                                 udelay(100);
5870
5871                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5872                         pci_write_config_dword(tp->pdev, 0xc4,
5873                                                cfg_val | (1 << 15));
5874                 }
5875                 /* Set PCIE max payload size and clear error status.  */
5876                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5877         }
5878
5879         tg3_restore_pci_state(tp);
5880
5881         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5882
5883         val = 0;
5884         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5885                 val = tr32(MEMARB_MODE);
5886         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5887
5888         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5889                 tg3_stop_fw(tp);
5890                 tw32(0x5000, 0x400);
5891         }
5892
5893         tw32(GRC_MODE, tp->grc_mode);
5894
5895         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5896                 val = tr32(0xc4);
5897
5898                 tw32(0xc4, val | (1 << 15));
5899         }
5900
5901         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5903                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5904                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5905                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5906                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5907         }
5908
5909         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5910                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5911                 tw32_f(MAC_MODE, tp->mac_mode);
5912         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5913                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5914                 tw32_f(MAC_MODE, tp->mac_mode);
5915         } else
5916                 tw32_f(MAC_MODE, 0);
5917         udelay(40);
5918
5919         tg3_mdio_start(tp);
5920
5921         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
5922
5923         err = tg3_poll_fw(tp);
5924         if (err)
5925                 return err;
5926
5927         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5928             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5929                 val = tr32(0x7c00);
5930
5931                 tw32(0x7c00, val | (1 << 25));
5932         }
5933
5934         /* Reprobe ASF enable state.  */
5935         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5936         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5937         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5938         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5939                 u32 nic_cfg;
5940
5941                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5942                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5943                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5944                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5945                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5946                 }
5947         }
5948
5949         return 0;
5950 }
5951
5952 /* tp->lock is held. */
5953 static void tg3_stop_fw(struct tg3 *tp)
5954 {
5955         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5956            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5957                 u32 val;
5958
5959                 /* Wait for RX cpu to ACK the previous event. */
5960                 tg3_wait_for_event_ack(tp);
5961
5962                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5963                 val = tr32(GRC_RX_CPU_EVENT);
5964                 val |= GRC_RX_CPU_DRIVER_EVENT;
5965                 tw32(GRC_RX_CPU_EVENT, val);
5966
5967                 /* Wait for RX cpu to ACK this event. */
5968                 tg3_wait_for_event_ack(tp);
5969         }
5970 }
5971
5972 /* tp->lock is held. */
5973 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5974 {
5975         int err;
5976
5977         tg3_stop_fw(tp);
5978
5979         tg3_write_sig_pre_reset(tp, kind);
5980
5981         tg3_abort_hw(tp, silent);
5982         err = tg3_chip_reset(tp);
5983
5984         tg3_write_sig_legacy(tp, kind);
5985         tg3_write_sig_post_reset(tp, kind);
5986
5987         if (err)
5988                 return err;
5989
5990         return 0;
5991 }
5992
5993 #define TG3_FW_RELEASE_MAJOR    0x0
5994 #define TG3_FW_RELASE_MINOR     0x0
5995 #define TG3_FW_RELEASE_FIX      0x0
5996 #define TG3_FW_START_ADDR       0x08000000
5997 #define TG3_FW_TEXT_ADDR        0x08000000
5998 #define TG3_FW_TEXT_LEN         0x9c0
5999 #define TG3_FW_RODATA_ADDR      0x080009c0
6000 #define TG3_FW_RODATA_LEN       0x60
6001 #define TG3_FW_DATA_ADDR        0x08000a40
6002 #define TG3_FW_DATA_LEN         0x20
6003 #define TG3_FW_SBSS_ADDR        0x08000a60
6004 #define TG3_FW_SBSS_LEN         0xc
6005 #define TG3_FW_BSS_ADDR         0x08000a70
6006 #define TG3_FW_BSS_LEN          0x10
6007
6008 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
6009         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
6010         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
6011         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
6012         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
6013         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
6014         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
6015         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
6016         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
6017         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
6018         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
6019         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
6020         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
6021         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
6022         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
6023         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
6024         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6025         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
6026         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
6027         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
6028         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6029         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
6030         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
6031         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6032         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6033         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6034         0, 0, 0, 0, 0, 0,
6035         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
6036         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6037         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6038         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6039         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
6040         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
6041         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
6042         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
6043         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6044         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6045         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
6046         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6047         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6048         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6049         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
6050         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
6051         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
6052         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
6053         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
6054         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
6055         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
6056         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
6057         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
6058         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
6059         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
6060         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
6061         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
6062         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
6063         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
6064         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
6065         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
6066         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
6067         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
6068         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
6069         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6070         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6071         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6072         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6073         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6074         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6075         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6076         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6077         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6078         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6079         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6080         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6081         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6082         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6083         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6084         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6085         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6086         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6087         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6088         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6089         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6090         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6091         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6092         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6093         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6094         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6095         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6096         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6097         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6098         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6099         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6100 };
6101
6102 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6103         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6104         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6105         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6106         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6107         0x00000000
6108 };
6109
6110 #if 0 /* All zeros, don't eat up space with it. */
6111 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6112         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6113         0x00000000, 0x00000000, 0x00000000, 0x00000000
6114 };
6115 #endif
6116
6117 #define RX_CPU_SCRATCH_BASE     0x30000
6118 #define RX_CPU_SCRATCH_SIZE     0x04000
6119 #define TX_CPU_SCRATCH_BASE     0x34000
6120 #define TX_CPU_SCRATCH_SIZE     0x04000
6121
6122 /* tp->lock is held. */
6123 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6124 {
6125         int i;
6126
6127         BUG_ON(offset == TX_CPU_BASE &&
6128             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6129
6130         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6131                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6132
6133                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6134                 return 0;
6135         }
6136         if (offset == RX_CPU_BASE) {
6137                 for (i = 0; i < 10000; i++) {
6138                         tw32(offset + CPU_STATE, 0xffffffff);
6139                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6140                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6141                                 break;
6142                 }
6143
6144                 tw32(offset + CPU_STATE, 0xffffffff);
6145                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6146                 udelay(10);
6147         } else {
6148                 for (i = 0; i < 10000; i++) {
6149                         tw32(offset + CPU_STATE, 0xffffffff);
6150                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6151                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6152                                 break;
6153                 }
6154         }
6155
6156         if (i >= 10000) {
6157                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6158                        "and %s CPU\n",
6159                        tp->dev->name,
6160                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6161                 return -ENODEV;
6162         }
6163
6164         /* Clear firmware's nvram arbitration. */
6165         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6166                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6167         return 0;
6168 }
6169
6170 struct fw_info {
6171         unsigned int text_base;
6172         unsigned int text_len;
6173         const u32 *text_data;
6174         unsigned int rodata_base;
6175         unsigned int rodata_len;
6176         const u32 *rodata_data;
6177         unsigned int data_base;
6178         unsigned int data_len;
6179         const u32 *data_data;
6180 };
6181
6182 /* tp->lock is held. */
6183 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6184                                  int cpu_scratch_size, struct fw_info *info)
6185 {
6186         int err, lock_err, i;
6187         void (*write_op)(struct tg3 *, u32, u32);
6188
6189         if (cpu_base == TX_CPU_BASE &&
6190             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6191                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6192                        "TX cpu firmware on %s which is 5705.\n",
6193                        tp->dev->name);
6194                 return -EINVAL;
6195         }
6196
6197         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6198                 write_op = tg3_write_mem;
6199         else
6200                 write_op = tg3_write_indirect_reg32;
6201
6202         /* It is possible that bootcode is still loading at this point.
6203          * Get the nvram lock first before halting the cpu.
6204          */
6205         lock_err = tg3_nvram_lock(tp);
6206         err = tg3_halt_cpu(tp, cpu_base);
6207         if (!lock_err)
6208                 tg3_nvram_unlock(tp);
6209         if (err)
6210                 goto out;
6211
6212         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6213                 write_op(tp, cpu_scratch_base + i, 0);
6214         tw32(cpu_base + CPU_STATE, 0xffffffff);
6215         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6216         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6217                 write_op(tp, (cpu_scratch_base +
6218                               (info->text_base & 0xffff) +
6219                               (i * sizeof(u32))),
6220                          (info->text_data ?
6221                           info->text_data[i] : 0));
6222         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6223                 write_op(tp, (cpu_scratch_base +
6224                               (info->rodata_base & 0xffff) +
6225                               (i * sizeof(u32))),
6226                          (info->rodata_data ?
6227                           info->rodata_data[i] : 0));
6228         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6229                 write_op(tp, (cpu_scratch_base +
6230                               (info->data_base & 0xffff) +
6231                               (i * sizeof(u32))),
6232                          (info->data_data ?
6233                           info->data_data[i] : 0));
6234
6235         err = 0;
6236
6237 out:
6238         return err;
6239 }
6240
6241 /* tp->lock is held. */
6242 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6243 {
6244         struct fw_info info;
6245         int err, i;
6246
6247         info.text_base = TG3_FW_TEXT_ADDR;
6248         info.text_len = TG3_FW_TEXT_LEN;
6249         info.text_data = &tg3FwText[0];
6250         info.rodata_base = TG3_FW_RODATA_ADDR;
6251         info.rodata_len = TG3_FW_RODATA_LEN;
6252         info.rodata_data = &tg3FwRodata[0];
6253         info.data_base = TG3_FW_DATA_ADDR;
6254         info.data_len = TG3_FW_DATA_LEN;
6255         info.data_data = NULL;
6256
6257         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6258                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6259                                     &info);
6260         if (err)
6261                 return err;
6262
6263         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6264                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6265                                     &info);
6266         if (err)
6267                 return err;
6268
6269         /* Now startup only the RX cpu. */
6270         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6271         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6272
6273         for (i = 0; i < 5; i++) {
6274                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6275                         break;
6276                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6277                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6278                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6279                 udelay(1000);
6280         }
6281         if (i >= 5) {
6282                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6283                        "to set RX CPU PC, is %08x should be %08x\n",
6284                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6285                        TG3_FW_TEXT_ADDR);
6286                 return -ENODEV;
6287         }
6288         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6289         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6290
6291         return 0;
6292 }
6293
6294
6295 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
6296 #define TG3_TSO_FW_RELASE_MINOR         0x6
6297 #define TG3_TSO_FW_RELEASE_FIX          0x0
6298 #define TG3_TSO_FW_START_ADDR           0x08000000
6299 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
6300 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
6301 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
6302 #define TG3_TSO_FW_RODATA_LEN           0x60
6303 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
6304 #define TG3_TSO_FW_DATA_LEN             0x30
6305 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
6306 #define TG3_TSO_FW_SBSS_LEN             0x2c
6307 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
6308 #define TG3_TSO_FW_BSS_LEN              0x894
6309
6310 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6311         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6312         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6313         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6314         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6315         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6316         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6317         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6318         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6319         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6320         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6321         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6322         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6323         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6324         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6325         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6326         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6327         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6328         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6329         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6330         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6331         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6332         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6333         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6334         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6335         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6336         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6337         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6338         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6339         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6340         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6341         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6342         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6343         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6344         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6345         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6346         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6347         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6348         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6349         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6350         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6351         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6352         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6353         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6354         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6355         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6356         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6357         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6358         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6359         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6360         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6361         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6362         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6363         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6364         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6365         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6366         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6367         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6368         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6369         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6370         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6371         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6372         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6373         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6374         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6375         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6376         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6377         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6378         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6379         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6380         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6381         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6382         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6383         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6384         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6385         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6386         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6387         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6388         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6389         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6390         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6391         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6392         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6393         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6394         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6395         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6396         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6397         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6398         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6399         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6400         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6401         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6402         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6403         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6404         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6405         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6406         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6407         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6408         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6409         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6410         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6411         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6412         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6413         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6414         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6415         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6416         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6417         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6418         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6419         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6420         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6421         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6422         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6423         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6424         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6425         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6426         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6427         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6428         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6429         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6430         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6431         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6432         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6433         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6434         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6435         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6436         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6437         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6438         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6439         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6440         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6441         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6442         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6443         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6444         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6445         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6446         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6447         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6448         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6449         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6450         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6451         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6452         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6453         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6454         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6455         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6456         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6457         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6458         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6459         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6460         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6461         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6462         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6463         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6464         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6465         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6466         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6467         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6468         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6469         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6470         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6471         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6472         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6473         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6474         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6475         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6476         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6477         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6478         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6479         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6480         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6481         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6482         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6483         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6484         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6485         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6486         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6487         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6488         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6489         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6490         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6491         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6492         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6493         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6494         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6495         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6496         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6497         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6498         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6499         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6500         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6501         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6502         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6503         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6504         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6505         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6506         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6507         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6508         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6509         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6510         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6511         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6512         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6513         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6514         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6515         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6516         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6517         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6518         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6519         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6520         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6521         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6522         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6523         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6524         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6525         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6526         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6527         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6528         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6529         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6530         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6531         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6532         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6533         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6534         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6535         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6536         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6537         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6538         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6539         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6540         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6541         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6542         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6543         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6544         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6545         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6546         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6547         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6548         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6549         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6550         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6551         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6552         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6553         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6554         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6555         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6556         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6557         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6558         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6559         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6560         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6561         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6562         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6563         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6564         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6565         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6566         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6567         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6568         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6569         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6570         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6571         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6572         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6573         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6574         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6575         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6576         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6577         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6578         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6579         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6580         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6581         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6582         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6583         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6584         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6585         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6586         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6587         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6588         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6589         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6590         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6591         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6592         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6593         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6594         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6595 };
6596
6597 static const u32 tg3TsoFwRodata[] = {
6598         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6599         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6600         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6601         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6602         0x00000000,
6603 };
6604
6605 static const u32 tg3TsoFwData[] = {
6606         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6607         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6608         0x00000000,
6609 };
6610
6611 /* 5705 needs a special version of the TSO firmware.  */
6612 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
6613 #define TG3_TSO5_FW_RELASE_MINOR        0x2
6614 #define TG3_TSO5_FW_RELEASE_FIX         0x0
6615 #define TG3_TSO5_FW_START_ADDR          0x00010000
6616 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
6617 #define TG3_TSO5_FW_TEXT_LEN            0xe90
6618 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
6619 #define TG3_TSO5_FW_RODATA_LEN          0x50
6620 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
6621 #define TG3_TSO5_FW_DATA_LEN            0x20
6622 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
6623 #define TG3_TSO5_FW_SBSS_LEN            0x28
6624 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
6625 #define TG3_TSO5_FW_BSS_LEN             0x88
6626
6627 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6628         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6629         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6630         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6631         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6632         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6633         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6634         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6635         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6636         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6637         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6638         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6639         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6640         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6641         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6642         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6643         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6644         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6645         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6646         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6647         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6648         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6649         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6650         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6651         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6652         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6653         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6654         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6655         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6656         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6657         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6658         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6659         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6660         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6661         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6662         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6663         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6664         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6665         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6666         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6667         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6668         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6669         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6670         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6671         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6672         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6673         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6674         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6675         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6676         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6677         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6678         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6679         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6680         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6681         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6682         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6683         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6684         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6685         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6686         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6687         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6688         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6689         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6690         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6691         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6692         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6693         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6694         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6695         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6696         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6697         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6698         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6699         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6700         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6701         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6702         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6703         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6704         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6705         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6706         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6707         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6708         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6709         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6710         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6711         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6712         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6713         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6714         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6715         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6716         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6717         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6718         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6719         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6720         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6721         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6722         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6723         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6724         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6725         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6726         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6727         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6728         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6729         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6730         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6731         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6732         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6733         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6734         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6735         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6736         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6737         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6738         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6739         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6740         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6741         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6742         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6743         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6744         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6745         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6746         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6747         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6748         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6749         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6750         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6751         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6752         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6753         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6754         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6755         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6756         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6757         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6758         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6759         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6760         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6761         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6762         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6763         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6764         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6765         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6766         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6767         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6768         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6769         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6770         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6771         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6772         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6773         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6774         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6775         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6776         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6777         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6778         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6779         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6780         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6781         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6782         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6783         0x00000000, 0x00000000, 0x00000000,
6784 };
6785
6786 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6787         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6788         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6789         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6790         0x00000000, 0x00000000, 0x00000000,
6791 };
6792
6793 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6794         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6795         0x00000000, 0x00000000, 0x00000000,
6796 };
6797
6798 /* tp->lock is held. */
6799 static int tg3_load_tso_firmware(struct tg3 *tp)
6800 {
6801         struct fw_info info;
6802         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6803         int err, i;
6804
6805         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6806                 return 0;
6807
6808         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6809                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6810                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6811                 info.text_data = &tg3Tso5FwText[0];
6812                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6813                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6814                 info.rodata_data = &tg3Tso5FwRodata[0];
6815                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6816                 info.data_len = TG3_TSO5_FW_DATA_LEN;
6817                 info.data_data = &tg3Tso5FwData[0];
6818                 cpu_base = RX_CPU_BASE;
6819                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6820                 cpu_scratch_size = (info.text_len +
6821                                     info.rodata_len +
6822                                     info.data_len +
6823                                     TG3_TSO5_FW_SBSS_LEN +
6824                                     TG3_TSO5_FW_BSS_LEN);
6825         } else {
6826                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6827                 info.text_len = TG3_TSO_FW_TEXT_LEN;
6828                 info.text_data = &tg3TsoFwText[0];
6829                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6830                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6831                 info.rodata_data = &tg3TsoFwRodata[0];
6832                 info.data_base = TG3_TSO_FW_DATA_ADDR;
6833                 info.data_len = TG3_TSO_FW_DATA_LEN;
6834                 info.data_data = &tg3TsoFwData[0];
6835                 cpu_base = TX_CPU_BASE;
6836                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6837                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6838         }
6839
6840         err = tg3_load_firmware_cpu(tp, cpu_base,
6841                                     cpu_scratch_base, cpu_scratch_size,
6842                                     &info);
6843         if (err)
6844                 return err;
6845
6846         /* Now startup the cpu. */
6847         tw32(cpu_base + CPU_STATE, 0xffffffff);
6848         tw32_f(cpu_base + CPU_PC,    info.text_base);
6849
6850         for (i = 0; i < 5; i++) {
6851                 if (tr32(cpu_base + CPU_PC) == info.text_base)
6852                         break;
6853                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6854                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6855                 tw32_f(cpu_base + CPU_PC,    info.text_base);
6856                 udelay(1000);
6857         }
6858         if (i >= 5) {
6859                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6860                        "to set CPU PC, is %08x should be %08x\n",
6861                        tp->dev->name, tr32(cpu_base + CPU_PC),
6862                        info.text_base);
6863                 return -ENODEV;
6864         }
6865         tw32(cpu_base + CPU_STATE, 0xffffffff);
6866         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6867         return 0;
6868 }
6869
6870
6871 /* tp->lock is held. */
6872 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6873 {
6874         u32 addr_high, addr_low;
6875         int i;
6876
6877         addr_high = ((tp->dev->dev_addr[0] << 8) |
6878                      tp->dev->dev_addr[1]);
6879         addr_low = ((tp->dev->dev_addr[2] << 24) |
6880                     (tp->dev->dev_addr[3] << 16) |
6881                     (tp->dev->dev_addr[4] <<  8) |
6882                     (tp->dev->dev_addr[5] <<  0));
6883         for (i = 0; i < 4; i++) {
6884                 if (i == 1 && skip_mac_1)
6885                         continue;
6886                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6887                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6888         }
6889
6890         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6891             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6892                 for (i = 0; i < 12; i++) {
6893                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6894                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6895                 }
6896         }
6897
6898         addr_high = (tp->dev->dev_addr[0] +
6899                      tp->dev->dev_addr[1] +
6900                      tp->dev->dev_addr[2] +
6901                      tp->dev->dev_addr[3] +
6902                      tp->dev->dev_addr[4] +
6903                      tp->dev->dev_addr[5]) &
6904                 TX_BACKOFF_SEED_MASK;
6905         tw32(MAC_TX_BACKOFF_SEED, addr_high);
6906 }
6907
6908 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6909 {
6910         struct tg3 *tp = netdev_priv(dev);
6911         struct sockaddr *addr = p;
6912         int err = 0, skip_mac_1 = 0;
6913
6914         if (!is_valid_ether_addr(addr->sa_data))
6915                 return -EINVAL;
6916
6917         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6918
6919         if (!netif_running(dev))
6920                 return 0;
6921
6922         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6923                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6924
6925                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6926                 addr0_low = tr32(MAC_ADDR_0_LOW);
6927                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6928                 addr1_low = tr32(MAC_ADDR_1_LOW);
6929
6930                 /* Skip MAC addr 1 if ASF is using it. */
6931                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6932                     !(addr1_high == 0 && addr1_low == 0))
6933                         skip_mac_1 = 1;
6934         }
6935         spin_lock_bh(&tp->lock);
6936         __tg3_set_mac_addr(tp, skip_mac_1);
6937         spin_unlock_bh(&tp->lock);
6938
6939         return err;
6940 }
6941
6942 /* tp->lock is held. */
6943 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6944                            dma_addr_t mapping, u32 maxlen_flags,
6945                            u32 nic_addr)
6946 {
6947         tg3_write_mem(tp,
6948                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6949                       ((u64) mapping >> 32));
6950         tg3_write_mem(tp,
6951                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6952                       ((u64) mapping & 0xffffffff));
6953         tg3_write_mem(tp,
6954                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6955                        maxlen_flags);
6956
6957         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6958                 tg3_write_mem(tp,
6959                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6960                               nic_addr);
6961 }
6962
6963 static void __tg3_set_rx_mode(struct net_device *);
6964 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6965 {
6966         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6967         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6968         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6969         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6970         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6971                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6972                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6973         }
6974         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6975         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6976         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6977                 u32 val = ec->stats_block_coalesce_usecs;
6978
6979                 if (!netif_carrier_ok(tp->dev))
6980                         val = 0;
6981
6982                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6983         }
6984 }
6985
6986 /* tp->lock is held. */
6987 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6988 {
6989         u32 val, rdmac_mode;
6990         int i, err, limit;
6991
6992         tg3_disable_ints(tp);
6993
6994         tg3_stop_fw(tp);
6995
6996         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6997
6998         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6999                 tg3_abort_hw(tp, 1);
7000         }
7001
7002         if (reset_phy &&
7003             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7004                 tg3_phy_reset(tp);
7005
7006         err = tg3_chip_reset(tp);
7007         if (err)
7008                 return err;
7009
7010         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7011
7012         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
7013             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
7014                 val = tr32(TG3_CPMU_CTRL);
7015                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7016                 tw32(TG3_CPMU_CTRL, val);
7017
7018                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7019                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7020                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7021                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7022
7023                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7024                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7025                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7026                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7027
7028                 val = tr32(TG3_CPMU_HST_ACC);
7029                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7030                 val |= CPMU_HST_ACC_MACCLK_6_25;
7031                 tw32(TG3_CPMU_HST_ACC, val);
7032         }
7033
7034         /* This works around an issue with Athlon chipsets on
7035          * B3 tigon3 silicon.  This bit has no effect on any
7036          * other revision.  But do not set this on PCI Express
7037          * chips and don't even touch the clocks if the CPMU is present.
7038          */
7039         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7040                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7041                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7042                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7043         }
7044
7045         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7046             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7047                 val = tr32(TG3PCI_PCISTATE);
7048                 val |= PCISTATE_RETRY_SAME_DMA;
7049                 tw32(TG3PCI_PCISTATE, val);
7050         }
7051
7052         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7053                 /* Allow reads and writes to the
7054                  * APE register and memory space.
7055                  */
7056                 val = tr32(TG3PCI_PCISTATE);
7057                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7058                        PCISTATE_ALLOW_APE_SHMEM_WR;
7059                 tw32(TG3PCI_PCISTATE, val);
7060         }
7061
7062         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7063                 /* Enable some hw fixes.  */
7064                 val = tr32(TG3PCI_MSI_DATA);
7065                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7066                 tw32(TG3PCI_MSI_DATA, val);
7067         }
7068
7069         /* Descriptor ring init may make accesses to the
7070          * NIC SRAM area to setup the TX descriptors, so we
7071          * can only do this after the hardware has been
7072          * successfully reset.
7073          */
7074         err = tg3_init_rings(tp);
7075         if (err)
7076                 return err;
7077
7078         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7079             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7080             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7081                 /* This value is determined during the probe time DMA
7082                  * engine test, tg3_test_dma.
7083                  */
7084                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7085         }
7086
7087         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7088                           GRC_MODE_4X_NIC_SEND_RINGS |
7089                           GRC_MODE_NO_TX_PHDR_CSUM |
7090                           GRC_MODE_NO_RX_PHDR_CSUM);
7091         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7092
7093         /* Pseudo-header checksum is done by hardware logic and not
7094          * the offload processers, so make the chip do the pseudo-
7095          * header checksums on receive.  For transmit it is more
7096          * convenient to do the pseudo-header checksum in software
7097          * as Linux does that on transmit for us in all cases.
7098          */
7099         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7100
7101         tw32(GRC_MODE,
7102              tp->grc_mode |
7103              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7104
7105         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7106         val = tr32(GRC_MISC_CFG);
7107         val &= ~0xff;
7108         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7109         tw32(GRC_MISC_CFG, val);
7110
7111         /* Initialize MBUF/DESC pool. */
7112         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7113                 /* Do nothing.  */
7114         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7115                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7116                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7117                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7118                 else
7119                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7120                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7121                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7122         }
7123         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7124                 int fw_len;
7125
7126                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7127                           TG3_TSO5_FW_RODATA_LEN +
7128                           TG3_TSO5_FW_DATA_LEN +
7129                           TG3_TSO5_FW_SBSS_LEN +
7130                           TG3_TSO5_FW_BSS_LEN);
7131                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7132                 tw32(BUFMGR_MB_POOL_ADDR,
7133                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7134                 tw32(BUFMGR_MB_POOL_SIZE,
7135                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7136         }
7137
7138         if (tp->dev->mtu <= ETH_DATA_LEN) {
7139                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7140                      tp->bufmgr_config.mbuf_read_dma_low_water);
7141                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7142                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7143                 tw32(BUFMGR_MB_HIGH_WATER,
7144                      tp->bufmgr_config.mbuf_high_water);
7145         } else {
7146                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7147                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7148                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7149                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7150                 tw32(BUFMGR_MB_HIGH_WATER,
7151                      tp->bufmgr_config.mbuf_high_water_jumbo);
7152         }
7153         tw32(BUFMGR_DMA_LOW_WATER,
7154              tp->bufmgr_config.dma_low_water);
7155         tw32(BUFMGR_DMA_HIGH_WATER,
7156              tp->bufmgr_config.dma_high_water);
7157
7158         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7159         for (i = 0; i < 2000; i++) {
7160                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7161                         break;
7162                 udelay(10);
7163         }
7164         if (i >= 2000) {
7165                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7166                        tp->dev->name);
7167                 return -ENODEV;
7168         }
7169
7170         /* Setup replenish threshold. */
7171         val = tp->rx_pending / 8;
7172         if (val == 0)
7173                 val = 1;
7174         else if (val > tp->rx_std_max_post)
7175                 val = tp->rx_std_max_post;
7176         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7177                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7178                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7179
7180                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7181                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7182         }
7183
7184         tw32(RCVBDI_STD_THRESH, val);
7185
7186         /* Initialize TG3_BDINFO's at:
7187          *  RCVDBDI_STD_BD:     standard eth size rx ring
7188          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7189          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7190          *
7191          * like so:
7192          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7193          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7194          *                              ring attribute flags
7195          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7196          *
7197          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7198          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7199          *
7200          * The size of each ring is fixed in the firmware, but the location is
7201          * configurable.
7202          */
7203         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7204              ((u64) tp->rx_std_mapping >> 32));
7205         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7206              ((u64) tp->rx_std_mapping & 0xffffffff));
7207         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7208              NIC_SRAM_RX_BUFFER_DESC);
7209
7210         /* Don't even try to program the JUMBO/MINI buffer descriptor
7211          * configs on 5705.
7212          */
7213         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7214                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7215                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7216         } else {
7217                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7218                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7219
7220                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7221                      BDINFO_FLAGS_DISABLED);
7222
7223                 /* Setup replenish threshold. */
7224                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7225
7226                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7227                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7228                              ((u64) tp->rx_jumbo_mapping >> 32));
7229                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7230                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7231                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7232                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7233                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7234                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7235                 } else {
7236                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7237                              BDINFO_FLAGS_DISABLED);
7238                 }
7239
7240         }
7241
7242         /* There is only one send ring on 5705/5750, no need to explicitly
7243          * disable the others.
7244          */
7245         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7246                 /* Clear out send RCB ring in SRAM. */
7247                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7248                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7249                                       BDINFO_FLAGS_DISABLED);
7250         }
7251
7252         tp->tx_prod = 0;
7253         tp->tx_cons = 0;
7254         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7255         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7256
7257         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7258                        tp->tx_desc_mapping,
7259                        (TG3_TX_RING_SIZE <<
7260                         BDINFO_FLAGS_MAXLEN_SHIFT),
7261                        NIC_SRAM_TX_BUFFER_DESC);
7262
7263         /* There is only one receive return ring on 5705/5750, no need
7264          * to explicitly disable the others.
7265          */
7266         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7267                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7268                      i += TG3_BDINFO_SIZE) {
7269                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7270                                       BDINFO_FLAGS_DISABLED);
7271                 }
7272         }
7273
7274         tp->rx_rcb_ptr = 0;
7275         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7276
7277         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7278                        tp->rx_rcb_mapping,
7279                        (TG3_RX_RCB_RING_SIZE(tp) <<
7280                         BDINFO_FLAGS_MAXLEN_SHIFT),
7281                        0);
7282
7283         tp->rx_std_ptr = tp->rx_pending;
7284         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7285                      tp->rx_std_ptr);
7286
7287         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7288                                                 tp->rx_jumbo_pending : 0;
7289         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7290                      tp->rx_jumbo_ptr);
7291
7292         /* Initialize MAC address and backoff seed. */
7293         __tg3_set_mac_addr(tp, 0);
7294
7295         /* MTU + ethernet header + FCS + optional VLAN tag */
7296         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7297
7298         /* The slot time is changed by tg3_setup_phy if we
7299          * run at gigabit with half duplex.
7300          */
7301         tw32(MAC_TX_LENGTHS,
7302              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7303              (6 << TX_LENGTHS_IPG_SHIFT) |
7304              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7305
7306         /* Receive rules. */
7307         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7308         tw32(RCVLPC_CONFIG, 0x0181);
7309
7310         /* Calculate RDMAC_MODE setting early, we need it to determine
7311          * the RCVLPC_STATE_ENABLE mask.
7312          */
7313         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7314                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7315                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7316                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7317                       RDMAC_MODE_LNGREAD_ENAB);
7318
7319         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7320             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7321                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7322                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7323                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7324
7325         /* If statement applies to 5705 and 5750 PCI devices only */
7326         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7327              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7328             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7329                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7330                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7331                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7332                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7333                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7334                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7335                 }
7336         }
7337
7338         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7339                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7340
7341         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7342                 rdmac_mode |= (1 << 27);
7343
7344         /* Receive/send statistics. */
7345         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7346                 val = tr32(RCVLPC_STATS_ENABLE);
7347                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7348                 tw32(RCVLPC_STATS_ENABLE, val);
7349         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7350                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7351                 val = tr32(RCVLPC_STATS_ENABLE);
7352                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7353                 tw32(RCVLPC_STATS_ENABLE, val);
7354         } else {
7355                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7356         }
7357         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7358         tw32(SNDDATAI_STATSENAB, 0xffffff);
7359         tw32(SNDDATAI_STATSCTRL,
7360              (SNDDATAI_SCTRL_ENABLE |
7361               SNDDATAI_SCTRL_FASTUPD));
7362
7363         /* Setup host coalescing engine. */
7364         tw32(HOSTCC_MODE, 0);
7365         for (i = 0; i < 2000; i++) {
7366                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7367                         break;
7368                 udelay(10);
7369         }
7370
7371         __tg3_set_coalesce(tp, &tp->coal);
7372
7373         /* set status block DMA address */
7374         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7375              ((u64) tp->status_mapping >> 32));
7376         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7377              ((u64) tp->status_mapping & 0xffffffff));
7378
7379         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7380                 /* Status/statistics block address.  See tg3_timer,
7381                  * the tg3_periodic_fetch_stats call there, and
7382                  * tg3_get_stats to see how this works for 5705/5750 chips.
7383                  */
7384                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7385                      ((u64) tp->stats_mapping >> 32));
7386                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7387                      ((u64) tp->stats_mapping & 0xffffffff));
7388                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7389                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7390         }
7391
7392         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7393
7394         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7395         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7396         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7397                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7398
7399         /* Clear statistics/status block in chip, and status block in ram. */
7400         for (i = NIC_SRAM_STATS_BLK;
7401              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7402              i += sizeof(u32)) {
7403                 tg3_write_mem(tp, i, 0);
7404                 udelay(40);
7405         }
7406         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7407
7408         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7409                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7410                 /* reset to prevent losing 1st rx packet intermittently */
7411                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7412                 udelay(10);
7413         }
7414
7415         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7416                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7417         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7418             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7419             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7420                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7421         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7422         udelay(40);
7423
7424         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7425          * If TG3_FLG2_IS_NIC is zero, we should read the
7426          * register to preserve the GPIO settings for LOMs. The GPIOs,
7427          * whether used as inputs or outputs, are set by boot code after
7428          * reset.
7429          */
7430         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7431                 u32 gpio_mask;
7432
7433                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7434                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7435                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7436
7437                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7438                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7439                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7440
7441                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7442                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7443
7444                 tp->grc_local_ctrl &= ~gpio_mask;
7445                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7446
7447                 /* GPIO1 must be driven high for eeprom write protect */
7448                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7449                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7450                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7451         }
7452         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7453         udelay(100);
7454
7455         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7456         tp->last_tag = 0;
7457
7458         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7459                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7460                 udelay(40);
7461         }
7462
7463         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7464                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7465                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7466                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7467                WDMAC_MODE_LNGREAD_ENAB);
7468
7469         /* If statement applies to 5705 and 5750 PCI devices only */
7470         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7471              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7472             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7473                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7474                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7475                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7476                         /* nothing */
7477                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7478                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7479                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7480                         val |= WDMAC_MODE_RX_ACCEL;
7481                 }
7482         }
7483
7484         /* Enable host coalescing bug fix */
7485         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7486             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7487             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7488             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7489             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7490                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7491
7492         tw32_f(WDMAC_MODE, val);
7493         udelay(40);
7494
7495         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7496                 u16 pcix_cmd;
7497
7498                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7499                                      &pcix_cmd);
7500                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7501                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7502                         pcix_cmd |= PCI_X_CMD_READ_2K;
7503                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7504                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7505                         pcix_cmd |= PCI_X_CMD_READ_2K;
7506                 }
7507                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7508                                       pcix_cmd);
7509         }
7510
7511         tw32_f(RDMAC_MODE, rdmac_mode);
7512         udelay(40);
7513
7514         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7515         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7516                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7517
7518         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7519                 tw32(SNDDATAC_MODE,
7520                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7521         else
7522                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7523
7524         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7525         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7526         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7527         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7528         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7529                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7530         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7531         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7532
7533         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7534                 err = tg3_load_5701_a0_firmware_fix(tp);
7535                 if (err)
7536                         return err;
7537         }
7538
7539         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7540                 err = tg3_load_tso_firmware(tp);
7541                 if (err)
7542                         return err;
7543         }
7544
7545         tp->tx_mode = TX_MODE_ENABLE;
7546         tw32_f(MAC_TX_MODE, tp->tx_mode);
7547         udelay(100);
7548
7549         tp->rx_mode = RX_MODE_ENABLE;
7550         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7551             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7552             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7553             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7554                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7555
7556         tw32_f(MAC_RX_MODE, tp->rx_mode);
7557         udelay(10);
7558
7559         tw32(MAC_LED_CTRL, tp->led_ctrl);
7560
7561         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7562         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7563                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7564                 udelay(10);
7565         }
7566         tw32_f(MAC_RX_MODE, tp->rx_mode);
7567         udelay(10);
7568
7569         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7570                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7571                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7572                         /* Set drive transmission level to 1.2V  */
7573                         /* only if the signal pre-emphasis bit is not set  */
7574                         val = tr32(MAC_SERDES_CFG);
7575                         val &= 0xfffff000;
7576                         val |= 0x880;
7577                         tw32(MAC_SERDES_CFG, val);
7578                 }
7579                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7580                         tw32(MAC_SERDES_CFG, 0x616000);
7581         }
7582
7583         /* Prevent chip from dropping frames when flow control
7584          * is enabled.
7585          */
7586         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7587
7588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7589             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7590                 /* Use hardware link auto-negotiation */
7591                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7592         }
7593
7594         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7595             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7596                 u32 tmp;
7597
7598                 tmp = tr32(SERDES_RX_CTRL);
7599                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7600                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7601                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7602                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7603         }
7604
7605         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7606                 if (tp->link_config.phy_is_low_power) {
7607                         tp->link_config.phy_is_low_power = 0;
7608                         tp->link_config.speed = tp->link_config.orig_speed;
7609                         tp->link_config.duplex = tp->link_config.orig_duplex;
7610                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7611                 }
7612
7613                 err = tg3_setup_phy(tp, 0);
7614                 if (err)
7615                         return err;
7616
7617                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7618                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7619                         u32 tmp;
7620
7621                         /* Clear CRC stats. */
7622                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7623                                 tg3_writephy(tp, MII_TG3_TEST1,
7624                                              tmp | MII_TG3_TEST1_CRC_EN);
7625                                 tg3_readphy(tp, 0x14, &tmp);
7626                         }
7627                 }
7628         }
7629
7630         __tg3_set_rx_mode(tp->dev);
7631
7632         /* Initialize receive rules. */
7633         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7634         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7635         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7636         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7637
7638         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7639             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7640                 limit = 8;
7641         else
7642                 limit = 16;
7643         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7644                 limit -= 4;
7645         switch (limit) {
7646         case 16:
7647                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7648         case 15:
7649                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7650         case 14:
7651                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7652         case 13:
7653                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7654         case 12:
7655                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7656         case 11:
7657                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7658         case 10:
7659                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7660         case 9:
7661                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7662         case 8:
7663                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7664         case 7:
7665                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7666         case 6:
7667                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7668         case 5:
7669                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7670         case 4:
7671                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7672         case 3:
7673                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7674         case 2:
7675         case 1:
7676
7677         default:
7678                 break;
7679         }
7680
7681         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7682                 /* Write our heartbeat update interval to APE. */
7683                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7684                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7685
7686         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7687
7688         return 0;
7689 }
7690
7691 /* Called at device open time to get the chip ready for
7692  * packet processing.  Invoked with tp->lock held.
7693  */
7694 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7695 {
7696         tg3_switch_clocks(tp);
7697
7698         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7699
7700         return tg3_reset_hw(tp, reset_phy);
7701 }
7702
7703 #define TG3_STAT_ADD32(PSTAT, REG) \
7704 do {    u32 __val = tr32(REG); \
7705         (PSTAT)->low += __val; \
7706         if ((PSTAT)->low < __val) \
7707                 (PSTAT)->high += 1; \
7708 } while (0)
7709
7710 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7711 {
7712         struct tg3_hw_stats *sp = tp->hw_stats;
7713
7714         if (!netif_carrier_ok(tp->dev))
7715                 return;
7716
7717         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7718         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7719         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7720         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7721         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7722         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7723         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7724         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7725         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7726         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7727         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7728         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7729         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7730
7731         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7732         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7733         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7734         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7735         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7736         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7737         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7738         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7739         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7740         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7741         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7742         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7743         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7744         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7745
7746         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7747         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7748         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7749 }
7750
7751 static void tg3_timer(unsigned long __opaque)
7752 {
7753         struct tg3 *tp = (struct tg3 *) __opaque;
7754
7755         if (tp->irq_sync)
7756                 goto restart_timer;
7757
7758         spin_lock(&tp->lock);
7759
7760         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7761                 /* All of this garbage is because when using non-tagged
7762                  * IRQ status the mailbox/status_block protocol the chip
7763                  * uses with the cpu is race prone.
7764                  */
7765                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7766                         tw32(GRC_LOCAL_CTRL,
7767                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7768                 } else {
7769                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7770                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7771                 }
7772
7773                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7774                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7775                         spin_unlock(&tp->lock);
7776                         schedule_work(&tp->reset_task);
7777                         return;
7778                 }
7779         }
7780
7781         /* This part only runs once per second. */
7782         if (!--tp->timer_counter) {
7783                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7784                         tg3_periodic_fetch_stats(tp);
7785
7786                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7787                         u32 mac_stat;
7788                         int phy_event;
7789
7790                         mac_stat = tr32(MAC_STATUS);
7791
7792                         phy_event = 0;
7793                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7794                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7795                                         phy_event = 1;
7796                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7797                                 phy_event = 1;
7798
7799                         if (phy_event)
7800                                 tg3_setup_phy(tp, 0);
7801                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7802                         u32 mac_stat = tr32(MAC_STATUS);
7803                         int need_setup = 0;
7804
7805                         if (netif_carrier_ok(tp->dev) &&
7806                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7807                                 need_setup = 1;
7808                         }
7809                         if (! netif_carrier_ok(tp->dev) &&
7810                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7811                                          MAC_STATUS_SIGNAL_DET))) {
7812                                 need_setup = 1;
7813                         }
7814                         if (need_setup) {
7815                                 if (!tp->serdes_counter) {
7816                                         tw32_f(MAC_MODE,
7817                                              (tp->mac_mode &
7818                                               ~MAC_MODE_PORT_MODE_MASK));
7819                                         udelay(40);
7820                                         tw32_f(MAC_MODE, tp->mac_mode);
7821                                         udelay(40);
7822                                 }
7823                                 tg3_setup_phy(tp, 0);
7824                         }
7825                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7826                         tg3_serdes_parallel_detect(tp);
7827
7828                 tp->timer_counter = tp->timer_multiplier;
7829         }
7830
7831         /* Heartbeat is only sent once every 2 seconds.
7832          *
7833          * The heartbeat is to tell the ASF firmware that the host
7834          * driver is still alive.  In the event that the OS crashes,
7835          * ASF needs to reset the hardware to free up the FIFO space
7836          * that may be filled with rx packets destined for the host.
7837          * If the FIFO is full, ASF will no longer function properly.
7838          *
7839          * Unintended resets have been reported on real time kernels
7840          * where the timer doesn't run on time.  Netpoll will also have
7841          * same problem.
7842          *
7843          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7844          * to check the ring condition when the heartbeat is expiring
7845          * before doing the reset.  This will prevent most unintended
7846          * resets.
7847          */
7848         if (!--tp->asf_counter) {
7849                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7850                         u32 val;
7851
7852                         tg3_wait_for_event_ack(tp);
7853
7854                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7855                                       FWCMD_NICDRV_ALIVE3);
7856                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7857                         /* 5 seconds timeout */
7858                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7859                         val = tr32(GRC_RX_CPU_EVENT);
7860                         val |= GRC_RX_CPU_DRIVER_EVENT;
7861                         tw32_f(GRC_RX_CPU_EVENT, val);
7862                 }
7863                 tp->asf_counter = tp->asf_multiplier;
7864         }
7865
7866         spin_unlock(&tp->lock);
7867
7868 restart_timer:
7869         tp->timer.expires = jiffies + tp->timer_offset;
7870         add_timer(&tp->timer);
7871 }
7872
7873 static int tg3_request_irq(struct tg3 *tp)
7874 {
7875         irq_handler_t fn;
7876         unsigned long flags;
7877         struct net_device *dev = tp->dev;
7878
7879         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7880                 fn = tg3_msi;
7881                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7882                         fn = tg3_msi_1shot;
7883                 flags = IRQF_SAMPLE_RANDOM;
7884         } else {
7885                 fn = tg3_interrupt;
7886                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7887                         fn = tg3_interrupt_tagged;
7888                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7889         }
7890         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7891 }
7892
7893 static int tg3_test_interrupt(struct tg3 *tp)
7894 {
7895         struct net_device *dev = tp->dev;
7896         int err, i, intr_ok = 0;
7897
7898         if (!netif_running(dev))
7899                 return -ENODEV;
7900
7901         tg3_disable_ints(tp);
7902
7903         free_irq(tp->pdev->irq, dev);
7904
7905         err = request_irq(tp->pdev->irq, tg3_test_isr,
7906                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7907         if (err)
7908                 return err;
7909
7910         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7911         tg3_enable_ints(tp);
7912
7913         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7914                HOSTCC_MODE_NOW);
7915
7916         for (i = 0; i < 5; i++) {
7917                 u32 int_mbox, misc_host_ctrl;
7918
7919                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7920                                         TG3_64BIT_REG_LOW);
7921                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7922
7923                 if ((int_mbox != 0) ||
7924                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7925                         intr_ok = 1;
7926                         break;
7927                 }
7928
7929                 msleep(10);
7930         }
7931
7932         tg3_disable_ints(tp);
7933
7934         free_irq(tp->pdev->irq, dev);
7935
7936         err = tg3_request_irq(tp);
7937
7938         if (err)
7939                 return err;
7940
7941         if (intr_ok)
7942                 return 0;
7943
7944         return -EIO;
7945 }
7946
7947 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7948  * successfully restored
7949  */
7950 static int tg3_test_msi(struct tg3 *tp)
7951 {
7952         struct net_device *dev = tp->dev;
7953         int err;
7954         u16 pci_cmd;
7955
7956         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7957                 return 0;
7958
7959         /* Turn off SERR reporting in case MSI terminates with Master
7960          * Abort.
7961          */
7962         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7963         pci_write_config_word(tp->pdev, PCI_COMMAND,
7964                               pci_cmd & ~PCI_COMMAND_SERR);
7965
7966         err = tg3_test_interrupt(tp);
7967
7968         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7969
7970         if (!err)
7971                 return 0;
7972
7973         /* other failures */
7974         if (err != -EIO)
7975                 return err;
7976
7977         /* MSI test failed, go back to INTx mode */
7978         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7979                "switching to INTx mode. Please report this failure to "
7980                "the PCI maintainer and include system chipset information.\n",
7981                        tp->dev->name);
7982
7983         free_irq(tp->pdev->irq, dev);
7984         pci_disable_msi(tp->pdev);
7985
7986         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7987
7988         err = tg3_request_irq(tp);
7989         if (err)
7990                 return err;
7991
7992         /* Need to reset the chip because the MSI cycle may have terminated
7993          * with Master Abort.
7994          */
7995         tg3_full_lock(tp, 1);
7996
7997         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7998         err = tg3_init_hw(tp, 1);
7999
8000         tg3_full_unlock(tp);
8001
8002         if (err)
8003                 free_irq(tp->pdev->irq, dev);
8004
8005         return err;
8006 }
8007
8008 static int tg3_open(struct net_device *dev)
8009 {
8010         struct tg3 *tp = netdev_priv(dev);
8011         int err;
8012
8013         netif_carrier_off(tp->dev);
8014
8015         err = tg3_set_power_state(tp, PCI_D0);
8016         if (err)
8017                 return err;
8018
8019         tg3_full_lock(tp, 0);
8020
8021         tg3_disable_ints(tp);
8022         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8023
8024         tg3_full_unlock(tp);
8025
8026         /* The placement of this call is tied
8027          * to the setup and use of Host TX descriptors.
8028          */
8029         err = tg3_alloc_consistent(tp);
8030         if (err)
8031                 return err;
8032
8033         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
8034                 /* All MSI supporting chips should support tagged
8035                  * status.  Assert that this is the case.
8036                  */
8037                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8038                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8039                                "Not using MSI.\n", tp->dev->name);
8040                 } else if (pci_enable_msi(tp->pdev) == 0) {
8041                         u32 msi_mode;
8042
8043                         msi_mode = tr32(MSGINT_MODE);
8044                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8045                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8046                 }
8047         }
8048         err = tg3_request_irq(tp);
8049
8050         if (err) {
8051                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8052                         pci_disable_msi(tp->pdev);
8053                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8054                 }
8055                 tg3_free_consistent(tp);
8056                 return err;
8057         }
8058
8059         napi_enable(&tp->napi);
8060
8061         tg3_full_lock(tp, 0);
8062
8063         err = tg3_init_hw(tp, 1);
8064         if (err) {
8065                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8066                 tg3_free_rings(tp);
8067         } else {
8068                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8069                         tp->timer_offset = HZ;
8070                 else
8071                         tp->timer_offset = HZ / 10;
8072
8073                 BUG_ON(tp->timer_offset > HZ);
8074                 tp->timer_counter = tp->timer_multiplier =
8075                         (HZ / tp->timer_offset);
8076                 tp->asf_counter = tp->asf_multiplier =
8077                         ((HZ / tp->timer_offset) * 2);
8078
8079                 init_timer(&tp->timer);
8080                 tp->timer.expires = jiffies + tp->timer_offset;
8081                 tp->timer.data = (unsigned long) tp;
8082                 tp->timer.function = tg3_timer;
8083         }
8084
8085         tg3_full_unlock(tp);
8086
8087         if (err) {
8088                 napi_disable(&tp->napi);
8089                 free_irq(tp->pdev->irq, dev);
8090                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8091                         pci_disable_msi(tp->pdev);
8092                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8093                 }
8094                 tg3_free_consistent(tp);
8095                 return err;
8096         }
8097
8098         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8099                 err = tg3_test_msi(tp);
8100
8101                 if (err) {
8102                         tg3_full_lock(tp, 0);
8103
8104                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8105                                 pci_disable_msi(tp->pdev);
8106                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8107                         }
8108                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8109                         tg3_free_rings(tp);
8110                         tg3_free_consistent(tp);
8111
8112                         tg3_full_unlock(tp);
8113
8114                         napi_disable(&tp->napi);
8115
8116                         return err;
8117                 }
8118
8119                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8120                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8121                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
8122
8123                                 tw32(PCIE_TRANSACTION_CFG,
8124                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
8125                         }
8126                 }
8127         }
8128
8129         tg3_phy_start(tp);
8130
8131         tg3_full_lock(tp, 0);
8132
8133         add_timer(&tp->timer);
8134         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8135         tg3_enable_ints(tp);
8136
8137         tg3_full_unlock(tp);
8138
8139         netif_start_queue(dev);
8140
8141         return 0;
8142 }
8143
8144 #if 0
8145 /*static*/ void tg3_dump_state(struct tg3 *tp)
8146 {
8147         u32 val32, val32_2, val32_3, val32_4, val32_5;
8148         u16 val16;
8149         int i;
8150
8151         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8152         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8153         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8154                val16, val32);
8155
8156         /* MAC block */
8157         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8158                tr32(MAC_MODE), tr32(MAC_STATUS));
8159         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8160                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8161         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8162                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8163         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8164                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8165
8166         /* Send data initiator control block */
8167         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8168                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8169         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8170                tr32(SNDDATAI_STATSCTRL));
8171
8172         /* Send data completion control block */
8173         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8174
8175         /* Send BD ring selector block */
8176         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8177                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8178
8179         /* Send BD initiator control block */
8180         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8181                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8182
8183         /* Send BD completion control block */
8184         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8185
8186         /* Receive list placement control block */
8187         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8188                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8189         printk("       RCVLPC_STATSCTRL[%08x]\n",
8190                tr32(RCVLPC_STATSCTRL));
8191
8192         /* Receive data and receive BD initiator control block */
8193         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8194                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8195
8196         /* Receive data completion control block */
8197         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8198                tr32(RCVDCC_MODE));
8199
8200         /* Receive BD initiator control block */
8201         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8202                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8203
8204         /* Receive BD completion control block */
8205         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8206                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8207
8208         /* Receive list selector control block */
8209         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8210                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8211
8212         /* Mbuf cluster free block */
8213         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8214                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8215
8216         /* Host coalescing control block */
8217         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8218                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8219         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8220                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8221                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8222         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8223                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8224                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8225         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8226                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8227         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8228                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8229
8230         /* Memory arbiter control block */
8231         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8232                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8233
8234         /* Buffer manager control block */
8235         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8236                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8237         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8238                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8239         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8240                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8241                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8242                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8243
8244         /* Read DMA control block */
8245         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8246                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8247
8248         /* Write DMA control block */
8249         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8250                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8251
8252         /* DMA completion block */
8253         printk("DEBUG: DMAC_MODE[%08x]\n",
8254                tr32(DMAC_MODE));
8255
8256         /* GRC block */
8257         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8258                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8259         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8260                tr32(GRC_LOCAL_CTRL));
8261
8262         /* TG3_BDINFOs */
8263         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8264                tr32(RCVDBDI_JUMBO_BD + 0x0),
8265                tr32(RCVDBDI_JUMBO_BD + 0x4),
8266                tr32(RCVDBDI_JUMBO_BD + 0x8),
8267                tr32(RCVDBDI_JUMBO_BD + 0xc));
8268         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8269                tr32(RCVDBDI_STD_BD + 0x0),
8270                tr32(RCVDBDI_STD_BD + 0x4),
8271                tr32(RCVDBDI_STD_BD + 0x8),
8272                tr32(RCVDBDI_STD_BD + 0xc));
8273         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8274                tr32(RCVDBDI_MINI_BD + 0x0),
8275                tr32(RCVDBDI_MINI_BD + 0x4),
8276                tr32(RCVDBDI_MINI_BD + 0x8),
8277                tr32(RCVDBDI_MINI_BD + 0xc));
8278
8279         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8280         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8281         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8282         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8283         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8284                val32, val32_2, val32_3, val32_4);
8285
8286         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8287         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8288         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8289         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8290         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8291                val32, val32_2, val32_3, val32_4);
8292
8293         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8294         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8295         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8296         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8297         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8298         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8299                val32, val32_2, val32_3, val32_4, val32_5);
8300
8301         /* SW status block */
8302         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8303                tp->hw_status->status,
8304                tp->hw_status->status_tag,
8305                tp->hw_status->rx_jumbo_consumer,
8306                tp->hw_status->rx_consumer,
8307                tp->hw_status->rx_mini_consumer,
8308                tp->hw_status->idx[0].rx_producer,
8309                tp->hw_status->idx[0].tx_consumer);
8310
8311         /* SW statistics block */
8312         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8313                ((u32 *)tp->hw_stats)[0],
8314                ((u32 *)tp->hw_stats)[1],
8315                ((u32 *)tp->hw_stats)[2],
8316                ((u32 *)tp->hw_stats)[3]);
8317
8318         /* Mailboxes */
8319         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8320                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8321                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8322                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8323                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8324
8325         /* NIC side send descriptors. */
8326         for (i = 0; i < 6; i++) {
8327                 unsigned long txd;
8328
8329                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8330                         + (i * sizeof(struct tg3_tx_buffer_desc));
8331                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8332                        i,
8333                        readl(txd + 0x0), readl(txd + 0x4),
8334                        readl(txd + 0x8), readl(txd + 0xc));
8335         }
8336
8337         /* NIC side RX descriptors. */
8338         for (i = 0; i < 6; i++) {
8339                 unsigned long rxd;
8340
8341                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8342                         + (i * sizeof(struct tg3_rx_buffer_desc));
8343                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8344                        i,
8345                        readl(rxd + 0x0), readl(rxd + 0x4),
8346                        readl(rxd + 0x8), readl(rxd + 0xc));
8347                 rxd += (4 * sizeof(u32));
8348                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8349                        i,
8350                        readl(rxd + 0x0), readl(rxd + 0x4),
8351                        readl(rxd + 0x8), readl(rxd + 0xc));
8352         }
8353
8354         for (i = 0; i < 6; i++) {
8355                 unsigned long rxd;
8356
8357                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8358                         + (i * sizeof(struct tg3_rx_buffer_desc));
8359                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8360                        i,
8361                        readl(rxd + 0x0), readl(rxd + 0x4),
8362                        readl(rxd + 0x8), readl(rxd + 0xc));
8363                 rxd += (4 * sizeof(u32));
8364                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8365                        i,
8366                        readl(rxd + 0x0), readl(rxd + 0x4),
8367                        readl(rxd + 0x8), readl(rxd + 0xc));
8368         }
8369 }
8370 #endif
8371
8372 static struct net_device_stats *tg3_get_stats(struct net_device *);
8373 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8374
8375 static int tg3_close(struct net_device *dev)
8376 {
8377         struct tg3 *tp = netdev_priv(dev);
8378
8379         napi_disable(&tp->napi);
8380         cancel_work_sync(&tp->reset_task);
8381
8382         netif_stop_queue(dev);
8383
8384         del_timer_sync(&tp->timer);
8385
8386         tg3_full_lock(tp, 1);
8387 #if 0
8388         tg3_dump_state(tp);
8389 #endif
8390
8391         tg3_disable_ints(tp);
8392
8393         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8394         tg3_free_rings(tp);
8395         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8396
8397         tg3_full_unlock(tp);
8398
8399         free_irq(tp->pdev->irq, dev);
8400         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8401                 pci_disable_msi(tp->pdev);
8402                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8403         }
8404
8405         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8406                sizeof(tp->net_stats_prev));
8407         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8408                sizeof(tp->estats_prev));
8409
8410         tg3_free_consistent(tp);
8411
8412         tg3_set_power_state(tp, PCI_D3hot);
8413
8414         netif_carrier_off(tp->dev);
8415
8416         return 0;
8417 }
8418
8419 static inline unsigned long get_stat64(tg3_stat64_t *val)
8420 {
8421         unsigned long ret;
8422
8423 #if (BITS_PER_LONG == 32)
8424         ret = val->low;
8425 #else
8426         ret = ((u64)val->high << 32) | ((u64)val->low);
8427 #endif
8428         return ret;
8429 }
8430
8431 static unsigned long calc_crc_errors(struct tg3 *tp)
8432 {
8433         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8434
8435         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8436             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8437              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8438                 u32 val;
8439
8440                 spin_lock_bh(&tp->lock);
8441                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8442                         tg3_writephy(tp, MII_TG3_TEST1,
8443                                      val | MII_TG3_TEST1_CRC_EN);
8444                         tg3_readphy(tp, 0x14, &val);
8445                 } else
8446                         val = 0;
8447                 spin_unlock_bh(&tp->lock);
8448
8449                 tp->phy_crc_errors += val;
8450
8451                 return tp->phy_crc_errors;
8452         }
8453
8454         return get_stat64(&hw_stats->rx_fcs_errors);
8455 }
8456
8457 #define ESTAT_ADD(member) \
8458         estats->member =        old_estats->member + \
8459                                 get_stat64(&hw_stats->member)
8460
8461 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8462 {
8463         struct tg3_ethtool_stats *estats = &tp->estats;
8464         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8465         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8466
8467         if (!hw_stats)
8468                 return old_estats;
8469
8470         ESTAT_ADD(rx_octets);
8471         ESTAT_ADD(rx_fragments);
8472         ESTAT_ADD(rx_ucast_packets);
8473         ESTAT_ADD(rx_mcast_packets);
8474         ESTAT_ADD(rx_bcast_packets);
8475         ESTAT_ADD(rx_fcs_errors);
8476         ESTAT_ADD(rx_align_errors);
8477         ESTAT_ADD(rx_xon_pause_rcvd);
8478         ESTAT_ADD(rx_xoff_pause_rcvd);
8479         ESTAT_ADD(rx_mac_ctrl_rcvd);
8480         ESTAT_ADD(rx_xoff_entered);
8481         ESTAT_ADD(rx_frame_too_long_errors);
8482         ESTAT_ADD(rx_jabbers);
8483         ESTAT_ADD(rx_undersize_packets);
8484         ESTAT_ADD(rx_in_length_errors);
8485         ESTAT_ADD(rx_out_length_errors);
8486         ESTAT_ADD(rx_64_or_less_octet_packets);
8487         ESTAT_ADD(rx_65_to_127_octet_packets);
8488         ESTAT_ADD(rx_128_to_255_octet_packets);
8489         ESTAT_ADD(rx_256_to_511_octet_packets);
8490         ESTAT_ADD(rx_512_to_1023_octet_packets);
8491         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8492         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8493         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8494         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8495         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8496
8497         ESTAT_ADD(tx_octets);
8498         ESTAT_ADD(tx_collisions);
8499         ESTAT_ADD(tx_xon_sent);
8500         ESTAT_ADD(tx_xoff_sent);
8501         ESTAT_ADD(tx_flow_control);
8502         ESTAT_ADD(tx_mac_errors);
8503         ESTAT_ADD(tx_single_collisions);
8504         ESTAT_ADD(tx_mult_collisions);
8505         ESTAT_ADD(tx_deferred);
8506         ESTAT_ADD(tx_excessive_collisions);
8507         ESTAT_ADD(tx_late_collisions);
8508         ESTAT_ADD(tx_collide_2times);
8509         ESTAT_ADD(tx_collide_3times);
8510         ESTAT_ADD(tx_collide_4times);
8511         ESTAT_ADD(tx_collide_5times);
8512         ESTAT_ADD(tx_collide_6times);
8513         ESTAT_ADD(tx_collide_7times);
8514         ESTAT_ADD(tx_collide_8times);
8515         ESTAT_ADD(tx_collide_9times);
8516         ESTAT_ADD(tx_collide_10times);
8517         ESTAT_ADD(tx_collide_11times);
8518         ESTAT_ADD(tx_collide_12times);
8519         ESTAT_ADD(tx_collide_13times);
8520         ESTAT_ADD(tx_collide_14times);
8521         ESTAT_ADD(tx_collide_15times);
8522         ESTAT_ADD(tx_ucast_packets);
8523         ESTAT_ADD(tx_mcast_packets);
8524         ESTAT_ADD(tx_bcast_packets);
8525         ESTAT_ADD(tx_carrier_sense_errors);
8526         ESTAT_ADD(tx_discards);
8527         ESTAT_ADD(tx_errors);
8528
8529         ESTAT_ADD(dma_writeq_full);
8530         ESTAT_ADD(dma_write_prioq_full);
8531         ESTAT_ADD(rxbds_empty);
8532         ESTAT_ADD(rx_discards);
8533         ESTAT_ADD(rx_errors);
8534         ESTAT_ADD(rx_threshold_hit);
8535
8536         ESTAT_ADD(dma_readq_full);
8537         ESTAT_ADD(dma_read_prioq_full);
8538         ESTAT_ADD(tx_comp_queue_full);
8539
8540         ESTAT_ADD(ring_set_send_prod_index);
8541         ESTAT_ADD(ring_status_update);
8542         ESTAT_ADD(nic_irqs);
8543         ESTAT_ADD(nic_avoided_irqs);
8544         ESTAT_ADD(nic_tx_threshold_hit);
8545
8546         return estats;
8547 }
8548
8549 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8550 {
8551         struct tg3 *tp = netdev_priv(dev);
8552         struct net_device_stats *stats = &tp->net_stats;
8553         struct net_device_stats *old_stats = &tp->net_stats_prev;
8554         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8555
8556         if (!hw_stats)
8557                 return old_stats;
8558
8559         stats->rx_packets = old_stats->rx_packets +
8560                 get_stat64(&hw_stats->rx_ucast_packets) +
8561                 get_stat64(&hw_stats->rx_mcast_packets) +
8562                 get_stat64(&hw_stats->rx_bcast_packets);
8563
8564         stats->tx_packets = old_stats->tx_packets +
8565                 get_stat64(&hw_stats->tx_ucast_packets) +
8566                 get_stat64(&hw_stats->tx_mcast_packets) +
8567                 get_stat64(&hw_stats->tx_bcast_packets);
8568
8569         stats->rx_bytes = old_stats->rx_bytes +
8570                 get_stat64(&hw_stats->rx_octets);
8571         stats->tx_bytes = old_stats->tx_bytes +
8572                 get_stat64(&hw_stats->tx_octets);
8573
8574         stats->rx_errors = old_stats->rx_errors +
8575                 get_stat64(&hw_stats->rx_errors);
8576         stats->tx_errors = old_stats->tx_errors +
8577                 get_stat64(&hw_stats->tx_errors) +
8578                 get_stat64(&hw_stats->tx_mac_errors) +
8579                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8580                 get_stat64(&hw_stats->tx_discards);
8581
8582         stats->multicast = old_stats->multicast +
8583                 get_stat64(&hw_stats->rx_mcast_packets);
8584         stats->collisions = old_stats->collisions +
8585                 get_stat64(&hw_stats->tx_collisions);
8586
8587         stats->rx_length_errors = old_stats->rx_length_errors +
8588                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8589                 get_stat64(&hw_stats->rx_undersize_packets);
8590
8591         stats->rx_over_errors = old_stats->rx_over_errors +
8592                 get_stat64(&hw_stats->rxbds_empty);
8593         stats->rx_frame_errors = old_stats->rx_frame_errors +
8594                 get_stat64(&hw_stats->rx_align_errors);
8595         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8596                 get_stat64(&hw_stats->tx_discards);
8597         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8598                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8599
8600         stats->rx_crc_errors = old_stats->rx_crc_errors +
8601                 calc_crc_errors(tp);
8602
8603         stats->rx_missed_errors = old_stats->rx_missed_errors +
8604                 get_stat64(&hw_stats->rx_discards);
8605
8606         return stats;
8607 }
8608
8609 static inline u32 calc_crc(unsigned char *buf, int len)
8610 {
8611         u32 reg;
8612         u32 tmp;
8613         int j, k;
8614
8615         reg = 0xffffffff;
8616
8617         for (j = 0; j < len; j++) {
8618                 reg ^= buf[j];
8619
8620                 for (k = 0; k < 8; k++) {
8621                         tmp = reg & 0x01;
8622
8623                         reg >>= 1;
8624
8625                         if (tmp) {
8626                                 reg ^= 0xedb88320;
8627                         }
8628                 }
8629         }
8630
8631         return ~reg;
8632 }
8633
8634 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8635 {
8636         /* accept or reject all multicast frames */
8637         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8638         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8639         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8640         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8641 }
8642
8643 static void __tg3_set_rx_mode(struct net_device *dev)
8644 {
8645         struct tg3 *tp = netdev_priv(dev);
8646         u32 rx_mode;
8647
8648         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8649                                   RX_MODE_KEEP_VLAN_TAG);
8650
8651         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8652          * flag clear.
8653          */
8654 #if TG3_VLAN_TAG_USED
8655         if (!tp->vlgrp &&
8656             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8657                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8658 #else
8659         /* By definition, VLAN is disabled always in this
8660          * case.
8661          */
8662         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8663                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8664 #endif
8665
8666         if (dev->flags & IFF_PROMISC) {
8667                 /* Promiscuous mode. */
8668                 rx_mode |= RX_MODE_PROMISC;
8669         } else if (dev->flags & IFF_ALLMULTI) {
8670                 /* Accept all multicast. */
8671                 tg3_set_multi (tp, 1);
8672         } else if (dev->mc_count < 1) {
8673                 /* Reject all multicast. */
8674                 tg3_set_multi (tp, 0);
8675         } else {
8676                 /* Accept one or more multicast(s). */
8677                 struct dev_mc_list *mclist;
8678                 unsigned int i;
8679                 u32 mc_filter[4] = { 0, };
8680                 u32 regidx;
8681                 u32 bit;
8682                 u32 crc;
8683
8684                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8685                      i++, mclist = mclist->next) {
8686
8687                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8688                         bit = ~crc & 0x7f;
8689                         regidx = (bit & 0x60) >> 5;
8690                         bit &= 0x1f;
8691                         mc_filter[regidx] |= (1 << bit);
8692                 }
8693
8694                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8695                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8696                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8697                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8698         }
8699
8700         if (rx_mode != tp->rx_mode) {
8701                 tp->rx_mode = rx_mode;
8702                 tw32_f(MAC_RX_MODE, rx_mode);
8703                 udelay(10);
8704         }
8705 }
8706
8707 static void tg3_set_rx_mode(struct net_device *dev)
8708 {
8709         struct tg3 *tp = netdev_priv(dev);
8710
8711         if (!netif_running(dev))
8712                 return;
8713
8714         tg3_full_lock(tp, 0);
8715         __tg3_set_rx_mode(dev);
8716         tg3_full_unlock(tp);
8717 }
8718
8719 #define TG3_REGDUMP_LEN         (32 * 1024)
8720
8721 static int tg3_get_regs_len(struct net_device *dev)
8722 {
8723         return TG3_REGDUMP_LEN;
8724 }
8725
8726 static void tg3_get_regs(struct net_device *dev,
8727                 struct ethtool_regs *regs, void *_p)
8728 {
8729         u32 *p = _p;
8730         struct tg3 *tp = netdev_priv(dev);
8731         u8 *orig_p = _p;
8732         int i;
8733
8734         regs->version = 0;
8735
8736         memset(p, 0, TG3_REGDUMP_LEN);
8737
8738         if (tp->link_config.phy_is_low_power)
8739                 return;
8740
8741         tg3_full_lock(tp, 0);
8742
8743 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8744 #define GET_REG32_LOOP(base,len)                \
8745 do {    p = (u32 *)(orig_p + (base));           \
8746         for (i = 0; i < len; i += 4)            \
8747                 __GET_REG32((base) + i);        \
8748 } while (0)
8749 #define GET_REG32_1(reg)                        \
8750 do {    p = (u32 *)(orig_p + (reg));            \
8751         __GET_REG32((reg));                     \
8752 } while (0)
8753
8754         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8755         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8756         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8757         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8758         GET_REG32_1(SNDDATAC_MODE);
8759         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8760         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8761         GET_REG32_1(SNDBDC_MODE);
8762         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8763         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8764         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8765         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8766         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8767         GET_REG32_1(RCVDCC_MODE);
8768         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8769         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8770         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8771         GET_REG32_1(MBFREE_MODE);
8772         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8773         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8774         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8775         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8776         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8777         GET_REG32_1(RX_CPU_MODE);
8778         GET_REG32_1(RX_CPU_STATE);
8779         GET_REG32_1(RX_CPU_PGMCTR);
8780         GET_REG32_1(RX_CPU_HWBKPT);
8781         GET_REG32_1(TX_CPU_MODE);
8782         GET_REG32_1(TX_CPU_STATE);
8783         GET_REG32_1(TX_CPU_PGMCTR);
8784         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8785         GET_REG32_LOOP(FTQ_RESET, 0x120);
8786         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8787         GET_REG32_1(DMAC_MODE);
8788         GET_REG32_LOOP(GRC_MODE, 0x4c);
8789         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8790                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8791
8792 #undef __GET_REG32
8793 #undef GET_REG32_LOOP
8794 #undef GET_REG32_1
8795
8796         tg3_full_unlock(tp);
8797 }
8798
8799 static int tg3_get_eeprom_len(struct net_device *dev)
8800 {
8801         struct tg3 *tp = netdev_priv(dev);
8802
8803         return tp->nvram_size;
8804 }
8805
8806 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8807 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8808 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8809
8810 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8811 {
8812         struct tg3 *tp = netdev_priv(dev);
8813         int ret;
8814         u8  *pd;
8815         u32 i, offset, len, b_offset, b_count;
8816         __le32 val;
8817
8818         if (tp->link_config.phy_is_low_power)
8819                 return -EAGAIN;
8820
8821         offset = eeprom->offset;
8822         len = eeprom->len;
8823         eeprom->len = 0;
8824
8825         eeprom->magic = TG3_EEPROM_MAGIC;
8826
8827         if (offset & 3) {
8828                 /* adjustments to start on required 4 byte boundary */
8829                 b_offset = offset & 3;
8830                 b_count = 4 - b_offset;
8831                 if (b_count > len) {
8832                         /* i.e. offset=1 len=2 */
8833                         b_count = len;
8834                 }
8835                 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8836                 if (ret)
8837                         return ret;
8838                 memcpy(data, ((char*)&val) + b_offset, b_count);
8839                 len -= b_count;
8840                 offset += b_count;
8841                 eeprom->len += b_count;
8842         }
8843
8844         /* read bytes upto the last 4 byte boundary */
8845         pd = &data[eeprom->len];
8846         for (i = 0; i < (len - (len & 3)); i += 4) {
8847                 ret = tg3_nvram_read_le(tp, offset + i, &val);
8848                 if (ret) {
8849                         eeprom->len += i;
8850                         return ret;
8851                 }
8852                 memcpy(pd + i, &val, 4);
8853         }
8854         eeprom->len += i;
8855
8856         if (len & 3) {
8857                 /* read last bytes not ending on 4 byte boundary */
8858                 pd = &data[eeprom->len];
8859                 b_count = len & 3;
8860                 b_offset = offset + len - b_count;
8861                 ret = tg3_nvram_read_le(tp, b_offset, &val);
8862                 if (ret)
8863                         return ret;
8864                 memcpy(pd, &val, b_count);
8865                 eeprom->len += b_count;
8866         }
8867         return 0;
8868 }
8869
8870 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8871
8872 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8873 {
8874         struct tg3 *tp = netdev_priv(dev);
8875         int ret;
8876         u32 offset, len, b_offset, odd_len;
8877         u8 *buf;
8878         __le32 start, end;
8879
8880         if (tp->link_config.phy_is_low_power)
8881                 return -EAGAIN;
8882
8883         if (eeprom->magic != TG3_EEPROM_MAGIC)
8884                 return -EINVAL;
8885
8886         offset = eeprom->offset;
8887         len = eeprom->len;
8888
8889         if ((b_offset = (offset & 3))) {
8890                 /* adjustments to start on required 4 byte boundary */
8891                 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8892                 if (ret)
8893                         return ret;
8894                 len += b_offset;
8895                 offset &= ~3;
8896                 if (len < 4)
8897                         len = 4;
8898         }
8899
8900         odd_len = 0;
8901         if (len & 3) {
8902                 /* adjustments to end on required 4 byte boundary */
8903                 odd_len = 1;
8904                 len = (len + 3) & ~3;
8905                 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8906                 if (ret)
8907                         return ret;
8908         }
8909
8910         buf = data;
8911         if (b_offset || odd_len) {
8912                 buf = kmalloc(len, GFP_KERNEL);
8913                 if (!buf)
8914                         return -ENOMEM;
8915                 if (b_offset)
8916                         memcpy(buf, &start, 4);
8917                 if (odd_len)
8918                         memcpy(buf+len-4, &end, 4);
8919                 memcpy(buf + b_offset, data, eeprom->len);
8920         }
8921
8922         ret = tg3_nvram_write_block(tp, offset, len, buf);
8923
8924         if (buf != data)
8925                 kfree(buf);
8926
8927         return ret;
8928 }
8929
8930 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8931 {
8932         struct tg3 *tp = netdev_priv(dev);
8933
8934         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8935                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8936                         return -EAGAIN;
8937                 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8938         }
8939
8940         cmd->supported = (SUPPORTED_Autoneg);
8941
8942         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8943                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8944                                    SUPPORTED_1000baseT_Full);
8945
8946         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8947                 cmd->supported |= (SUPPORTED_100baseT_Half |
8948                                   SUPPORTED_100baseT_Full |
8949                                   SUPPORTED_10baseT_Half |
8950                                   SUPPORTED_10baseT_Full |
8951                                   SUPPORTED_TP);
8952                 cmd->port = PORT_TP;
8953         } else {
8954                 cmd->supported |= SUPPORTED_FIBRE;
8955                 cmd->port = PORT_FIBRE;
8956         }
8957
8958         cmd->advertising = tp->link_config.advertising;
8959         if (netif_running(dev)) {
8960                 cmd->speed = tp->link_config.active_speed;
8961                 cmd->duplex = tp->link_config.active_duplex;
8962         }
8963         cmd->phy_address = PHY_ADDR;
8964         cmd->transceiver = 0;
8965         cmd->autoneg = tp->link_config.autoneg;
8966         cmd->maxtxpkt = 0;
8967         cmd->maxrxpkt = 0;
8968         return 0;
8969 }
8970
8971 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8972 {
8973         struct tg3 *tp = netdev_priv(dev);
8974
8975         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8976                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8977                         return -EAGAIN;
8978                 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8979         }
8980
8981         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8982                 /* These are the only valid advertisement bits allowed.  */
8983                 if (cmd->autoneg == AUTONEG_ENABLE &&
8984                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8985                                           ADVERTISED_1000baseT_Full |
8986                                           ADVERTISED_Autoneg |
8987                                           ADVERTISED_FIBRE)))
8988                         return -EINVAL;
8989                 /* Fiber can only do SPEED_1000.  */
8990                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8991                          (cmd->speed != SPEED_1000))
8992                         return -EINVAL;
8993         /* Copper cannot force SPEED_1000.  */
8994         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8995                    (cmd->speed == SPEED_1000))
8996                 return -EINVAL;
8997         else if ((cmd->speed == SPEED_1000) &&
8998                  (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8999                 return -EINVAL;
9000
9001         tg3_full_lock(tp, 0);
9002
9003         tp->link_config.autoneg = cmd->autoneg;
9004         if (cmd->autoneg == AUTONEG_ENABLE) {
9005                 tp->link_config.advertising = (cmd->advertising |
9006                                               ADVERTISED_Autoneg);
9007                 tp->link_config.speed = SPEED_INVALID;
9008                 tp->link_config.duplex = DUPLEX_INVALID;
9009         } else {
9010                 tp->link_config.advertising = 0;
9011                 tp->link_config.speed = cmd->speed;
9012                 tp->link_config.duplex = cmd->duplex;
9013         }
9014
9015         tp->link_config.orig_speed = tp->link_config.speed;
9016         tp->link_config.orig_duplex = tp->link_config.duplex;
9017         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9018
9019         if (netif_running(dev))
9020                 tg3_setup_phy(tp, 1);
9021
9022         tg3_full_unlock(tp);
9023
9024         return 0;
9025 }
9026
9027 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9028 {
9029         struct tg3 *tp = netdev_priv(dev);
9030
9031         strcpy(info->driver, DRV_MODULE_NAME);
9032         strcpy(info->version, DRV_MODULE_VERSION);
9033         strcpy(info->fw_version, tp->fw_ver);
9034         strcpy(info->bus_info, pci_name(tp->pdev));
9035 }
9036
9037 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9038 {
9039         struct tg3 *tp = netdev_priv(dev);
9040
9041         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9042             device_can_wakeup(&tp->pdev->dev))
9043                 wol->supported = WAKE_MAGIC;
9044         else
9045                 wol->supported = 0;
9046         wol->wolopts = 0;
9047         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
9048                 wol->wolopts = WAKE_MAGIC;
9049         memset(&wol->sopass, 0, sizeof(wol->sopass));
9050 }
9051
9052 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9053 {
9054         struct tg3 *tp = netdev_priv(dev);
9055         struct device *dp = &tp->pdev->dev;
9056
9057         if (wol->wolopts & ~WAKE_MAGIC)
9058                 return -EINVAL;
9059         if ((wol->wolopts & WAKE_MAGIC) &&
9060             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9061                 return -EINVAL;
9062
9063         spin_lock_bh(&tp->lock);
9064         if (wol->wolopts & WAKE_MAGIC) {
9065                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9066                 device_set_wakeup_enable(dp, true);
9067         } else {
9068                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9069                 device_set_wakeup_enable(dp, false);
9070         }
9071         spin_unlock_bh(&tp->lock);
9072
9073         return 0;
9074 }
9075
9076 static u32 tg3_get_msglevel(struct net_device *dev)
9077 {
9078         struct tg3 *tp = netdev_priv(dev);
9079         return tp->msg_enable;
9080 }
9081
9082 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9083 {
9084         struct tg3 *tp = netdev_priv(dev);
9085         tp->msg_enable = value;
9086 }
9087
9088 static int tg3_set_tso(struct net_device *dev, u32 value)
9089 {
9090         struct tg3 *tp = netdev_priv(dev);
9091
9092         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9093                 if (value)
9094                         return -EINVAL;
9095                 return 0;
9096         }
9097         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9098             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9099                 if (value) {
9100                         dev->features |= NETIF_F_TSO6;
9101                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9102                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9103                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9104                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9105                                 dev->features |= NETIF_F_TSO_ECN;
9106                 } else
9107                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9108         }
9109         return ethtool_op_set_tso(dev, value);
9110 }
9111
9112 static int tg3_nway_reset(struct net_device *dev)
9113 {
9114         struct tg3 *tp = netdev_priv(dev);
9115         int r;
9116
9117         if (!netif_running(dev))
9118                 return -EAGAIN;
9119
9120         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9121                 return -EINVAL;
9122
9123         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9124                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9125                         return -EAGAIN;
9126                 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
9127         } else {
9128                 u32 bmcr;
9129
9130                 spin_lock_bh(&tp->lock);
9131                 r = -EINVAL;
9132                 tg3_readphy(tp, MII_BMCR, &bmcr);
9133                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9134                     ((bmcr & BMCR_ANENABLE) ||
9135                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9136                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9137                                                    BMCR_ANENABLE);
9138                         r = 0;
9139                 }
9140                 spin_unlock_bh(&tp->lock);
9141         }
9142
9143         return r;
9144 }
9145
9146 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9147 {
9148         struct tg3 *tp = netdev_priv(dev);
9149
9150         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9151         ering->rx_mini_max_pending = 0;
9152         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9153                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9154         else
9155                 ering->rx_jumbo_max_pending = 0;
9156
9157         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9158
9159         ering->rx_pending = tp->rx_pending;
9160         ering->rx_mini_pending = 0;
9161         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9162                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9163         else
9164                 ering->rx_jumbo_pending = 0;
9165
9166         ering->tx_pending = tp->tx_pending;
9167 }
9168
9169 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9170 {
9171         struct tg3 *tp = netdev_priv(dev);
9172         int irq_sync = 0, err = 0;
9173
9174         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9175             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9176             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9177             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9178             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9179              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9180                 return -EINVAL;
9181
9182         if (netif_running(dev)) {
9183                 tg3_phy_stop(tp);
9184                 tg3_netif_stop(tp);
9185                 irq_sync = 1;
9186         }
9187
9188         tg3_full_lock(tp, irq_sync);
9189
9190         tp->rx_pending = ering->rx_pending;
9191
9192         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9193             tp->rx_pending > 63)
9194                 tp->rx_pending = 63;
9195         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9196         tp->tx_pending = ering->tx_pending;
9197
9198         if (netif_running(dev)) {
9199                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9200                 err = tg3_restart_hw(tp, 1);
9201                 if (!err)
9202                         tg3_netif_start(tp);
9203         }
9204
9205         tg3_full_unlock(tp);
9206
9207         if (irq_sync && !err)
9208                 tg3_phy_start(tp);
9209
9210         return err;
9211 }
9212
9213 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9214 {
9215         struct tg3 *tp = netdev_priv(dev);
9216
9217         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9218
9219         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
9220                 epause->rx_pause = 1;
9221         else
9222                 epause->rx_pause = 0;
9223
9224         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
9225                 epause->tx_pause = 1;
9226         else
9227                 epause->tx_pause = 0;
9228 }
9229
9230 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9231 {
9232         struct tg3 *tp = netdev_priv(dev);
9233         int err = 0;
9234
9235         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9236                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9237                         return -EAGAIN;
9238
9239                 if (epause->autoneg) {
9240                         u32 newadv;
9241                         struct phy_device *phydev;
9242
9243                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
9244
9245                         if (epause->rx_pause) {
9246                                 if (epause->tx_pause)
9247                                         newadv = ADVERTISED_Pause;
9248                                 else
9249                                         newadv = ADVERTISED_Pause |
9250                                                  ADVERTISED_Asym_Pause;
9251                         } else if (epause->tx_pause) {
9252                                 newadv = ADVERTISED_Asym_Pause;
9253                         } else
9254                                 newadv = 0;
9255
9256                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9257                                 u32 oldadv = phydev->advertising &
9258                                              (ADVERTISED_Pause |
9259                                               ADVERTISED_Asym_Pause);
9260                                 if (oldadv != newadv) {
9261                                         phydev->advertising &=
9262                                                 ~(ADVERTISED_Pause |
9263                                                   ADVERTISED_Asym_Pause);
9264                                         phydev->advertising |= newadv;
9265                                         err = phy_start_aneg(phydev);
9266                                 }
9267                         } else {
9268                                 tp->link_config.advertising &=
9269                                                 ~(ADVERTISED_Pause |
9270                                                   ADVERTISED_Asym_Pause);
9271                                 tp->link_config.advertising |= newadv;
9272                         }
9273                 } else {
9274                         if (epause->rx_pause)
9275                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9276                         else
9277                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9278
9279                         if (epause->tx_pause)
9280                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9281                         else
9282                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9283
9284                         if (netif_running(dev))
9285                                 tg3_setup_flow_control(tp, 0, 0);
9286                 }
9287         } else {
9288                 int irq_sync = 0;
9289
9290                 if (netif_running(dev)) {
9291                         tg3_netif_stop(tp);
9292                         irq_sync = 1;
9293                 }
9294
9295                 tg3_full_lock(tp, irq_sync);
9296
9297                 if (epause->autoneg)
9298                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9299                 else
9300                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9301                 if (epause->rx_pause)
9302                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9303                 else
9304                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9305                 if (epause->tx_pause)
9306                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9307                 else
9308                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9309
9310                 if (netif_running(dev)) {
9311                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9312                         err = tg3_restart_hw(tp, 1);
9313                         if (!err)
9314                                 tg3_netif_start(tp);
9315                 }
9316
9317                 tg3_full_unlock(tp);
9318         }
9319
9320         return err;
9321 }
9322
9323 static u32 tg3_get_rx_csum(struct net_device *dev)
9324 {
9325         struct tg3 *tp = netdev_priv(dev);
9326         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9327 }
9328
9329 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9330 {
9331         struct tg3 *tp = netdev_priv(dev);
9332
9333         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9334                 if (data != 0)
9335                         return -EINVAL;
9336                 return 0;
9337         }
9338
9339         spin_lock_bh(&tp->lock);
9340         if (data)
9341                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9342         else
9343                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9344         spin_unlock_bh(&tp->lock);
9345
9346         return 0;
9347 }
9348
9349 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9350 {
9351         struct tg3 *tp = netdev_priv(dev);
9352
9353         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9354                 if (data != 0)
9355                         return -EINVAL;
9356                 return 0;
9357         }
9358
9359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9360             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9361             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9362             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9363             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9364                 ethtool_op_set_tx_ipv6_csum(dev, data);
9365         else
9366                 ethtool_op_set_tx_csum(dev, data);
9367
9368         return 0;
9369 }
9370
9371 static int tg3_get_sset_count (struct net_device *dev, int sset)
9372 {
9373         switch (sset) {
9374         case ETH_SS_TEST:
9375                 return TG3_NUM_TEST;
9376         case ETH_SS_STATS:
9377                 return TG3_NUM_STATS;
9378         default:
9379                 return -EOPNOTSUPP;
9380         }
9381 }
9382
9383 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9384 {
9385         switch (stringset) {
9386         case ETH_SS_STATS:
9387                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9388                 break;
9389         case ETH_SS_TEST:
9390                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9391                 break;
9392         default:
9393                 WARN_ON(1);     /* we need a WARN() */
9394                 break;
9395         }
9396 }
9397
9398 static int tg3_phys_id(struct net_device *dev, u32 data)
9399 {
9400         struct tg3 *tp = netdev_priv(dev);
9401         int i;
9402
9403         if (!netif_running(tp->dev))
9404                 return -EAGAIN;
9405
9406         if (data == 0)
9407                 data = UINT_MAX / 2;
9408
9409         for (i = 0; i < (data * 2); i++) {
9410                 if ((i % 2) == 0)
9411                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9412                                            LED_CTRL_1000MBPS_ON |
9413                                            LED_CTRL_100MBPS_ON |
9414                                            LED_CTRL_10MBPS_ON |
9415                                            LED_CTRL_TRAFFIC_OVERRIDE |
9416                                            LED_CTRL_TRAFFIC_BLINK |
9417                                            LED_CTRL_TRAFFIC_LED);
9418
9419                 else
9420                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9421                                            LED_CTRL_TRAFFIC_OVERRIDE);
9422
9423                 if (msleep_interruptible(500))
9424                         break;
9425         }
9426         tw32(MAC_LED_CTRL, tp->led_ctrl);
9427         return 0;
9428 }
9429
9430 static void tg3_get_ethtool_stats (struct net_device *dev,
9431                                    struct ethtool_stats *estats, u64 *tmp_stats)
9432 {
9433         struct tg3 *tp = netdev_priv(dev);
9434         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9435 }
9436
9437 #define NVRAM_TEST_SIZE 0x100
9438 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9439 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9440 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9441 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9442 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9443
9444 static int tg3_test_nvram(struct tg3 *tp)
9445 {
9446         u32 csum, magic;
9447         __le32 *buf;
9448         int i, j, k, err = 0, size;
9449
9450         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9451                 return -EIO;
9452
9453         if (magic == TG3_EEPROM_MAGIC)
9454                 size = NVRAM_TEST_SIZE;
9455         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9456                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9457                     TG3_EEPROM_SB_FORMAT_1) {
9458                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9459                         case TG3_EEPROM_SB_REVISION_0:
9460                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9461                                 break;
9462                         case TG3_EEPROM_SB_REVISION_2:
9463                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9464                                 break;
9465                         case TG3_EEPROM_SB_REVISION_3:
9466                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9467                                 break;
9468                         default:
9469                                 return 0;
9470                         }
9471                 } else
9472                         return 0;
9473         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9474                 size = NVRAM_SELFBOOT_HW_SIZE;
9475         else
9476                 return -EIO;
9477
9478         buf = kmalloc(size, GFP_KERNEL);
9479         if (buf == NULL)
9480                 return -ENOMEM;
9481
9482         err = -EIO;
9483         for (i = 0, j = 0; i < size; i += 4, j++) {
9484                 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9485                         break;
9486         }
9487         if (i < size)
9488                 goto out;
9489
9490         /* Selfboot format */
9491         magic = swab32(le32_to_cpu(buf[0]));
9492         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9493             TG3_EEPROM_MAGIC_FW) {
9494                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9495
9496                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9497                     TG3_EEPROM_SB_REVISION_2) {
9498                         /* For rev 2, the csum doesn't include the MBA. */
9499                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9500                                 csum8 += buf8[i];
9501                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9502                                 csum8 += buf8[i];
9503                 } else {
9504                         for (i = 0; i < size; i++)
9505                                 csum8 += buf8[i];
9506                 }
9507
9508                 if (csum8 == 0) {
9509                         err = 0;
9510                         goto out;
9511                 }
9512
9513                 err = -EIO;
9514                 goto out;
9515         }
9516
9517         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9518             TG3_EEPROM_MAGIC_HW) {
9519                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9520                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9521                 u8 *buf8 = (u8 *) buf;
9522
9523                 /* Separate the parity bits and the data bytes.  */
9524                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9525                         if ((i == 0) || (i == 8)) {
9526                                 int l;
9527                                 u8 msk;
9528
9529                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9530                                         parity[k++] = buf8[i] & msk;
9531                                 i++;
9532                         }
9533                         else if (i == 16) {
9534                                 int l;
9535                                 u8 msk;
9536
9537                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9538                                         parity[k++] = buf8[i] & msk;
9539                                 i++;
9540
9541                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9542                                         parity[k++] = buf8[i] & msk;
9543                                 i++;
9544                         }
9545                         data[j++] = buf8[i];
9546                 }
9547
9548                 err = -EIO;
9549                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9550                         u8 hw8 = hweight8(data[i]);
9551
9552                         if ((hw8 & 0x1) && parity[i])
9553                                 goto out;
9554                         else if (!(hw8 & 0x1) && !parity[i])
9555                                 goto out;
9556                 }
9557                 err = 0;
9558                 goto out;
9559         }
9560
9561         /* Bootstrap checksum at offset 0x10 */
9562         csum = calc_crc((unsigned char *) buf, 0x10);
9563         if(csum != le32_to_cpu(buf[0x10/4]))
9564                 goto out;
9565
9566         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9567         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9568         if (csum != le32_to_cpu(buf[0xfc/4]))
9569                  goto out;
9570
9571         err = 0;
9572
9573 out:
9574         kfree(buf);
9575         return err;
9576 }
9577
9578 #define TG3_SERDES_TIMEOUT_SEC  2
9579 #define TG3_COPPER_TIMEOUT_SEC  6
9580
9581 static int tg3_test_link(struct tg3 *tp)
9582 {
9583         int i, max;
9584
9585         if (!netif_running(tp->dev))
9586                 return -ENODEV;
9587
9588         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9589                 max = TG3_SERDES_TIMEOUT_SEC;
9590         else
9591                 max = TG3_COPPER_TIMEOUT_SEC;
9592
9593         for (i = 0; i < max; i++) {
9594                 if (netif_carrier_ok(tp->dev))
9595                         return 0;
9596
9597                 if (msleep_interruptible(1000))
9598                         break;
9599         }
9600
9601         return -EIO;
9602 }
9603
9604 /* Only test the commonly used registers */
9605 static int tg3_test_registers(struct tg3 *tp)
9606 {
9607         int i, is_5705, is_5750;
9608         u32 offset, read_mask, write_mask, val, save_val, read_val;
9609         static struct {
9610                 u16 offset;
9611                 u16 flags;
9612 #define TG3_FL_5705     0x1
9613 #define TG3_FL_NOT_5705 0x2
9614 #define TG3_FL_NOT_5788 0x4
9615 #define TG3_FL_NOT_5750 0x8
9616                 u32 read_mask;
9617                 u32 write_mask;
9618         } reg_tbl[] = {
9619                 /* MAC Control Registers */
9620                 { MAC_MODE, TG3_FL_NOT_5705,
9621                         0x00000000, 0x00ef6f8c },
9622                 { MAC_MODE, TG3_FL_5705,
9623                         0x00000000, 0x01ef6b8c },
9624                 { MAC_STATUS, TG3_FL_NOT_5705,
9625                         0x03800107, 0x00000000 },
9626                 { MAC_STATUS, TG3_FL_5705,
9627                         0x03800100, 0x00000000 },
9628                 { MAC_ADDR_0_HIGH, 0x0000,
9629                         0x00000000, 0x0000ffff },
9630                 { MAC_ADDR_0_LOW, 0x0000,
9631                         0x00000000, 0xffffffff },
9632                 { MAC_RX_MTU_SIZE, 0x0000,
9633                         0x00000000, 0x0000ffff },
9634                 { MAC_TX_MODE, 0x0000,
9635                         0x00000000, 0x00000070 },
9636                 { MAC_TX_LENGTHS, 0x0000,
9637                         0x00000000, 0x00003fff },
9638                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9639                         0x00000000, 0x000007fc },
9640                 { MAC_RX_MODE, TG3_FL_5705,
9641                         0x00000000, 0x000007dc },
9642                 { MAC_HASH_REG_0, 0x0000,
9643                         0x00000000, 0xffffffff },
9644                 { MAC_HASH_REG_1, 0x0000,
9645                         0x00000000, 0xffffffff },
9646                 { MAC_HASH_REG_2, 0x0000,
9647                         0x00000000, 0xffffffff },
9648                 { MAC_HASH_REG_3, 0x0000,
9649                         0x00000000, 0xffffffff },
9650
9651                 /* Receive Data and Receive BD Initiator Control Registers. */
9652                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9653                         0x00000000, 0xffffffff },
9654                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9655                         0x00000000, 0xffffffff },
9656                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9657                         0x00000000, 0x00000003 },
9658                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9659                         0x00000000, 0xffffffff },
9660                 { RCVDBDI_STD_BD+0, 0x0000,
9661                         0x00000000, 0xffffffff },
9662                 { RCVDBDI_STD_BD+4, 0x0000,
9663                         0x00000000, 0xffffffff },
9664                 { RCVDBDI_STD_BD+8, 0x0000,
9665                         0x00000000, 0xffff0002 },
9666                 { RCVDBDI_STD_BD+0xc, 0x0000,
9667                         0x00000000, 0xffffffff },
9668
9669                 /* Receive BD Initiator Control Registers. */
9670                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9671                         0x00000000, 0xffffffff },
9672                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9673                         0x00000000, 0x000003ff },
9674                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9675                         0x00000000, 0xffffffff },
9676
9677                 /* Host Coalescing Control Registers. */
9678                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9679                         0x00000000, 0x00000004 },
9680                 { HOSTCC_MODE, TG3_FL_5705,
9681                         0x00000000, 0x000000f6 },
9682                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9683                         0x00000000, 0xffffffff },
9684                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9685                         0x00000000, 0x000003ff },
9686                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9687                         0x00000000, 0xffffffff },
9688                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9689                         0x00000000, 0x000003ff },
9690                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9691                         0x00000000, 0xffffffff },
9692                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9693                         0x00000000, 0x000000ff },
9694                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9695                         0x00000000, 0xffffffff },
9696                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9697                         0x00000000, 0x000000ff },
9698                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9699                         0x00000000, 0xffffffff },
9700                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9701                         0x00000000, 0xffffffff },
9702                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9703                         0x00000000, 0xffffffff },
9704                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9705                         0x00000000, 0x000000ff },
9706                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9707                         0x00000000, 0xffffffff },
9708                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9709                         0x00000000, 0x000000ff },
9710                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9711                         0x00000000, 0xffffffff },
9712                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9713                         0x00000000, 0xffffffff },
9714                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9715                         0x00000000, 0xffffffff },
9716                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9717                         0x00000000, 0xffffffff },
9718                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9719                         0x00000000, 0xffffffff },
9720                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9721                         0xffffffff, 0x00000000 },
9722                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9723                         0xffffffff, 0x00000000 },
9724
9725                 /* Buffer Manager Control Registers. */
9726                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9727                         0x00000000, 0x007fff80 },
9728                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9729                         0x00000000, 0x007fffff },
9730                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9731                         0x00000000, 0x0000003f },
9732                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9733                         0x00000000, 0x000001ff },
9734                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9735                         0x00000000, 0x000001ff },
9736                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9737                         0xffffffff, 0x00000000 },
9738                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9739                         0xffffffff, 0x00000000 },
9740
9741                 /* Mailbox Registers */
9742                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9743                         0x00000000, 0x000001ff },
9744                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9745                         0x00000000, 0x000001ff },
9746                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9747                         0x00000000, 0x000007ff },
9748                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9749                         0x00000000, 0x000001ff },
9750
9751                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9752         };
9753
9754         is_5705 = is_5750 = 0;
9755         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9756                 is_5705 = 1;
9757                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9758                         is_5750 = 1;
9759         }
9760
9761         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9762                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9763                         continue;
9764
9765                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9766                         continue;
9767
9768                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9769                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9770                         continue;
9771
9772                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9773                         continue;
9774
9775                 offset = (u32) reg_tbl[i].offset;
9776                 read_mask = reg_tbl[i].read_mask;
9777                 write_mask = reg_tbl[i].write_mask;
9778
9779                 /* Save the original register content */
9780                 save_val = tr32(offset);
9781
9782                 /* Determine the read-only value. */
9783                 read_val = save_val & read_mask;
9784
9785                 /* Write zero to the register, then make sure the read-only bits
9786                  * are not changed and the read/write bits are all zeros.
9787                  */
9788                 tw32(offset, 0);
9789
9790                 val = tr32(offset);
9791
9792                 /* Test the read-only and read/write bits. */
9793                 if (((val & read_mask) != read_val) || (val & write_mask))
9794                         goto out;
9795
9796                 /* Write ones to all the bits defined by RdMask and WrMask, then
9797                  * make sure the read-only bits are not changed and the
9798                  * read/write bits are all ones.
9799                  */
9800                 tw32(offset, read_mask | write_mask);
9801
9802                 val = tr32(offset);
9803
9804                 /* Test the read-only bits. */
9805                 if ((val & read_mask) != read_val)
9806                         goto out;
9807
9808                 /* Test the read/write bits. */
9809                 if ((val & write_mask) != write_mask)
9810                         goto out;
9811
9812                 tw32(offset, save_val);
9813         }
9814
9815         return 0;
9816
9817 out:
9818         if (netif_msg_hw(tp))
9819                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9820                        offset);
9821         tw32(offset, save_val);
9822         return -EIO;
9823 }
9824
9825 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9826 {
9827         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9828         int i;
9829         u32 j;
9830
9831         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9832                 for (j = 0; j < len; j += 4) {
9833                         u32 val;
9834
9835                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9836                         tg3_read_mem(tp, offset + j, &val);
9837                         if (val != test_pattern[i])
9838                                 return -EIO;
9839                 }
9840         }
9841         return 0;
9842 }
9843
9844 static int tg3_test_memory(struct tg3 *tp)
9845 {
9846         static struct mem_entry {
9847                 u32 offset;
9848                 u32 len;
9849         } mem_tbl_570x[] = {
9850                 { 0x00000000, 0x00b50},
9851                 { 0x00002000, 0x1c000},
9852                 { 0xffffffff, 0x00000}
9853         }, mem_tbl_5705[] = {
9854                 { 0x00000100, 0x0000c},
9855                 { 0x00000200, 0x00008},
9856                 { 0x00004000, 0x00800},
9857                 { 0x00006000, 0x01000},
9858                 { 0x00008000, 0x02000},
9859                 { 0x00010000, 0x0e000},
9860                 { 0xffffffff, 0x00000}
9861         }, mem_tbl_5755[] = {
9862                 { 0x00000200, 0x00008},
9863                 { 0x00004000, 0x00800},
9864                 { 0x00006000, 0x00800},
9865                 { 0x00008000, 0x02000},
9866                 { 0x00010000, 0x0c000},
9867                 { 0xffffffff, 0x00000}
9868         }, mem_tbl_5906[] = {
9869                 { 0x00000200, 0x00008},
9870                 { 0x00004000, 0x00400},
9871                 { 0x00006000, 0x00400},
9872                 { 0x00008000, 0x01000},
9873                 { 0x00010000, 0x01000},
9874                 { 0xffffffff, 0x00000}
9875         };
9876         struct mem_entry *mem_tbl;
9877         int err = 0;
9878         int i;
9879
9880         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9881                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9882                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9883                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9884                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9885                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9886                         mem_tbl = mem_tbl_5755;
9887                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9888                         mem_tbl = mem_tbl_5906;
9889                 else
9890                         mem_tbl = mem_tbl_5705;
9891         } else
9892                 mem_tbl = mem_tbl_570x;
9893
9894         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9895                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9896                     mem_tbl[i].len)) != 0)
9897                         break;
9898         }
9899
9900         return err;
9901 }
9902
9903 #define TG3_MAC_LOOPBACK        0
9904 #define TG3_PHY_LOOPBACK        1
9905
9906 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9907 {
9908         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9909         u32 desc_idx;
9910         struct sk_buff *skb, *rx_skb;
9911         u8 *tx_data;
9912         dma_addr_t map;
9913         int num_pkts, tx_len, rx_len, i, err;
9914         struct tg3_rx_buffer_desc *desc;
9915
9916         if (loopback_mode == TG3_MAC_LOOPBACK) {
9917                 /* HW errata - mac loopback fails in some cases on 5780.
9918                  * Normal traffic and PHY loopback are not affected by
9919                  * errata.
9920                  */
9921                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9922                         return 0;
9923
9924                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9925                            MAC_MODE_PORT_INT_LPBACK;
9926                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9927                         mac_mode |= MAC_MODE_LINK_POLARITY;
9928                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9929                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9930                 else
9931                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9932                 tw32(MAC_MODE, mac_mode);
9933         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9934                 u32 val;
9935
9936                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9937                         u32 phytest;
9938
9939                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9940                                 u32 phy;
9941
9942                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9943                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9944                                 if (!tg3_readphy(tp, 0x1b, &phy))
9945                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9946                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9947                         }
9948                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9949                 } else
9950                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9951
9952                 tg3_phy_toggle_automdix(tp, 0);
9953
9954                 tg3_writephy(tp, MII_BMCR, val);
9955                 udelay(40);
9956
9957                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9958                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9959                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9960                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9961                 } else
9962                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9963
9964                 /* reset to prevent losing 1st rx packet intermittently */
9965                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9966                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9967                         udelay(10);
9968                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9969                 }
9970                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9971                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9972                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9973                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9974                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9975                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9976                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9977                 }
9978                 tw32(MAC_MODE, mac_mode);
9979         }
9980         else
9981                 return -EINVAL;
9982
9983         err = -EIO;
9984
9985         tx_len = 1514;
9986         skb = netdev_alloc_skb(tp->dev, tx_len);
9987         if (!skb)
9988                 return -ENOMEM;
9989
9990         tx_data = skb_put(skb, tx_len);
9991         memcpy(tx_data, tp->dev->dev_addr, 6);
9992         memset(tx_data + 6, 0x0, 8);
9993
9994         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9995
9996         for (i = 14; i < tx_len; i++)
9997                 tx_data[i] = (u8) (i & 0xff);
9998
9999         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10000
10001         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10002              HOSTCC_MODE_NOW);
10003
10004         udelay(10);
10005
10006         rx_start_idx = tp->hw_status->idx[0].rx_producer;
10007
10008         num_pkts = 0;
10009
10010         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
10011
10012         tp->tx_prod++;
10013         num_pkts++;
10014
10015         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
10016                      tp->tx_prod);
10017         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
10018
10019         udelay(10);
10020
10021         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10022         for (i = 0; i < 25; i++) {
10023                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10024                        HOSTCC_MODE_NOW);
10025
10026                 udelay(10);
10027
10028                 tx_idx = tp->hw_status->idx[0].tx_consumer;
10029                 rx_idx = tp->hw_status->idx[0].rx_producer;
10030                 if ((tx_idx == tp->tx_prod) &&
10031                     (rx_idx == (rx_start_idx + num_pkts)))
10032                         break;
10033         }
10034
10035         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10036         dev_kfree_skb(skb);
10037
10038         if (tx_idx != tp->tx_prod)
10039                 goto out;
10040
10041         if (rx_idx != rx_start_idx + num_pkts)
10042                 goto out;
10043
10044         desc = &tp->rx_rcb[rx_start_idx];
10045         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10046         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10047         if (opaque_key != RXD_OPAQUE_RING_STD)
10048                 goto out;
10049
10050         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10051             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10052                 goto out;
10053
10054         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10055         if (rx_len != tx_len)
10056                 goto out;
10057
10058         rx_skb = tp->rx_std_buffers[desc_idx].skb;
10059
10060         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
10061         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10062
10063         for (i = 14; i < tx_len; i++) {
10064                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10065                         goto out;
10066         }
10067         err = 0;
10068
10069         /* tg3_free_rings will unmap and free the rx_skb */
10070 out:
10071         return err;
10072 }
10073
10074 #define TG3_MAC_LOOPBACK_FAILED         1
10075 #define TG3_PHY_LOOPBACK_FAILED         2
10076 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10077                                          TG3_PHY_LOOPBACK_FAILED)
10078
10079 static int tg3_test_loopback(struct tg3 *tp)
10080 {
10081         int err = 0;
10082         u32 cpmuctrl = 0;
10083
10084         if (!netif_running(tp->dev))
10085                 return TG3_LOOPBACK_FAILED;
10086
10087         err = tg3_reset_hw(tp, 1);
10088         if (err)
10089                 return TG3_LOOPBACK_FAILED;
10090
10091         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10092             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10094                 int i;
10095                 u32 status;
10096
10097                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10098
10099                 /* Wait for up to 40 microseconds to acquire lock. */
10100                 for (i = 0; i < 4; i++) {
10101                         status = tr32(TG3_CPMU_MUTEX_GNT);
10102                         if (status == CPMU_MUTEX_GNT_DRIVER)
10103                                 break;
10104                         udelay(10);
10105                 }
10106
10107                 if (status != CPMU_MUTEX_GNT_DRIVER)
10108                         return TG3_LOOPBACK_FAILED;
10109
10110                 /* Turn off link-based power management. */
10111                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10112                 tw32(TG3_CPMU_CTRL,
10113                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10114                                   CPMU_CTRL_LINK_AWARE_MODE));
10115         }
10116
10117         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10118                 err |= TG3_MAC_LOOPBACK_FAILED;
10119
10120         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10121             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10122             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10123                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10124
10125                 /* Release the mutex */
10126                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10127         }
10128
10129         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10130             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10131                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10132                         err |= TG3_PHY_LOOPBACK_FAILED;
10133         }
10134
10135         return err;
10136 }
10137
10138 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10139                           u64 *data)
10140 {
10141         struct tg3 *tp = netdev_priv(dev);
10142
10143         if (tp->link_config.phy_is_low_power)
10144                 tg3_set_power_state(tp, PCI_D0);
10145
10146         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10147
10148         if (tg3_test_nvram(tp) != 0) {
10149                 etest->flags |= ETH_TEST_FL_FAILED;
10150                 data[0] = 1;
10151         }
10152         if (tg3_test_link(tp) != 0) {
10153                 etest->flags |= ETH_TEST_FL_FAILED;
10154                 data[1] = 1;
10155         }
10156         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10157                 int err, err2 = 0, irq_sync = 0;
10158
10159                 if (netif_running(dev)) {
10160                         tg3_phy_stop(tp);
10161                         tg3_netif_stop(tp);
10162                         irq_sync = 1;
10163                 }
10164
10165                 tg3_full_lock(tp, irq_sync);
10166
10167                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10168                 err = tg3_nvram_lock(tp);
10169                 tg3_halt_cpu(tp, RX_CPU_BASE);
10170                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10171                         tg3_halt_cpu(tp, TX_CPU_BASE);
10172                 if (!err)
10173                         tg3_nvram_unlock(tp);
10174
10175                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10176                         tg3_phy_reset(tp);
10177
10178                 if (tg3_test_registers(tp) != 0) {
10179                         etest->flags |= ETH_TEST_FL_FAILED;
10180                         data[2] = 1;
10181                 }
10182                 if (tg3_test_memory(tp) != 0) {
10183                         etest->flags |= ETH_TEST_FL_FAILED;
10184                         data[3] = 1;
10185                 }
10186                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10187                         etest->flags |= ETH_TEST_FL_FAILED;
10188
10189                 tg3_full_unlock(tp);
10190
10191                 if (tg3_test_interrupt(tp) != 0) {
10192                         etest->flags |= ETH_TEST_FL_FAILED;
10193                         data[5] = 1;
10194                 }
10195
10196                 tg3_full_lock(tp, 0);
10197
10198                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10199                 if (netif_running(dev)) {
10200                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10201                         err2 = tg3_restart_hw(tp, 1);
10202                         if (!err2)
10203                                 tg3_netif_start(tp);
10204                 }
10205
10206                 tg3_full_unlock(tp);
10207
10208                 if (irq_sync && !err2)
10209                         tg3_phy_start(tp);
10210         }
10211         if (tp->link_config.phy_is_low_power)
10212                 tg3_set_power_state(tp, PCI_D3hot);
10213
10214 }
10215
10216 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10217 {
10218         struct mii_ioctl_data *data = if_mii(ifr);
10219         struct tg3 *tp = netdev_priv(dev);
10220         int err;
10221
10222         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10223                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10224                         return -EAGAIN;
10225                 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10226         }
10227
10228         switch(cmd) {
10229         case SIOCGMIIPHY:
10230                 data->phy_id = PHY_ADDR;
10231
10232                 /* fallthru */
10233         case SIOCGMIIREG: {
10234                 u32 mii_regval;
10235
10236                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10237                         break;                  /* We have no PHY */
10238
10239                 if (tp->link_config.phy_is_low_power)
10240                         return -EAGAIN;
10241
10242                 spin_lock_bh(&tp->lock);
10243                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10244                 spin_unlock_bh(&tp->lock);
10245
10246                 data->val_out = mii_regval;
10247
10248                 return err;
10249         }
10250
10251         case SIOCSMIIREG:
10252                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10253                         break;                  /* We have no PHY */
10254
10255                 if (!capable(CAP_NET_ADMIN))
10256                         return -EPERM;
10257
10258                 if (tp->link_config.phy_is_low_power)
10259                         return -EAGAIN;
10260
10261                 spin_lock_bh(&tp->lock);
10262                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10263                 spin_unlock_bh(&tp->lock);
10264
10265                 return err;
10266
10267         default:
10268                 /* do nothing */
10269                 break;
10270         }
10271         return -EOPNOTSUPP;
10272 }
10273
10274 #if TG3_VLAN_TAG_USED
10275 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10276 {
10277         struct tg3 *tp = netdev_priv(dev);
10278
10279         if (netif_running(dev))
10280                 tg3_netif_stop(tp);
10281
10282         tg3_full_lock(tp, 0);
10283
10284         tp->vlgrp = grp;
10285
10286         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10287         __tg3_set_rx_mode(dev);
10288
10289         if (netif_running(dev))
10290                 tg3_netif_start(tp);
10291
10292         tg3_full_unlock(tp);
10293 }
10294 #endif
10295
10296 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10297 {
10298         struct tg3 *tp = netdev_priv(dev);
10299
10300         memcpy(ec, &tp->coal, sizeof(*ec));
10301         return 0;
10302 }
10303
10304 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10305 {
10306         struct tg3 *tp = netdev_priv(dev);
10307         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10308         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10309
10310         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10311                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10312                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10313                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10314                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10315         }
10316
10317         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10318             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10319             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10320             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10321             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10322             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10323             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10324             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10325             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10326             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10327                 return -EINVAL;
10328
10329         /* No rx interrupts will be generated if both are zero */
10330         if ((ec->rx_coalesce_usecs == 0) &&
10331             (ec->rx_max_coalesced_frames == 0))
10332                 return -EINVAL;
10333
10334         /* No tx interrupts will be generated if both are zero */
10335         if ((ec->tx_coalesce_usecs == 0) &&
10336             (ec->tx_max_coalesced_frames == 0))
10337                 return -EINVAL;
10338
10339         /* Only copy relevant parameters, ignore all others. */
10340         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10341         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10342         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10343         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10344         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10345         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10346         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10347         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10348         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10349
10350         if (netif_running(dev)) {
10351                 tg3_full_lock(tp, 0);
10352                 __tg3_set_coalesce(tp, &tp->coal);
10353                 tg3_full_unlock(tp);
10354         }
10355         return 0;
10356 }
10357
10358 static const struct ethtool_ops tg3_ethtool_ops = {
10359         .get_settings           = tg3_get_settings,
10360         .set_settings           = tg3_set_settings,
10361         .get_drvinfo            = tg3_get_drvinfo,
10362         .get_regs_len           = tg3_get_regs_len,
10363         .get_regs               = tg3_get_regs,
10364         .get_wol                = tg3_get_wol,
10365         .set_wol                = tg3_set_wol,
10366         .get_msglevel           = tg3_get_msglevel,
10367         .set_msglevel           = tg3_set_msglevel,
10368         .nway_reset             = tg3_nway_reset,
10369         .get_link               = ethtool_op_get_link,
10370         .get_eeprom_len         = tg3_get_eeprom_len,
10371         .get_eeprom             = tg3_get_eeprom,
10372         .set_eeprom             = tg3_set_eeprom,
10373         .get_ringparam          = tg3_get_ringparam,
10374         .set_ringparam          = tg3_set_ringparam,
10375         .get_pauseparam         = tg3_get_pauseparam,
10376         .set_pauseparam         = tg3_set_pauseparam,
10377         .get_rx_csum            = tg3_get_rx_csum,
10378         .set_rx_csum            = tg3_set_rx_csum,
10379         .set_tx_csum            = tg3_set_tx_csum,
10380         .set_sg                 = ethtool_op_set_sg,
10381         .set_tso                = tg3_set_tso,
10382         .self_test              = tg3_self_test,
10383         .get_strings            = tg3_get_strings,
10384         .phys_id                = tg3_phys_id,
10385         .get_ethtool_stats      = tg3_get_ethtool_stats,
10386         .get_coalesce           = tg3_get_coalesce,
10387         .set_coalesce           = tg3_set_coalesce,
10388         .get_sset_count         = tg3_get_sset_count,
10389 };
10390
10391 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10392 {
10393         u32 cursize, val, magic;
10394
10395         tp->nvram_size = EEPROM_CHIP_SIZE;
10396
10397         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10398                 return;
10399
10400         if ((magic != TG3_EEPROM_MAGIC) &&
10401             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10402             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10403                 return;
10404
10405         /*
10406          * Size the chip by reading offsets at increasing powers of two.
10407          * When we encounter our validation signature, we know the addressing
10408          * has wrapped around, and thus have our chip size.
10409          */
10410         cursize = 0x10;
10411
10412         while (cursize < tp->nvram_size) {
10413                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10414                         return;
10415
10416                 if (val == magic)
10417                         break;
10418
10419                 cursize <<= 1;
10420         }
10421
10422         tp->nvram_size = cursize;
10423 }
10424
10425 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10426 {
10427         u32 val;
10428
10429         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10430                 return;
10431
10432         /* Selfboot format */
10433         if (val != TG3_EEPROM_MAGIC) {
10434                 tg3_get_eeprom_size(tp);
10435                 return;
10436         }
10437
10438         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10439                 if (val != 0) {
10440                         tp->nvram_size = (val >> 16) * 1024;
10441                         return;
10442                 }
10443         }
10444         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10445 }
10446
10447 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10448 {
10449         u32 nvcfg1;
10450
10451         nvcfg1 = tr32(NVRAM_CFG1);
10452         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10453                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10454         }
10455         else {
10456                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10457                 tw32(NVRAM_CFG1, nvcfg1);
10458         }
10459
10460         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10461             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10462                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10463                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10464                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10465                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10466                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10467                                 break;
10468                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10469                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10470                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10471                                 break;
10472                         case FLASH_VENDOR_ATMEL_EEPROM:
10473                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10474                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10475                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10476                                 break;
10477                         case FLASH_VENDOR_ST:
10478                                 tp->nvram_jedecnum = JEDEC_ST;
10479                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10480                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10481                                 break;
10482                         case FLASH_VENDOR_SAIFUN:
10483                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10484                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10485                                 break;
10486                         case FLASH_VENDOR_SST_SMALL:
10487                         case FLASH_VENDOR_SST_LARGE:
10488                                 tp->nvram_jedecnum = JEDEC_SST;
10489                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10490                                 break;
10491                 }
10492         }
10493         else {
10494                 tp->nvram_jedecnum = JEDEC_ATMEL;
10495                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10496                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10497         }
10498 }
10499
10500 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10501 {
10502         u32 nvcfg1;
10503
10504         nvcfg1 = tr32(NVRAM_CFG1);
10505
10506         /* NVRAM protection for TPM */
10507         if (nvcfg1 & (1 << 27))
10508                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10509
10510         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10511                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10512                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10513                         tp->nvram_jedecnum = JEDEC_ATMEL;
10514                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10515                         break;
10516                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10517                         tp->nvram_jedecnum = JEDEC_ATMEL;
10518                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10519                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10520                         break;
10521                 case FLASH_5752VENDOR_ST_M45PE10:
10522                 case FLASH_5752VENDOR_ST_M45PE20:
10523                 case FLASH_5752VENDOR_ST_M45PE40:
10524                         tp->nvram_jedecnum = JEDEC_ST;
10525                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10526                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10527                         break;
10528         }
10529
10530         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10531                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10532                         case FLASH_5752PAGE_SIZE_256:
10533                                 tp->nvram_pagesize = 256;
10534                                 break;
10535                         case FLASH_5752PAGE_SIZE_512:
10536                                 tp->nvram_pagesize = 512;
10537                                 break;
10538                         case FLASH_5752PAGE_SIZE_1K:
10539                                 tp->nvram_pagesize = 1024;
10540                                 break;
10541                         case FLASH_5752PAGE_SIZE_2K:
10542                                 tp->nvram_pagesize = 2048;
10543                                 break;
10544                         case FLASH_5752PAGE_SIZE_4K:
10545                                 tp->nvram_pagesize = 4096;
10546                                 break;
10547                         case FLASH_5752PAGE_SIZE_264:
10548                                 tp->nvram_pagesize = 264;
10549                                 break;
10550                 }
10551         }
10552         else {
10553                 /* For eeprom, set pagesize to maximum eeprom size */
10554                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10555
10556                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10557                 tw32(NVRAM_CFG1, nvcfg1);
10558         }
10559 }
10560
10561 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10562 {
10563         u32 nvcfg1, protect = 0;
10564
10565         nvcfg1 = tr32(NVRAM_CFG1);
10566
10567         /* NVRAM protection for TPM */
10568         if (nvcfg1 & (1 << 27)) {
10569                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10570                 protect = 1;
10571         }
10572
10573         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10574         switch (nvcfg1) {
10575                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10576                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10577                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10578                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10579                         tp->nvram_jedecnum = JEDEC_ATMEL;
10580                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10581                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10582                         tp->nvram_pagesize = 264;
10583                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10584                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10585                                 tp->nvram_size = (protect ? 0x3e200 :
10586                                                   TG3_NVRAM_SIZE_512KB);
10587                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10588                                 tp->nvram_size = (protect ? 0x1f200 :
10589                                                   TG3_NVRAM_SIZE_256KB);
10590                         else
10591                                 tp->nvram_size = (protect ? 0x1f200 :
10592                                                   TG3_NVRAM_SIZE_128KB);
10593                         break;
10594                 case FLASH_5752VENDOR_ST_M45PE10:
10595                 case FLASH_5752VENDOR_ST_M45PE20:
10596                 case FLASH_5752VENDOR_ST_M45PE40:
10597                         tp->nvram_jedecnum = JEDEC_ST;
10598                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10599                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10600                         tp->nvram_pagesize = 256;
10601                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10602                                 tp->nvram_size = (protect ?
10603                                                   TG3_NVRAM_SIZE_64KB :
10604                                                   TG3_NVRAM_SIZE_128KB);
10605                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10606                                 tp->nvram_size = (protect ?
10607                                                   TG3_NVRAM_SIZE_64KB :
10608                                                   TG3_NVRAM_SIZE_256KB);
10609                         else
10610                                 tp->nvram_size = (protect ?
10611                                                   TG3_NVRAM_SIZE_128KB :
10612                                                   TG3_NVRAM_SIZE_512KB);
10613                         break;
10614         }
10615 }
10616
10617 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10618 {
10619         u32 nvcfg1;
10620
10621         nvcfg1 = tr32(NVRAM_CFG1);
10622
10623         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10624                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10625                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10626                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10627                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10628                         tp->nvram_jedecnum = JEDEC_ATMEL;
10629                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10630                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10631
10632                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10633                         tw32(NVRAM_CFG1, nvcfg1);
10634                         break;
10635                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10636                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10637                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10638                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10639                         tp->nvram_jedecnum = JEDEC_ATMEL;
10640                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10641                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10642                         tp->nvram_pagesize = 264;
10643                         break;
10644                 case FLASH_5752VENDOR_ST_M45PE10:
10645                 case FLASH_5752VENDOR_ST_M45PE20:
10646                 case FLASH_5752VENDOR_ST_M45PE40:
10647                         tp->nvram_jedecnum = JEDEC_ST;
10648                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10649                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10650                         tp->nvram_pagesize = 256;
10651                         break;
10652         }
10653 }
10654
10655 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10656 {
10657         u32 nvcfg1, protect = 0;
10658
10659         nvcfg1 = tr32(NVRAM_CFG1);
10660
10661         /* NVRAM protection for TPM */
10662         if (nvcfg1 & (1 << 27)) {
10663                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10664                 protect = 1;
10665         }
10666
10667         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10668         switch (nvcfg1) {
10669                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10670                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10671                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10672                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10673                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10674                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10675                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10676                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10677                         tp->nvram_jedecnum = JEDEC_ATMEL;
10678                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10679                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10680                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10681                         tp->nvram_pagesize = 256;
10682                         break;
10683                 case FLASH_5761VENDOR_ST_A_M45PE20:
10684                 case FLASH_5761VENDOR_ST_A_M45PE40:
10685                 case FLASH_5761VENDOR_ST_A_M45PE80:
10686                 case FLASH_5761VENDOR_ST_A_M45PE16:
10687                 case FLASH_5761VENDOR_ST_M_M45PE20:
10688                 case FLASH_5761VENDOR_ST_M_M45PE40:
10689                 case FLASH_5761VENDOR_ST_M_M45PE80:
10690                 case FLASH_5761VENDOR_ST_M_M45PE16:
10691                         tp->nvram_jedecnum = JEDEC_ST;
10692                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10693                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10694                         tp->nvram_pagesize = 256;
10695                         break;
10696         }
10697
10698         if (protect) {
10699                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10700         } else {
10701                 switch (nvcfg1) {
10702                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10703                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10704                         case FLASH_5761VENDOR_ST_A_M45PE16:
10705                         case FLASH_5761VENDOR_ST_M_M45PE16:
10706                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10707                                 break;
10708                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10709                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10710                         case FLASH_5761VENDOR_ST_A_M45PE80:
10711                         case FLASH_5761VENDOR_ST_M_M45PE80:
10712                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10713                                 break;
10714                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10715                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10716                         case FLASH_5761VENDOR_ST_A_M45PE40:
10717                         case FLASH_5761VENDOR_ST_M_M45PE40:
10718                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10719                                 break;
10720                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10721                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10722                         case FLASH_5761VENDOR_ST_A_M45PE20:
10723                         case FLASH_5761VENDOR_ST_M_M45PE20:
10724                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10725                                 break;
10726                 }
10727         }
10728 }
10729
10730 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10731 {
10732         tp->nvram_jedecnum = JEDEC_ATMEL;
10733         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10734         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10735 }
10736
10737 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10738 static void __devinit tg3_nvram_init(struct tg3 *tp)
10739 {
10740         tw32_f(GRC_EEPROM_ADDR,
10741              (EEPROM_ADDR_FSM_RESET |
10742               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10743                EEPROM_ADDR_CLKPERD_SHIFT)));
10744
10745         msleep(1);
10746
10747         /* Enable seeprom accesses. */
10748         tw32_f(GRC_LOCAL_CTRL,
10749              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10750         udelay(100);
10751
10752         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10753             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10754                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10755
10756                 if (tg3_nvram_lock(tp)) {
10757                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10758                                "tg3_nvram_init failed.\n", tp->dev->name);
10759                         return;
10760                 }
10761                 tg3_enable_nvram_access(tp);
10762
10763                 tp->nvram_size = 0;
10764
10765                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10766                         tg3_get_5752_nvram_info(tp);
10767                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10768                         tg3_get_5755_nvram_info(tp);
10769                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10770                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10771                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10772                         tg3_get_5787_nvram_info(tp);
10773                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10774                         tg3_get_5761_nvram_info(tp);
10775                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10776                         tg3_get_5906_nvram_info(tp);
10777                 else
10778                         tg3_get_nvram_info(tp);
10779
10780                 if (tp->nvram_size == 0)
10781                         tg3_get_nvram_size(tp);
10782
10783                 tg3_disable_nvram_access(tp);
10784                 tg3_nvram_unlock(tp);
10785
10786         } else {
10787                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10788
10789                 tg3_get_eeprom_size(tp);
10790         }
10791 }
10792
10793 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10794                                         u32 offset, u32 *val)
10795 {
10796         u32 tmp;
10797         int i;
10798
10799         if (offset > EEPROM_ADDR_ADDR_MASK ||
10800             (offset % 4) != 0)
10801                 return -EINVAL;
10802
10803         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10804                                         EEPROM_ADDR_DEVID_MASK |
10805                                         EEPROM_ADDR_READ);
10806         tw32(GRC_EEPROM_ADDR,
10807              tmp |
10808              (0 << EEPROM_ADDR_DEVID_SHIFT) |
10809              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10810               EEPROM_ADDR_ADDR_MASK) |
10811              EEPROM_ADDR_READ | EEPROM_ADDR_START);
10812
10813         for (i = 0; i < 1000; i++) {
10814                 tmp = tr32(GRC_EEPROM_ADDR);
10815
10816                 if (tmp & EEPROM_ADDR_COMPLETE)
10817                         break;
10818                 msleep(1);
10819         }
10820         if (!(tmp & EEPROM_ADDR_COMPLETE))
10821                 return -EBUSY;
10822
10823         *val = tr32(GRC_EEPROM_DATA);
10824         return 0;
10825 }
10826
10827 #define NVRAM_CMD_TIMEOUT 10000
10828
10829 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10830 {
10831         int i;
10832
10833         tw32(NVRAM_CMD, nvram_cmd);
10834         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10835                 udelay(10);
10836                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10837                         udelay(10);
10838                         break;
10839                 }
10840         }
10841         if (i == NVRAM_CMD_TIMEOUT) {
10842                 return -EBUSY;
10843         }
10844         return 0;
10845 }
10846
10847 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10848 {
10849         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10850             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10851             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10852            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10853             (tp->nvram_jedecnum == JEDEC_ATMEL))
10854
10855                 addr = ((addr / tp->nvram_pagesize) <<
10856                         ATMEL_AT45DB0X1B_PAGE_POS) +
10857                        (addr % tp->nvram_pagesize);
10858
10859         return addr;
10860 }
10861
10862 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10863 {
10864         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10865             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10866             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10867            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10868             (tp->nvram_jedecnum == JEDEC_ATMEL))
10869
10870                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10871                         tp->nvram_pagesize) +
10872                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10873
10874         return addr;
10875 }
10876
10877 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10878 {
10879         int ret;
10880
10881         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10882                 return tg3_nvram_read_using_eeprom(tp, offset, val);
10883
10884         offset = tg3_nvram_phys_addr(tp, offset);
10885
10886         if (offset > NVRAM_ADDR_MSK)
10887                 return -EINVAL;
10888
10889         ret = tg3_nvram_lock(tp);
10890         if (ret)
10891                 return ret;
10892
10893         tg3_enable_nvram_access(tp);
10894
10895         tw32(NVRAM_ADDR, offset);
10896         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10897                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10898
10899         if (ret == 0)
10900                 *val = swab32(tr32(NVRAM_RDDATA));
10901
10902         tg3_disable_nvram_access(tp);
10903
10904         tg3_nvram_unlock(tp);
10905
10906         return ret;
10907 }
10908
10909 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10910 {
10911         u32 v;
10912         int res = tg3_nvram_read(tp, offset, &v);
10913         if (!res)
10914                 *val = cpu_to_le32(v);
10915         return res;
10916 }
10917
10918 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10919 {
10920         int err;
10921         u32 tmp;
10922
10923         err = tg3_nvram_read(tp, offset, &tmp);
10924         *val = swab32(tmp);
10925         return err;
10926 }
10927
10928 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10929                                     u32 offset, u32 len, u8 *buf)
10930 {
10931         int i, j, rc = 0;
10932         u32 val;
10933
10934         for (i = 0; i < len; i += 4) {
10935                 u32 addr;
10936                 __le32 data;
10937
10938                 addr = offset + i;
10939
10940                 memcpy(&data, buf + i, 4);
10941
10942                 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10943
10944                 val = tr32(GRC_EEPROM_ADDR);
10945                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10946
10947                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10948                         EEPROM_ADDR_READ);
10949                 tw32(GRC_EEPROM_ADDR, val |
10950                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10951                         (addr & EEPROM_ADDR_ADDR_MASK) |
10952                         EEPROM_ADDR_START |
10953                         EEPROM_ADDR_WRITE);
10954
10955                 for (j = 0; j < 1000; j++) {
10956                         val = tr32(GRC_EEPROM_ADDR);
10957
10958                         if (val & EEPROM_ADDR_COMPLETE)
10959                                 break;
10960                         msleep(1);
10961                 }
10962                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10963                         rc = -EBUSY;
10964                         break;
10965                 }
10966         }
10967
10968         return rc;
10969 }
10970
10971 /* offset and length are dword aligned */
10972 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10973                 u8 *buf)
10974 {
10975         int ret = 0;
10976         u32 pagesize = tp->nvram_pagesize;
10977         u32 pagemask = pagesize - 1;
10978         u32 nvram_cmd;
10979         u8 *tmp;
10980
10981         tmp = kmalloc(pagesize, GFP_KERNEL);
10982         if (tmp == NULL)
10983                 return -ENOMEM;
10984
10985         while (len) {
10986                 int j;
10987                 u32 phy_addr, page_off, size;
10988
10989                 phy_addr = offset & ~pagemask;
10990
10991                 for (j = 0; j < pagesize; j += 4) {
10992                         if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10993                                                 (__le32 *) (tmp + j))))
10994                                 break;
10995                 }
10996                 if (ret)
10997                         break;
10998
10999                 page_off = offset & pagemask;
11000                 size = pagesize;
11001                 if (len < size)
11002                         size = len;
11003
11004                 len -= size;
11005
11006                 memcpy(tmp + page_off, buf, size);
11007
11008                 offset = offset + (pagesize - page_off);
11009
11010                 tg3_enable_nvram_access(tp);
11011
11012                 /*
11013                  * Before we can erase the flash page, we need
11014                  * to issue a special "write enable" command.
11015                  */
11016                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11017
11018                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11019                         break;
11020
11021                 /* Erase the target page */
11022                 tw32(NVRAM_ADDR, phy_addr);
11023
11024                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11025                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11026
11027                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11028                         break;
11029
11030                 /* Issue another write enable to start the write. */
11031                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11032
11033                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11034                         break;
11035
11036                 for (j = 0; j < pagesize; j += 4) {
11037                         __be32 data;
11038
11039                         data = *((__be32 *) (tmp + j));
11040                         /* swab32(le32_to_cpu(data)), actually */
11041                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11042
11043                         tw32(NVRAM_ADDR, phy_addr + j);
11044
11045                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11046                                 NVRAM_CMD_WR;
11047
11048                         if (j == 0)
11049                                 nvram_cmd |= NVRAM_CMD_FIRST;
11050                         else if (j == (pagesize - 4))
11051                                 nvram_cmd |= NVRAM_CMD_LAST;
11052
11053                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11054                                 break;
11055                 }
11056                 if (ret)
11057                         break;
11058         }
11059
11060         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11061         tg3_nvram_exec_cmd(tp, nvram_cmd);
11062
11063         kfree(tmp);
11064
11065         return ret;
11066 }
11067
11068 /* offset and length are dword aligned */
11069 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11070                 u8 *buf)
11071 {
11072         int i, ret = 0;
11073
11074         for (i = 0; i < len; i += 4, offset += 4) {
11075                 u32 page_off, phy_addr, nvram_cmd;
11076                 __be32 data;
11077
11078                 memcpy(&data, buf + i, 4);
11079                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11080
11081                 page_off = offset % tp->nvram_pagesize;
11082
11083                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11084
11085                 tw32(NVRAM_ADDR, phy_addr);
11086
11087                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11088
11089                 if ((page_off == 0) || (i == 0))
11090                         nvram_cmd |= NVRAM_CMD_FIRST;
11091                 if (page_off == (tp->nvram_pagesize - 4))
11092                         nvram_cmd |= NVRAM_CMD_LAST;
11093
11094                 if (i == (len - 4))
11095                         nvram_cmd |= NVRAM_CMD_LAST;
11096
11097                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
11098                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
11099                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11100                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11101                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11102                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
11103                     (tp->nvram_jedecnum == JEDEC_ST) &&
11104                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11105
11106                         if ((ret = tg3_nvram_exec_cmd(tp,
11107                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11108                                 NVRAM_CMD_DONE)))
11109
11110                                 break;
11111                 }
11112                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11113                         /* We always do complete word writes to eeprom. */
11114                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11115                 }
11116
11117                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11118                         break;
11119         }
11120         return ret;
11121 }
11122
11123 /* offset and length are dword aligned */
11124 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11125 {
11126         int ret;
11127
11128         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11129                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11130                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11131                 udelay(40);
11132         }
11133
11134         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11135                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11136         }
11137         else {
11138                 u32 grc_mode;
11139
11140                 ret = tg3_nvram_lock(tp);
11141                 if (ret)
11142                         return ret;
11143
11144                 tg3_enable_nvram_access(tp);
11145                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11146                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11147                         tw32(NVRAM_WRITE1, 0x406);
11148
11149                 grc_mode = tr32(GRC_MODE);
11150                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11151
11152                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11153                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11154
11155                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11156                                 buf);
11157                 }
11158                 else {
11159                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11160                                 buf);
11161                 }
11162
11163                 grc_mode = tr32(GRC_MODE);
11164                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11165
11166                 tg3_disable_nvram_access(tp);
11167                 tg3_nvram_unlock(tp);
11168         }
11169
11170         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11171                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11172                 udelay(40);
11173         }
11174
11175         return ret;
11176 }
11177
11178 struct subsys_tbl_ent {
11179         u16 subsys_vendor, subsys_devid;
11180         u32 phy_id;
11181 };
11182
11183 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11184         /* Broadcom boards. */
11185         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11186         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11187         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11188         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11189         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11190         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11191         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11192         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11193         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11194         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11195         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11196
11197         /* 3com boards. */
11198         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11199         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11200         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11201         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11202         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11203
11204         /* DELL boards. */
11205         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11206         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11207         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11208         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11209
11210         /* Compaq boards. */
11211         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11212         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11213         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11214         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11215         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11216
11217         /* IBM boards. */
11218         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11219 };
11220
11221 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11222 {
11223         int i;
11224
11225         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11226                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11227                      tp->pdev->subsystem_vendor) &&
11228                     (subsys_id_to_phy_id[i].subsys_devid ==
11229                      tp->pdev->subsystem_device))
11230                         return &subsys_id_to_phy_id[i];
11231         }
11232         return NULL;
11233 }
11234
11235 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11236 {
11237         u32 val;
11238         u16 pmcsr;
11239
11240         /* On some early chips the SRAM cannot be accessed in D3hot state,
11241          * so need make sure we're in D0.
11242          */
11243         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11244         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11245         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11246         msleep(1);
11247
11248         /* Make sure register accesses (indirect or otherwise)
11249          * will function correctly.
11250          */
11251         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11252                                tp->misc_host_ctrl);
11253
11254         /* The memory arbiter has to be enabled in order for SRAM accesses
11255          * to succeed.  Normally on powerup the tg3 chip firmware will make
11256          * sure it is enabled, but other entities such as system netboot
11257          * code might disable it.
11258          */
11259         val = tr32(MEMARB_MODE);
11260         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11261
11262         tp->phy_id = PHY_ID_INVALID;
11263         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11264
11265         /* Assume an onboard device and WOL capable by default.  */
11266         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11267
11268         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11269                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11270                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11271                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11272                 }
11273                 val = tr32(VCPU_CFGSHDW);
11274                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11275                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11276                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11277                     (val & VCPU_CFGSHDW_WOL_MAGPKT) &&
11278                     device_may_wakeup(&tp->pdev->dev))
11279                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11280                 return;
11281         }
11282
11283         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11284         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11285                 u32 nic_cfg, led_cfg;
11286                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11287                 int eeprom_phy_serdes = 0;
11288
11289                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11290                 tp->nic_sram_data_cfg = nic_cfg;
11291
11292                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11293                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11294                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11295                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11296                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11297                     (ver > 0) && (ver < 0x100))
11298                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11299
11300                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11301                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11302
11303                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11304                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11305                         eeprom_phy_serdes = 1;
11306
11307                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11308                 if (nic_phy_id != 0) {
11309                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11310                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11311
11312                         eeprom_phy_id  = (id1 >> 16) << 10;
11313                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11314                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11315                 } else
11316                         eeprom_phy_id = 0;
11317
11318                 tp->phy_id = eeprom_phy_id;
11319                 if (eeprom_phy_serdes) {
11320                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11321                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11322                         else
11323                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11324                 }
11325
11326                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11327                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11328                                     SHASTA_EXT_LED_MODE_MASK);
11329                 else
11330                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11331
11332                 switch (led_cfg) {
11333                 default:
11334                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11335                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11336                         break;
11337
11338                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11339                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11340                         break;
11341
11342                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11343                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11344
11345                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11346                          * read on some older 5700/5701 bootcode.
11347                          */
11348                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11349                             ASIC_REV_5700 ||
11350                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11351                             ASIC_REV_5701)
11352                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11353
11354                         break;
11355
11356                 case SHASTA_EXT_LED_SHARED:
11357                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11358                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11359                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11360                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11361                                                  LED_CTRL_MODE_PHY_2);
11362                         break;
11363
11364                 case SHASTA_EXT_LED_MAC:
11365                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11366                         break;
11367
11368                 case SHASTA_EXT_LED_COMBO:
11369                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11370                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11371                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11372                                                  LED_CTRL_MODE_PHY_2);
11373                         break;
11374
11375                 }
11376
11377                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11378                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11379                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11380                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11381
11382                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11383                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11384
11385                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11386                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11387                         if ((tp->pdev->subsystem_vendor ==
11388                              PCI_VENDOR_ID_ARIMA) &&
11389                             (tp->pdev->subsystem_device == 0x205a ||
11390                              tp->pdev->subsystem_device == 0x2063))
11391                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11392                 } else {
11393                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11394                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11395                 }
11396
11397                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11398                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11399                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11400                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11401                 }
11402                 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
11403                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11404                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11405                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11406                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11407
11408                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11409                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE) &&
11410                     device_may_wakeup(&tp->pdev->dev))
11411                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11412
11413                 if (cfg2 & (1 << 17))
11414                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11415
11416                 /* serdes signal pre-emphasis in register 0x590 set by */
11417                 /* bootcode if bit 18 is set */
11418                 if (cfg2 & (1 << 18))
11419                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11420
11421                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11422                         u32 cfg3;
11423
11424                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11425                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11426                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11427                 }
11428
11429                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11430                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11431                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11432                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11433                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11434                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11435         }
11436 }
11437
11438 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11439 {
11440         int i;
11441         u32 val;
11442
11443         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11444         tw32(OTP_CTRL, cmd);
11445
11446         /* Wait for up to 1 ms for command to execute. */
11447         for (i = 0; i < 100; i++) {
11448                 val = tr32(OTP_STATUS);
11449                 if (val & OTP_STATUS_CMD_DONE)
11450                         break;
11451                 udelay(10);
11452         }
11453
11454         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11455 }
11456
11457 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11458  * configuration is a 32-bit value that straddles the alignment boundary.
11459  * We do two 32-bit reads and then shift and merge the results.
11460  */
11461 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11462 {
11463         u32 bhalf_otp, thalf_otp;
11464
11465         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11466
11467         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11468                 return 0;
11469
11470         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11471
11472         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11473                 return 0;
11474
11475         thalf_otp = tr32(OTP_READ_DATA);
11476
11477         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11478
11479         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11480                 return 0;
11481
11482         bhalf_otp = tr32(OTP_READ_DATA);
11483
11484         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11485 }
11486
11487 static int __devinit tg3_phy_probe(struct tg3 *tp)
11488 {
11489         u32 hw_phy_id_1, hw_phy_id_2;
11490         u32 hw_phy_id, hw_phy_id_masked;
11491         int err;
11492
11493         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11494                 return tg3_phy_init(tp);
11495
11496         /* Reading the PHY ID register can conflict with ASF
11497          * firwmare access to the PHY hardware.
11498          */
11499         err = 0;
11500         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11501             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11502                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11503         } else {
11504                 /* Now read the physical PHY_ID from the chip and verify
11505                  * that it is sane.  If it doesn't look good, we fall back
11506                  * to either the hard-coded table based PHY_ID and failing
11507                  * that the value found in the eeprom area.
11508                  */
11509                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11510                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11511
11512                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11513                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11514                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11515
11516                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11517         }
11518
11519         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11520                 tp->phy_id = hw_phy_id;
11521                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11522                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11523                 else
11524                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11525         } else {
11526                 if (tp->phy_id != PHY_ID_INVALID) {
11527                         /* Do nothing, phy ID already set up in
11528                          * tg3_get_eeprom_hw_cfg().
11529                          */
11530                 } else {
11531                         struct subsys_tbl_ent *p;
11532
11533                         /* No eeprom signature?  Try the hardcoded
11534                          * subsys device table.
11535                          */
11536                         p = lookup_by_subsys(tp);
11537                         if (!p)
11538                                 return -ENODEV;
11539
11540                         tp->phy_id = p->phy_id;
11541                         if (!tp->phy_id ||
11542                             tp->phy_id == PHY_ID_BCM8002)
11543                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11544                 }
11545         }
11546
11547         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11548             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11549             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11550                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11551
11552                 tg3_readphy(tp, MII_BMSR, &bmsr);
11553                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11554                     (bmsr & BMSR_LSTATUS))
11555                         goto skip_phy_reset;
11556
11557                 err = tg3_phy_reset(tp);
11558                 if (err)
11559                         return err;
11560
11561                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11562                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11563                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11564                 tg3_ctrl = 0;
11565                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11566                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11567                                     MII_TG3_CTRL_ADV_1000_FULL);
11568                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11569                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11570                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11571                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11572                 }
11573
11574                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11575                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11576                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11577                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11578                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11579
11580                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11581                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11582
11583                         tg3_writephy(tp, MII_BMCR,
11584                                      BMCR_ANENABLE | BMCR_ANRESTART);
11585                 }
11586                 tg3_phy_set_wirespeed(tp);
11587
11588                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11589                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11590                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11591         }
11592
11593 skip_phy_reset:
11594         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11595                 err = tg3_init_5401phy_dsp(tp);
11596                 if (err)
11597                         return err;
11598         }
11599
11600         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11601                 err = tg3_init_5401phy_dsp(tp);
11602         }
11603
11604         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11605                 tp->link_config.advertising =
11606                         (ADVERTISED_1000baseT_Half |
11607                          ADVERTISED_1000baseT_Full |
11608                          ADVERTISED_Autoneg |
11609                          ADVERTISED_FIBRE);
11610         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11611                 tp->link_config.advertising &=
11612                         ~(ADVERTISED_1000baseT_Half |
11613                           ADVERTISED_1000baseT_Full);
11614
11615         return err;
11616 }
11617
11618 static void __devinit tg3_read_partno(struct tg3 *tp)
11619 {
11620         unsigned char vpd_data[256];
11621         unsigned int i;
11622         u32 magic;
11623
11624         if (tg3_nvram_read_swab(tp, 0x0, &magic))
11625                 goto out_not_found;
11626
11627         if (magic == TG3_EEPROM_MAGIC) {
11628                 for (i = 0; i < 256; i += 4) {
11629                         u32 tmp;
11630
11631                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11632                                 goto out_not_found;
11633
11634                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
11635                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
11636                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11637                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11638                 }
11639         } else {
11640                 int vpd_cap;
11641
11642                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11643                 for (i = 0; i < 256; i += 4) {
11644                         u32 tmp, j = 0;
11645                         __le32 v;
11646                         u16 tmp16;
11647
11648                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11649                                               i);
11650                         while (j++ < 100) {
11651                                 pci_read_config_word(tp->pdev, vpd_cap +
11652                                                      PCI_VPD_ADDR, &tmp16);
11653                                 if (tmp16 & 0x8000)
11654                                         break;
11655                                 msleep(1);
11656                         }
11657                         if (!(tmp16 & 0x8000))
11658                                 goto out_not_found;
11659
11660                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11661                                               &tmp);
11662                         v = cpu_to_le32(tmp);
11663                         memcpy(&vpd_data[i], &v, 4);
11664                 }
11665         }
11666
11667         /* Now parse and find the part number. */
11668         for (i = 0; i < 254; ) {
11669                 unsigned char val = vpd_data[i];
11670                 unsigned int block_end;
11671
11672                 if (val == 0x82 || val == 0x91) {
11673                         i = (i + 3 +
11674                              (vpd_data[i + 1] +
11675                               (vpd_data[i + 2] << 8)));
11676                         continue;
11677                 }
11678
11679                 if (val != 0x90)
11680                         goto out_not_found;
11681
11682                 block_end = (i + 3 +
11683                              (vpd_data[i + 1] +
11684                               (vpd_data[i + 2] << 8)));
11685                 i += 3;
11686
11687                 if (block_end > 256)
11688                         goto out_not_found;
11689
11690                 while (i < (block_end - 2)) {
11691                         if (vpd_data[i + 0] == 'P' &&
11692                             vpd_data[i + 1] == 'N') {
11693                                 int partno_len = vpd_data[i + 2];
11694
11695                                 i += 3;
11696                                 if (partno_len > 24 || (partno_len + i) > 256)
11697                                         goto out_not_found;
11698
11699                                 memcpy(tp->board_part_number,
11700                                        &vpd_data[i], partno_len);
11701
11702                                 /* Success. */
11703                                 return;
11704                         }
11705                         i += 3 + vpd_data[i + 2];
11706                 }
11707
11708                 /* Part number not found. */
11709                 goto out_not_found;
11710         }
11711
11712 out_not_found:
11713         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11714                 strcpy(tp->board_part_number, "BCM95906");
11715         else
11716                 strcpy(tp->board_part_number, "none");
11717 }
11718
11719 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11720 {
11721         u32 val;
11722
11723         if (tg3_nvram_read_swab(tp, offset, &val) ||
11724             (val & 0xfc000000) != 0x0c000000 ||
11725             tg3_nvram_read_swab(tp, offset + 4, &val) ||
11726             val != 0)
11727                 return 0;
11728
11729         return 1;
11730 }
11731
11732 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11733 {
11734         u32 val, offset, start;
11735         u32 ver_offset;
11736         int i, bcnt;
11737
11738         if (tg3_nvram_read_swab(tp, 0, &val))
11739                 return;
11740
11741         if (val != TG3_EEPROM_MAGIC)
11742                 return;
11743
11744         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11745             tg3_nvram_read_swab(tp, 0x4, &start))
11746                 return;
11747
11748         offset = tg3_nvram_logical_addr(tp, offset);
11749
11750         if (!tg3_fw_img_is_valid(tp, offset) ||
11751             tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11752                 return;
11753
11754         offset = offset + ver_offset - start;
11755         for (i = 0; i < 16; i += 4) {
11756                 __le32 v;
11757                 if (tg3_nvram_read_le(tp, offset + i, &v))
11758                         return;
11759
11760                 memcpy(tp->fw_ver + i, &v, 4);
11761         }
11762
11763         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11764              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11765                 return;
11766
11767         for (offset = TG3_NVM_DIR_START;
11768              offset < TG3_NVM_DIR_END;
11769              offset += TG3_NVM_DIRENT_SIZE) {
11770                 if (tg3_nvram_read_swab(tp, offset, &val))
11771                         return;
11772
11773                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11774                         break;
11775         }
11776
11777         if (offset == TG3_NVM_DIR_END)
11778                 return;
11779
11780         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11781                 start = 0x08000000;
11782         else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11783                 return;
11784
11785         if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11786             !tg3_fw_img_is_valid(tp, offset) ||
11787             tg3_nvram_read_swab(tp, offset + 8, &val))
11788                 return;
11789
11790         offset += val - start;
11791
11792         bcnt = strlen(tp->fw_ver);
11793
11794         tp->fw_ver[bcnt++] = ',';
11795         tp->fw_ver[bcnt++] = ' ';
11796
11797         for (i = 0; i < 4; i++) {
11798                 __le32 v;
11799                 if (tg3_nvram_read_le(tp, offset, &v))
11800                         return;
11801
11802                 offset += sizeof(v);
11803
11804                 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11805                         memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11806                         break;
11807                 }
11808
11809                 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11810                 bcnt += sizeof(v);
11811         }
11812
11813         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11814 }
11815
11816 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11817
11818 static int __devinit tg3_get_invariants(struct tg3 *tp)
11819 {
11820         static struct pci_device_id write_reorder_chipsets[] = {
11821                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11822                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11823                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11824                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11825                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11826                              PCI_DEVICE_ID_VIA_8385_0) },
11827                 { },
11828         };
11829         u32 misc_ctrl_reg;
11830         u32 cacheline_sz_reg;
11831         u32 pci_state_reg, grc_misc_cfg;
11832         u32 val;
11833         u16 pci_cmd;
11834         int err, pcie_cap;
11835
11836         /* Force memory write invalidate off.  If we leave it on,
11837          * then on 5700_BX chips we have to enable a workaround.
11838          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11839          * to match the cacheline size.  The Broadcom driver have this
11840          * workaround but turns MWI off all the times so never uses
11841          * it.  This seems to suggest that the workaround is insufficient.
11842          */
11843         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11844         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11845         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11846
11847         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11848          * has the register indirect write enable bit set before
11849          * we try to access any of the MMIO registers.  It is also
11850          * critical that the PCI-X hw workaround situation is decided
11851          * before that as well.
11852          */
11853         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11854                               &misc_ctrl_reg);
11855
11856         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11857                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11859                 u32 prod_id_asic_rev;
11860
11861                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11862                                       &prod_id_asic_rev);
11863                 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11864         }
11865
11866         /* Wrong chip ID in 5752 A0. This code can be removed later
11867          * as A0 is not in production.
11868          */
11869         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11870                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11871
11872         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11873          * we need to disable memory and use config. cycles
11874          * only to access all registers. The 5702/03 chips
11875          * can mistakenly decode the special cycles from the
11876          * ICH chipsets as memory write cycles, causing corruption
11877          * of register and memory space. Only certain ICH bridges
11878          * will drive special cycles with non-zero data during the
11879          * address phase which can fall within the 5703's address
11880          * range. This is not an ICH bug as the PCI spec allows
11881          * non-zero address during special cycles. However, only
11882          * these ICH bridges are known to drive non-zero addresses
11883          * during special cycles.
11884          *
11885          * Since special cycles do not cross PCI bridges, we only
11886          * enable this workaround if the 5703 is on the secondary
11887          * bus of these ICH bridges.
11888          */
11889         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11890             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11891                 static struct tg3_dev_id {
11892                         u32     vendor;
11893                         u32     device;
11894                         u32     rev;
11895                 } ich_chipsets[] = {
11896                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11897                           PCI_ANY_ID },
11898                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11899                           PCI_ANY_ID },
11900                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11901                           0xa },
11902                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11903                           PCI_ANY_ID },
11904                         { },
11905                 };
11906                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11907                 struct pci_dev *bridge = NULL;
11908
11909                 while (pci_id->vendor != 0) {
11910                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11911                                                 bridge);
11912                         if (!bridge) {
11913                                 pci_id++;
11914                                 continue;
11915                         }
11916                         if (pci_id->rev != PCI_ANY_ID) {
11917                                 if (bridge->revision > pci_id->rev)
11918                                         continue;
11919                         }
11920                         if (bridge->subordinate &&
11921                             (bridge->subordinate->number ==
11922                              tp->pdev->bus->number)) {
11923
11924                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11925                                 pci_dev_put(bridge);
11926                                 break;
11927                         }
11928                 }
11929         }
11930
11931         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11932                 static struct tg3_dev_id {
11933                         u32     vendor;
11934                         u32     device;
11935                 } bridge_chipsets[] = {
11936                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11937                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11938                         { },
11939                 };
11940                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11941                 struct pci_dev *bridge = NULL;
11942
11943                 while (pci_id->vendor != 0) {
11944                         bridge = pci_get_device(pci_id->vendor,
11945                                                 pci_id->device,
11946                                                 bridge);
11947                         if (!bridge) {
11948                                 pci_id++;
11949                                 continue;
11950                         }
11951                         if (bridge->subordinate &&
11952                             (bridge->subordinate->number <=
11953                              tp->pdev->bus->number) &&
11954                             (bridge->subordinate->subordinate >=
11955                              tp->pdev->bus->number)) {
11956                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11957                                 pci_dev_put(bridge);
11958                                 break;
11959                         }
11960                 }
11961         }
11962
11963         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11964          * DMA addresses > 40-bit. This bridge may have other additional
11965          * 57xx devices behind it in some 4-port NIC designs for example.
11966          * Any tg3 device found behind the bridge will also need the 40-bit
11967          * DMA workaround.
11968          */
11969         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11970             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11971                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11972                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11973                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11974         }
11975         else {
11976                 struct pci_dev *bridge = NULL;
11977
11978                 do {
11979                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11980                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
11981                                                 bridge);
11982                         if (bridge && bridge->subordinate &&
11983                             (bridge->subordinate->number <=
11984                              tp->pdev->bus->number) &&
11985                             (bridge->subordinate->subordinate >=
11986                              tp->pdev->bus->number)) {
11987                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11988                                 pci_dev_put(bridge);
11989                                 break;
11990                         }
11991                 } while (bridge);
11992         }
11993
11994         /* Initialize misc host control in PCI block. */
11995         tp->misc_host_ctrl |= (misc_ctrl_reg &
11996                                MISC_HOST_CTRL_CHIPREV);
11997         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11998                                tp->misc_host_ctrl);
11999
12000         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12001                               &cacheline_sz_reg);
12002
12003         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
12004         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
12005         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
12006         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
12007
12008         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12009             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12010                 tp->pdev_peer = tg3_find_peer(tp);
12011
12012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12020             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12021                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12022
12023         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12024             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12025                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12026
12027         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12028                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12029                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12030                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12031                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12032                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12033                      tp->pdev_peer == tp->pdev))
12034                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12035
12036                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12037                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12038                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12039                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12040                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12041                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12042                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12043                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12044                 } else {
12045                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12046                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12047                                 ASIC_REV_5750 &&
12048                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12049                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12050                 }
12051         }
12052
12053         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12054              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12055                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12056
12057         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12058         if (pcie_cap != 0) {
12059                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12060
12061                 pcie_set_readrq(tp->pdev, 4096);
12062
12063                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12064                         u16 lnkctl;
12065
12066                         pci_read_config_word(tp->pdev,
12067                                              pcie_cap + PCI_EXP_LNKCTL,
12068                                              &lnkctl);
12069                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
12070                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12071                 }
12072         }
12073
12074         /* If we have an AMD 762 or VIA K8T800 chipset, write
12075          * reordering to the mailbox registers done by the host
12076          * controller can cause major troubles.  We read back from
12077          * every mailbox register write to force the writes to be
12078          * posted to the chip in order.
12079          */
12080         if (pci_dev_present(write_reorder_chipsets) &&
12081             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12082                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12083
12084         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12085             tp->pci_lat_timer < 64) {
12086                 tp->pci_lat_timer = 64;
12087
12088                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
12089                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
12090                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
12091                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
12092
12093                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12094                                        cacheline_sz_reg);
12095         }
12096
12097         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12098             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12099                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12100                 if (!tp->pcix_cap) {
12101                         printk(KERN_ERR PFX "Cannot find PCI-X "
12102                                             "capability, aborting.\n");
12103                         return -EIO;
12104                 }
12105         }
12106
12107         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12108                               &pci_state_reg);
12109
12110         if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
12111                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12112
12113                 /* If this is a 5700 BX chipset, and we are in PCI-X
12114                  * mode, enable register write workaround.
12115                  *
12116                  * The workaround is to use indirect register accesses
12117                  * for all chip writes not to mailbox registers.
12118                  */
12119                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12120                         u32 pm_reg;
12121
12122                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12123
12124                         /* The chip can have it's power management PCI config
12125                          * space registers clobbered due to this bug.
12126                          * So explicitly force the chip into D0 here.
12127                          */
12128                         pci_read_config_dword(tp->pdev,
12129                                               tp->pm_cap + PCI_PM_CTRL,
12130                                               &pm_reg);
12131                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12132                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12133                         pci_write_config_dword(tp->pdev,
12134                                                tp->pm_cap + PCI_PM_CTRL,
12135                                                pm_reg);
12136
12137                         /* Also, force SERR#/PERR# in PCI command. */
12138                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12139                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12140                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12141                 }
12142         }
12143
12144         /* 5700 BX chips need to have their TX producer index mailboxes
12145          * written twice to workaround a bug.
12146          */
12147         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
12148                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12149
12150         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12151                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12152         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12153                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12154
12155         /* Chip-specific fixup from Broadcom driver */
12156         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12157             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12158                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12159                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12160         }
12161
12162         /* Default fast path register access methods */
12163         tp->read32 = tg3_read32;
12164         tp->write32 = tg3_write32;
12165         tp->read32_mbox = tg3_read32;
12166         tp->write32_mbox = tg3_write32;
12167         tp->write32_tx_mbox = tg3_write32;
12168         tp->write32_rx_mbox = tg3_write32;
12169
12170         /* Various workaround register access methods */
12171         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12172                 tp->write32 = tg3_write_indirect_reg32;
12173         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12174                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12175                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12176                 /*
12177                  * Back to back register writes can cause problems on these
12178                  * chips, the workaround is to read back all reg writes
12179                  * except those to mailbox regs.
12180                  *
12181                  * See tg3_write_indirect_reg32().
12182                  */
12183                 tp->write32 = tg3_write_flush_reg32;
12184         }
12185
12186
12187         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12188             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12189                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12190                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12191                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12192         }
12193
12194         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12195                 tp->read32 = tg3_read_indirect_reg32;
12196                 tp->write32 = tg3_write_indirect_reg32;
12197                 tp->read32_mbox = tg3_read_indirect_mbox;
12198                 tp->write32_mbox = tg3_write_indirect_mbox;
12199                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12200                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12201
12202                 iounmap(tp->regs);
12203                 tp->regs = NULL;
12204
12205                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12206                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12207                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12208         }
12209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12210                 tp->read32_mbox = tg3_read32_mbox_5906;
12211                 tp->write32_mbox = tg3_write32_mbox_5906;
12212                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12213                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12214         }
12215
12216         if (tp->write32 == tg3_write_indirect_reg32 ||
12217             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12218              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12219               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12220                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12221
12222         /* Get eeprom hw config before calling tg3_set_power_state().
12223          * In particular, the TG3_FLG2_IS_NIC flag must be
12224          * determined before calling tg3_set_power_state() so that
12225          * we know whether or not to switch out of Vaux power.
12226          * When the flag is set, it means that GPIO1 is used for eeprom
12227          * write protect and also implies that it is a LOM where GPIOs
12228          * are not used to switch power.
12229          */
12230         tg3_get_eeprom_hw_cfg(tp);
12231
12232         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12233                 /* Allow reads and writes to the
12234                  * APE register and memory space.
12235                  */
12236                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12237                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12238                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12239                                        pci_state_reg);
12240         }
12241
12242         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12243             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12244             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12245                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12246
12247                 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12248                     tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12249                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12250                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12251                         tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12252         }
12253
12254         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12255          * GPIO1 driven high will bring 5700's external PHY out of reset.
12256          * It is also used as eeprom write protect on LOMs.
12257          */
12258         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12259         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12260             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12261                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12262                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12263         /* Unused GPIO3 must be driven as output on 5752 because there
12264          * are no pull-up resistors on unused GPIO pins.
12265          */
12266         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12267                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12268
12269         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12270                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12271
12272         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12273                 /* Turn off the debug UART. */
12274                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12275                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12276                         /* Keep VMain power. */
12277                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12278                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12279         }
12280
12281         /* Force the chip into D0. */
12282         err = tg3_set_power_state(tp, PCI_D0);
12283         if (err) {
12284                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12285                        pci_name(tp->pdev));
12286                 return err;
12287         }
12288
12289         /* 5700 B0 chips do not support checksumming correctly due
12290          * to hardware bugs.
12291          */
12292         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12293                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12294
12295         /* Derive initial jumbo mode from MTU assigned in
12296          * ether_setup() via the alloc_etherdev() call
12297          */
12298         if (tp->dev->mtu > ETH_DATA_LEN &&
12299             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12300                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12301
12302         /* Determine WakeOnLan speed to use. */
12303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12304             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12305             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12306             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12307                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12308         } else {
12309                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12310         }
12311
12312         /* A few boards don't want Ethernet@WireSpeed phy feature */
12313         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12314             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12315              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12316              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12318             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12319                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12320
12321         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12322             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12323                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12324         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12325                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12326
12327         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12328                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12329                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12330                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12331                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12332                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12333                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12334                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12335                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12336                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12337                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12338                            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
12339                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12340         }
12341
12342         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12343             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12344                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12345                 if (tp->phy_otp == 0)
12346                         tp->phy_otp = TG3_OTP_DEFAULT;
12347         }
12348
12349         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12350                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12351         else
12352                 tp->mi_mode = MAC_MI_MODE_BASE;
12353
12354         tp->coalesce_mode = 0;
12355         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12356             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12357                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12358
12359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12360                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12361
12362         err = tg3_mdio_init(tp);
12363         if (err)
12364                 return err;
12365
12366         /* Initialize data/descriptor byte/word swapping. */
12367         val = tr32(GRC_MODE);
12368         val &= GRC_MODE_HOST_STACKUP;
12369         tw32(GRC_MODE, val | tp->grc_mode);
12370
12371         tg3_switch_clocks(tp);
12372
12373         /* Clear this out for sanity. */
12374         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12375
12376         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12377                               &pci_state_reg);
12378         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12379             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12380                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12381
12382                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12383                     chiprevid == CHIPREV_ID_5701_B0 ||
12384                     chiprevid == CHIPREV_ID_5701_B2 ||
12385                     chiprevid == CHIPREV_ID_5701_B5) {
12386                         void __iomem *sram_base;
12387
12388                         /* Write some dummy words into the SRAM status block
12389                          * area, see if it reads back correctly.  If the return
12390                          * value is bad, force enable the PCIX workaround.
12391                          */
12392                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12393
12394                         writel(0x00000000, sram_base);
12395                         writel(0x00000000, sram_base + 4);
12396                         writel(0xffffffff, sram_base + 4);
12397                         if (readl(sram_base) != 0x00000000)
12398                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12399                 }
12400         }
12401
12402         udelay(50);
12403         tg3_nvram_init(tp);
12404
12405         grc_misc_cfg = tr32(GRC_MISC_CFG);
12406         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12407
12408         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12409             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12410              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12411                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12412
12413         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12414             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12415                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12416         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12417                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12418                                       HOSTCC_MODE_CLRTICK_TXBD);
12419
12420                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12421                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12422                                        tp->misc_host_ctrl);
12423         }
12424
12425         /* these are limited to 10/100 only */
12426         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12427              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12428             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12429              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12430              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12431               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12432               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12433             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12434              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12435               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12436               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12437             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12438                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12439
12440         err = tg3_phy_probe(tp);
12441         if (err) {
12442                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12443                        pci_name(tp->pdev), err);
12444                 /* ... but do not return immediately ... */
12445                 tg3_mdio_fini(tp);
12446         }
12447
12448         tg3_read_partno(tp);
12449         tg3_read_fw_ver(tp);
12450
12451         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12452                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12453         } else {
12454                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12455                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12456                 else
12457                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12458         }
12459
12460         /* 5700 {AX,BX} chips have a broken status block link
12461          * change bit implementation, so we must use the
12462          * status register in those cases.
12463          */
12464         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12465                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12466         else
12467                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12468
12469         /* The led_ctrl is set during tg3_phy_probe, here we might
12470          * have to force the link status polling mechanism based
12471          * upon subsystem IDs.
12472          */
12473         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12474             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12475             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12476                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12477                                   TG3_FLAG_USE_LINKCHG_REG);
12478         }
12479
12480         /* For all SERDES we poll the MAC status register. */
12481         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12482                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12483         else
12484                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12485
12486         /* All chips before 5787 can get confused if TX buffers
12487          * straddle the 4GB address boundary in some cases.
12488          */
12489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12490             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12491             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12492             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12493             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12494             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12495                 tp->dev->hard_start_xmit = tg3_start_xmit;
12496         else
12497                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
12498
12499         tp->rx_offset = 2;
12500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12501             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12502                 tp->rx_offset = 0;
12503
12504         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12505
12506         /* Increment the rx prod index on the rx std ring by at most
12507          * 8 for these chips to workaround hw errata.
12508          */
12509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12510             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12511             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12512                 tp->rx_std_max_post = 8;
12513
12514         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12515                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12516                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12517
12518         return err;
12519 }
12520
12521 #ifdef CONFIG_SPARC
12522 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12523 {
12524         struct net_device *dev = tp->dev;
12525         struct pci_dev *pdev = tp->pdev;
12526         struct device_node *dp = pci_device_to_OF_node(pdev);
12527         const unsigned char *addr;
12528         int len;
12529
12530         addr = of_get_property(dp, "local-mac-address", &len);
12531         if (addr && len == 6) {
12532                 memcpy(dev->dev_addr, addr, 6);
12533                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12534                 return 0;
12535         }
12536         return -ENODEV;
12537 }
12538
12539 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12540 {
12541         struct net_device *dev = tp->dev;
12542
12543         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12544         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12545         return 0;
12546 }
12547 #endif
12548
12549 static int __devinit tg3_get_device_address(struct tg3 *tp)
12550 {
12551         struct net_device *dev = tp->dev;
12552         u32 hi, lo, mac_offset;
12553         int addr_ok = 0;
12554
12555 #ifdef CONFIG_SPARC
12556         if (!tg3_get_macaddr_sparc(tp))
12557                 return 0;
12558 #endif
12559
12560         mac_offset = 0x7c;
12561         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12562             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12563                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12564                         mac_offset = 0xcc;
12565                 if (tg3_nvram_lock(tp))
12566                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12567                 else
12568                         tg3_nvram_unlock(tp);
12569         }
12570         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12571                 mac_offset = 0x10;
12572
12573         /* First try to get it from MAC address mailbox. */
12574         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12575         if ((hi >> 16) == 0x484b) {
12576                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12577                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12578
12579                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12580                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12581                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12582                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12583                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12584
12585                 /* Some old bootcode may report a 0 MAC address in SRAM */
12586                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12587         }
12588         if (!addr_ok) {
12589                 /* Next, try NVRAM. */
12590                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12591                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12592                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
12593                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
12594                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
12595                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
12596                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
12597                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
12598                 }
12599                 /* Finally just fetch it out of the MAC control regs. */
12600                 else {
12601                         hi = tr32(MAC_ADDR_0_HIGH);
12602                         lo = tr32(MAC_ADDR_0_LOW);
12603
12604                         dev->dev_addr[5] = lo & 0xff;
12605                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12606                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12607                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12608                         dev->dev_addr[1] = hi & 0xff;
12609                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12610                 }
12611         }
12612
12613         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12614 #ifdef CONFIG_SPARC
12615                 if (!tg3_get_default_macaddr_sparc(tp))
12616                         return 0;
12617 #endif
12618                 return -EINVAL;
12619         }
12620         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12621         return 0;
12622 }
12623
12624 #define BOUNDARY_SINGLE_CACHELINE       1
12625 #define BOUNDARY_MULTI_CACHELINE        2
12626
12627 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12628 {
12629         int cacheline_size;
12630         u8 byte;
12631         int goal;
12632
12633         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12634         if (byte == 0)
12635                 cacheline_size = 1024;
12636         else
12637                 cacheline_size = (int) byte * 4;
12638
12639         /* On 5703 and later chips, the boundary bits have no
12640          * effect.
12641          */
12642         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12643             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12644             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12645                 goto out;
12646
12647 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12648         goal = BOUNDARY_MULTI_CACHELINE;
12649 #else
12650 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12651         goal = BOUNDARY_SINGLE_CACHELINE;
12652 #else
12653         goal = 0;
12654 #endif
12655 #endif
12656
12657         if (!goal)
12658                 goto out;
12659
12660         /* PCI controllers on most RISC systems tend to disconnect
12661          * when a device tries to burst across a cache-line boundary.
12662          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12663          *
12664          * Unfortunately, for PCI-E there are only limited
12665          * write-side controls for this, and thus for reads
12666          * we will still get the disconnects.  We'll also waste
12667          * these PCI cycles for both read and write for chips
12668          * other than 5700 and 5701 which do not implement the
12669          * boundary bits.
12670          */
12671         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12672             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12673                 switch (cacheline_size) {
12674                 case 16:
12675                 case 32:
12676                 case 64:
12677                 case 128:
12678                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12679                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12680                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12681                         } else {
12682                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12683                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12684                         }
12685                         break;
12686
12687                 case 256:
12688                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12689                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12690                         break;
12691
12692                 default:
12693                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12694                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12695                         break;
12696                 }
12697         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12698                 switch (cacheline_size) {
12699                 case 16:
12700                 case 32:
12701                 case 64:
12702                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12703                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12704                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12705                                 break;
12706                         }
12707                         /* fallthrough */
12708                 case 128:
12709                 default:
12710                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12711                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12712                         break;
12713                 }
12714         } else {
12715                 switch (cacheline_size) {
12716                 case 16:
12717                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12718                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12719                                         DMA_RWCTRL_WRITE_BNDRY_16);
12720                                 break;
12721                         }
12722                         /* fallthrough */
12723                 case 32:
12724                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12725                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12726                                         DMA_RWCTRL_WRITE_BNDRY_32);
12727                                 break;
12728                         }
12729                         /* fallthrough */
12730                 case 64:
12731                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12732                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12733                                         DMA_RWCTRL_WRITE_BNDRY_64);
12734                                 break;
12735                         }
12736                         /* fallthrough */
12737                 case 128:
12738                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12739                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12740                                         DMA_RWCTRL_WRITE_BNDRY_128);
12741                                 break;
12742                         }
12743                         /* fallthrough */
12744                 case 256:
12745                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12746                                 DMA_RWCTRL_WRITE_BNDRY_256);
12747                         break;
12748                 case 512:
12749                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12750                                 DMA_RWCTRL_WRITE_BNDRY_512);
12751                         break;
12752                 case 1024:
12753                 default:
12754                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12755                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12756                         break;
12757                 }
12758         }
12759
12760 out:
12761         return val;
12762 }
12763
12764 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12765 {
12766         struct tg3_internal_buffer_desc test_desc;
12767         u32 sram_dma_descs;
12768         int i, ret;
12769
12770         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12771
12772         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12773         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12774         tw32(RDMAC_STATUS, 0);
12775         tw32(WDMAC_STATUS, 0);
12776
12777         tw32(BUFMGR_MODE, 0);
12778         tw32(FTQ_RESET, 0);
12779
12780         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12781         test_desc.addr_lo = buf_dma & 0xffffffff;
12782         test_desc.nic_mbuf = 0x00002100;
12783         test_desc.len = size;
12784
12785         /*
12786          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12787          * the *second* time the tg3 driver was getting loaded after an
12788          * initial scan.
12789          *
12790          * Broadcom tells me:
12791          *   ...the DMA engine is connected to the GRC block and a DMA
12792          *   reset may affect the GRC block in some unpredictable way...
12793          *   The behavior of resets to individual blocks has not been tested.
12794          *
12795          * Broadcom noted the GRC reset will also reset all sub-components.
12796          */
12797         if (to_device) {
12798                 test_desc.cqid_sqid = (13 << 8) | 2;
12799
12800                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12801                 udelay(40);
12802         } else {
12803                 test_desc.cqid_sqid = (16 << 8) | 7;
12804
12805                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12806                 udelay(40);
12807         }
12808         test_desc.flags = 0x00000005;
12809
12810         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12811                 u32 val;
12812
12813                 val = *(((u32 *)&test_desc) + i);
12814                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12815                                        sram_dma_descs + (i * sizeof(u32)));
12816                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12817         }
12818         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12819
12820         if (to_device) {
12821                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12822         } else {
12823                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12824         }
12825
12826         ret = -ENODEV;
12827         for (i = 0; i < 40; i++) {
12828                 u32 val;
12829
12830                 if (to_device)
12831                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12832                 else
12833                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12834                 if ((val & 0xffff) == sram_dma_descs) {
12835                         ret = 0;
12836                         break;
12837                 }
12838
12839                 udelay(100);
12840         }
12841
12842         return ret;
12843 }
12844
12845 #define TEST_BUFFER_SIZE        0x2000
12846
12847 static int __devinit tg3_test_dma(struct tg3 *tp)
12848 {
12849         dma_addr_t buf_dma;
12850         u32 *buf, saved_dma_rwctrl;
12851         int ret;
12852
12853         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12854         if (!buf) {
12855                 ret = -ENOMEM;
12856                 goto out_nofree;
12857         }
12858
12859         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12860                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12861
12862         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12863
12864         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12865                 /* DMA read watermark not used on PCIE */
12866                 tp->dma_rwctrl |= 0x00180000;
12867         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12868                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12869                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12870                         tp->dma_rwctrl |= 0x003f0000;
12871                 else
12872                         tp->dma_rwctrl |= 0x003f000f;
12873         } else {
12874                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12875                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12876                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12877                         u32 read_water = 0x7;
12878
12879                         /* If the 5704 is behind the EPB bridge, we can
12880                          * do the less restrictive ONE_DMA workaround for
12881                          * better performance.
12882                          */
12883                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12884                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12885                                 tp->dma_rwctrl |= 0x8000;
12886                         else if (ccval == 0x6 || ccval == 0x7)
12887                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12888
12889                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12890                                 read_water = 4;
12891                         /* Set bit 23 to enable PCIX hw bug fix */
12892                         tp->dma_rwctrl |=
12893                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12894                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12895                                 (1 << 23);
12896                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12897                         /* 5780 always in PCIX mode */
12898                         tp->dma_rwctrl |= 0x00144000;
12899                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12900                         /* 5714 always in PCIX mode */
12901                         tp->dma_rwctrl |= 0x00148000;
12902                 } else {
12903                         tp->dma_rwctrl |= 0x001b000f;
12904                 }
12905         }
12906
12907         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12908             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12909                 tp->dma_rwctrl &= 0xfffffff0;
12910
12911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12912             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12913                 /* Remove this if it causes problems for some boards. */
12914                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12915
12916                 /* On 5700/5701 chips, we need to set this bit.
12917                  * Otherwise the chip will issue cacheline transactions
12918                  * to streamable DMA memory with not all the byte
12919                  * enables turned on.  This is an error on several
12920                  * RISC PCI controllers, in particular sparc64.
12921                  *
12922                  * On 5703/5704 chips, this bit has been reassigned
12923                  * a different meaning.  In particular, it is used
12924                  * on those chips to enable a PCI-X workaround.
12925                  */
12926                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12927         }
12928
12929         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12930
12931 #if 0
12932         /* Unneeded, already done by tg3_get_invariants.  */
12933         tg3_switch_clocks(tp);
12934 #endif
12935
12936         ret = 0;
12937         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12938             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12939                 goto out;
12940
12941         /* It is best to perform DMA test with maximum write burst size
12942          * to expose the 5700/5701 write DMA bug.
12943          */
12944         saved_dma_rwctrl = tp->dma_rwctrl;
12945         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12946         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12947
12948         while (1) {
12949                 u32 *p = buf, i;
12950
12951                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12952                         p[i] = i;
12953
12954                 /* Send the buffer to the chip. */
12955                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12956                 if (ret) {
12957                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12958                         break;
12959                 }
12960
12961 #if 0
12962                 /* validate data reached card RAM correctly. */
12963                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12964                         u32 val;
12965                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12966                         if (le32_to_cpu(val) != p[i]) {
12967                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12968                                 /* ret = -ENODEV here? */
12969                         }
12970                         p[i] = 0;
12971                 }
12972 #endif
12973                 /* Now read it back. */
12974                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12975                 if (ret) {
12976                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12977
12978                         break;
12979                 }
12980
12981                 /* Verify it. */
12982                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12983                         if (p[i] == i)
12984                                 continue;
12985
12986                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12987                             DMA_RWCTRL_WRITE_BNDRY_16) {
12988                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12989                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12990                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12991                                 break;
12992                         } else {
12993                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12994                                 ret = -ENODEV;
12995                                 goto out;
12996                         }
12997                 }
12998
12999                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13000                         /* Success. */
13001                         ret = 0;
13002                         break;
13003                 }
13004         }
13005         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13006             DMA_RWCTRL_WRITE_BNDRY_16) {
13007                 static struct pci_device_id dma_wait_state_chipsets[] = {
13008                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13009                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13010                         { },
13011                 };
13012
13013                 /* DMA test passed without adjusting DMA boundary,
13014                  * now look for chipsets that are known to expose the
13015                  * DMA bug without failing the test.
13016                  */
13017                 if (pci_dev_present(dma_wait_state_chipsets)) {
13018                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13019                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13020                 }
13021                 else
13022                         /* Safe to use the calculated DMA boundary. */
13023                         tp->dma_rwctrl = saved_dma_rwctrl;
13024
13025                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13026         }
13027
13028 out:
13029         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13030 out_nofree:
13031         return ret;
13032 }
13033
13034 static void __devinit tg3_init_link_config(struct tg3 *tp)
13035 {
13036         tp->link_config.advertising =
13037                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13038                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13039                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13040                  ADVERTISED_Autoneg | ADVERTISED_MII);
13041         tp->link_config.speed = SPEED_INVALID;
13042         tp->link_config.duplex = DUPLEX_INVALID;
13043         tp->link_config.autoneg = AUTONEG_ENABLE;
13044         tp->link_config.active_speed = SPEED_INVALID;
13045         tp->link_config.active_duplex = DUPLEX_INVALID;
13046         tp->link_config.phy_is_low_power = 0;
13047         tp->link_config.orig_speed = SPEED_INVALID;
13048         tp->link_config.orig_duplex = DUPLEX_INVALID;
13049         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13050 }
13051
13052 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13053 {
13054         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13055                 tp->bufmgr_config.mbuf_read_dma_low_water =
13056                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13057                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13058                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13059                 tp->bufmgr_config.mbuf_high_water =
13060                         DEFAULT_MB_HIGH_WATER_5705;
13061                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13062                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13063                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13064                         tp->bufmgr_config.mbuf_high_water =
13065                                 DEFAULT_MB_HIGH_WATER_5906;
13066                 }
13067
13068                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13069                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13070                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13071                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13072                 tp->bufmgr_config.mbuf_high_water_jumbo =
13073                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13074         } else {
13075                 tp->bufmgr_config.mbuf_read_dma_low_water =
13076                         DEFAULT_MB_RDMA_LOW_WATER;
13077                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13078                         DEFAULT_MB_MACRX_LOW_WATER;
13079                 tp->bufmgr_config.mbuf_high_water =
13080                         DEFAULT_MB_HIGH_WATER;
13081
13082                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13083                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13084                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13085                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13086                 tp->bufmgr_config.mbuf_high_water_jumbo =
13087                         DEFAULT_MB_HIGH_WATER_JUMBO;
13088         }
13089
13090         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13091         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13092 }
13093
13094 static char * __devinit tg3_phy_string(struct tg3 *tp)
13095 {
13096         switch (tp->phy_id & PHY_ID_MASK) {
13097         case PHY_ID_BCM5400:    return "5400";
13098         case PHY_ID_BCM5401:    return "5401";
13099         case PHY_ID_BCM5411:    return "5411";
13100         case PHY_ID_BCM5701:    return "5701";
13101         case PHY_ID_BCM5703:    return "5703";
13102         case PHY_ID_BCM5704:    return "5704";
13103         case PHY_ID_BCM5705:    return "5705";
13104         case PHY_ID_BCM5750:    return "5750";
13105         case PHY_ID_BCM5752:    return "5752";
13106         case PHY_ID_BCM5714:    return "5714";
13107         case PHY_ID_BCM5780:    return "5780";
13108         case PHY_ID_BCM5755:    return "5755";
13109         case PHY_ID_BCM5787:    return "5787";
13110         case PHY_ID_BCM5784:    return "5784";
13111         case PHY_ID_BCM5756:    return "5722/5756";
13112         case PHY_ID_BCM5906:    return "5906";
13113         case PHY_ID_BCM5761:    return "5761";
13114         case PHY_ID_BCM8002:    return "8002/serdes";
13115         case 0:                 return "serdes";
13116         default:                return "unknown";
13117         }
13118 }
13119
13120 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13121 {
13122         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13123                 strcpy(str, "PCI Express");
13124                 return str;
13125         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13126                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13127
13128                 strcpy(str, "PCIX:");
13129
13130                 if ((clock_ctrl == 7) ||
13131                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13132                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13133                         strcat(str, "133MHz");
13134                 else if (clock_ctrl == 0)
13135                         strcat(str, "33MHz");
13136                 else if (clock_ctrl == 2)
13137                         strcat(str, "50MHz");
13138                 else if (clock_ctrl == 4)
13139                         strcat(str, "66MHz");
13140                 else if (clock_ctrl == 6)
13141                         strcat(str, "100MHz");
13142         } else {
13143                 strcpy(str, "PCI:");
13144                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13145                         strcat(str, "66MHz");
13146                 else
13147                         strcat(str, "33MHz");
13148         }
13149         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13150                 strcat(str, ":32-bit");
13151         else
13152                 strcat(str, ":64-bit");
13153         return str;
13154 }
13155
13156 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13157 {
13158         struct pci_dev *peer;
13159         unsigned int func, devnr = tp->pdev->devfn & ~7;
13160
13161         for (func = 0; func < 8; func++) {
13162                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13163                 if (peer && peer != tp->pdev)
13164                         break;
13165                 pci_dev_put(peer);
13166         }
13167         /* 5704 can be configured in single-port mode, set peer to
13168          * tp->pdev in that case.
13169          */
13170         if (!peer) {
13171                 peer = tp->pdev;
13172                 return peer;
13173         }
13174
13175         /*
13176          * We don't need to keep the refcount elevated; there's no way
13177          * to remove one half of this device without removing the other
13178          */
13179         pci_dev_put(peer);
13180
13181         return peer;
13182 }
13183
13184 static void __devinit tg3_init_coal(struct tg3 *tp)
13185 {
13186         struct ethtool_coalesce *ec = &tp->coal;
13187
13188         memset(ec, 0, sizeof(*ec));
13189         ec->cmd = ETHTOOL_GCOALESCE;
13190         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13191         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13192         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13193         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13194         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13195         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13196         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13197         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13198         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13199
13200         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13201                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13202                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13203                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13204                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13205                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13206         }
13207
13208         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13209                 ec->rx_coalesce_usecs_irq = 0;
13210                 ec->tx_coalesce_usecs_irq = 0;
13211                 ec->stats_block_coalesce_usecs = 0;
13212         }
13213 }
13214
13215 static int __devinit tg3_init_one(struct pci_dev *pdev,
13216                                   const struct pci_device_id *ent)
13217 {
13218         static int tg3_version_printed = 0;
13219         resource_size_t tg3reg_base;
13220         unsigned long tg3reg_len;
13221         struct net_device *dev;
13222         struct tg3 *tp;
13223         int err, pm_cap;
13224         char str[40];
13225         u64 dma_mask, persist_dma_mask;
13226         DECLARE_MAC_BUF(mac);
13227
13228         if (tg3_version_printed++ == 0)
13229                 printk(KERN_INFO "%s", version);
13230
13231         err = pci_enable_device(pdev);
13232         if (err) {
13233                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13234                        "aborting.\n");
13235                 return err;
13236         }
13237
13238         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13239                 printk(KERN_ERR PFX "Cannot find proper PCI device "
13240                        "base address, aborting.\n");
13241                 err = -ENODEV;
13242                 goto err_out_disable_pdev;
13243         }
13244
13245         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13246         if (err) {
13247                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13248                        "aborting.\n");
13249                 goto err_out_disable_pdev;
13250         }
13251
13252         pci_set_master(pdev);
13253
13254         /* Find power-management capability. */
13255         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13256         if (pm_cap == 0) {
13257                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13258                        "aborting.\n");
13259                 err = -EIO;
13260                 goto err_out_free_res;
13261         }
13262
13263         tg3reg_base = pci_resource_start(pdev, 0);
13264         tg3reg_len = pci_resource_len(pdev, 0);
13265
13266         dev = alloc_etherdev(sizeof(*tp));
13267         if (!dev) {
13268                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13269                 err = -ENOMEM;
13270                 goto err_out_free_res;
13271         }
13272
13273         SET_NETDEV_DEV(dev, &pdev->dev);
13274
13275 #if TG3_VLAN_TAG_USED
13276         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13277         dev->vlan_rx_register = tg3_vlan_rx_register;
13278 #endif
13279
13280         tp = netdev_priv(dev);
13281         tp->pdev = pdev;
13282         tp->dev = dev;
13283         tp->pm_cap = pm_cap;
13284         tp->mac_mode = TG3_DEF_MAC_MODE;
13285         tp->rx_mode = TG3_DEF_RX_MODE;
13286         tp->tx_mode = TG3_DEF_TX_MODE;
13287
13288         if (tg3_debug > 0)
13289                 tp->msg_enable = tg3_debug;
13290         else
13291                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13292
13293         /* The word/byte swap controls here control register access byte
13294          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13295          * setting below.
13296          */
13297         tp->misc_host_ctrl =
13298                 MISC_HOST_CTRL_MASK_PCI_INT |
13299                 MISC_HOST_CTRL_WORD_SWAP |
13300                 MISC_HOST_CTRL_INDIR_ACCESS |
13301                 MISC_HOST_CTRL_PCISTATE_RW;
13302
13303         /* The NONFRM (non-frame) byte/word swap controls take effect
13304          * on descriptor entries, anything which isn't packet data.
13305          *
13306          * The StrongARM chips on the board (one for tx, one for rx)
13307          * are running in big-endian mode.
13308          */
13309         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13310                         GRC_MODE_WSWAP_NONFRM_DATA);
13311 #ifdef __BIG_ENDIAN
13312         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13313 #endif
13314         spin_lock_init(&tp->lock);
13315         spin_lock_init(&tp->indirect_lock);
13316         INIT_WORK(&tp->reset_task, tg3_reset_task);
13317
13318         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
13319         if (!tp->regs) {
13320                 printk(KERN_ERR PFX "Cannot map device registers, "
13321                        "aborting.\n");
13322                 err = -ENOMEM;
13323                 goto err_out_free_dev;
13324         }
13325
13326         tg3_init_link_config(tp);
13327
13328         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13329         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13330         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13331
13332         dev->open = tg3_open;
13333         dev->stop = tg3_close;
13334         dev->get_stats = tg3_get_stats;
13335         dev->set_multicast_list = tg3_set_rx_mode;
13336         dev->set_mac_address = tg3_set_mac_addr;
13337         dev->do_ioctl = tg3_ioctl;
13338         dev->tx_timeout = tg3_tx_timeout;
13339         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13340         dev->ethtool_ops = &tg3_ethtool_ops;
13341         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13342         dev->change_mtu = tg3_change_mtu;
13343         dev->irq = pdev->irq;
13344 #ifdef CONFIG_NET_POLL_CONTROLLER
13345         dev->poll_controller = tg3_poll_controller;
13346 #endif
13347
13348         err = tg3_get_invariants(tp);
13349         if (err) {
13350                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13351                        "aborting.\n");
13352                 goto err_out_iounmap;
13353         }
13354
13355         /* The EPB bridge inside 5714, 5715, and 5780 and any
13356          * device behind the EPB cannot support DMA addresses > 40-bit.
13357          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13358          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13359          * do DMA address check in tg3_start_xmit().
13360          */
13361         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13362                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13363         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13364                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13365 #ifdef CONFIG_HIGHMEM
13366                 dma_mask = DMA_64BIT_MASK;
13367 #endif
13368         } else
13369                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13370
13371         /* Configure DMA attributes. */
13372         if (dma_mask > DMA_32BIT_MASK) {
13373                 err = pci_set_dma_mask(pdev, dma_mask);
13374                 if (!err) {
13375                         dev->features |= NETIF_F_HIGHDMA;
13376                         err = pci_set_consistent_dma_mask(pdev,
13377                                                           persist_dma_mask);
13378                         if (err < 0) {
13379                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13380                                        "DMA for consistent allocations\n");
13381                                 goto err_out_iounmap;
13382                         }
13383                 }
13384         }
13385         if (err || dma_mask == DMA_32BIT_MASK) {
13386                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13387                 if (err) {
13388                         printk(KERN_ERR PFX "No usable DMA configuration, "
13389                                "aborting.\n");
13390                         goto err_out_iounmap;
13391                 }
13392         }
13393
13394         tg3_init_bufmgr_config(tp);
13395
13396         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13397                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13398         }
13399         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13400             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13401             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13402             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13403             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13404                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13405         } else {
13406                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13407         }
13408
13409         /* TSO is on by default on chips that support hardware TSO.
13410          * Firmware TSO on older chips gives lower performance, so it
13411          * is off by default, but can be enabled using ethtool.
13412          */
13413         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13414                 dev->features |= NETIF_F_TSO;
13415                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13416                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
13417                         dev->features |= NETIF_F_TSO6;
13418                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13419                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13420                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13421                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13422                         dev->features |= NETIF_F_TSO_ECN;
13423         }
13424
13425
13426         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13427             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13428             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13429                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13430                 tp->rx_pending = 63;
13431         }
13432
13433         err = tg3_get_device_address(tp);
13434         if (err) {
13435                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13436                        "aborting.\n");
13437                 goto err_out_iounmap;
13438         }
13439
13440         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13441                 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13442                         printk(KERN_ERR PFX "Cannot find proper PCI device "
13443                                "base address for APE, aborting.\n");
13444                         err = -ENODEV;
13445                         goto err_out_iounmap;
13446                 }
13447
13448                 tg3reg_base = pci_resource_start(pdev, 2);
13449                 tg3reg_len = pci_resource_len(pdev, 2);
13450
13451                 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13452                 if (!tp->aperegs) {
13453                         printk(KERN_ERR PFX "Cannot map APE registers, "
13454                                "aborting.\n");
13455                         err = -ENOMEM;
13456                         goto err_out_iounmap;
13457                 }
13458
13459                 tg3_ape_lock_init(tp);
13460         }
13461
13462         /*
13463          * Reset chip in case UNDI or EFI driver did not shutdown
13464          * DMA self test will enable WDMAC and we'll see (spurious)
13465          * pending DMA on the PCI bus at that point.
13466          */
13467         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13468             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13469                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13470                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13471         }
13472
13473         err = tg3_test_dma(tp);
13474         if (err) {
13475                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13476                 goto err_out_apeunmap;
13477         }
13478
13479         /* Tigon3 can do ipv4 only... and some chips have buggy
13480          * checksumming.
13481          */
13482         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13483                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13484                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13485                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13486                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13487                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13488                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13489                         dev->features |= NETIF_F_IPV6_CSUM;
13490
13491                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13492         } else
13493                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13494
13495         /* flow control autonegotiation is default behavior */
13496         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13497         tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
13498
13499         tg3_init_coal(tp);
13500
13501         pci_set_drvdata(pdev, dev);
13502
13503         err = register_netdev(dev);
13504         if (err) {
13505                 printk(KERN_ERR PFX "Cannot register net device, "
13506                        "aborting.\n");
13507                 goto err_out_apeunmap;
13508         }
13509
13510         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
13511                "(%s) %s Ethernet %s\n",
13512                dev->name,
13513                tp->board_part_number,
13514                tp->pci_chip_rev_id,
13515                tg3_phy_string(tp),
13516                tg3_bus_string(tp, str),
13517                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13518                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13519                  "10/100/1000Base-T")),
13520                print_mac(mac, dev->dev_addr));
13521
13522         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13523                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13524                dev->name,
13525                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13526                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13527                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13528                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13529                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13530                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13531         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13532                dev->name, tp->dma_rwctrl,
13533                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13534                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13535
13536         return 0;
13537
13538 err_out_apeunmap:
13539         if (tp->aperegs) {
13540                 iounmap(tp->aperegs);
13541                 tp->aperegs = NULL;
13542         }
13543
13544 err_out_iounmap:
13545         if (tp->regs) {
13546                 iounmap(tp->regs);
13547                 tp->regs = NULL;
13548         }
13549
13550 err_out_free_dev:
13551         free_netdev(dev);
13552
13553 err_out_free_res:
13554         pci_release_regions(pdev);
13555
13556 err_out_disable_pdev:
13557         pci_disable_device(pdev);
13558         pci_set_drvdata(pdev, NULL);
13559         return err;
13560 }
13561
13562 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13563 {
13564         struct net_device *dev = pci_get_drvdata(pdev);
13565
13566         if (dev) {
13567                 struct tg3 *tp = netdev_priv(dev);
13568
13569                 flush_scheduled_work();
13570
13571                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13572                         tg3_phy_fini(tp);
13573                         tg3_mdio_fini(tp);
13574                 }
13575
13576                 unregister_netdev(dev);
13577                 if (tp->aperegs) {
13578                         iounmap(tp->aperegs);
13579                         tp->aperegs = NULL;
13580                 }
13581                 if (tp->regs) {
13582                         iounmap(tp->regs);
13583                         tp->regs = NULL;
13584                 }
13585                 free_netdev(dev);
13586                 pci_release_regions(pdev);
13587                 pci_disable_device(pdev);
13588                 pci_set_drvdata(pdev, NULL);
13589         }
13590 }
13591
13592 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13593 {
13594         struct net_device *dev = pci_get_drvdata(pdev);
13595         struct tg3 *tp = netdev_priv(dev);
13596         pci_power_t target_state;
13597         int err;
13598
13599         /* PCI register 4 needs to be saved whether netif_running() or not.
13600          * MSI address and data need to be saved if using MSI and
13601          * netif_running().
13602          */
13603         pci_save_state(pdev);
13604
13605         if (!netif_running(dev))
13606                 return 0;
13607
13608         flush_scheduled_work();
13609         tg3_phy_stop(tp);
13610         tg3_netif_stop(tp);
13611
13612         del_timer_sync(&tp->timer);
13613
13614         tg3_full_lock(tp, 1);
13615         tg3_disable_ints(tp);
13616         tg3_full_unlock(tp);
13617
13618         netif_device_detach(dev);
13619
13620         tg3_full_lock(tp, 0);
13621         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13622         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13623         tg3_full_unlock(tp);
13624
13625         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13626
13627         err = tg3_set_power_state(tp, target_state);
13628         if (err) {
13629                 int err2;
13630
13631                 tg3_full_lock(tp, 0);
13632
13633                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13634                 err2 = tg3_restart_hw(tp, 1);
13635                 if (err2)
13636                         goto out;
13637
13638                 tp->timer.expires = jiffies + tp->timer_offset;
13639                 add_timer(&tp->timer);
13640
13641                 netif_device_attach(dev);
13642                 tg3_netif_start(tp);
13643
13644 out:
13645                 tg3_full_unlock(tp);
13646
13647                 if (!err2)
13648                         tg3_phy_start(tp);
13649         }
13650
13651         return err;
13652 }
13653
13654 static int tg3_resume(struct pci_dev *pdev)
13655 {
13656         struct net_device *dev = pci_get_drvdata(pdev);
13657         struct tg3 *tp = netdev_priv(dev);
13658         int err;
13659
13660         pci_restore_state(tp->pdev);
13661
13662         if (!netif_running(dev))
13663                 return 0;
13664
13665         err = tg3_set_power_state(tp, PCI_D0);
13666         if (err)
13667                 return err;
13668
13669         netif_device_attach(dev);
13670
13671         tg3_full_lock(tp, 0);
13672
13673         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13674         err = tg3_restart_hw(tp, 1);
13675         if (err)
13676                 goto out;
13677
13678         tp->timer.expires = jiffies + tp->timer_offset;
13679         add_timer(&tp->timer);
13680
13681         tg3_netif_start(tp);
13682
13683 out:
13684         tg3_full_unlock(tp);
13685
13686         if (!err)
13687                 tg3_phy_start(tp);
13688
13689         return err;
13690 }
13691
13692 static struct pci_driver tg3_driver = {
13693         .name           = DRV_MODULE_NAME,
13694         .id_table       = tg3_pci_tbl,
13695         .probe          = tg3_init_one,
13696         .remove         = __devexit_p(tg3_remove_one),
13697         .suspend        = tg3_suspend,
13698         .resume         = tg3_resume
13699 };
13700
13701 static int __init tg3_init(void)
13702 {
13703         return pci_register_driver(&tg3_driver);
13704 }
13705
13706 static void __exit tg3_cleanup(void)
13707 {
13708         pci_unregister_driver(&tg3_driver);
13709 }
13710
13711 module_init(tg3_init);
13712 module_exit(tg3_cleanup);