2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
18 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/if_vlan.h>
38 #include <linux/tcp.h>
39 #include <linux/workqueue.h>
40 #include <linux/prefetch.h>
41 #include <linux/dma-mapping.h>
43 #include <net/checksum.h>
45 #include <asm/system.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
51 #include <asm/idprom.h>
52 #include <asm/oplib.h>
56 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
57 #define TG3_VLAN_TAG_USED 1
59 #define TG3_VLAN_TAG_USED 0
63 #define TG3_TSO_SUPPORT 1
65 #define TG3_TSO_SUPPORT 0
70 #define DRV_MODULE_NAME "tg3"
71 #define PFX DRV_MODULE_NAME ": "
72 #define DRV_MODULE_VERSION "3.57"
73 #define DRV_MODULE_RELDATE "Apr 28, 2006"
75 #define TG3_DEF_MAC_MODE 0
76 #define TG3_DEF_RX_MODE 0
77 #define TG3_DEF_TX_MODE 0
78 #define TG3_DEF_MSG_ENABLE \
88 /* length of time before we decide the hardware is borked,
89 * and dev->tx_timeout() should be called to fix the problem
91 #define TG3_TX_TIMEOUT (5 * HZ)
93 /* hardware minimum and maximum for a single frame's data payload */
94 #define TG3_MIN_MTU 60
95 #define TG3_MAX_MTU(tp) \
96 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
98 /* These numbers seem to be hard coded in the NIC firmware somehow.
99 * You can't change the ring sizes, but you can change where you place
100 * them in the NIC onboard memory.
102 #define TG3_RX_RING_SIZE 512
103 #define TG3_DEF_RX_RING_PENDING 200
104 #define TG3_RX_JUMBO_RING_SIZE 256
105 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define TX_BUFFS_AVAIL(TP) \
128 ((TP)->tx_pending - \
129 (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
130 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
132 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
133 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
135 /* minimum number of free TX descriptors required to wake up TX process */
136 #define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
138 /* number of ETHTOOL_GSTATS u64's */
139 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
141 #define TG3_NUM_TEST 6
143 static char version[] __devinitdata =
144 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
146 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
147 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
148 MODULE_LICENSE("GPL");
149 MODULE_VERSION(DRV_MODULE_VERSION);
151 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
152 module_param(tg3_debug, int, 0);
153 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
155 static struct pci_device_id tg3_pci_tbl[] = {
156 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
212 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
214 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
216 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
218 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
228 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
244 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
246 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
248 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
250 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
252 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
254 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
256 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
258 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
260 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
262 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
267 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
270 const char string[ETH_GSTRING_LEN];
271 } ethtool_stats_keys[TG3_NUM_STATS] = {
274 { "rx_ucast_packets" },
275 { "rx_mcast_packets" },
276 { "rx_bcast_packets" },
278 { "rx_align_errors" },
279 { "rx_xon_pause_rcvd" },
280 { "rx_xoff_pause_rcvd" },
281 { "rx_mac_ctrl_rcvd" },
282 { "rx_xoff_entered" },
283 { "rx_frame_too_long_errors" },
285 { "rx_undersize_packets" },
286 { "rx_in_length_errors" },
287 { "rx_out_length_errors" },
288 { "rx_64_or_less_octet_packets" },
289 { "rx_65_to_127_octet_packets" },
290 { "rx_128_to_255_octet_packets" },
291 { "rx_256_to_511_octet_packets" },
292 { "rx_512_to_1023_octet_packets" },
293 { "rx_1024_to_1522_octet_packets" },
294 { "rx_1523_to_2047_octet_packets" },
295 { "rx_2048_to_4095_octet_packets" },
296 { "rx_4096_to_8191_octet_packets" },
297 { "rx_8192_to_9022_octet_packets" },
304 { "tx_flow_control" },
306 { "tx_single_collisions" },
307 { "tx_mult_collisions" },
309 { "tx_excessive_collisions" },
310 { "tx_late_collisions" },
311 { "tx_collide_2times" },
312 { "tx_collide_3times" },
313 { "tx_collide_4times" },
314 { "tx_collide_5times" },
315 { "tx_collide_6times" },
316 { "tx_collide_7times" },
317 { "tx_collide_8times" },
318 { "tx_collide_9times" },
319 { "tx_collide_10times" },
320 { "tx_collide_11times" },
321 { "tx_collide_12times" },
322 { "tx_collide_13times" },
323 { "tx_collide_14times" },
324 { "tx_collide_15times" },
325 { "tx_ucast_packets" },
326 { "tx_mcast_packets" },
327 { "tx_bcast_packets" },
328 { "tx_carrier_sense_errors" },
332 { "dma_writeq_full" },
333 { "dma_write_prioq_full" },
337 { "rx_threshold_hit" },
339 { "dma_readq_full" },
340 { "dma_read_prioq_full" },
341 { "tx_comp_queue_full" },
343 { "ring_set_send_prod_index" },
344 { "ring_status_update" },
346 { "nic_avoided_irqs" },
347 { "nic_tx_threshold_hit" }
351 const char string[ETH_GSTRING_LEN];
352 } ethtool_test_keys[TG3_NUM_TEST] = {
353 { "nvram test (online) " },
354 { "link test (online) " },
355 { "register test (offline)" },
356 { "memory test (offline)" },
357 { "loopback test (offline)" },
358 { "interrupt test (offline)" },
361 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
363 writel(val, tp->regs + off);
366 static u32 tg3_read32(struct tg3 *tp, u32 off)
368 return (readl(tp->regs + off));
371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
408 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
441 /* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
454 tg3_write32(tp, off, val);
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
468 tp->write32_mbox(tp, off, val);
469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
476 void __iomem *mbox = tp->regs + off;
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
484 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
485 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
486 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
487 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
488 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
490 #define tw32(reg,val) tp->write32(tp, reg, val)
491 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
492 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
493 #define tr32(reg) tp->read32(tp, reg)
495 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
504 /* Always leave this as zero. */
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 tw32_f(TG3PCI_MEM_WIN_DATA, val);
510 /* Always leave this as zero. */
511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
520 spin_lock_irqsave(&tp->indirect_lock, flags);
521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
537 static void tg3_disable_ints(struct tg3 *tp)
539 tw32(TG3PCI_MISC_HOST_CTRL,
540 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
541 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
544 static inline void tg3_cond_int(struct tg3 *tp)
546 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
547 (tp->hw_status->status & SD_STATUS_UPDATED))
548 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
551 static void tg3_enable_ints(struct tg3 *tp)
556 tw32(TG3PCI_MISC_HOST_CTRL,
557 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
558 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
559 (tp->last_tag << 24));
560 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
561 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
562 (tp->last_tag << 24));
566 static inline unsigned int tg3_has_work(struct tg3 *tp)
568 struct tg3_hw_status *sblk = tp->hw_status;
569 unsigned int work_exists = 0;
571 /* check for phy events */
572 if (!(tp->tg3_flags &
573 (TG3_FLAG_USE_LINKCHG_REG |
574 TG3_FLAG_POLL_SERDES))) {
575 if (sblk->status & SD_STATUS_LINK_CHG)
578 /* check for RX/TX work to do */
579 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
580 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
587 * similar to tg3_enable_ints, but it accurately determines whether there
588 * is new work pending and can return without flushing the PIO write
589 * which reenables interrupts
591 static void tg3_restart_ints(struct tg3 *tp)
593 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
597 /* When doing tagged status, this work check is unnecessary.
598 * The last_tag we write above tells the chip which piece of
599 * work we've completed.
601 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
603 tw32(HOSTCC_MODE, tp->coalesce_mode |
604 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
607 static inline void tg3_netif_stop(struct tg3 *tp)
609 tp->dev->trans_start = jiffies; /* prevent tx timeout */
610 netif_poll_disable(tp->dev);
611 netif_tx_disable(tp->dev);
614 static inline void tg3_netif_start(struct tg3 *tp)
616 netif_wake_queue(tp->dev);
617 /* NOTE: unconditional netif_wake_queue is only appropriate
618 * so long as all callers are assured to have free tx slots
619 * (such as after tg3_init_hw)
621 netif_poll_enable(tp->dev);
622 tp->hw_status->status |= SD_STATUS_UPDATED;
626 static void tg3_switch_clocks(struct tg3 *tp)
628 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
631 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
634 orig_clock_ctrl = clock_ctrl;
635 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
636 CLOCK_CTRL_CLKRUN_OENABLE |
638 tp->pci_clock_ctrl = clock_ctrl;
640 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
641 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
642 tw32_wait_f(TG3PCI_CLOCK_CTRL,
643 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
645 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
646 tw32_wait_f(TG3PCI_CLOCK_CTRL,
648 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
650 tw32_wait_f(TG3PCI_CLOCK_CTRL,
651 clock_ctrl | (CLOCK_CTRL_ALTCLK),
654 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
657 #define PHY_BUSY_LOOPS 5000
659 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
665 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
667 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
673 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
674 MI_COM_PHY_ADDR_MASK);
675 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
676 MI_COM_REG_ADDR_MASK);
677 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
679 tw32_f(MAC_MI_COM, frame_val);
681 loops = PHY_BUSY_LOOPS;
684 frame_val = tr32(MAC_MI_COM);
686 if ((frame_val & MI_COM_BUSY) == 0) {
688 frame_val = tr32(MAC_MI_COM);
696 *val = frame_val & MI_COM_DATA_MASK;
700 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
701 tw32_f(MAC_MI_MODE, tp->mi_mode);
708 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
714 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
716 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
720 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
721 MI_COM_PHY_ADDR_MASK);
722 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
723 MI_COM_REG_ADDR_MASK);
724 frame_val |= (val & MI_COM_DATA_MASK);
725 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
727 tw32_f(MAC_MI_COM, frame_val);
729 loops = PHY_BUSY_LOOPS;
732 frame_val = tr32(MAC_MI_COM);
733 if ((frame_val & MI_COM_BUSY) == 0) {
735 frame_val = tr32(MAC_MI_COM);
745 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
746 tw32_f(MAC_MI_MODE, tp->mi_mode);
753 static void tg3_phy_set_wirespeed(struct tg3 *tp)
757 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
760 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
761 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
762 tg3_writephy(tp, MII_TG3_AUX_CTRL,
763 (val | (1 << 15) | (1 << 4)));
766 static int tg3_bmcr_reset(struct tg3 *tp)
771 /* OK, reset it, and poll the BMCR_RESET bit until it
772 * clears or we time out.
774 phy_control = BMCR_RESET;
775 err = tg3_writephy(tp, MII_BMCR, phy_control);
781 err = tg3_readphy(tp, MII_BMCR, &phy_control);
785 if ((phy_control & BMCR_RESET) == 0) {
797 static int tg3_wait_macro_done(struct tg3 *tp)
804 if (!tg3_readphy(tp, 0x16, &tmp32)) {
805 if ((tmp32 & 0x1000) == 0)
815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
817 static const u32 test_pat[4][6] = {
818 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
819 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
820 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
821 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
825 for (chan = 0; chan < 4; chan++) {
828 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
829 (chan * 0x2000) | 0x0200);
830 tg3_writephy(tp, 0x16, 0x0002);
832 for (i = 0; i < 6; i++)
833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
836 tg3_writephy(tp, 0x16, 0x0202);
837 if (tg3_wait_macro_done(tp)) {
842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
843 (chan * 0x2000) | 0x0200);
844 tg3_writephy(tp, 0x16, 0x0082);
845 if (tg3_wait_macro_done(tp)) {
850 tg3_writephy(tp, 0x16, 0x0802);
851 if (tg3_wait_macro_done(tp)) {
856 for (i = 0; i < 6; i += 2) {
859 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
860 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
861 tg3_wait_macro_done(tp)) {
867 if (low != test_pat[chan][i] ||
868 high != test_pat[chan][i+1]) {
869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
871 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
885 for (chan = 0; chan < 4; chan++) {
888 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
889 (chan * 0x2000) | 0x0200);
890 tg3_writephy(tp, 0x16, 0x0002);
891 for (i = 0; i < 6; i++)
892 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
893 tg3_writephy(tp, 0x16, 0x0202);
894 if (tg3_wait_macro_done(tp))
901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
903 u32 reg32, phy9_orig;
904 int retries, do_phy_reset, err;
910 err = tg3_bmcr_reset(tp);
916 /* Disable transmitter and interrupt. */
917 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
921 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
923 /* Set full-duplex, 1000 mbps. */
924 tg3_writephy(tp, MII_BMCR,
925 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
927 /* Set to master mode. */
928 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
931 tg3_writephy(tp, MII_TG3_CTRL,
932 (MII_TG3_CTRL_AS_MASTER |
933 MII_TG3_CTRL_ENABLE_AS_MASTER));
935 /* Enable SM_DSP_CLOCK and 6dB. */
936 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
938 /* Block the PHY control access. */
939 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
940 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
942 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
947 err = tg3_phy_reset_chanpat(tp);
951 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
955 tg3_writephy(tp, 0x16, 0x0000);
957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
959 /* Set Extended packet length bit for jumbo frames */
960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
966 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
968 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
970 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
977 static void tg3_link_report(struct tg3 *);
979 /* This will reset the tigon3 PHY if there is no valid
980 * link unless the FORCE argument is non-zero.
982 static int tg3_phy_reset(struct tg3 *tp)
987 err = tg3_readphy(tp, MII_BMSR, &phy_status);
988 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
992 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
993 netif_carrier_off(tp->dev);
997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1000 err = tg3_phy_reset_5703_4_5(tp);
1006 err = tg3_bmcr_reset(tp);
1011 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1014 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1015 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1016 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1017 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1019 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1020 tg3_writephy(tp, 0x1c, 0x8d68);
1021 tg3_writephy(tp, 0x1c, 0x8d68);
1023 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1024 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1025 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1026 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1027 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1028 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1031 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1033 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1035 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1036 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1037 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1039 /* Set Extended packet length bit (bit 14) on all chips that */
1040 /* support jumbo frames */
1041 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1042 /* Cannot do read-modify-write on 5401 */
1043 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1044 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1047 /* Set bit 14 with read-modify-write to preserve other bits */
1048 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1049 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1050 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1053 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1054 * jumbo frames transmission.
1056 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1059 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1060 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1061 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1064 tg3_phy_set_wirespeed(tp);
1068 static void tg3_frob_aux_power(struct tg3 *tp)
1070 struct tg3 *tp_peer = tp;
1072 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1075 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1076 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1077 struct net_device *dev_peer;
1079 dev_peer = pci_get_drvdata(tp->pdev_peer);
1080 /* remove_one() may have been run on the peer. */
1084 tp_peer = netdev_priv(dev_peer);
1087 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1088 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1089 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094 (GRC_LCLCTRL_GPIO_OE0 |
1095 GRC_LCLCTRL_GPIO_OE1 |
1096 GRC_LCLCTRL_GPIO_OE2 |
1097 GRC_LCLCTRL_GPIO_OUTPUT0 |
1098 GRC_LCLCTRL_GPIO_OUTPUT1),
1102 u32 grc_local_ctrl = 0;
1104 if (tp_peer != tp &&
1105 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1108 /* Workaround to prevent overdrawing Amps. */
1109 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1112 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1113 grc_local_ctrl, 100);
1116 /* On 5753 and variants, GPIO2 cannot be used. */
1117 no_gpio2 = tp->nic_sram_data_cfg &
1118 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1121 GRC_LCLCTRL_GPIO_OE1 |
1122 GRC_LCLCTRL_GPIO_OE2 |
1123 GRC_LCLCTRL_GPIO_OUTPUT1 |
1124 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1127 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1130 grc_local_ctrl, 100);
1132 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1135 grc_local_ctrl, 100);
1138 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 grc_local_ctrl, 100);
1144 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1145 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1146 if (tp_peer != tp &&
1147 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1150 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151 (GRC_LCLCTRL_GPIO_OE1 |
1152 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1155 GRC_LCLCTRL_GPIO_OE1, 100);
1157 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1158 (GRC_LCLCTRL_GPIO_OE1 |
1159 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1164 static int tg3_setup_phy(struct tg3 *, int);
1166 #define RESET_KIND_SHUTDOWN 0
1167 #define RESET_KIND_INIT 1
1168 #define RESET_KIND_SUSPEND 2
1170 static void tg3_write_sig_post_reset(struct tg3 *, int);
1171 static int tg3_halt_cpu(struct tg3 *, u32);
1172 static int tg3_nvram_lock(struct tg3 *);
1173 static void tg3_nvram_unlock(struct tg3 *);
1175 static void tg3_power_down_phy(struct tg3 *tp)
1177 /* The PHY should not be powered down on some chips because
1180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1182 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1183 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1185 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1188 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1191 u16 power_control, power_caps;
1192 int pm = tp->pm_cap;
1194 /* Make sure register accesses (indirect or otherwise)
1195 * will function correctly.
1197 pci_write_config_dword(tp->pdev,
1198 TG3PCI_MISC_HOST_CTRL,
1199 tp->misc_host_ctrl);
1201 pci_read_config_word(tp->pdev,
1204 power_control |= PCI_PM_CTRL_PME_STATUS;
1205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1209 pci_write_config_word(tp->pdev,
1212 udelay(100); /* Delay after power state change */
1214 /* Switch out of Vaux if it is not a LOM */
1215 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1216 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1233 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1235 tp->dev->name, state);
1239 power_control |= PCI_PM_CTRL_PME_ENABLE;
1241 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1242 tw32(TG3PCI_MISC_HOST_CTRL,
1243 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1245 if (tp->link_config.phy_is_low_power == 0) {
1246 tp->link_config.phy_is_low_power = 1;
1247 tp->link_config.orig_speed = tp->link_config.speed;
1248 tp->link_config.orig_duplex = tp->link_config.duplex;
1249 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1252 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1253 tp->link_config.speed = SPEED_10;
1254 tp->link_config.duplex = DUPLEX_HALF;
1255 tp->link_config.autoneg = AUTONEG_ENABLE;
1256 tg3_setup_phy(tp, 0);
1259 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1263 for (i = 0; i < 200; i++) {
1264 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1265 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1270 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1271 WOL_DRV_STATE_SHUTDOWN |
1272 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1274 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1276 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1279 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1280 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1283 mac_mode = MAC_MODE_PORT_MODE_MII;
1285 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1286 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1287 mac_mode |= MAC_MODE_LINK_POLARITY;
1289 mac_mode = MAC_MODE_PORT_MODE_TBI;
1292 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1293 tw32(MAC_LED_CTRL, tp->led_ctrl);
1295 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1296 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1297 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1299 tw32_f(MAC_MODE, mac_mode);
1302 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1306 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1307 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1311 base_val = tp->pci_clock_ctrl;
1312 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1313 CLOCK_CTRL_TXCLK_DISABLE);
1315 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1316 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1317 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1319 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1320 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1321 u32 newbits1, newbits2;
1323 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1325 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1326 CLOCK_CTRL_TXCLK_DISABLE |
1328 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1329 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1330 newbits1 = CLOCK_CTRL_625_CORE;
1331 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1333 newbits1 = CLOCK_CTRL_ALTCLK;
1334 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1337 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1340 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1343 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1346 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1347 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1348 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1349 CLOCK_CTRL_TXCLK_DISABLE |
1350 CLOCK_CTRL_44MHZ_CORE);
1352 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1355 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1356 tp->pci_clock_ctrl | newbits3, 40);
1360 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1361 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1362 /* Turn off the PHY */
1363 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1364 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1365 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1366 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1367 tg3_power_down_phy(tp);
1371 tg3_frob_aux_power(tp);
1373 /* Workaround for unstable PLL clock */
1374 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1375 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1376 u32 val = tr32(0x7d00);
1378 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1380 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1383 err = tg3_nvram_lock(tp);
1384 tg3_halt_cpu(tp, RX_CPU_BASE);
1386 tg3_nvram_unlock(tp);
1390 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1392 /* Finally, set the new power state. */
1393 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1394 udelay(100); /* Delay after power state change */
1399 static void tg3_link_report(struct tg3 *tp)
1401 if (!netif_carrier_ok(tp->dev)) {
1402 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1404 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1406 (tp->link_config.active_speed == SPEED_1000 ?
1408 (tp->link_config.active_speed == SPEED_100 ?
1410 (tp->link_config.active_duplex == DUPLEX_FULL ?
1413 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1416 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1417 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1421 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1423 u32 new_tg3_flags = 0;
1424 u32 old_rx_mode = tp->rx_mode;
1425 u32 old_tx_mode = tp->tx_mode;
1427 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1429 /* Convert 1000BaseX flow control bits to 1000BaseT
1430 * bits before resolving flow control.
1432 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1433 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1434 ADVERTISE_PAUSE_ASYM);
1435 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1437 if (local_adv & ADVERTISE_1000XPAUSE)
1438 local_adv |= ADVERTISE_PAUSE_CAP;
1439 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1440 local_adv |= ADVERTISE_PAUSE_ASYM;
1441 if (remote_adv & LPA_1000XPAUSE)
1442 remote_adv |= LPA_PAUSE_CAP;
1443 if (remote_adv & LPA_1000XPAUSE_ASYM)
1444 remote_adv |= LPA_PAUSE_ASYM;
1447 if (local_adv & ADVERTISE_PAUSE_CAP) {
1448 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1449 if (remote_adv & LPA_PAUSE_CAP)
1451 (TG3_FLAG_RX_PAUSE |
1453 else if (remote_adv & LPA_PAUSE_ASYM)
1455 (TG3_FLAG_RX_PAUSE);
1457 if (remote_adv & LPA_PAUSE_CAP)
1459 (TG3_FLAG_RX_PAUSE |
1462 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1463 if ((remote_adv & LPA_PAUSE_CAP) &&
1464 (remote_adv & LPA_PAUSE_ASYM))
1465 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1468 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1469 tp->tg3_flags |= new_tg3_flags;
1471 new_tg3_flags = tp->tg3_flags;
1474 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1475 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1477 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1479 if (old_rx_mode != tp->rx_mode) {
1480 tw32_f(MAC_RX_MODE, tp->rx_mode);
1483 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1484 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1486 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1488 if (old_tx_mode != tp->tx_mode) {
1489 tw32_f(MAC_TX_MODE, tp->tx_mode);
1493 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1495 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1496 case MII_TG3_AUX_STAT_10HALF:
1498 *duplex = DUPLEX_HALF;
1501 case MII_TG3_AUX_STAT_10FULL:
1503 *duplex = DUPLEX_FULL;
1506 case MII_TG3_AUX_STAT_100HALF:
1508 *duplex = DUPLEX_HALF;
1511 case MII_TG3_AUX_STAT_100FULL:
1513 *duplex = DUPLEX_FULL;
1516 case MII_TG3_AUX_STAT_1000HALF:
1517 *speed = SPEED_1000;
1518 *duplex = DUPLEX_HALF;
1521 case MII_TG3_AUX_STAT_1000FULL:
1522 *speed = SPEED_1000;
1523 *duplex = DUPLEX_FULL;
1527 *speed = SPEED_INVALID;
1528 *duplex = DUPLEX_INVALID;
1533 static void tg3_phy_copper_begin(struct tg3 *tp)
1538 if (tp->link_config.phy_is_low_power) {
1539 /* Entering low power mode. Disable gigabit and
1540 * 100baseT advertisements.
1542 tg3_writephy(tp, MII_TG3_CTRL, 0);
1544 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1545 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1546 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1547 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1549 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1550 } else if (tp->link_config.speed == SPEED_INVALID) {
1551 tp->link_config.advertising =
1552 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1553 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1554 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1555 ADVERTISED_Autoneg | ADVERTISED_MII);
1557 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1558 tp->link_config.advertising &=
1559 ~(ADVERTISED_1000baseT_Half |
1560 ADVERTISED_1000baseT_Full);
1562 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1563 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1564 new_adv |= ADVERTISE_10HALF;
1565 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1566 new_adv |= ADVERTISE_10FULL;
1567 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1568 new_adv |= ADVERTISE_100HALF;
1569 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1570 new_adv |= ADVERTISE_100FULL;
1571 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1573 if (tp->link_config.advertising &
1574 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1576 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1577 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1578 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1579 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1580 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1581 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1582 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1583 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1584 MII_TG3_CTRL_ENABLE_AS_MASTER);
1585 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1587 tg3_writephy(tp, MII_TG3_CTRL, 0);
1590 /* Asking for a specific link mode. */
1591 if (tp->link_config.speed == SPEED_1000) {
1592 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1593 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1595 if (tp->link_config.duplex == DUPLEX_FULL)
1596 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1598 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1599 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1600 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1601 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1602 MII_TG3_CTRL_ENABLE_AS_MASTER);
1603 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1605 tg3_writephy(tp, MII_TG3_CTRL, 0);
1607 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1608 if (tp->link_config.speed == SPEED_100) {
1609 if (tp->link_config.duplex == DUPLEX_FULL)
1610 new_adv |= ADVERTISE_100FULL;
1612 new_adv |= ADVERTISE_100HALF;
1614 if (tp->link_config.duplex == DUPLEX_FULL)
1615 new_adv |= ADVERTISE_10FULL;
1617 new_adv |= ADVERTISE_10HALF;
1619 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1623 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1624 tp->link_config.speed != SPEED_INVALID) {
1625 u32 bmcr, orig_bmcr;
1627 tp->link_config.active_speed = tp->link_config.speed;
1628 tp->link_config.active_duplex = tp->link_config.duplex;
1631 switch (tp->link_config.speed) {
1637 bmcr |= BMCR_SPEED100;
1641 bmcr |= TG3_BMCR_SPEED1000;
1645 if (tp->link_config.duplex == DUPLEX_FULL)
1646 bmcr |= BMCR_FULLDPLX;
1648 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1649 (bmcr != orig_bmcr)) {
1650 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1651 for (i = 0; i < 1500; i++) {
1655 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1656 tg3_readphy(tp, MII_BMSR, &tmp))
1658 if (!(tmp & BMSR_LSTATUS)) {
1663 tg3_writephy(tp, MII_BMCR, bmcr);
1667 tg3_writephy(tp, MII_BMCR,
1668 BMCR_ANENABLE | BMCR_ANRESTART);
1672 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1676 /* Turn off tap power management. */
1677 /* Set Extended packet length bit */
1678 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1680 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1681 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1683 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1684 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1686 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1687 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1689 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1690 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1692 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1693 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1700 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1702 u32 adv_reg, all_mask;
1704 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1707 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1708 ADVERTISE_100HALF | ADVERTISE_100FULL);
1709 if ((adv_reg & all_mask) != all_mask)
1711 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1714 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1717 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1718 MII_TG3_CTRL_ADV_1000_FULL);
1719 if ((tg3_ctrl & all_mask) != all_mask)
1725 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1727 int current_link_up;
1736 (MAC_STATUS_SYNC_CHANGED |
1737 MAC_STATUS_CFG_CHANGED |
1738 MAC_STATUS_MI_COMPLETION |
1739 MAC_STATUS_LNKSTATE_CHANGED));
1742 tp->mi_mode = MAC_MI_MODE_BASE;
1743 tw32_f(MAC_MI_MODE, tp->mi_mode);
1746 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1748 /* Some third-party PHYs need to be reset on link going
1751 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1752 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1753 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1754 netif_carrier_ok(tp->dev)) {
1755 tg3_readphy(tp, MII_BMSR, &bmsr);
1756 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1757 !(bmsr & BMSR_LSTATUS))
1763 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1764 tg3_readphy(tp, MII_BMSR, &bmsr);
1765 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1766 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1769 if (!(bmsr & BMSR_LSTATUS)) {
1770 err = tg3_init_5401phy_dsp(tp);
1774 tg3_readphy(tp, MII_BMSR, &bmsr);
1775 for (i = 0; i < 1000; i++) {
1777 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1778 (bmsr & BMSR_LSTATUS)) {
1784 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1785 !(bmsr & BMSR_LSTATUS) &&
1786 tp->link_config.active_speed == SPEED_1000) {
1787 err = tg3_phy_reset(tp);
1789 err = tg3_init_5401phy_dsp(tp);
1794 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1795 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1796 /* 5701 {A0,B0} CRC bug workaround */
1797 tg3_writephy(tp, 0x15, 0x0a75);
1798 tg3_writephy(tp, 0x1c, 0x8c68);
1799 tg3_writephy(tp, 0x1c, 0x8d68);
1800 tg3_writephy(tp, 0x1c, 0x8c68);
1803 /* Clear pending interrupts... */
1804 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1805 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1807 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1808 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1810 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1814 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1815 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1816 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1818 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1821 current_link_up = 0;
1822 current_speed = SPEED_INVALID;
1823 current_duplex = DUPLEX_INVALID;
1825 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1828 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1829 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1830 if (!(val & (1 << 10))) {
1832 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1838 for (i = 0; i < 100; i++) {
1839 tg3_readphy(tp, MII_BMSR, &bmsr);
1840 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1841 (bmsr & BMSR_LSTATUS))
1846 if (bmsr & BMSR_LSTATUS) {
1849 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1850 for (i = 0; i < 2000; i++) {
1852 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1857 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1862 for (i = 0; i < 200; i++) {
1863 tg3_readphy(tp, MII_BMCR, &bmcr);
1864 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1866 if (bmcr && bmcr != 0x7fff)
1871 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1872 if (bmcr & BMCR_ANENABLE) {
1873 current_link_up = 1;
1875 /* Force autoneg restart if we are exiting
1878 if (!tg3_copper_is_advertising_all(tp))
1879 current_link_up = 0;
1881 current_link_up = 0;
1884 if (!(bmcr & BMCR_ANENABLE) &&
1885 tp->link_config.speed == current_speed &&
1886 tp->link_config.duplex == current_duplex) {
1887 current_link_up = 1;
1889 current_link_up = 0;
1893 tp->link_config.active_speed = current_speed;
1894 tp->link_config.active_duplex = current_duplex;
1897 if (current_link_up == 1 &&
1898 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1899 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1900 u32 local_adv, remote_adv;
1902 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1904 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1906 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1909 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1911 /* If we are not advertising full pause capability,
1912 * something is wrong. Bring the link down and reconfigure.
1914 if (local_adv != ADVERTISE_PAUSE_CAP) {
1915 current_link_up = 0;
1917 tg3_setup_flow_control(tp, local_adv, remote_adv);
1921 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1924 tg3_phy_copper_begin(tp);
1926 tg3_readphy(tp, MII_BMSR, &tmp);
1927 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1928 (tmp & BMSR_LSTATUS))
1929 current_link_up = 1;
1932 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1933 if (current_link_up == 1) {
1934 if (tp->link_config.active_speed == SPEED_100 ||
1935 tp->link_config.active_speed == SPEED_10)
1936 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1938 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1940 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1942 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1943 if (tp->link_config.active_duplex == DUPLEX_HALF)
1944 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1946 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1948 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1949 (current_link_up == 1 &&
1950 tp->link_config.active_speed == SPEED_10))
1951 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1953 if (current_link_up == 1)
1954 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1957 /* ??? Without this setting Netgear GA302T PHY does not
1958 * ??? send/receive packets...
1960 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1961 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1962 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1963 tw32_f(MAC_MI_MODE, tp->mi_mode);
1967 tw32_f(MAC_MODE, tp->mac_mode);
1970 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1971 /* Polled via timer. */
1972 tw32_f(MAC_EVENT, 0);
1974 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1978 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1979 current_link_up == 1 &&
1980 tp->link_config.active_speed == SPEED_1000 &&
1981 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1982 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1985 (MAC_STATUS_SYNC_CHANGED |
1986 MAC_STATUS_CFG_CHANGED));
1989 NIC_SRAM_FIRMWARE_MBOX,
1990 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1993 if (current_link_up != netif_carrier_ok(tp->dev)) {
1994 if (current_link_up)
1995 netif_carrier_on(tp->dev);
1997 netif_carrier_off(tp->dev);
1998 tg3_link_report(tp);
2004 struct tg3_fiber_aneginfo {
2006 #define ANEG_STATE_UNKNOWN 0
2007 #define ANEG_STATE_AN_ENABLE 1
2008 #define ANEG_STATE_RESTART_INIT 2
2009 #define ANEG_STATE_RESTART 3
2010 #define ANEG_STATE_DISABLE_LINK_OK 4
2011 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2012 #define ANEG_STATE_ABILITY_DETECT 6
2013 #define ANEG_STATE_ACK_DETECT_INIT 7
2014 #define ANEG_STATE_ACK_DETECT 8
2015 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2016 #define ANEG_STATE_COMPLETE_ACK 10
2017 #define ANEG_STATE_IDLE_DETECT_INIT 11
2018 #define ANEG_STATE_IDLE_DETECT 12
2019 #define ANEG_STATE_LINK_OK 13
2020 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2021 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2024 #define MR_AN_ENABLE 0x00000001
2025 #define MR_RESTART_AN 0x00000002
2026 #define MR_AN_COMPLETE 0x00000004
2027 #define MR_PAGE_RX 0x00000008
2028 #define MR_NP_LOADED 0x00000010
2029 #define MR_TOGGLE_TX 0x00000020
2030 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2031 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2032 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2033 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2034 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2035 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2036 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2037 #define MR_TOGGLE_RX 0x00002000
2038 #define MR_NP_RX 0x00004000
2040 #define MR_LINK_OK 0x80000000
2042 unsigned long link_time, cur_time;
2044 u32 ability_match_cfg;
2045 int ability_match_count;
2047 char ability_match, idle_match, ack_match;
2049 u32 txconfig, rxconfig;
2050 #define ANEG_CFG_NP 0x00000080
2051 #define ANEG_CFG_ACK 0x00000040
2052 #define ANEG_CFG_RF2 0x00000020
2053 #define ANEG_CFG_RF1 0x00000010
2054 #define ANEG_CFG_PS2 0x00000001
2055 #define ANEG_CFG_PS1 0x00008000
2056 #define ANEG_CFG_HD 0x00004000
2057 #define ANEG_CFG_FD 0x00002000
2058 #define ANEG_CFG_INVAL 0x00001f06
2063 #define ANEG_TIMER_ENAB 2
2064 #define ANEG_FAILED -1
2066 #define ANEG_STATE_SETTLE_TIME 10000
2068 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2069 struct tg3_fiber_aneginfo *ap)
2071 unsigned long delta;
2075 if (ap->state == ANEG_STATE_UNKNOWN) {
2079 ap->ability_match_cfg = 0;
2080 ap->ability_match_count = 0;
2081 ap->ability_match = 0;
2087 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2088 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2090 if (rx_cfg_reg != ap->ability_match_cfg) {
2091 ap->ability_match_cfg = rx_cfg_reg;
2092 ap->ability_match = 0;
2093 ap->ability_match_count = 0;
2095 if (++ap->ability_match_count > 1) {
2096 ap->ability_match = 1;
2097 ap->ability_match_cfg = rx_cfg_reg;
2100 if (rx_cfg_reg & ANEG_CFG_ACK)
2108 ap->ability_match_cfg = 0;
2109 ap->ability_match_count = 0;
2110 ap->ability_match = 0;
2116 ap->rxconfig = rx_cfg_reg;
2120 case ANEG_STATE_UNKNOWN:
2121 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2122 ap->state = ANEG_STATE_AN_ENABLE;
2125 case ANEG_STATE_AN_ENABLE:
2126 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2127 if (ap->flags & MR_AN_ENABLE) {
2130 ap->ability_match_cfg = 0;
2131 ap->ability_match_count = 0;
2132 ap->ability_match = 0;
2136 ap->state = ANEG_STATE_RESTART_INIT;
2138 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2142 case ANEG_STATE_RESTART_INIT:
2143 ap->link_time = ap->cur_time;
2144 ap->flags &= ~(MR_NP_LOADED);
2146 tw32(MAC_TX_AUTO_NEG, 0);
2147 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2148 tw32_f(MAC_MODE, tp->mac_mode);
2151 ret = ANEG_TIMER_ENAB;
2152 ap->state = ANEG_STATE_RESTART;
2155 case ANEG_STATE_RESTART:
2156 delta = ap->cur_time - ap->link_time;
2157 if (delta > ANEG_STATE_SETTLE_TIME) {
2158 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2160 ret = ANEG_TIMER_ENAB;
2164 case ANEG_STATE_DISABLE_LINK_OK:
2168 case ANEG_STATE_ABILITY_DETECT_INIT:
2169 ap->flags &= ~(MR_TOGGLE_TX);
2170 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2171 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2172 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2173 tw32_f(MAC_MODE, tp->mac_mode);
2176 ap->state = ANEG_STATE_ABILITY_DETECT;
2179 case ANEG_STATE_ABILITY_DETECT:
2180 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2181 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2185 case ANEG_STATE_ACK_DETECT_INIT:
2186 ap->txconfig |= ANEG_CFG_ACK;
2187 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2188 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2189 tw32_f(MAC_MODE, tp->mac_mode);
2192 ap->state = ANEG_STATE_ACK_DETECT;
2195 case ANEG_STATE_ACK_DETECT:
2196 if (ap->ack_match != 0) {
2197 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2198 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2199 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2201 ap->state = ANEG_STATE_AN_ENABLE;
2203 } else if (ap->ability_match != 0 &&
2204 ap->rxconfig == 0) {
2205 ap->state = ANEG_STATE_AN_ENABLE;
2209 case ANEG_STATE_COMPLETE_ACK_INIT:
2210 if (ap->rxconfig & ANEG_CFG_INVAL) {
2214 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2215 MR_LP_ADV_HALF_DUPLEX |
2216 MR_LP_ADV_SYM_PAUSE |
2217 MR_LP_ADV_ASYM_PAUSE |
2218 MR_LP_ADV_REMOTE_FAULT1 |
2219 MR_LP_ADV_REMOTE_FAULT2 |
2220 MR_LP_ADV_NEXT_PAGE |
2223 if (ap->rxconfig & ANEG_CFG_FD)
2224 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2225 if (ap->rxconfig & ANEG_CFG_HD)
2226 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2227 if (ap->rxconfig & ANEG_CFG_PS1)
2228 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2229 if (ap->rxconfig & ANEG_CFG_PS2)
2230 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2231 if (ap->rxconfig & ANEG_CFG_RF1)
2232 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2233 if (ap->rxconfig & ANEG_CFG_RF2)
2234 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2235 if (ap->rxconfig & ANEG_CFG_NP)
2236 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2238 ap->link_time = ap->cur_time;
2240 ap->flags ^= (MR_TOGGLE_TX);
2241 if (ap->rxconfig & 0x0008)
2242 ap->flags |= MR_TOGGLE_RX;
2243 if (ap->rxconfig & ANEG_CFG_NP)
2244 ap->flags |= MR_NP_RX;
2245 ap->flags |= MR_PAGE_RX;
2247 ap->state = ANEG_STATE_COMPLETE_ACK;
2248 ret = ANEG_TIMER_ENAB;
2251 case ANEG_STATE_COMPLETE_ACK:
2252 if (ap->ability_match != 0 &&
2253 ap->rxconfig == 0) {
2254 ap->state = ANEG_STATE_AN_ENABLE;
2257 delta = ap->cur_time - ap->link_time;
2258 if (delta > ANEG_STATE_SETTLE_TIME) {
2259 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2260 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2262 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2263 !(ap->flags & MR_NP_RX)) {
2264 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2272 case ANEG_STATE_IDLE_DETECT_INIT:
2273 ap->link_time = ap->cur_time;
2274 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2275 tw32_f(MAC_MODE, tp->mac_mode);
2278 ap->state = ANEG_STATE_IDLE_DETECT;
2279 ret = ANEG_TIMER_ENAB;
2282 case ANEG_STATE_IDLE_DETECT:
2283 if (ap->ability_match != 0 &&
2284 ap->rxconfig == 0) {
2285 ap->state = ANEG_STATE_AN_ENABLE;
2288 delta = ap->cur_time - ap->link_time;
2289 if (delta > ANEG_STATE_SETTLE_TIME) {
2290 /* XXX another gem from the Broadcom driver :( */
2291 ap->state = ANEG_STATE_LINK_OK;
2295 case ANEG_STATE_LINK_OK:
2296 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2300 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2301 /* ??? unimplemented */
2304 case ANEG_STATE_NEXT_PAGE_WAIT:
2305 /* ??? unimplemented */
2316 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2319 struct tg3_fiber_aneginfo aninfo;
2320 int status = ANEG_FAILED;
2324 tw32_f(MAC_TX_AUTO_NEG, 0);
2326 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2327 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2330 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2333 memset(&aninfo, 0, sizeof(aninfo));
2334 aninfo.flags |= MR_AN_ENABLE;
2335 aninfo.state = ANEG_STATE_UNKNOWN;
2336 aninfo.cur_time = 0;
2338 while (++tick < 195000) {
2339 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2340 if (status == ANEG_DONE || status == ANEG_FAILED)
2346 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2347 tw32_f(MAC_MODE, tp->mac_mode);
2350 *flags = aninfo.flags;
2352 if (status == ANEG_DONE &&
2353 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2354 MR_LP_ADV_FULL_DUPLEX)))
2360 static void tg3_init_bcm8002(struct tg3 *tp)
2362 u32 mac_status = tr32(MAC_STATUS);
2365 /* Reset when initting first time or we have a link. */
2366 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2367 !(mac_status & MAC_STATUS_PCS_SYNCED))
2370 /* Set PLL lock range. */
2371 tg3_writephy(tp, 0x16, 0x8007);
2374 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2376 /* Wait for reset to complete. */
2377 /* XXX schedule_timeout() ... */
2378 for (i = 0; i < 500; i++)
2381 /* Config mode; select PMA/Ch 1 regs. */
2382 tg3_writephy(tp, 0x10, 0x8411);
2384 /* Enable auto-lock and comdet, select txclk for tx. */
2385 tg3_writephy(tp, 0x11, 0x0a10);
2387 tg3_writephy(tp, 0x18, 0x00a0);
2388 tg3_writephy(tp, 0x16, 0x41ff);
2390 /* Assert and deassert POR. */
2391 tg3_writephy(tp, 0x13, 0x0400);
2393 tg3_writephy(tp, 0x13, 0x0000);
2395 tg3_writephy(tp, 0x11, 0x0a50);
2397 tg3_writephy(tp, 0x11, 0x0a10);
2399 /* Wait for signal to stabilize */
2400 /* XXX schedule_timeout() ... */
2401 for (i = 0; i < 15000; i++)
2404 /* Deselect the channel register so we can read the PHYID
2407 tg3_writephy(tp, 0x10, 0x8011);
2410 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2412 u32 sg_dig_ctrl, sg_dig_status;
2413 u32 serdes_cfg, expected_sg_dig_ctrl;
2414 int workaround, port_a;
2415 int current_link_up;
2418 expected_sg_dig_ctrl = 0;
2421 current_link_up = 0;
2423 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2424 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2426 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2429 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2430 /* preserve bits 20-23 for voltage regulator */
2431 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2434 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2436 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2437 if (sg_dig_ctrl & (1 << 31)) {
2439 u32 val = serdes_cfg;
2445 tw32_f(MAC_SERDES_CFG, val);
2447 tw32_f(SG_DIG_CTRL, 0x01388400);
2449 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2450 tg3_setup_flow_control(tp, 0, 0);
2451 current_link_up = 1;
2456 /* Want auto-negotiation. */
2457 expected_sg_dig_ctrl = 0x81388400;
2459 /* Pause capability */
2460 expected_sg_dig_ctrl |= (1 << 11);
2462 /* Asymettric pause */
2463 expected_sg_dig_ctrl |= (1 << 12);
2465 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2467 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2468 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2470 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2472 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2473 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2474 MAC_STATUS_SIGNAL_DET)) {
2477 /* Giver time to negotiate (~200ms) */
2478 for (i = 0; i < 40000; i++) {
2479 sg_dig_status = tr32(SG_DIG_STATUS);
2480 if (sg_dig_status & (0x3))
2484 mac_status = tr32(MAC_STATUS);
2486 if ((sg_dig_status & (1 << 1)) &&
2487 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2488 u32 local_adv, remote_adv;
2490 local_adv = ADVERTISE_PAUSE_CAP;
2492 if (sg_dig_status & (1 << 19))
2493 remote_adv |= LPA_PAUSE_CAP;
2494 if (sg_dig_status & (1 << 20))
2495 remote_adv |= LPA_PAUSE_ASYM;
2497 tg3_setup_flow_control(tp, local_adv, remote_adv);
2498 current_link_up = 1;
2499 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2500 } else if (!(sg_dig_status & (1 << 1))) {
2501 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2502 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2505 u32 val = serdes_cfg;
2512 tw32_f(MAC_SERDES_CFG, val);
2515 tw32_f(SG_DIG_CTRL, 0x01388400);
2518 /* Link parallel detection - link is up */
2519 /* only if we have PCS_SYNC and not */
2520 /* receiving config code words */
2521 mac_status = tr32(MAC_STATUS);
2522 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2523 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2524 tg3_setup_flow_control(tp, 0, 0);
2525 current_link_up = 1;
2532 return current_link_up;
2535 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2537 int current_link_up = 0;
2539 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2540 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2544 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2548 if (fiber_autoneg(tp, &flags)) {
2549 u32 local_adv, remote_adv;
2551 local_adv = ADVERTISE_PAUSE_CAP;
2553 if (flags & MR_LP_ADV_SYM_PAUSE)
2554 remote_adv |= LPA_PAUSE_CAP;
2555 if (flags & MR_LP_ADV_ASYM_PAUSE)
2556 remote_adv |= LPA_PAUSE_ASYM;
2558 tg3_setup_flow_control(tp, local_adv, remote_adv);
2560 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2561 current_link_up = 1;
2563 for (i = 0; i < 30; i++) {
2566 (MAC_STATUS_SYNC_CHANGED |
2567 MAC_STATUS_CFG_CHANGED));
2569 if ((tr32(MAC_STATUS) &
2570 (MAC_STATUS_SYNC_CHANGED |
2571 MAC_STATUS_CFG_CHANGED)) == 0)
2575 mac_status = tr32(MAC_STATUS);
2576 if (current_link_up == 0 &&
2577 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2578 !(mac_status & MAC_STATUS_RCVD_CFG))
2579 current_link_up = 1;
2581 /* Forcing 1000FD link up. */
2582 current_link_up = 1;
2583 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2585 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2590 return current_link_up;
2593 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2596 u16 orig_active_speed;
2597 u8 orig_active_duplex;
2599 int current_link_up;
2603 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2604 TG3_FLAG_TX_PAUSE));
2605 orig_active_speed = tp->link_config.active_speed;
2606 orig_active_duplex = tp->link_config.active_duplex;
2608 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2609 netif_carrier_ok(tp->dev) &&
2610 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2611 mac_status = tr32(MAC_STATUS);
2612 mac_status &= (MAC_STATUS_PCS_SYNCED |
2613 MAC_STATUS_SIGNAL_DET |
2614 MAC_STATUS_CFG_CHANGED |
2615 MAC_STATUS_RCVD_CFG);
2616 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2617 MAC_STATUS_SIGNAL_DET)) {
2618 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2619 MAC_STATUS_CFG_CHANGED));
2624 tw32_f(MAC_TX_AUTO_NEG, 0);
2626 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2627 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2628 tw32_f(MAC_MODE, tp->mac_mode);
2631 if (tp->phy_id == PHY_ID_BCM8002)
2632 tg3_init_bcm8002(tp);
2634 /* Enable link change event even when serdes polling. */
2635 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2638 current_link_up = 0;
2639 mac_status = tr32(MAC_STATUS);
2641 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2642 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2644 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2646 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2647 tw32_f(MAC_MODE, tp->mac_mode);
2650 tp->hw_status->status =
2651 (SD_STATUS_UPDATED |
2652 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2654 for (i = 0; i < 100; i++) {
2655 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2656 MAC_STATUS_CFG_CHANGED));
2658 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2659 MAC_STATUS_CFG_CHANGED)) == 0)
2663 mac_status = tr32(MAC_STATUS);
2664 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2665 current_link_up = 0;
2666 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2667 tw32_f(MAC_MODE, (tp->mac_mode |
2668 MAC_MODE_SEND_CONFIGS));
2670 tw32_f(MAC_MODE, tp->mac_mode);
2674 if (current_link_up == 1) {
2675 tp->link_config.active_speed = SPEED_1000;
2676 tp->link_config.active_duplex = DUPLEX_FULL;
2677 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2678 LED_CTRL_LNKLED_OVERRIDE |
2679 LED_CTRL_1000MBPS_ON));
2681 tp->link_config.active_speed = SPEED_INVALID;
2682 tp->link_config.active_duplex = DUPLEX_INVALID;
2683 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2684 LED_CTRL_LNKLED_OVERRIDE |
2685 LED_CTRL_TRAFFIC_OVERRIDE));
2688 if (current_link_up != netif_carrier_ok(tp->dev)) {
2689 if (current_link_up)
2690 netif_carrier_on(tp->dev);
2692 netif_carrier_off(tp->dev);
2693 tg3_link_report(tp);
2696 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2698 if (orig_pause_cfg != now_pause_cfg ||
2699 orig_active_speed != tp->link_config.active_speed ||
2700 orig_active_duplex != tp->link_config.active_duplex)
2701 tg3_link_report(tp);
2707 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2709 int current_link_up, err = 0;
2714 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2715 tw32_f(MAC_MODE, tp->mac_mode);
2721 (MAC_STATUS_SYNC_CHANGED |
2722 MAC_STATUS_CFG_CHANGED |
2723 MAC_STATUS_MI_COMPLETION |
2724 MAC_STATUS_LNKSTATE_CHANGED));
2730 current_link_up = 0;
2731 current_speed = SPEED_INVALID;
2732 current_duplex = DUPLEX_INVALID;
2734 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2735 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2736 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2737 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2738 bmsr |= BMSR_LSTATUS;
2740 bmsr &= ~BMSR_LSTATUS;
2743 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2745 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2746 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2747 /* do nothing, just check for link up at the end */
2748 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2751 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2752 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2753 ADVERTISE_1000XPAUSE |
2754 ADVERTISE_1000XPSE_ASYM |
2757 /* Always advertise symmetric PAUSE just like copper */
2758 new_adv |= ADVERTISE_1000XPAUSE;
2760 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2761 new_adv |= ADVERTISE_1000XHALF;
2762 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2763 new_adv |= ADVERTISE_1000XFULL;
2765 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2766 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2767 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2768 tg3_writephy(tp, MII_BMCR, bmcr);
2770 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2771 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2772 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2779 bmcr &= ~BMCR_SPEED1000;
2780 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2782 if (tp->link_config.duplex == DUPLEX_FULL)
2783 new_bmcr |= BMCR_FULLDPLX;
2785 if (new_bmcr != bmcr) {
2786 /* BMCR_SPEED1000 is a reserved bit that needs
2787 * to be set on write.
2789 new_bmcr |= BMCR_SPEED1000;
2791 /* Force a linkdown */
2792 if (netif_carrier_ok(tp->dev)) {
2795 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2796 adv &= ~(ADVERTISE_1000XFULL |
2797 ADVERTISE_1000XHALF |
2799 tg3_writephy(tp, MII_ADVERTISE, adv);
2800 tg3_writephy(tp, MII_BMCR, bmcr |
2804 netif_carrier_off(tp->dev);
2806 tg3_writephy(tp, MII_BMCR, new_bmcr);
2808 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2809 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2810 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2812 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2813 bmsr |= BMSR_LSTATUS;
2815 bmsr &= ~BMSR_LSTATUS;
2817 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2821 if (bmsr & BMSR_LSTATUS) {
2822 current_speed = SPEED_1000;
2823 current_link_up = 1;
2824 if (bmcr & BMCR_FULLDPLX)
2825 current_duplex = DUPLEX_FULL;
2827 current_duplex = DUPLEX_HALF;
2829 if (bmcr & BMCR_ANENABLE) {
2830 u32 local_adv, remote_adv, common;
2832 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2833 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2834 common = local_adv & remote_adv;
2835 if (common & (ADVERTISE_1000XHALF |
2836 ADVERTISE_1000XFULL)) {
2837 if (common & ADVERTISE_1000XFULL)
2838 current_duplex = DUPLEX_FULL;
2840 current_duplex = DUPLEX_HALF;
2842 tg3_setup_flow_control(tp, local_adv,
2846 current_link_up = 0;
2850 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2851 if (tp->link_config.active_duplex == DUPLEX_HALF)
2852 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2854 tw32_f(MAC_MODE, tp->mac_mode);
2857 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2859 tp->link_config.active_speed = current_speed;
2860 tp->link_config.active_duplex = current_duplex;
2862 if (current_link_up != netif_carrier_ok(tp->dev)) {
2863 if (current_link_up)
2864 netif_carrier_on(tp->dev);
2866 netif_carrier_off(tp->dev);
2867 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2869 tg3_link_report(tp);
2874 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2876 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2877 /* Give autoneg time to complete. */
2878 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2881 if (!netif_carrier_ok(tp->dev) &&
2882 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2885 tg3_readphy(tp, MII_BMCR, &bmcr);
2886 if (bmcr & BMCR_ANENABLE) {
2889 /* Select shadow register 0x1f */
2890 tg3_writephy(tp, 0x1c, 0x7c00);
2891 tg3_readphy(tp, 0x1c, &phy1);
2893 /* Select expansion interrupt status register */
2894 tg3_writephy(tp, 0x17, 0x0f01);
2895 tg3_readphy(tp, 0x15, &phy2);
2896 tg3_readphy(tp, 0x15, &phy2);
2898 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2899 /* We have signal detect and not receiving
2900 * config code words, link is up by parallel
2904 bmcr &= ~BMCR_ANENABLE;
2905 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2906 tg3_writephy(tp, MII_BMCR, bmcr);
2907 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2911 else if (netif_carrier_ok(tp->dev) &&
2912 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2913 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2916 /* Select expansion interrupt status register */
2917 tg3_writephy(tp, 0x17, 0x0f01);
2918 tg3_readphy(tp, 0x15, &phy2);
2922 /* Config code words received, turn on autoneg. */
2923 tg3_readphy(tp, MII_BMCR, &bmcr);
2924 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2926 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2932 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2936 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2937 err = tg3_setup_fiber_phy(tp, force_reset);
2938 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2939 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2941 err = tg3_setup_copper_phy(tp, force_reset);
2944 if (tp->link_config.active_speed == SPEED_1000 &&
2945 tp->link_config.active_duplex == DUPLEX_HALF)
2946 tw32(MAC_TX_LENGTHS,
2947 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2948 (6 << TX_LENGTHS_IPG_SHIFT) |
2949 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2951 tw32(MAC_TX_LENGTHS,
2952 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2953 (6 << TX_LENGTHS_IPG_SHIFT) |
2954 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2956 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2957 if (netif_carrier_ok(tp->dev)) {
2958 tw32(HOSTCC_STAT_COAL_TICKS,
2959 tp->coal.stats_block_coalesce_usecs);
2961 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2968 /* Tigon3 never reports partial packet sends. So we do not
2969 * need special logic to handle SKBs that have not had all
2970 * of their frags sent yet, like SunGEM does.
2972 static void tg3_tx(struct tg3 *tp)
2974 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2975 u32 sw_idx = tp->tx_cons;
2977 while (sw_idx != hw_idx) {
2978 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2979 struct sk_buff *skb = ri->skb;
2982 BUG_ON(skb == NULL);
2983 pci_unmap_single(tp->pdev,
2984 pci_unmap_addr(ri, mapping),
2990 sw_idx = NEXT_TX(sw_idx);
2992 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2993 BUG_ON(sw_idx == hw_idx);
2995 ri = &tp->tx_buffers[sw_idx];
2996 BUG_ON(ri->skb != NULL);
2998 pci_unmap_page(tp->pdev,
2999 pci_unmap_addr(ri, mapping),
3000 skb_shinfo(skb)->frags[i].size,
3003 sw_idx = NEXT_TX(sw_idx);
3009 tp->tx_cons = sw_idx;
3011 if (unlikely(netif_queue_stopped(tp->dev))) {
3012 spin_lock(&tp->tx_lock);
3013 if (netif_queue_stopped(tp->dev) &&
3014 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
3015 netif_wake_queue(tp->dev);
3016 spin_unlock(&tp->tx_lock);
3020 /* Returns size of skb allocated or < 0 on error.
3022 * We only need to fill in the address because the other members
3023 * of the RX descriptor are invariant, see tg3_init_rings.
3025 * Note the purposeful assymetry of cpu vs. chip accesses. For
3026 * posting buffers we only dirty the first cache line of the RX
3027 * descriptor (containing the address). Whereas for the RX status
3028 * buffers the cpu only reads the last cacheline of the RX descriptor
3029 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3031 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3032 int src_idx, u32 dest_idx_unmasked)
3034 struct tg3_rx_buffer_desc *desc;
3035 struct ring_info *map, *src_map;
3036 struct sk_buff *skb;
3038 int skb_size, dest_idx;
3041 switch (opaque_key) {
3042 case RXD_OPAQUE_RING_STD:
3043 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3044 desc = &tp->rx_std[dest_idx];
3045 map = &tp->rx_std_buffers[dest_idx];
3047 src_map = &tp->rx_std_buffers[src_idx];
3048 skb_size = tp->rx_pkt_buf_sz;
3051 case RXD_OPAQUE_RING_JUMBO:
3052 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3053 desc = &tp->rx_jumbo[dest_idx];
3054 map = &tp->rx_jumbo_buffers[dest_idx];
3056 src_map = &tp->rx_jumbo_buffers[src_idx];
3057 skb_size = RX_JUMBO_PKT_BUF_SZ;
3064 /* Do not overwrite any of the map or rp information
3065 * until we are sure we can commit to a new buffer.
3067 * Callers depend upon this behavior and assume that
3068 * we leave everything unchanged if we fail.
3070 skb = dev_alloc_skb(skb_size);
3075 skb_reserve(skb, tp->rx_offset);
3077 mapping = pci_map_single(tp->pdev, skb->data,
3078 skb_size - tp->rx_offset,
3079 PCI_DMA_FROMDEVICE);
3082 pci_unmap_addr_set(map, mapping, mapping);
3084 if (src_map != NULL)
3085 src_map->skb = NULL;
3087 desc->addr_hi = ((u64)mapping >> 32);
3088 desc->addr_lo = ((u64)mapping & 0xffffffff);
3093 /* We only need to move over in the address because the other
3094 * members of the RX descriptor are invariant. See notes above
3095 * tg3_alloc_rx_skb for full details.
3097 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3098 int src_idx, u32 dest_idx_unmasked)
3100 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3101 struct ring_info *src_map, *dest_map;
3104 switch (opaque_key) {
3105 case RXD_OPAQUE_RING_STD:
3106 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3107 dest_desc = &tp->rx_std[dest_idx];
3108 dest_map = &tp->rx_std_buffers[dest_idx];
3109 src_desc = &tp->rx_std[src_idx];
3110 src_map = &tp->rx_std_buffers[src_idx];
3113 case RXD_OPAQUE_RING_JUMBO:
3114 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3115 dest_desc = &tp->rx_jumbo[dest_idx];
3116 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3117 src_desc = &tp->rx_jumbo[src_idx];
3118 src_map = &tp->rx_jumbo_buffers[src_idx];
3125 dest_map->skb = src_map->skb;
3126 pci_unmap_addr_set(dest_map, mapping,
3127 pci_unmap_addr(src_map, mapping));
3128 dest_desc->addr_hi = src_desc->addr_hi;
3129 dest_desc->addr_lo = src_desc->addr_lo;
3131 src_map->skb = NULL;
3134 #if TG3_VLAN_TAG_USED
3135 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3137 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3141 /* The RX ring scheme is composed of multiple rings which post fresh
3142 * buffers to the chip, and one special ring the chip uses to report
3143 * status back to the host.
3145 * The special ring reports the status of received packets to the
3146 * host. The chip does not write into the original descriptor the
3147 * RX buffer was obtained from. The chip simply takes the original
3148 * descriptor as provided by the host, updates the status and length
3149 * field, then writes this into the next status ring entry.
3151 * Each ring the host uses to post buffers to the chip is described
3152 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3153 * it is first placed into the on-chip ram. When the packet's length
3154 * is known, it walks down the TG3_BDINFO entries to select the ring.
3155 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3156 * which is within the range of the new packet's length is chosen.
3158 * The "separate ring for rx status" scheme may sound queer, but it makes
3159 * sense from a cache coherency perspective. If only the host writes
3160 * to the buffer post rings, and only the chip writes to the rx status
3161 * rings, then cache lines never move beyond shared-modified state.
3162 * If both the host and chip were to write into the same ring, cache line
3163 * eviction could occur since both entities want it in an exclusive state.
3165 static int tg3_rx(struct tg3 *tp, int budget)
3168 u32 sw_idx = tp->rx_rcb_ptr;
3172 hw_idx = tp->hw_status->idx[0].rx_producer;
3174 * We need to order the read of hw_idx and the read of
3175 * the opaque cookie.
3180 while (sw_idx != hw_idx && budget > 0) {
3181 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3183 struct sk_buff *skb;
3184 dma_addr_t dma_addr;
3185 u32 opaque_key, desc_idx, *post_ptr;
3187 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3188 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3189 if (opaque_key == RXD_OPAQUE_RING_STD) {
3190 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3192 skb = tp->rx_std_buffers[desc_idx].skb;
3193 post_ptr = &tp->rx_std_ptr;
3194 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3195 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3197 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3198 post_ptr = &tp->rx_jumbo_ptr;
3201 goto next_pkt_nopost;
3204 work_mask |= opaque_key;
3206 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3207 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3209 tg3_recycle_rx(tp, opaque_key,
3210 desc_idx, *post_ptr);
3212 /* Other statistics kept track of by card. */
3213 tp->net_stats.rx_dropped++;
3217 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3219 if (len > RX_COPY_THRESHOLD
3220 && tp->rx_offset == 2
3221 /* rx_offset != 2 iff this is a 5701 card running
3222 * in PCI-X mode [see tg3_get_invariants()] */
3226 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3227 desc_idx, *post_ptr);
3231 pci_unmap_single(tp->pdev, dma_addr,
3232 skb_size - tp->rx_offset,
3233 PCI_DMA_FROMDEVICE);
3237 struct sk_buff *copy_skb;
3239 tg3_recycle_rx(tp, opaque_key,
3240 desc_idx, *post_ptr);
3242 copy_skb = dev_alloc_skb(len + 2);
3243 if (copy_skb == NULL)
3244 goto drop_it_no_recycle;
3246 copy_skb->dev = tp->dev;
3247 skb_reserve(copy_skb, 2);
3248 skb_put(copy_skb, len);
3249 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3250 memcpy(copy_skb->data, skb->data, len);
3251 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3253 /* We'll reuse the original ring buffer. */
3257 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3258 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3259 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3260 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3261 skb->ip_summed = CHECKSUM_UNNECESSARY;
3263 skb->ip_summed = CHECKSUM_NONE;
3265 skb->protocol = eth_type_trans(skb, tp->dev);
3266 #if TG3_VLAN_TAG_USED
3267 if (tp->vlgrp != NULL &&
3268 desc->type_flags & RXD_FLAG_VLAN) {
3269 tg3_vlan_rx(tp, skb,
3270 desc->err_vlan & RXD_VLAN_MASK);
3273 netif_receive_skb(skb);
3275 tp->dev->last_rx = jiffies;
3283 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3285 /* Refresh hw_idx to see if there is new work */
3286 if (sw_idx == hw_idx) {
3287 hw_idx = tp->hw_status->idx[0].rx_producer;
3292 /* ACK the status ring. */
3293 tp->rx_rcb_ptr = sw_idx;
3294 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3296 /* Refill RX ring(s). */
3297 if (work_mask & RXD_OPAQUE_RING_STD) {
3298 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3299 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3302 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3303 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3304 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3312 static int tg3_poll(struct net_device *netdev, int *budget)
3314 struct tg3 *tp = netdev_priv(netdev);
3315 struct tg3_hw_status *sblk = tp->hw_status;
3318 /* handle link change and other phy events */
3319 if (!(tp->tg3_flags &
3320 (TG3_FLAG_USE_LINKCHG_REG |
3321 TG3_FLAG_POLL_SERDES))) {
3322 if (sblk->status & SD_STATUS_LINK_CHG) {
3323 sblk->status = SD_STATUS_UPDATED |
3324 (sblk->status & ~SD_STATUS_LINK_CHG);
3325 spin_lock(&tp->lock);
3326 tg3_setup_phy(tp, 0);
3327 spin_unlock(&tp->lock);
3331 /* run TX completion thread */
3332 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3336 /* run RX thread, within the bounds set by NAPI.
3337 * All RX "locking" is done by ensuring outside
3338 * code synchronizes with dev->poll()
3340 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3341 int orig_budget = *budget;
3344 if (orig_budget > netdev->quota)
3345 orig_budget = netdev->quota;
3347 work_done = tg3_rx(tp, orig_budget);
3349 *budget -= work_done;
3350 netdev->quota -= work_done;
3353 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3354 tp->last_tag = sblk->status_tag;
3357 sblk->status &= ~SD_STATUS_UPDATED;
3359 /* if no more work, tell net stack and NIC we're done */
3360 done = !tg3_has_work(tp);
3362 netif_rx_complete(netdev);
3363 tg3_restart_ints(tp);
3366 return (done ? 0 : 1);
3369 static void tg3_irq_quiesce(struct tg3 *tp)
3371 BUG_ON(tp->irq_sync);
3376 synchronize_irq(tp->pdev->irq);
3379 static inline int tg3_irq_sync(struct tg3 *tp)
3381 return tp->irq_sync;
3384 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3385 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3386 * with as well. Most of the time, this is not necessary except when
3387 * shutting down the device.
3389 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3392 tg3_irq_quiesce(tp);
3393 spin_lock_bh(&tp->lock);
3394 spin_lock(&tp->tx_lock);
3397 static inline void tg3_full_unlock(struct tg3 *tp)
3399 spin_unlock(&tp->tx_lock);
3400 spin_unlock_bh(&tp->lock);
3403 /* One-shot MSI handler - Chip automatically disables interrupt
3404 * after sending MSI so driver doesn't have to do it.
3406 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id, struct pt_regs *regs)
3408 struct net_device *dev = dev_id;
3409 struct tg3 *tp = netdev_priv(dev);
3411 prefetch(tp->hw_status);
3412 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3414 if (likely(!tg3_irq_sync(tp)))
3415 netif_rx_schedule(dev); /* schedule NAPI poll */
3420 /* MSI ISR - No need to check for interrupt sharing and no need to
3421 * flush status block and interrupt mailbox. PCI ordering rules
3422 * guarantee that MSI will arrive after the status block.
3424 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3426 struct net_device *dev = dev_id;
3427 struct tg3 *tp = netdev_priv(dev);
3429 prefetch(tp->hw_status);
3430 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3432 * Writing any value to intr-mbox-0 clears PCI INTA# and
3433 * chip-internal interrupt pending events.
3434 * Writing non-zero to intr-mbox-0 additional tells the
3435 * NIC to stop sending us irqs, engaging "in-intr-handler"
3438 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3439 if (likely(!tg3_irq_sync(tp)))
3440 netif_rx_schedule(dev); /* schedule NAPI poll */
3442 return IRQ_RETVAL(1);
3445 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3447 struct net_device *dev = dev_id;
3448 struct tg3 *tp = netdev_priv(dev);
3449 struct tg3_hw_status *sblk = tp->hw_status;
3450 unsigned int handled = 1;
3452 /* In INTx mode, it is possible for the interrupt to arrive at
3453 * the CPU before the status block posted prior to the interrupt.
3454 * Reading the PCI State register will confirm whether the
3455 * interrupt is ours and will flush the status block.
3457 if ((sblk->status & SD_STATUS_UPDATED) ||
3458 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3460 * Writing any value to intr-mbox-0 clears PCI INTA# and
3461 * chip-internal interrupt pending events.
3462 * Writing non-zero to intr-mbox-0 additional tells the
3463 * NIC to stop sending us irqs, engaging "in-intr-handler"
3466 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3468 if (tg3_irq_sync(tp))
3470 sblk->status &= ~SD_STATUS_UPDATED;
3471 if (likely(tg3_has_work(tp))) {
3472 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3473 netif_rx_schedule(dev); /* schedule NAPI poll */
3475 /* No work, shared interrupt perhaps? re-enable
3476 * interrupts, and flush that PCI write
3478 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3481 } else { /* shared interrupt */
3485 return IRQ_RETVAL(handled);
3488 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3490 struct net_device *dev = dev_id;
3491 struct tg3 *tp = netdev_priv(dev);
3492 struct tg3_hw_status *sblk = tp->hw_status;
3493 unsigned int handled = 1;
3495 /* In INTx mode, it is possible for the interrupt to arrive at
3496 * the CPU before the status block posted prior to the interrupt.
3497 * Reading the PCI State register will confirm whether the
3498 * interrupt is ours and will flush the status block.
3500 if ((sblk->status_tag != tp->last_tag) ||
3501 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3503 * writing any value to intr-mbox-0 clears PCI INTA# and
3504 * chip-internal interrupt pending events.
3505 * writing non-zero to intr-mbox-0 additional tells the
3506 * NIC to stop sending us irqs, engaging "in-intr-handler"
3509 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3511 if (tg3_irq_sync(tp))
3513 if (netif_rx_schedule_prep(dev)) {
3514 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3515 /* Update last_tag to mark that this status has been
3516 * seen. Because interrupt may be shared, we may be
3517 * racing with tg3_poll(), so only update last_tag
3518 * if tg3_poll() is not scheduled.
3520 tp->last_tag = sblk->status_tag;
3521 __netif_rx_schedule(dev);
3523 } else { /* shared interrupt */
3527 return IRQ_RETVAL(handled);
3530 /* ISR for interrupt test */
3531 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3532 struct pt_regs *regs)
3534 struct net_device *dev = dev_id;
3535 struct tg3 *tp = netdev_priv(dev);
3536 struct tg3_hw_status *sblk = tp->hw_status;
3538 if ((sblk->status & SD_STATUS_UPDATED) ||
3539 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3540 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3542 return IRQ_RETVAL(1);
3544 return IRQ_RETVAL(0);
3547 static int tg3_init_hw(struct tg3 *, int);
3548 static int tg3_halt(struct tg3 *, int, int);
3550 #ifdef CONFIG_NET_POLL_CONTROLLER
3551 static void tg3_poll_controller(struct net_device *dev)
3553 struct tg3 *tp = netdev_priv(dev);
3555 tg3_interrupt(tp->pdev->irq, dev, NULL);
3559 static void tg3_reset_task(void *_data)
3561 struct tg3 *tp = _data;
3562 unsigned int restart_timer;
3564 tg3_full_lock(tp, 0);
3565 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3567 if (!netif_running(tp->dev)) {
3568 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3569 tg3_full_unlock(tp);
3573 tg3_full_unlock(tp);
3577 tg3_full_lock(tp, 1);
3579 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3580 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3582 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3585 tg3_netif_start(tp);
3588 mod_timer(&tp->timer, jiffies + 1);
3590 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3592 tg3_full_unlock(tp);
3595 static void tg3_tx_timeout(struct net_device *dev)
3597 struct tg3 *tp = netdev_priv(dev);
3599 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3602 schedule_work(&tp->reset_task);
3605 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3606 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3608 u32 base = (u32) mapping & 0xffffffff;
3610 return ((base > 0xffffdcc0) &&
3611 (base + len + 8 < base));
3614 /* Test for DMA addresses > 40-bit */
3615 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3618 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3619 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3620 return (((u64) mapping + len) > DMA_40BIT_MASK);
3627 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3629 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3630 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3631 u32 last_plus_one, u32 *start,
3632 u32 base_flags, u32 mss)
3634 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3635 dma_addr_t new_addr = 0;
3642 /* New SKB is guaranteed to be linear. */
3644 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3646 /* Make sure new skb does not cross any 4G boundaries.
3647 * Drop the packet if it does.
3649 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3651 dev_kfree_skb(new_skb);
3654 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3655 base_flags, 1 | (mss << 1));
3656 *start = NEXT_TX(entry);
3660 /* Now clean up the sw ring entries. */
3662 while (entry != last_plus_one) {
3666 len = skb_headlen(skb);
3668 len = skb_shinfo(skb)->frags[i-1].size;
3669 pci_unmap_single(tp->pdev,
3670 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3671 len, PCI_DMA_TODEVICE);
3673 tp->tx_buffers[entry].skb = new_skb;
3674 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3676 tp->tx_buffers[entry].skb = NULL;
3678 entry = NEXT_TX(entry);
3687 static void tg3_set_txd(struct tg3 *tp, int entry,
3688 dma_addr_t mapping, int len, u32 flags,
3691 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3692 int is_end = (mss_and_is_end & 0x1);
3693 u32 mss = (mss_and_is_end >> 1);
3697 flags |= TXD_FLAG_END;
3698 if (flags & TXD_FLAG_VLAN) {
3699 vlan_tag = flags >> 16;
3702 vlan_tag |= (mss << TXD_MSS_SHIFT);
3704 txd->addr_hi = ((u64) mapping >> 32);
3705 txd->addr_lo = ((u64) mapping & 0xffffffff);
3706 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3707 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3710 /* hard_start_xmit for devices that don't have any bugs and
3711 * support TG3_FLG2_HW_TSO_2 only.
3713 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3715 struct tg3 *tp = netdev_priv(dev);
3717 u32 len, entry, base_flags, mss;
3719 len = skb_headlen(skb);
3721 /* No BH disabling for tx_lock here. We are running in BH disabled
3722 * context and TX reclaim runs via tp->poll inside of a software
3723 * interrupt. Furthermore, IRQ processing runs lockless so we have
3724 * no IRQ context deadlocks to worry about either. Rejoice!
3726 if (!spin_trylock(&tp->tx_lock))
3727 return NETDEV_TX_LOCKED;
3729 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3730 if (!netif_queue_stopped(dev)) {
3731 netif_stop_queue(dev);
3733 /* This is a hard error, log it. */
3734 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3735 "queue awake!\n", dev->name);
3737 spin_unlock(&tp->tx_lock);
3738 return NETDEV_TX_BUSY;
3741 entry = tp->tx_prod;
3743 #if TG3_TSO_SUPPORT != 0
3745 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3746 (mss = skb_shinfo(skb)->tso_size) != 0) {
3747 int tcp_opt_len, ip_tcp_len;
3749 if (skb_header_cloned(skb) &&
3750 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3755 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3756 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3758 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3759 TXD_FLAG_CPU_POST_DMA);
3761 skb->nh.iph->check = 0;
3762 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3764 skb->h.th->check = 0;
3766 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3768 else if (skb->ip_summed == CHECKSUM_HW)
3769 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3772 if (skb->ip_summed == CHECKSUM_HW)
3773 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3775 #if TG3_VLAN_TAG_USED
3776 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3777 base_flags |= (TXD_FLAG_VLAN |
3778 (vlan_tx_tag_get(skb) << 16));
3781 /* Queue skb data, a.k.a. the main skb fragment. */
3782 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3784 tp->tx_buffers[entry].skb = skb;
3785 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3787 tg3_set_txd(tp, entry, mapping, len, base_flags,
3788 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3790 entry = NEXT_TX(entry);
3792 /* Now loop through additional data fragments, and queue them. */
3793 if (skb_shinfo(skb)->nr_frags > 0) {
3794 unsigned int i, last;
3796 last = skb_shinfo(skb)->nr_frags - 1;
3797 for (i = 0; i <= last; i++) {
3798 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3801 mapping = pci_map_page(tp->pdev,
3804 len, PCI_DMA_TODEVICE);
3806 tp->tx_buffers[entry].skb = NULL;
3807 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3809 tg3_set_txd(tp, entry, mapping, len,
3810 base_flags, (i == last) | (mss << 1));
3812 entry = NEXT_TX(entry);
3816 /* Packets are ready, update Tx producer idx local and on card. */
3817 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3819 tp->tx_prod = entry;
3820 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3821 netif_stop_queue(dev);
3822 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3823 netif_wake_queue(tp->dev);
3828 spin_unlock(&tp->tx_lock);
3830 dev->trans_start = jiffies;
3832 return NETDEV_TX_OK;
3835 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3836 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3838 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3840 struct tg3 *tp = netdev_priv(dev);
3842 u32 len, entry, base_flags, mss;
3843 int would_hit_hwbug;
3845 len = skb_headlen(skb);
3847 /* No BH disabling for tx_lock here. We are running in BH disabled
3848 * context and TX reclaim runs via tp->poll inside of a software
3849 * interrupt. Furthermore, IRQ processing runs lockless so we have
3850 * no IRQ context deadlocks to worry about either. Rejoice!
3852 if (!spin_trylock(&tp->tx_lock))
3853 return NETDEV_TX_LOCKED;
3855 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3856 if (!netif_queue_stopped(dev)) {
3857 netif_stop_queue(dev);
3859 /* This is a hard error, log it. */
3860 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3861 "queue awake!\n", dev->name);
3863 spin_unlock(&tp->tx_lock);
3864 return NETDEV_TX_BUSY;
3867 entry = tp->tx_prod;
3869 if (skb->ip_summed == CHECKSUM_HW)
3870 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3871 #if TG3_TSO_SUPPORT != 0
3873 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3874 (mss = skb_shinfo(skb)->tso_size) != 0) {
3875 int tcp_opt_len, ip_tcp_len;
3877 if (skb_header_cloned(skb) &&
3878 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3883 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3884 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3886 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3887 TXD_FLAG_CPU_POST_DMA);
3889 skb->nh.iph->check = 0;
3890 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3891 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3892 skb->h.th->check = 0;
3893 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3897 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3902 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3903 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3904 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3907 tsflags = ((skb->nh.iph->ihl - 5) +
3908 (tcp_opt_len >> 2));
3909 mss |= (tsflags << 11);
3912 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3915 tsflags = ((skb->nh.iph->ihl - 5) +
3916 (tcp_opt_len >> 2));
3917 base_flags |= tsflags << 12;
3924 #if TG3_VLAN_TAG_USED
3925 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3926 base_flags |= (TXD_FLAG_VLAN |
3927 (vlan_tx_tag_get(skb) << 16));
3930 /* Queue skb data, a.k.a. the main skb fragment. */
3931 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3933 tp->tx_buffers[entry].skb = skb;
3934 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3936 would_hit_hwbug = 0;
3938 if (tg3_4g_overflow_test(mapping, len))
3939 would_hit_hwbug = 1;
3941 tg3_set_txd(tp, entry, mapping, len, base_flags,
3942 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3944 entry = NEXT_TX(entry);
3946 /* Now loop through additional data fragments, and queue them. */
3947 if (skb_shinfo(skb)->nr_frags > 0) {
3948 unsigned int i, last;
3950 last = skb_shinfo(skb)->nr_frags - 1;
3951 for (i = 0; i <= last; i++) {
3952 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3955 mapping = pci_map_page(tp->pdev,
3958 len, PCI_DMA_TODEVICE);
3960 tp->tx_buffers[entry].skb = NULL;
3961 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3963 if (tg3_4g_overflow_test(mapping, len))
3964 would_hit_hwbug = 1;
3966 if (tg3_40bit_overflow_test(tp, mapping, len))
3967 would_hit_hwbug = 1;
3969 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3970 tg3_set_txd(tp, entry, mapping, len,
3971 base_flags, (i == last)|(mss << 1));
3973 tg3_set_txd(tp, entry, mapping, len,
3974 base_flags, (i == last));
3976 entry = NEXT_TX(entry);
3980 if (would_hit_hwbug) {
3981 u32 last_plus_one = entry;
3984 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3985 start &= (TG3_TX_RING_SIZE - 1);
3987 /* If the workaround fails due to memory/mapping
3988 * failure, silently drop this packet.
3990 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
3991 &start, base_flags, mss))
3997 /* Packets are ready, update Tx producer idx local and on card. */
3998 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4000 tp->tx_prod = entry;
4001 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
4002 netif_stop_queue(dev);
4003 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
4004 netif_wake_queue(tp->dev);
4009 spin_unlock(&tp->tx_lock);
4011 dev->trans_start = jiffies;
4013 return NETDEV_TX_OK;
4016 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4021 if (new_mtu > ETH_DATA_LEN) {
4022 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4023 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4024 ethtool_op_set_tso(dev, 0);
4027 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4029 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4030 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4031 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4035 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4037 struct tg3 *tp = netdev_priv(dev);
4039 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4042 if (!netif_running(dev)) {
4043 /* We'll just catch it later when the
4046 tg3_set_mtu(dev, tp, new_mtu);
4052 tg3_full_lock(tp, 1);
4054 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4056 tg3_set_mtu(dev, tp, new_mtu);
4060 tg3_netif_start(tp);
4062 tg3_full_unlock(tp);
4067 /* Free up pending packets in all rx/tx rings.
4069 * The chip has been shut down and the driver detached from
4070 * the networking, so no interrupts or new tx packets will
4071 * end up in the driver. tp->{tx,}lock is not held and we are not
4072 * in an interrupt context and thus may sleep.
4074 static void tg3_free_rings(struct tg3 *tp)
4076 struct ring_info *rxp;
4079 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4080 rxp = &tp->rx_std_buffers[i];
4082 if (rxp->skb == NULL)
4084 pci_unmap_single(tp->pdev,
4085 pci_unmap_addr(rxp, mapping),
4086 tp->rx_pkt_buf_sz - tp->rx_offset,
4087 PCI_DMA_FROMDEVICE);
4088 dev_kfree_skb_any(rxp->skb);
4092 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4093 rxp = &tp->rx_jumbo_buffers[i];
4095 if (rxp->skb == NULL)
4097 pci_unmap_single(tp->pdev,
4098 pci_unmap_addr(rxp, mapping),
4099 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4100 PCI_DMA_FROMDEVICE);
4101 dev_kfree_skb_any(rxp->skb);
4105 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4106 struct tx_ring_info *txp;
4107 struct sk_buff *skb;
4110 txp = &tp->tx_buffers[i];
4118 pci_unmap_single(tp->pdev,
4119 pci_unmap_addr(txp, mapping),
4126 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4127 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4128 pci_unmap_page(tp->pdev,
4129 pci_unmap_addr(txp, mapping),
4130 skb_shinfo(skb)->frags[j].size,
4135 dev_kfree_skb_any(skb);
4139 /* Initialize tx/rx rings for packet processing.
4141 * The chip has been shut down and the driver detached from
4142 * the networking, so no interrupts or new tx packets will
4143 * end up in the driver. tp->{tx,}lock are held and thus
4146 static void tg3_init_rings(struct tg3 *tp)
4150 /* Free up all the SKBs. */
4153 /* Zero out all descriptors. */
4154 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4155 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4156 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4157 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4159 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4160 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4161 (tp->dev->mtu > ETH_DATA_LEN))
4162 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4164 /* Initialize invariants of the rings, we only set this
4165 * stuff once. This works because the card does not
4166 * write into the rx buffer posting rings.
4168 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4169 struct tg3_rx_buffer_desc *rxd;
4171 rxd = &tp->rx_std[i];
4172 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4174 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4175 rxd->opaque = (RXD_OPAQUE_RING_STD |
4176 (i << RXD_OPAQUE_INDEX_SHIFT));
4179 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4180 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4181 struct tg3_rx_buffer_desc *rxd;
4183 rxd = &tp->rx_jumbo[i];
4184 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4186 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4188 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4189 (i << RXD_OPAQUE_INDEX_SHIFT));
4193 /* Now allocate fresh SKBs for each rx ring. */
4194 for (i = 0; i < tp->rx_pending; i++) {
4195 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
4200 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4201 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4202 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4210 * Must not be invoked with interrupt sources disabled and
4211 * the hardware shutdown down.
4213 static void tg3_free_consistent(struct tg3 *tp)
4215 kfree(tp->rx_std_buffers);
4216 tp->rx_std_buffers = NULL;
4218 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4219 tp->rx_std, tp->rx_std_mapping);
4223 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4224 tp->rx_jumbo, tp->rx_jumbo_mapping);
4225 tp->rx_jumbo = NULL;
4228 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4229 tp->rx_rcb, tp->rx_rcb_mapping);
4233 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4234 tp->tx_ring, tp->tx_desc_mapping);
4237 if (tp->hw_status) {
4238 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4239 tp->hw_status, tp->status_mapping);
4240 tp->hw_status = NULL;
4243 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4244 tp->hw_stats, tp->stats_mapping);
4245 tp->hw_stats = NULL;
4250 * Must not be invoked with interrupt sources disabled and
4251 * the hardware shutdown down. Can sleep.
4253 static int tg3_alloc_consistent(struct tg3 *tp)
4255 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4257 TG3_RX_JUMBO_RING_SIZE)) +
4258 (sizeof(struct tx_ring_info) *
4261 if (!tp->rx_std_buffers)
4264 memset(tp->rx_std_buffers, 0,
4265 (sizeof(struct ring_info) *
4267 TG3_RX_JUMBO_RING_SIZE)) +
4268 (sizeof(struct tx_ring_info) *
4271 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4272 tp->tx_buffers = (struct tx_ring_info *)
4273 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4275 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4276 &tp->rx_std_mapping);
4280 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4281 &tp->rx_jumbo_mapping);
4286 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4287 &tp->rx_rcb_mapping);
4291 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4292 &tp->tx_desc_mapping);
4296 tp->hw_status = pci_alloc_consistent(tp->pdev,
4298 &tp->status_mapping);
4302 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4303 sizeof(struct tg3_hw_stats),
4304 &tp->stats_mapping);
4308 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4309 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4314 tg3_free_consistent(tp);
4318 #define MAX_WAIT_CNT 1000
4320 /* To stop a block, clear the enable bit and poll till it
4321 * clears. tp->lock is held.
4323 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4328 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4335 /* We can't enable/disable these bits of the
4336 * 5705/5750, just say success.
4349 for (i = 0; i < MAX_WAIT_CNT; i++) {
4352 if ((val & enable_bit) == 0)
4356 if (i == MAX_WAIT_CNT && !silent) {
4357 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4358 "ofs=%lx enable_bit=%x\n",
4366 /* tp->lock is held. */
4367 static int tg3_abort_hw(struct tg3 *tp, int silent)
4371 tg3_disable_ints(tp);
4373 tp->rx_mode &= ~RX_MODE_ENABLE;
4374 tw32_f(MAC_RX_MODE, tp->rx_mode);
4377 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4378 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4379 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4380 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4381 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4382 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4384 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4385 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4386 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4387 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4388 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4389 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4390 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4392 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4393 tw32_f(MAC_MODE, tp->mac_mode);
4396 tp->tx_mode &= ~TX_MODE_ENABLE;
4397 tw32_f(MAC_TX_MODE, tp->tx_mode);
4399 for (i = 0; i < MAX_WAIT_CNT; i++) {
4401 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4404 if (i >= MAX_WAIT_CNT) {
4405 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4406 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4407 tp->dev->name, tr32(MAC_TX_MODE));
4411 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4412 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4413 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4415 tw32(FTQ_RESET, 0xffffffff);
4416 tw32(FTQ_RESET, 0x00000000);
4418 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4419 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4422 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4424 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4429 /* tp->lock is held. */
4430 static int tg3_nvram_lock(struct tg3 *tp)
4432 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4435 if (tp->nvram_lock_cnt == 0) {
4436 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4437 for (i = 0; i < 8000; i++) {
4438 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4443 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4447 tp->nvram_lock_cnt++;
4452 /* tp->lock is held. */
4453 static void tg3_nvram_unlock(struct tg3 *tp)
4455 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4456 if (tp->nvram_lock_cnt > 0)
4457 tp->nvram_lock_cnt--;
4458 if (tp->nvram_lock_cnt == 0)
4459 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4463 /* tp->lock is held. */
4464 static void tg3_enable_nvram_access(struct tg3 *tp)
4466 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4467 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4468 u32 nvaccess = tr32(NVRAM_ACCESS);
4470 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4474 /* tp->lock is held. */
4475 static void tg3_disable_nvram_access(struct tg3 *tp)
4477 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4478 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4479 u32 nvaccess = tr32(NVRAM_ACCESS);
4481 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4485 /* tp->lock is held. */
4486 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4488 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4489 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4490 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4492 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4494 case RESET_KIND_INIT:
4495 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4499 case RESET_KIND_SHUTDOWN:
4500 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4504 case RESET_KIND_SUSPEND:
4505 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4515 /* tp->lock is held. */
4516 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4518 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4520 case RESET_KIND_INIT:
4521 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4522 DRV_STATE_START_DONE);
4525 case RESET_KIND_SHUTDOWN:
4526 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4527 DRV_STATE_UNLOAD_DONE);
4536 /* tp->lock is held. */
4537 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4539 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4541 case RESET_KIND_INIT:
4542 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4546 case RESET_KIND_SHUTDOWN:
4547 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4551 case RESET_KIND_SUSPEND:
4552 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4562 static void tg3_stop_fw(struct tg3 *);
4564 /* tp->lock is held. */
4565 static int tg3_chip_reset(struct tg3 *tp)
4568 void (*write_op)(struct tg3 *, u32, u32);
4571 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4573 /* No matching tg3_nvram_unlock() after this because
4574 * chip reset below will undo the nvram lock.
4576 tp->nvram_lock_cnt = 0;
4579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4581 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4582 tw32(GRC_FASTBOOT_PC, 0);
4585 * We must avoid the readl() that normally takes place.
4586 * It locks machines, causes machine checks, and other
4587 * fun things. So, temporarily disable the 5701
4588 * hardware workaround, while we do the reset.
4590 write_op = tp->write32;
4591 if (write_op == tg3_write_flush_reg32)
4592 tp->write32 = tg3_write32;
4595 val = GRC_MISC_CFG_CORECLK_RESET;
4597 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4598 if (tr32(0x7e2c) == 0x60) {
4601 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4602 tw32(GRC_MISC_CFG, (1 << 29));
4607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4608 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4609 tw32(GRC_MISC_CFG, val);
4611 /* restore 5701 hardware bug workaround write method */
4612 tp->write32 = write_op;
4614 /* Unfortunately, we have to delay before the PCI read back.
4615 * Some 575X chips even will not respond to a PCI cfg access
4616 * when the reset command is given to the chip.
4618 * How do these hardware designers expect things to work
4619 * properly if the PCI write is posted for a long period
4620 * of time? It is always necessary to have some method by
4621 * which a register read back can occur to push the write
4622 * out which does the reset.
4624 * For most tg3 variants the trick below was working.
4629 /* Flush PCI posted writes. The normal MMIO registers
4630 * are inaccessible at this time so this is the only
4631 * way to make this reliably (actually, this is no longer
4632 * the case, see above). I tried to use indirect
4633 * register read/write but this upset some 5701 variants.
4635 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4639 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4640 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4644 /* Wait for link training to complete. */
4645 for (i = 0; i < 5000; i++)
4648 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4649 pci_write_config_dword(tp->pdev, 0xc4,
4650 cfg_val | (1 << 15));
4652 /* Set PCIE max payload size and clear error status. */
4653 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4656 /* Re-enable indirect register accesses. */
4657 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4658 tp->misc_host_ctrl);
4660 /* Set MAX PCI retry to zero. */
4661 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4662 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4663 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4664 val |= PCISTATE_RETRY_SAME_DMA;
4665 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4667 pci_restore_state(tp->pdev);
4669 /* Make sure PCI-X relaxed ordering bit is clear. */
4670 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4671 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4672 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4674 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4677 /* Chip reset on 5780 will reset MSI enable bit,
4678 * so need to restore it.
4680 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4683 pci_read_config_word(tp->pdev,
4684 tp->msi_cap + PCI_MSI_FLAGS,
4686 pci_write_config_word(tp->pdev,
4687 tp->msi_cap + PCI_MSI_FLAGS,
4688 ctrl | PCI_MSI_FLAGS_ENABLE);
4689 val = tr32(MSGINT_MODE);
4690 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4693 val = tr32(MEMARB_MODE);
4694 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4697 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4699 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4701 tw32(0x5000, 0x400);
4704 tw32(GRC_MODE, tp->grc_mode);
4706 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4707 u32 val = tr32(0xc4);
4709 tw32(0xc4, val | (1 << 15));
4712 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4713 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4714 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4715 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4716 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4717 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4720 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4721 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4722 tw32_f(MAC_MODE, tp->mac_mode);
4723 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4724 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4725 tw32_f(MAC_MODE, tp->mac_mode);
4727 tw32_f(MAC_MODE, 0);
4730 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4731 /* Wait for firmware initialization to complete. */
4732 for (i = 0; i < 100000; i++) {
4733 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4734 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4739 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4740 "firmware will not restart magic=%08x\n",
4741 tp->dev->name, val);
4746 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4747 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4748 u32 val = tr32(0x7c00);
4750 tw32(0x7c00, val | (1 << 25));
4753 /* Reprobe ASF enable state. */
4754 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4755 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4756 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4757 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4760 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4761 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4762 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4763 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4764 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4771 /* tp->lock is held. */
4772 static void tg3_stop_fw(struct tg3 *tp)
4774 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4778 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4779 val = tr32(GRC_RX_CPU_EVENT);
4781 tw32(GRC_RX_CPU_EVENT, val);
4783 /* Wait for RX cpu to ACK the event. */
4784 for (i = 0; i < 100; i++) {
4785 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4792 /* tp->lock is held. */
4793 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4799 tg3_write_sig_pre_reset(tp, kind);
4801 tg3_abort_hw(tp, silent);
4802 err = tg3_chip_reset(tp);
4804 tg3_write_sig_legacy(tp, kind);
4805 tg3_write_sig_post_reset(tp, kind);
4813 #define TG3_FW_RELEASE_MAJOR 0x0
4814 #define TG3_FW_RELASE_MINOR 0x0
4815 #define TG3_FW_RELEASE_FIX 0x0
4816 #define TG3_FW_START_ADDR 0x08000000
4817 #define TG3_FW_TEXT_ADDR 0x08000000
4818 #define TG3_FW_TEXT_LEN 0x9c0
4819 #define TG3_FW_RODATA_ADDR 0x080009c0
4820 #define TG3_FW_RODATA_LEN 0x60
4821 #define TG3_FW_DATA_ADDR 0x08000a40
4822 #define TG3_FW_DATA_LEN 0x20
4823 #define TG3_FW_SBSS_ADDR 0x08000a60
4824 #define TG3_FW_SBSS_LEN 0xc
4825 #define TG3_FW_BSS_ADDR 0x08000a70
4826 #define TG3_FW_BSS_LEN 0x10
4828 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4829 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4830 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4831 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4832 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4833 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4834 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4835 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4836 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4837 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4838 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4839 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4840 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4841 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4842 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4843 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4844 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4845 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4846 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4847 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4848 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4849 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4850 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4851 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4852 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4855 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4856 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4857 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4858 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4859 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4860 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4861 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4862 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4863 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4864 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4865 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4868 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4869 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4870 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4871 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4872 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4873 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4874 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4875 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4876 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4877 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4878 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4879 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4880 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4881 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4882 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4883 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4884 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4885 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4886 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4887 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4888 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4889 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4890 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4891 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4892 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4893 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4894 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4895 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4896 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4897 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4898 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4899 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4900 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4901 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4902 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4903 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4904 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4905 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4906 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4907 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4908 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4909 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4910 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4911 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4912 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4913 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4914 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4915 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4916 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4917 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4918 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4919 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4922 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4923 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4924 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4925 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4926 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4930 #if 0 /* All zeros, don't eat up space with it. */
4931 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4932 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4933 0x00000000, 0x00000000, 0x00000000, 0x00000000
4937 #define RX_CPU_SCRATCH_BASE 0x30000
4938 #define RX_CPU_SCRATCH_SIZE 0x04000
4939 #define TX_CPU_SCRATCH_BASE 0x34000
4940 #define TX_CPU_SCRATCH_SIZE 0x04000
4942 /* tp->lock is held. */
4943 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4947 BUG_ON(offset == TX_CPU_BASE &&
4948 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
4950 if (offset == RX_CPU_BASE) {
4951 for (i = 0; i < 10000; i++) {
4952 tw32(offset + CPU_STATE, 0xffffffff);
4953 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4954 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4958 tw32(offset + CPU_STATE, 0xffffffff);
4959 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4962 for (i = 0; i < 10000; i++) {
4963 tw32(offset + CPU_STATE, 0xffffffff);
4964 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4965 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4971 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4974 (offset == RX_CPU_BASE ? "RX" : "TX"));
4978 /* Clear firmware's nvram arbitration. */
4979 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4980 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
4985 unsigned int text_base;
4986 unsigned int text_len;
4988 unsigned int rodata_base;
4989 unsigned int rodata_len;
4991 unsigned int data_base;
4992 unsigned int data_len;
4996 /* tp->lock is held. */
4997 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4998 int cpu_scratch_size, struct fw_info *info)
5000 int err, lock_err, i;
5001 void (*write_op)(struct tg3 *, u32, u32);
5003 if (cpu_base == TX_CPU_BASE &&
5004 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5005 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5006 "TX cpu firmware on %s which is 5705.\n",
5011 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5012 write_op = tg3_write_mem;
5014 write_op = tg3_write_indirect_reg32;
5016 /* It is possible that bootcode is still loading at this point.
5017 * Get the nvram lock first before halting the cpu.
5019 lock_err = tg3_nvram_lock(tp);
5020 err = tg3_halt_cpu(tp, cpu_base);
5022 tg3_nvram_unlock(tp);
5026 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5027 write_op(tp, cpu_scratch_base + i, 0);
5028 tw32(cpu_base + CPU_STATE, 0xffffffff);
5029 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5030 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5031 write_op(tp, (cpu_scratch_base +
5032 (info->text_base & 0xffff) +
5035 info->text_data[i] : 0));
5036 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5037 write_op(tp, (cpu_scratch_base +
5038 (info->rodata_base & 0xffff) +
5040 (info->rodata_data ?
5041 info->rodata_data[i] : 0));
5042 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5043 write_op(tp, (cpu_scratch_base +
5044 (info->data_base & 0xffff) +
5047 info->data_data[i] : 0));
5055 /* tp->lock is held. */
5056 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5058 struct fw_info info;
5061 info.text_base = TG3_FW_TEXT_ADDR;
5062 info.text_len = TG3_FW_TEXT_LEN;
5063 info.text_data = &tg3FwText[0];
5064 info.rodata_base = TG3_FW_RODATA_ADDR;
5065 info.rodata_len = TG3_FW_RODATA_LEN;
5066 info.rodata_data = &tg3FwRodata[0];
5067 info.data_base = TG3_FW_DATA_ADDR;
5068 info.data_len = TG3_FW_DATA_LEN;
5069 info.data_data = NULL;
5071 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5072 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5077 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5078 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5083 /* Now startup only the RX cpu. */
5084 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5085 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5087 for (i = 0; i < 5; i++) {
5088 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5090 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5091 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5092 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5096 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5097 "to set RX CPU PC, is %08x should be %08x\n",
5098 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5102 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5103 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5108 #if TG3_TSO_SUPPORT != 0
5110 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5111 #define TG3_TSO_FW_RELASE_MINOR 0x6
5112 #define TG3_TSO_FW_RELEASE_FIX 0x0
5113 #define TG3_TSO_FW_START_ADDR 0x08000000
5114 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5115 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5116 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5117 #define TG3_TSO_FW_RODATA_LEN 0x60
5118 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5119 #define TG3_TSO_FW_DATA_LEN 0x30
5120 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5121 #define TG3_TSO_FW_SBSS_LEN 0x2c
5122 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5123 #define TG3_TSO_FW_BSS_LEN 0x894
5125 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5126 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5127 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5128 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5129 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5130 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5131 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5132 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5133 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5134 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5135 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5136 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5137 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5138 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5139 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5140 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5141 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5142 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5143 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5144 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5145 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5146 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5147 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5148 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5149 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5150 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5151 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5152 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5153 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5154 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5155 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5156 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5157 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5158 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5159 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5160 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5161 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5162 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5163 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5164 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5165 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5166 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5167 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5168 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5169 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5170 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5171 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5172 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5173 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5174 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5175 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5176 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5177 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5178 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5179 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5180 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5181 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5182 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5183 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5184 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5185 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5186 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5187 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5188 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5189 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5190 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5191 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5192 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5193 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5194 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5195 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5196 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5197 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5198 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5199 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5200 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5201 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5202 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5203 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5204 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5205 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5206 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5207 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5208 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5209 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5210 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5211 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5212 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5213 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5214 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5215 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5216 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5217 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5218 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5219 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5220 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5221 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5222 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5223 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5224 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5225 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5226 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5227 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5228 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5229 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5230 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5231 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5232 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5233 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5234 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5235 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5236 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5237 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5238 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5239 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5240 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5241 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5242 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5243 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5244 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5245 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5246 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5247 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5248 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5249 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5250 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5251 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5252 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5253 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5254 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5255 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5256 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5257 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5258 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5259 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5260 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5261 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5262 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5263 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5264 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5265 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5266 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5267 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5268 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5269 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5270 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5271 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5272 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5273 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5274 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5275 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5276 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5277 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5278 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5279 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5280 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5281 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5282 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5283 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5284 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5285 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5286 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5287 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5288 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5289 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5290 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5291 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5292 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5293 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5294 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5295 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5296 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5297 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5298 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5299 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5300 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5301 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5302 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5303 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5304 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5305 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5306 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5307 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5308 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5309 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5310 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5311 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5312 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5313 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5314 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5315 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5316 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5317 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5318 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5319 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5320 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5321 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5322 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5323 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5324 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5325 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5326 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5327 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5328 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5329 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5330 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5331 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5332 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5333 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5334 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5335 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5336 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5337 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5338 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5339 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5340 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5341 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5342 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5343 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5344 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5345 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5346 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5347 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5348 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5349 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5350 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5351 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5352 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5353 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5354 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5355 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5356 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5357 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5358 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5359 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5360 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5361 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5362 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5363 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5364 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5365 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5366 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5367 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5368 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5369 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5370 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5371 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5372 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5373 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5374 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5375 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5376 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5377 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5378 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5379 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5380 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5381 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5382 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5383 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5384 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5385 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5386 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5387 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5388 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5389 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5390 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5391 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5392 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5393 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5394 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5395 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5396 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5397 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5398 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5399 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5400 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5401 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5402 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5403 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5404 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5405 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5406 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5407 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5408 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5409 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5412 static u32 tg3TsoFwRodata[] = {
5413 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5414 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5415 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5416 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5420 static u32 tg3TsoFwData[] = {
5421 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5422 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5426 /* 5705 needs a special version of the TSO firmware. */
5427 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5428 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5429 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5430 #define TG3_TSO5_FW_START_ADDR 0x00010000
5431 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5432 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5433 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5434 #define TG3_TSO5_FW_RODATA_LEN 0x50
5435 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5436 #define TG3_TSO5_FW_DATA_LEN 0x20
5437 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5438 #define TG3_TSO5_FW_SBSS_LEN 0x28
5439 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5440 #define TG3_TSO5_FW_BSS_LEN 0x88
5442 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5443 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5444 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5445 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5446 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5447 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5448 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5449 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5450 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5451 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5452 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5453 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5454 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5455 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5456 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5457 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5458 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5459 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5460 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5461 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5462 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5463 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5464 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5465 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5466 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5467 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5468 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5469 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5470 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5471 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5472 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5473 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5474 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5475 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5476 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5477 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5478 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5479 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5480 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5481 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5482 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5483 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5484 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5485 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5486 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5487 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5488 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5489 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5490 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5491 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5492 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5493 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5494 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5495 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5496 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5497 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5498 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5499 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5500 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5501 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5502 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5503 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5504 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5505 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5506 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5507 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5508 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5509 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5510 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5511 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5512 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5513 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5514 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5515 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5516 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5517 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5518 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5519 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5520 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5521 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5522 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5523 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5524 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5525 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5526 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5527 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5528 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5529 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5530 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5531 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5532 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5533 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5534 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5535 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5536 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5537 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5538 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5539 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5540 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5541 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5542 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5543 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5544 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5545 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5546 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5547 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5548 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5549 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5550 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5551 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5552 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5553 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5554 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5555 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5556 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5557 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5558 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5559 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5560 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5561 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5562 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5563 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5564 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5565 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5566 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5567 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5568 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5569 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5570 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5571 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5572 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5573 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5574 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5575 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5576 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5577 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5578 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5579 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5580 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5581 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5582 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5583 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5584 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5585 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5586 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5587 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5588 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5589 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5590 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5591 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5592 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5593 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5594 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5595 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5596 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5597 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5598 0x00000000, 0x00000000, 0x00000000,
5601 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5602 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5603 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5604 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5605 0x00000000, 0x00000000, 0x00000000,
5608 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5609 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5610 0x00000000, 0x00000000, 0x00000000,
5613 /* tp->lock is held. */
5614 static int tg3_load_tso_firmware(struct tg3 *tp)
5616 struct fw_info info;
5617 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5620 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5623 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5624 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5625 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5626 info.text_data = &tg3Tso5FwText[0];
5627 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5628 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5629 info.rodata_data = &tg3Tso5FwRodata[0];
5630 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5631 info.data_len = TG3_TSO5_FW_DATA_LEN;
5632 info.data_data = &tg3Tso5FwData[0];
5633 cpu_base = RX_CPU_BASE;
5634 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5635 cpu_scratch_size = (info.text_len +
5638 TG3_TSO5_FW_SBSS_LEN +
5639 TG3_TSO5_FW_BSS_LEN);
5641 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5642 info.text_len = TG3_TSO_FW_TEXT_LEN;
5643 info.text_data = &tg3TsoFwText[0];
5644 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5645 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5646 info.rodata_data = &tg3TsoFwRodata[0];
5647 info.data_base = TG3_TSO_FW_DATA_ADDR;
5648 info.data_len = TG3_TSO_FW_DATA_LEN;
5649 info.data_data = &tg3TsoFwData[0];
5650 cpu_base = TX_CPU_BASE;
5651 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5652 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5655 err = tg3_load_firmware_cpu(tp, cpu_base,
5656 cpu_scratch_base, cpu_scratch_size,
5661 /* Now startup the cpu. */
5662 tw32(cpu_base + CPU_STATE, 0xffffffff);
5663 tw32_f(cpu_base + CPU_PC, info.text_base);
5665 for (i = 0; i < 5; i++) {
5666 if (tr32(cpu_base + CPU_PC) == info.text_base)
5668 tw32(cpu_base + CPU_STATE, 0xffffffff);
5669 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5670 tw32_f(cpu_base + CPU_PC, info.text_base);
5674 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5675 "to set CPU PC, is %08x should be %08x\n",
5676 tp->dev->name, tr32(cpu_base + CPU_PC),
5680 tw32(cpu_base + CPU_STATE, 0xffffffff);
5681 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5685 #endif /* TG3_TSO_SUPPORT != 0 */
5687 /* tp->lock is held. */
5688 static void __tg3_set_mac_addr(struct tg3 *tp)
5690 u32 addr_high, addr_low;
5693 addr_high = ((tp->dev->dev_addr[0] << 8) |
5694 tp->dev->dev_addr[1]);
5695 addr_low = ((tp->dev->dev_addr[2] << 24) |
5696 (tp->dev->dev_addr[3] << 16) |
5697 (tp->dev->dev_addr[4] << 8) |
5698 (tp->dev->dev_addr[5] << 0));
5699 for (i = 0; i < 4; i++) {
5700 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5701 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5704 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5705 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5706 for (i = 0; i < 12; i++) {
5707 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5708 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5712 addr_high = (tp->dev->dev_addr[0] +
5713 tp->dev->dev_addr[1] +
5714 tp->dev->dev_addr[2] +
5715 tp->dev->dev_addr[3] +
5716 tp->dev->dev_addr[4] +
5717 tp->dev->dev_addr[5]) &
5718 TX_BACKOFF_SEED_MASK;
5719 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5722 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5724 struct tg3 *tp = netdev_priv(dev);
5725 struct sockaddr *addr = p;
5727 if (!is_valid_ether_addr(addr->sa_data))
5730 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5732 if (!netif_running(dev))
5735 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5736 /* Reset chip so that ASF can re-init any MAC addresses it
5740 tg3_full_lock(tp, 1);
5742 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5745 tg3_netif_start(tp);
5746 tg3_full_unlock(tp);
5748 spin_lock_bh(&tp->lock);
5749 __tg3_set_mac_addr(tp);
5750 spin_unlock_bh(&tp->lock);
5756 /* tp->lock is held. */
5757 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5758 dma_addr_t mapping, u32 maxlen_flags,
5762 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5763 ((u64) mapping >> 32));
5765 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5766 ((u64) mapping & 0xffffffff));
5768 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5771 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5773 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5777 static void __tg3_set_rx_mode(struct net_device *);
5778 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5780 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5781 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5782 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5783 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5785 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5786 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5788 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5789 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5790 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5791 u32 val = ec->stats_block_coalesce_usecs;
5793 if (!netif_carrier_ok(tp->dev))
5796 tw32(HOSTCC_STAT_COAL_TICKS, val);
5800 /* tp->lock is held. */
5801 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
5803 u32 val, rdmac_mode;
5806 tg3_disable_ints(tp);
5810 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5812 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5813 tg3_abort_hw(tp, 1);
5816 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && reset_phy)
5819 err = tg3_chip_reset(tp);
5823 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5825 /* This works around an issue with Athlon chipsets on
5826 * B3 tigon3 silicon. This bit has no effect on any
5827 * other revision. But do not set this on PCI Express
5830 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5831 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5832 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5834 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5835 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5836 val = tr32(TG3PCI_PCISTATE);
5837 val |= PCISTATE_RETRY_SAME_DMA;
5838 tw32(TG3PCI_PCISTATE, val);
5841 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5842 /* Enable some hw fixes. */
5843 val = tr32(TG3PCI_MSI_DATA);
5844 val |= (1 << 26) | (1 << 28) | (1 << 29);
5845 tw32(TG3PCI_MSI_DATA, val);
5848 /* Descriptor ring init may make accesses to the
5849 * NIC SRAM area to setup the TX descriptors, so we
5850 * can only do this after the hardware has been
5851 * successfully reset.
5855 /* This value is determined during the probe time DMA
5856 * engine test, tg3_test_dma.
5858 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5860 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5861 GRC_MODE_4X_NIC_SEND_RINGS |
5862 GRC_MODE_NO_TX_PHDR_CSUM |
5863 GRC_MODE_NO_RX_PHDR_CSUM);
5864 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5866 /* Pseudo-header checksum is done by hardware logic and not
5867 * the offload processers, so make the chip do the pseudo-
5868 * header checksums on receive. For transmit it is more
5869 * convenient to do the pseudo-header checksum in software
5870 * as Linux does that on transmit for us in all cases.
5872 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5876 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5878 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5879 val = tr32(GRC_MISC_CFG);
5881 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5882 tw32(GRC_MISC_CFG, val);
5884 /* Initialize MBUF/DESC pool. */
5885 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5887 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5888 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5890 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5892 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5893 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5894 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5896 #if TG3_TSO_SUPPORT != 0
5897 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5900 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5901 TG3_TSO5_FW_RODATA_LEN +
5902 TG3_TSO5_FW_DATA_LEN +
5903 TG3_TSO5_FW_SBSS_LEN +
5904 TG3_TSO5_FW_BSS_LEN);
5905 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5906 tw32(BUFMGR_MB_POOL_ADDR,
5907 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5908 tw32(BUFMGR_MB_POOL_SIZE,
5909 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5913 if (tp->dev->mtu <= ETH_DATA_LEN) {
5914 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5915 tp->bufmgr_config.mbuf_read_dma_low_water);
5916 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5917 tp->bufmgr_config.mbuf_mac_rx_low_water);
5918 tw32(BUFMGR_MB_HIGH_WATER,
5919 tp->bufmgr_config.mbuf_high_water);
5921 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5922 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5923 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5924 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5925 tw32(BUFMGR_MB_HIGH_WATER,
5926 tp->bufmgr_config.mbuf_high_water_jumbo);
5928 tw32(BUFMGR_DMA_LOW_WATER,
5929 tp->bufmgr_config.dma_low_water);
5930 tw32(BUFMGR_DMA_HIGH_WATER,
5931 tp->bufmgr_config.dma_high_water);
5933 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5934 for (i = 0; i < 2000; i++) {
5935 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5940 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5945 /* Setup replenish threshold. */
5946 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5948 /* Initialize TG3_BDINFO's at:
5949 * RCVDBDI_STD_BD: standard eth size rx ring
5950 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5951 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5954 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5955 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5956 * ring attribute flags
5957 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5959 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5960 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5962 * The size of each ring is fixed in the firmware, but the location is
5965 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5966 ((u64) tp->rx_std_mapping >> 32));
5967 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5968 ((u64) tp->rx_std_mapping & 0xffffffff));
5969 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5970 NIC_SRAM_RX_BUFFER_DESC);
5972 /* Don't even try to program the JUMBO/MINI buffer descriptor
5975 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5976 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5977 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5979 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5980 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5982 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5983 BDINFO_FLAGS_DISABLED);
5985 /* Setup replenish threshold. */
5986 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5988 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5989 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5990 ((u64) tp->rx_jumbo_mapping >> 32));
5991 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5992 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5993 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5994 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5995 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5996 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5998 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5999 BDINFO_FLAGS_DISABLED);
6004 /* There is only one send ring on 5705/5750, no need to explicitly
6005 * disable the others.
6007 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6008 /* Clear out send RCB ring in SRAM. */
6009 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6010 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6011 BDINFO_FLAGS_DISABLED);
6016 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6017 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6019 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6020 tp->tx_desc_mapping,
6021 (TG3_TX_RING_SIZE <<
6022 BDINFO_FLAGS_MAXLEN_SHIFT),
6023 NIC_SRAM_TX_BUFFER_DESC);
6025 /* There is only one receive return ring on 5705/5750, no need
6026 * to explicitly disable the others.
6028 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6029 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6030 i += TG3_BDINFO_SIZE) {
6031 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6032 BDINFO_FLAGS_DISABLED);
6037 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6039 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6041 (TG3_RX_RCB_RING_SIZE(tp) <<
6042 BDINFO_FLAGS_MAXLEN_SHIFT),
6045 tp->rx_std_ptr = tp->rx_pending;
6046 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6049 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6050 tp->rx_jumbo_pending : 0;
6051 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6054 /* Initialize MAC address and backoff seed. */
6055 __tg3_set_mac_addr(tp);
6057 /* MTU + ethernet header + FCS + optional VLAN tag */
6058 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6060 /* The slot time is changed by tg3_setup_phy if we
6061 * run at gigabit with half duplex.
6063 tw32(MAC_TX_LENGTHS,
6064 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6065 (6 << TX_LENGTHS_IPG_SHIFT) |
6066 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6068 /* Receive rules. */
6069 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6070 tw32(RCVLPC_CONFIG, 0x0181);
6072 /* Calculate RDMAC_MODE setting early, we need it to determine
6073 * the RCVLPC_STATE_ENABLE mask.
6075 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6076 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6077 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6078 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6079 RDMAC_MODE_LNGREAD_ENAB);
6080 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6081 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6083 /* If statement applies to 5705 and 5750 PCI devices only */
6084 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6085 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6086 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6087 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6088 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6089 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6090 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6091 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6092 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6093 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6097 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6098 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6100 #if TG3_TSO_SUPPORT != 0
6101 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6102 rdmac_mode |= (1 << 27);
6105 /* Receive/send statistics. */
6106 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6107 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6108 val = tr32(RCVLPC_STATS_ENABLE);
6109 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6110 tw32(RCVLPC_STATS_ENABLE, val);
6112 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6114 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6115 tw32(SNDDATAI_STATSENAB, 0xffffff);
6116 tw32(SNDDATAI_STATSCTRL,
6117 (SNDDATAI_SCTRL_ENABLE |
6118 SNDDATAI_SCTRL_FASTUPD));
6120 /* Setup host coalescing engine. */
6121 tw32(HOSTCC_MODE, 0);
6122 for (i = 0; i < 2000; i++) {
6123 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6128 __tg3_set_coalesce(tp, &tp->coal);
6130 /* set status block DMA address */
6131 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6132 ((u64) tp->status_mapping >> 32));
6133 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6134 ((u64) tp->status_mapping & 0xffffffff));
6136 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6137 /* Status/statistics block address. See tg3_timer,
6138 * the tg3_periodic_fetch_stats call there, and
6139 * tg3_get_stats to see how this works for 5705/5750 chips.
6141 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6142 ((u64) tp->stats_mapping >> 32));
6143 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6144 ((u64) tp->stats_mapping & 0xffffffff));
6145 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6146 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6149 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6151 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6152 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6153 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6154 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6156 /* Clear statistics/status block in chip, and status block in ram. */
6157 for (i = NIC_SRAM_STATS_BLK;
6158 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6160 tg3_write_mem(tp, i, 0);
6163 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6165 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6166 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6167 /* reset to prevent losing 1st rx packet intermittently */
6168 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6172 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6173 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6174 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6177 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6178 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6179 * register to preserve the GPIO settings for LOMs. The GPIOs,
6180 * whether used as inputs or outputs, are set by boot code after
6183 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6186 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6187 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6189 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6190 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6191 GRC_LCLCTRL_GPIO_OUTPUT3;
6193 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6194 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6196 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6198 /* GPIO1 must be driven high for eeprom write protect */
6199 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6200 GRC_LCLCTRL_GPIO_OUTPUT1);
6202 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6205 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6208 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6209 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6213 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6214 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6215 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6216 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6217 WDMAC_MODE_LNGREAD_ENAB);
6219 /* If statement applies to 5705 and 5750 PCI devices only */
6220 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6221 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6223 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6224 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6225 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6227 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6228 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6229 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6230 val |= WDMAC_MODE_RX_ACCEL;
6234 /* Enable host coalescing bug fix */
6235 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6236 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6239 tw32_f(WDMAC_MODE, val);
6242 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6243 val = tr32(TG3PCI_X_CAPS);
6244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6245 val &= ~PCIX_CAPS_BURST_MASK;
6246 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6247 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6248 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6249 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6250 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6251 val |= (tp->split_mode_max_reqs <<
6252 PCIX_CAPS_SPLIT_SHIFT);
6254 tw32(TG3PCI_X_CAPS, val);
6257 tw32_f(RDMAC_MODE, rdmac_mode);
6260 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6261 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6262 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6263 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6264 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6265 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6266 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6267 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6268 #if TG3_TSO_SUPPORT != 0
6269 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6270 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6272 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6273 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6275 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6276 err = tg3_load_5701_a0_firmware_fix(tp);
6281 #if TG3_TSO_SUPPORT != 0
6282 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6283 err = tg3_load_tso_firmware(tp);
6289 tp->tx_mode = TX_MODE_ENABLE;
6290 tw32_f(MAC_TX_MODE, tp->tx_mode);
6293 tp->rx_mode = RX_MODE_ENABLE;
6294 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6295 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6297 tw32_f(MAC_RX_MODE, tp->rx_mode);
6300 if (tp->link_config.phy_is_low_power) {
6301 tp->link_config.phy_is_low_power = 0;
6302 tp->link_config.speed = tp->link_config.orig_speed;
6303 tp->link_config.duplex = tp->link_config.orig_duplex;
6304 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6307 tp->mi_mode = MAC_MI_MODE_BASE;
6308 tw32_f(MAC_MI_MODE, tp->mi_mode);
6311 tw32(MAC_LED_CTRL, tp->led_ctrl);
6313 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6314 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6315 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6318 tw32_f(MAC_RX_MODE, tp->rx_mode);
6321 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6322 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6323 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6324 /* Set drive transmission level to 1.2V */
6325 /* only if the signal pre-emphasis bit is not set */
6326 val = tr32(MAC_SERDES_CFG);
6329 tw32(MAC_SERDES_CFG, val);
6331 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6332 tw32(MAC_SERDES_CFG, 0x616000);
6335 /* Prevent chip from dropping frames when flow control
6338 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6340 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6341 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6342 /* Use hardware link auto-negotiation */
6343 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6346 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6347 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6350 tmp = tr32(SERDES_RX_CTRL);
6351 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6352 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6353 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6354 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6357 err = tg3_setup_phy(tp, reset_phy);
6361 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6364 /* Clear CRC stats. */
6365 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6366 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6367 tg3_readphy(tp, 0x14, &tmp);
6371 __tg3_set_rx_mode(tp->dev);
6373 /* Initialize receive rules. */
6374 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6375 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6376 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6377 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6379 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6380 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6384 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6388 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6390 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6392 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6394 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6396 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6398 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6400 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6402 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6404 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6406 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6408 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6410 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6412 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6414 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6422 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6427 /* Called at device open time to get the chip ready for
6428 * packet processing. Invoked with tp->lock held.
6430 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6434 /* Force the chip into D0. */
6435 err = tg3_set_power_state(tp, PCI_D0);
6439 tg3_switch_clocks(tp);
6441 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6443 err = tg3_reset_hw(tp, reset_phy);
6449 #define TG3_STAT_ADD32(PSTAT, REG) \
6450 do { u32 __val = tr32(REG); \
6451 (PSTAT)->low += __val; \
6452 if ((PSTAT)->low < __val) \
6453 (PSTAT)->high += 1; \
6456 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6458 struct tg3_hw_stats *sp = tp->hw_stats;
6460 if (!netif_carrier_ok(tp->dev))
6463 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6464 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6465 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6466 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6467 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6468 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6469 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6470 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6471 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6472 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6473 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6474 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6475 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6477 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6478 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6479 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6480 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6481 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6482 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6483 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6484 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6485 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6486 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6487 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6488 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6489 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6490 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6493 static void tg3_timer(unsigned long __opaque)
6495 struct tg3 *tp = (struct tg3 *) __opaque;
6500 spin_lock(&tp->lock);
6502 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6503 /* All of this garbage is because when using non-tagged
6504 * IRQ status the mailbox/status_block protocol the chip
6505 * uses with the cpu is race prone.
6507 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6508 tw32(GRC_LOCAL_CTRL,
6509 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6511 tw32(HOSTCC_MODE, tp->coalesce_mode |
6512 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6515 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6516 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6517 spin_unlock(&tp->lock);
6518 schedule_work(&tp->reset_task);
6523 /* This part only runs once per second. */
6524 if (!--tp->timer_counter) {
6525 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6526 tg3_periodic_fetch_stats(tp);
6528 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6532 mac_stat = tr32(MAC_STATUS);
6535 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6536 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6538 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6542 tg3_setup_phy(tp, 0);
6543 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6544 u32 mac_stat = tr32(MAC_STATUS);
6547 if (netif_carrier_ok(tp->dev) &&
6548 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6551 if (! netif_carrier_ok(tp->dev) &&
6552 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6553 MAC_STATUS_SIGNAL_DET))) {
6559 ~MAC_MODE_PORT_MODE_MASK));
6561 tw32_f(MAC_MODE, tp->mac_mode);
6563 tg3_setup_phy(tp, 0);
6565 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6566 tg3_serdes_parallel_detect(tp);
6568 tp->timer_counter = tp->timer_multiplier;
6571 /* Heartbeat is only sent once every 2 seconds. */
6572 if (!--tp->asf_counter) {
6573 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6576 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6577 FWCMD_NICDRV_ALIVE2);
6578 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6579 /* 5 seconds timeout */
6580 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6581 val = tr32(GRC_RX_CPU_EVENT);
6583 tw32(GRC_RX_CPU_EVENT, val);
6585 tp->asf_counter = tp->asf_multiplier;
6588 spin_unlock(&tp->lock);
6591 tp->timer.expires = jiffies + tp->timer_offset;
6592 add_timer(&tp->timer);
6595 static int tg3_request_irq(struct tg3 *tp)
6597 irqreturn_t (*fn)(int, void *, struct pt_regs *);
6598 unsigned long flags;
6599 struct net_device *dev = tp->dev;
6601 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6603 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6605 flags = SA_SAMPLE_RANDOM;
6608 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6609 fn = tg3_interrupt_tagged;
6610 flags = SA_SHIRQ | SA_SAMPLE_RANDOM;
6612 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6615 static int tg3_test_interrupt(struct tg3 *tp)
6617 struct net_device *dev = tp->dev;
6621 if (!netif_running(dev))
6624 tg3_disable_ints(tp);
6626 free_irq(tp->pdev->irq, dev);
6628 err = request_irq(tp->pdev->irq, tg3_test_isr,
6629 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6633 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6634 tg3_enable_ints(tp);
6636 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6639 for (i = 0; i < 5; i++) {
6640 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6647 tg3_disable_ints(tp);
6649 free_irq(tp->pdev->irq, dev);
6651 err = tg3_request_irq(tp);
6662 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6663 * successfully restored
6665 static int tg3_test_msi(struct tg3 *tp)
6667 struct net_device *dev = tp->dev;
6671 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6674 /* Turn off SERR reporting in case MSI terminates with Master
6677 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6678 pci_write_config_word(tp->pdev, PCI_COMMAND,
6679 pci_cmd & ~PCI_COMMAND_SERR);
6681 err = tg3_test_interrupt(tp);
6683 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6688 /* other failures */
6692 /* MSI test failed, go back to INTx mode */
6693 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6694 "switching to INTx mode. Please report this failure to "
6695 "the PCI maintainer and include system chipset information.\n",
6698 free_irq(tp->pdev->irq, dev);
6699 pci_disable_msi(tp->pdev);
6701 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6703 err = tg3_request_irq(tp);
6707 /* Need to reset the chip because the MSI cycle may have terminated
6708 * with Master Abort.
6710 tg3_full_lock(tp, 1);
6712 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6713 err = tg3_init_hw(tp, 1);
6715 tg3_full_unlock(tp);
6718 free_irq(tp->pdev->irq, dev);
6723 static int tg3_open(struct net_device *dev)
6725 struct tg3 *tp = netdev_priv(dev);
6728 tg3_full_lock(tp, 0);
6730 err = tg3_set_power_state(tp, PCI_D0);
6734 tg3_disable_ints(tp);
6735 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6737 tg3_full_unlock(tp);
6739 /* The placement of this call is tied
6740 * to the setup and use of Host TX descriptors.
6742 err = tg3_alloc_consistent(tp);
6746 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6747 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6748 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
6749 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
6750 (tp->pdev_peer == tp->pdev))) {
6751 /* All MSI supporting chips should support tagged
6752 * status. Assert that this is the case.
6754 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6755 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6756 "Not using MSI.\n", tp->dev->name);
6757 } else if (pci_enable_msi(tp->pdev) == 0) {
6760 msi_mode = tr32(MSGINT_MODE);
6761 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6762 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6765 err = tg3_request_irq(tp);
6768 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6769 pci_disable_msi(tp->pdev);
6770 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6772 tg3_free_consistent(tp);
6776 tg3_full_lock(tp, 0);
6778 err = tg3_init_hw(tp, 1);
6780 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6783 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6784 tp->timer_offset = HZ;
6786 tp->timer_offset = HZ / 10;
6788 BUG_ON(tp->timer_offset > HZ);
6789 tp->timer_counter = tp->timer_multiplier =
6790 (HZ / tp->timer_offset);
6791 tp->asf_counter = tp->asf_multiplier =
6792 ((HZ / tp->timer_offset) * 2);
6794 init_timer(&tp->timer);
6795 tp->timer.expires = jiffies + tp->timer_offset;
6796 tp->timer.data = (unsigned long) tp;
6797 tp->timer.function = tg3_timer;
6800 tg3_full_unlock(tp);
6803 free_irq(tp->pdev->irq, dev);
6804 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6805 pci_disable_msi(tp->pdev);
6806 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6808 tg3_free_consistent(tp);
6812 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6813 err = tg3_test_msi(tp);
6816 tg3_full_lock(tp, 0);
6818 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6819 pci_disable_msi(tp->pdev);
6820 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6822 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6824 tg3_free_consistent(tp);
6826 tg3_full_unlock(tp);
6831 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6832 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
6833 u32 val = tr32(0x7c04);
6835 tw32(0x7c04, val | (1 << 29));
6840 tg3_full_lock(tp, 0);
6842 add_timer(&tp->timer);
6843 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6844 tg3_enable_ints(tp);
6846 tg3_full_unlock(tp);
6848 netif_start_queue(dev);
6854 /*static*/ void tg3_dump_state(struct tg3 *tp)
6856 u32 val32, val32_2, val32_3, val32_4, val32_5;
6860 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6861 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6862 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6866 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6867 tr32(MAC_MODE), tr32(MAC_STATUS));
6868 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6869 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6870 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6871 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6872 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6873 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6875 /* Send data initiator control block */
6876 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6877 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6878 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6879 tr32(SNDDATAI_STATSCTRL));
6881 /* Send data completion control block */
6882 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6884 /* Send BD ring selector block */
6885 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6886 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6888 /* Send BD initiator control block */
6889 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6890 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6892 /* Send BD completion control block */
6893 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6895 /* Receive list placement control block */
6896 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6897 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6898 printk(" RCVLPC_STATSCTRL[%08x]\n",
6899 tr32(RCVLPC_STATSCTRL));
6901 /* Receive data and receive BD initiator control block */
6902 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6903 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6905 /* Receive data completion control block */
6906 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6909 /* Receive BD initiator control block */
6910 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6911 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6913 /* Receive BD completion control block */
6914 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6915 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6917 /* Receive list selector control block */
6918 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6919 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6921 /* Mbuf cluster free block */
6922 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6923 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6925 /* Host coalescing control block */
6926 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6927 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6928 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6929 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6930 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6931 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6932 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6933 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6934 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6935 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6936 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6937 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6939 /* Memory arbiter control block */
6940 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6941 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6943 /* Buffer manager control block */
6944 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6945 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6946 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6947 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6948 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6949 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6950 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6951 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6953 /* Read DMA control block */
6954 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6955 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6957 /* Write DMA control block */
6958 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6959 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6961 /* DMA completion block */
6962 printk("DEBUG: DMAC_MODE[%08x]\n",
6966 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6967 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6968 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6969 tr32(GRC_LOCAL_CTRL));
6972 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6973 tr32(RCVDBDI_JUMBO_BD + 0x0),
6974 tr32(RCVDBDI_JUMBO_BD + 0x4),
6975 tr32(RCVDBDI_JUMBO_BD + 0x8),
6976 tr32(RCVDBDI_JUMBO_BD + 0xc));
6977 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6978 tr32(RCVDBDI_STD_BD + 0x0),
6979 tr32(RCVDBDI_STD_BD + 0x4),
6980 tr32(RCVDBDI_STD_BD + 0x8),
6981 tr32(RCVDBDI_STD_BD + 0xc));
6982 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6983 tr32(RCVDBDI_MINI_BD + 0x0),
6984 tr32(RCVDBDI_MINI_BD + 0x4),
6985 tr32(RCVDBDI_MINI_BD + 0x8),
6986 tr32(RCVDBDI_MINI_BD + 0xc));
6988 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6989 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6990 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6991 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6992 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6993 val32, val32_2, val32_3, val32_4);
6995 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6996 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6997 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6998 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6999 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7000 val32, val32_2, val32_3, val32_4);
7002 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7003 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7004 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7005 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7006 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7007 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7008 val32, val32_2, val32_3, val32_4, val32_5);
7010 /* SW status block */
7011 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7012 tp->hw_status->status,
7013 tp->hw_status->status_tag,
7014 tp->hw_status->rx_jumbo_consumer,
7015 tp->hw_status->rx_consumer,
7016 tp->hw_status->rx_mini_consumer,
7017 tp->hw_status->idx[0].rx_producer,
7018 tp->hw_status->idx[0].tx_consumer);
7020 /* SW statistics block */
7021 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7022 ((u32 *)tp->hw_stats)[0],
7023 ((u32 *)tp->hw_stats)[1],
7024 ((u32 *)tp->hw_stats)[2],
7025 ((u32 *)tp->hw_stats)[3]);
7028 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7029 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7030 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7031 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7032 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7034 /* NIC side send descriptors. */
7035 for (i = 0; i < 6; i++) {
7038 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7039 + (i * sizeof(struct tg3_tx_buffer_desc));
7040 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7042 readl(txd + 0x0), readl(txd + 0x4),
7043 readl(txd + 0x8), readl(txd + 0xc));
7046 /* NIC side RX descriptors. */
7047 for (i = 0; i < 6; i++) {
7050 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7051 + (i * sizeof(struct tg3_rx_buffer_desc));
7052 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7054 readl(rxd + 0x0), readl(rxd + 0x4),
7055 readl(rxd + 0x8), readl(rxd + 0xc));
7056 rxd += (4 * sizeof(u32));
7057 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7059 readl(rxd + 0x0), readl(rxd + 0x4),
7060 readl(rxd + 0x8), readl(rxd + 0xc));
7063 for (i = 0; i < 6; i++) {
7066 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7067 + (i * sizeof(struct tg3_rx_buffer_desc));
7068 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7070 readl(rxd + 0x0), readl(rxd + 0x4),
7071 readl(rxd + 0x8), readl(rxd + 0xc));
7072 rxd += (4 * sizeof(u32));
7073 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7075 readl(rxd + 0x0), readl(rxd + 0x4),
7076 readl(rxd + 0x8), readl(rxd + 0xc));
7081 static struct net_device_stats *tg3_get_stats(struct net_device *);
7082 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7084 static int tg3_close(struct net_device *dev)
7086 struct tg3 *tp = netdev_priv(dev);
7088 /* Calling flush_scheduled_work() may deadlock because
7089 * linkwatch_event() may be on the workqueue and it will try to get
7090 * the rtnl_lock which we are holding.
7092 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7095 netif_stop_queue(dev);
7097 del_timer_sync(&tp->timer);
7099 tg3_full_lock(tp, 1);
7104 tg3_disable_ints(tp);
7106 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7109 ~(TG3_FLAG_INIT_COMPLETE |
7110 TG3_FLAG_GOT_SERDES_FLOWCTL);
7112 tg3_full_unlock(tp);
7114 free_irq(tp->pdev->irq, dev);
7115 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7116 pci_disable_msi(tp->pdev);
7117 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7120 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7121 sizeof(tp->net_stats_prev));
7122 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7123 sizeof(tp->estats_prev));
7125 tg3_free_consistent(tp);
7127 tg3_set_power_state(tp, PCI_D3hot);
7129 netif_carrier_off(tp->dev);
7134 static inline unsigned long get_stat64(tg3_stat64_t *val)
7138 #if (BITS_PER_LONG == 32)
7141 ret = ((u64)val->high << 32) | ((u64)val->low);
7146 static unsigned long calc_crc_errors(struct tg3 *tp)
7148 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7150 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7151 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7155 spin_lock_bh(&tp->lock);
7156 if (!tg3_readphy(tp, 0x1e, &val)) {
7157 tg3_writephy(tp, 0x1e, val | 0x8000);
7158 tg3_readphy(tp, 0x14, &val);
7161 spin_unlock_bh(&tp->lock);
7163 tp->phy_crc_errors += val;
7165 return tp->phy_crc_errors;
7168 return get_stat64(&hw_stats->rx_fcs_errors);
7171 #define ESTAT_ADD(member) \
7172 estats->member = old_estats->member + \
7173 get_stat64(&hw_stats->member)
7175 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7177 struct tg3_ethtool_stats *estats = &tp->estats;
7178 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7179 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7184 ESTAT_ADD(rx_octets);
7185 ESTAT_ADD(rx_fragments);
7186 ESTAT_ADD(rx_ucast_packets);
7187 ESTAT_ADD(rx_mcast_packets);
7188 ESTAT_ADD(rx_bcast_packets);
7189 ESTAT_ADD(rx_fcs_errors);
7190 ESTAT_ADD(rx_align_errors);
7191 ESTAT_ADD(rx_xon_pause_rcvd);
7192 ESTAT_ADD(rx_xoff_pause_rcvd);
7193 ESTAT_ADD(rx_mac_ctrl_rcvd);
7194 ESTAT_ADD(rx_xoff_entered);
7195 ESTAT_ADD(rx_frame_too_long_errors);
7196 ESTAT_ADD(rx_jabbers);
7197 ESTAT_ADD(rx_undersize_packets);
7198 ESTAT_ADD(rx_in_length_errors);
7199 ESTAT_ADD(rx_out_length_errors);
7200 ESTAT_ADD(rx_64_or_less_octet_packets);
7201 ESTAT_ADD(rx_65_to_127_octet_packets);
7202 ESTAT_ADD(rx_128_to_255_octet_packets);
7203 ESTAT_ADD(rx_256_to_511_octet_packets);
7204 ESTAT_ADD(rx_512_to_1023_octet_packets);
7205 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7206 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7207 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7208 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7209 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7211 ESTAT_ADD(tx_octets);
7212 ESTAT_ADD(tx_collisions);
7213 ESTAT_ADD(tx_xon_sent);
7214 ESTAT_ADD(tx_xoff_sent);
7215 ESTAT_ADD(tx_flow_control);
7216 ESTAT_ADD(tx_mac_errors);
7217 ESTAT_ADD(tx_single_collisions);
7218 ESTAT_ADD(tx_mult_collisions);
7219 ESTAT_ADD(tx_deferred);
7220 ESTAT_ADD(tx_excessive_collisions);
7221 ESTAT_ADD(tx_late_collisions);
7222 ESTAT_ADD(tx_collide_2times);
7223 ESTAT_ADD(tx_collide_3times);
7224 ESTAT_ADD(tx_collide_4times);
7225 ESTAT_ADD(tx_collide_5times);
7226 ESTAT_ADD(tx_collide_6times);
7227 ESTAT_ADD(tx_collide_7times);
7228 ESTAT_ADD(tx_collide_8times);
7229 ESTAT_ADD(tx_collide_9times);
7230 ESTAT_ADD(tx_collide_10times);
7231 ESTAT_ADD(tx_collide_11times);
7232 ESTAT_ADD(tx_collide_12times);
7233 ESTAT_ADD(tx_collide_13times);
7234 ESTAT_ADD(tx_collide_14times);
7235 ESTAT_ADD(tx_collide_15times);
7236 ESTAT_ADD(tx_ucast_packets);
7237 ESTAT_ADD(tx_mcast_packets);
7238 ESTAT_ADD(tx_bcast_packets);
7239 ESTAT_ADD(tx_carrier_sense_errors);
7240 ESTAT_ADD(tx_discards);
7241 ESTAT_ADD(tx_errors);
7243 ESTAT_ADD(dma_writeq_full);
7244 ESTAT_ADD(dma_write_prioq_full);
7245 ESTAT_ADD(rxbds_empty);
7246 ESTAT_ADD(rx_discards);
7247 ESTAT_ADD(rx_errors);
7248 ESTAT_ADD(rx_threshold_hit);
7250 ESTAT_ADD(dma_readq_full);
7251 ESTAT_ADD(dma_read_prioq_full);
7252 ESTAT_ADD(tx_comp_queue_full);
7254 ESTAT_ADD(ring_set_send_prod_index);
7255 ESTAT_ADD(ring_status_update);
7256 ESTAT_ADD(nic_irqs);
7257 ESTAT_ADD(nic_avoided_irqs);
7258 ESTAT_ADD(nic_tx_threshold_hit);
7263 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7265 struct tg3 *tp = netdev_priv(dev);
7266 struct net_device_stats *stats = &tp->net_stats;
7267 struct net_device_stats *old_stats = &tp->net_stats_prev;
7268 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7273 stats->rx_packets = old_stats->rx_packets +
7274 get_stat64(&hw_stats->rx_ucast_packets) +
7275 get_stat64(&hw_stats->rx_mcast_packets) +
7276 get_stat64(&hw_stats->rx_bcast_packets);
7278 stats->tx_packets = old_stats->tx_packets +
7279 get_stat64(&hw_stats->tx_ucast_packets) +
7280 get_stat64(&hw_stats->tx_mcast_packets) +
7281 get_stat64(&hw_stats->tx_bcast_packets);
7283 stats->rx_bytes = old_stats->rx_bytes +
7284 get_stat64(&hw_stats->rx_octets);
7285 stats->tx_bytes = old_stats->tx_bytes +
7286 get_stat64(&hw_stats->tx_octets);
7288 stats->rx_errors = old_stats->rx_errors +
7289 get_stat64(&hw_stats->rx_errors);
7290 stats->tx_errors = old_stats->tx_errors +
7291 get_stat64(&hw_stats->tx_errors) +
7292 get_stat64(&hw_stats->tx_mac_errors) +
7293 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7294 get_stat64(&hw_stats->tx_discards);
7296 stats->multicast = old_stats->multicast +
7297 get_stat64(&hw_stats->rx_mcast_packets);
7298 stats->collisions = old_stats->collisions +
7299 get_stat64(&hw_stats->tx_collisions);
7301 stats->rx_length_errors = old_stats->rx_length_errors +
7302 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7303 get_stat64(&hw_stats->rx_undersize_packets);
7305 stats->rx_over_errors = old_stats->rx_over_errors +
7306 get_stat64(&hw_stats->rxbds_empty);
7307 stats->rx_frame_errors = old_stats->rx_frame_errors +
7308 get_stat64(&hw_stats->rx_align_errors);
7309 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7310 get_stat64(&hw_stats->tx_discards);
7311 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7312 get_stat64(&hw_stats->tx_carrier_sense_errors);
7314 stats->rx_crc_errors = old_stats->rx_crc_errors +
7315 calc_crc_errors(tp);
7317 stats->rx_missed_errors = old_stats->rx_missed_errors +
7318 get_stat64(&hw_stats->rx_discards);
7323 static inline u32 calc_crc(unsigned char *buf, int len)
7331 for (j = 0; j < len; j++) {
7334 for (k = 0; k < 8; k++) {
7348 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7350 /* accept or reject all multicast frames */
7351 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7352 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7353 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7354 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7357 static void __tg3_set_rx_mode(struct net_device *dev)
7359 struct tg3 *tp = netdev_priv(dev);
7362 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7363 RX_MODE_KEEP_VLAN_TAG);
7365 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7368 #if TG3_VLAN_TAG_USED
7370 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7371 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7373 /* By definition, VLAN is disabled always in this
7376 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7377 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7380 if (dev->flags & IFF_PROMISC) {
7381 /* Promiscuous mode. */
7382 rx_mode |= RX_MODE_PROMISC;
7383 } else if (dev->flags & IFF_ALLMULTI) {
7384 /* Accept all multicast. */
7385 tg3_set_multi (tp, 1);
7386 } else if (dev->mc_count < 1) {
7387 /* Reject all multicast. */
7388 tg3_set_multi (tp, 0);
7390 /* Accept one or more multicast(s). */
7391 struct dev_mc_list *mclist;
7393 u32 mc_filter[4] = { 0, };
7398 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7399 i++, mclist = mclist->next) {
7401 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7403 regidx = (bit & 0x60) >> 5;
7405 mc_filter[regidx] |= (1 << bit);
7408 tw32(MAC_HASH_REG_0, mc_filter[0]);
7409 tw32(MAC_HASH_REG_1, mc_filter[1]);
7410 tw32(MAC_HASH_REG_2, mc_filter[2]);
7411 tw32(MAC_HASH_REG_3, mc_filter[3]);
7414 if (rx_mode != tp->rx_mode) {
7415 tp->rx_mode = rx_mode;
7416 tw32_f(MAC_RX_MODE, rx_mode);
7421 static void tg3_set_rx_mode(struct net_device *dev)
7423 struct tg3 *tp = netdev_priv(dev);
7425 if (!netif_running(dev))
7428 tg3_full_lock(tp, 0);
7429 __tg3_set_rx_mode(dev);
7430 tg3_full_unlock(tp);
7433 #define TG3_REGDUMP_LEN (32 * 1024)
7435 static int tg3_get_regs_len(struct net_device *dev)
7437 return TG3_REGDUMP_LEN;
7440 static void tg3_get_regs(struct net_device *dev,
7441 struct ethtool_regs *regs, void *_p)
7444 struct tg3 *tp = netdev_priv(dev);
7450 memset(p, 0, TG3_REGDUMP_LEN);
7452 if (tp->link_config.phy_is_low_power)
7455 tg3_full_lock(tp, 0);
7457 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7458 #define GET_REG32_LOOP(base,len) \
7459 do { p = (u32 *)(orig_p + (base)); \
7460 for (i = 0; i < len; i += 4) \
7461 __GET_REG32((base) + i); \
7463 #define GET_REG32_1(reg) \
7464 do { p = (u32 *)(orig_p + (reg)); \
7465 __GET_REG32((reg)); \
7468 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7469 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7470 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7471 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7472 GET_REG32_1(SNDDATAC_MODE);
7473 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7474 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7475 GET_REG32_1(SNDBDC_MODE);
7476 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7477 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7478 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7479 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7480 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7481 GET_REG32_1(RCVDCC_MODE);
7482 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7483 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7484 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7485 GET_REG32_1(MBFREE_MODE);
7486 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7487 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7488 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7489 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7490 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7491 GET_REG32_1(RX_CPU_MODE);
7492 GET_REG32_1(RX_CPU_STATE);
7493 GET_REG32_1(RX_CPU_PGMCTR);
7494 GET_REG32_1(RX_CPU_HWBKPT);
7495 GET_REG32_1(TX_CPU_MODE);
7496 GET_REG32_1(TX_CPU_STATE);
7497 GET_REG32_1(TX_CPU_PGMCTR);
7498 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7499 GET_REG32_LOOP(FTQ_RESET, 0x120);
7500 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7501 GET_REG32_1(DMAC_MODE);
7502 GET_REG32_LOOP(GRC_MODE, 0x4c);
7503 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7504 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7507 #undef GET_REG32_LOOP
7510 tg3_full_unlock(tp);
7513 static int tg3_get_eeprom_len(struct net_device *dev)
7515 struct tg3 *tp = netdev_priv(dev);
7517 return tp->nvram_size;
7520 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7521 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7523 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7525 struct tg3 *tp = netdev_priv(dev);
7528 u32 i, offset, len, val, b_offset, b_count;
7530 if (tp->link_config.phy_is_low_power)
7533 offset = eeprom->offset;
7537 eeprom->magic = TG3_EEPROM_MAGIC;
7540 /* adjustments to start on required 4 byte boundary */
7541 b_offset = offset & 3;
7542 b_count = 4 - b_offset;
7543 if (b_count > len) {
7544 /* i.e. offset=1 len=2 */
7547 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7550 val = cpu_to_le32(val);
7551 memcpy(data, ((char*)&val) + b_offset, b_count);
7554 eeprom->len += b_count;
7557 /* read bytes upto the last 4 byte boundary */
7558 pd = &data[eeprom->len];
7559 for (i = 0; i < (len - (len & 3)); i += 4) {
7560 ret = tg3_nvram_read(tp, offset + i, &val);
7565 val = cpu_to_le32(val);
7566 memcpy(pd + i, &val, 4);
7571 /* read last bytes not ending on 4 byte boundary */
7572 pd = &data[eeprom->len];
7574 b_offset = offset + len - b_count;
7575 ret = tg3_nvram_read(tp, b_offset, &val);
7578 val = cpu_to_le32(val);
7579 memcpy(pd, ((char*)&val), b_count);
7580 eeprom->len += b_count;
7585 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7587 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7589 struct tg3 *tp = netdev_priv(dev);
7591 u32 offset, len, b_offset, odd_len, start, end;
7594 if (tp->link_config.phy_is_low_power)
7597 if (eeprom->magic != TG3_EEPROM_MAGIC)
7600 offset = eeprom->offset;
7603 if ((b_offset = (offset & 3))) {
7604 /* adjustments to start on required 4 byte boundary */
7605 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7608 start = cpu_to_le32(start);
7617 /* adjustments to end on required 4 byte boundary */
7619 len = (len + 3) & ~3;
7620 ret = tg3_nvram_read(tp, offset+len-4, &end);
7623 end = cpu_to_le32(end);
7627 if (b_offset || odd_len) {
7628 buf = kmalloc(len, GFP_KERNEL);
7632 memcpy(buf, &start, 4);
7634 memcpy(buf+len-4, &end, 4);
7635 memcpy(buf + b_offset, data, eeprom->len);
7638 ret = tg3_nvram_write_block(tp, offset, len, buf);
7646 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7648 struct tg3 *tp = netdev_priv(dev);
7650 cmd->supported = (SUPPORTED_Autoneg);
7652 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7653 cmd->supported |= (SUPPORTED_1000baseT_Half |
7654 SUPPORTED_1000baseT_Full);
7656 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
7657 cmd->supported |= (SUPPORTED_100baseT_Half |
7658 SUPPORTED_100baseT_Full |
7659 SUPPORTED_10baseT_Half |
7660 SUPPORTED_10baseT_Full |
7663 cmd->supported |= SUPPORTED_FIBRE;
7665 cmd->advertising = tp->link_config.advertising;
7666 if (netif_running(dev)) {
7667 cmd->speed = tp->link_config.active_speed;
7668 cmd->duplex = tp->link_config.active_duplex;
7671 cmd->phy_address = PHY_ADDR;
7672 cmd->transceiver = 0;
7673 cmd->autoneg = tp->link_config.autoneg;
7679 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7681 struct tg3 *tp = netdev_priv(dev);
7683 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7684 /* These are the only valid advertisement bits allowed. */
7685 if (cmd->autoneg == AUTONEG_ENABLE &&
7686 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7687 ADVERTISED_1000baseT_Full |
7688 ADVERTISED_Autoneg |
7691 /* Fiber can only do SPEED_1000. */
7692 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7693 (cmd->speed != SPEED_1000))
7695 /* Copper cannot force SPEED_1000. */
7696 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7697 (cmd->speed == SPEED_1000))
7699 else if ((cmd->speed == SPEED_1000) &&
7700 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7703 tg3_full_lock(tp, 0);
7705 tp->link_config.autoneg = cmd->autoneg;
7706 if (cmd->autoneg == AUTONEG_ENABLE) {
7707 tp->link_config.advertising = cmd->advertising;
7708 tp->link_config.speed = SPEED_INVALID;
7709 tp->link_config.duplex = DUPLEX_INVALID;
7711 tp->link_config.advertising = 0;
7712 tp->link_config.speed = cmd->speed;
7713 tp->link_config.duplex = cmd->duplex;
7716 if (netif_running(dev))
7717 tg3_setup_phy(tp, 1);
7719 tg3_full_unlock(tp);
7724 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7726 struct tg3 *tp = netdev_priv(dev);
7728 strcpy(info->driver, DRV_MODULE_NAME);
7729 strcpy(info->version, DRV_MODULE_VERSION);
7730 strcpy(info->fw_version, tp->fw_ver);
7731 strcpy(info->bus_info, pci_name(tp->pdev));
7734 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7736 struct tg3 *tp = netdev_priv(dev);
7738 wol->supported = WAKE_MAGIC;
7740 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7741 wol->wolopts = WAKE_MAGIC;
7742 memset(&wol->sopass, 0, sizeof(wol->sopass));
7745 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7747 struct tg3 *tp = netdev_priv(dev);
7749 if (wol->wolopts & ~WAKE_MAGIC)
7751 if ((wol->wolopts & WAKE_MAGIC) &&
7752 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7753 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7756 spin_lock_bh(&tp->lock);
7757 if (wol->wolopts & WAKE_MAGIC)
7758 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7760 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7761 spin_unlock_bh(&tp->lock);
7766 static u32 tg3_get_msglevel(struct net_device *dev)
7768 struct tg3 *tp = netdev_priv(dev);
7769 return tp->msg_enable;
7772 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7774 struct tg3 *tp = netdev_priv(dev);
7775 tp->msg_enable = value;
7778 #if TG3_TSO_SUPPORT != 0
7779 static int tg3_set_tso(struct net_device *dev, u32 value)
7781 struct tg3 *tp = netdev_priv(dev);
7783 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7788 return ethtool_op_set_tso(dev, value);
7792 static int tg3_nway_reset(struct net_device *dev)
7794 struct tg3 *tp = netdev_priv(dev);
7798 if (!netif_running(dev))
7801 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7804 spin_lock_bh(&tp->lock);
7806 tg3_readphy(tp, MII_BMCR, &bmcr);
7807 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7808 ((bmcr & BMCR_ANENABLE) ||
7809 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7810 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7814 spin_unlock_bh(&tp->lock);
7819 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7821 struct tg3 *tp = netdev_priv(dev);
7823 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7824 ering->rx_mini_max_pending = 0;
7825 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7826 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7828 ering->rx_jumbo_max_pending = 0;
7830 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
7832 ering->rx_pending = tp->rx_pending;
7833 ering->rx_mini_pending = 0;
7834 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
7835 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7837 ering->rx_jumbo_pending = 0;
7839 ering->tx_pending = tp->tx_pending;
7842 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7844 struct tg3 *tp = netdev_priv(dev);
7847 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7848 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7849 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7852 if (netif_running(dev)) {
7857 tg3_full_lock(tp, irq_sync);
7859 tp->rx_pending = ering->rx_pending;
7861 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7862 tp->rx_pending > 63)
7863 tp->rx_pending = 63;
7864 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7865 tp->tx_pending = ering->tx_pending;
7867 if (netif_running(dev)) {
7868 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7870 tg3_netif_start(tp);
7873 tg3_full_unlock(tp);
7878 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7880 struct tg3 *tp = netdev_priv(dev);
7882 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7883 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7884 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7887 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7889 struct tg3 *tp = netdev_priv(dev);
7892 if (netif_running(dev)) {
7897 tg3_full_lock(tp, irq_sync);
7899 if (epause->autoneg)
7900 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7902 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7903 if (epause->rx_pause)
7904 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7906 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7907 if (epause->tx_pause)
7908 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7910 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7912 if (netif_running(dev)) {
7913 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7915 tg3_netif_start(tp);
7918 tg3_full_unlock(tp);
7923 static u32 tg3_get_rx_csum(struct net_device *dev)
7925 struct tg3 *tp = netdev_priv(dev);
7926 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7929 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7931 struct tg3 *tp = netdev_priv(dev);
7933 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7939 spin_lock_bh(&tp->lock);
7941 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7943 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7944 spin_unlock_bh(&tp->lock);
7949 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7951 struct tg3 *tp = netdev_priv(dev);
7953 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7959 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7960 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7961 ethtool_op_set_tx_hw_csum(dev, data);
7963 ethtool_op_set_tx_csum(dev, data);
7968 static int tg3_get_stats_count (struct net_device *dev)
7970 return TG3_NUM_STATS;
7973 static int tg3_get_test_count (struct net_device *dev)
7975 return TG3_NUM_TEST;
7978 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7980 switch (stringset) {
7982 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
7985 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
7988 WARN_ON(1); /* we need a WARN() */
7993 static int tg3_phys_id(struct net_device *dev, u32 data)
7995 struct tg3 *tp = netdev_priv(dev);
7998 if (!netif_running(tp->dev))
8004 for (i = 0; i < (data * 2); i++) {
8006 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8007 LED_CTRL_1000MBPS_ON |
8008 LED_CTRL_100MBPS_ON |
8009 LED_CTRL_10MBPS_ON |
8010 LED_CTRL_TRAFFIC_OVERRIDE |
8011 LED_CTRL_TRAFFIC_BLINK |
8012 LED_CTRL_TRAFFIC_LED);
8015 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8016 LED_CTRL_TRAFFIC_OVERRIDE);
8018 if (msleep_interruptible(500))
8021 tw32(MAC_LED_CTRL, tp->led_ctrl);
8025 static void tg3_get_ethtool_stats (struct net_device *dev,
8026 struct ethtool_stats *estats, u64 *tmp_stats)
8028 struct tg3 *tp = netdev_priv(dev);
8029 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8032 #define NVRAM_TEST_SIZE 0x100
8033 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8035 static int tg3_test_nvram(struct tg3 *tp)
8037 u32 *buf, csum, magic;
8038 int i, j, err = 0, size;
8040 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8043 if (magic == TG3_EEPROM_MAGIC)
8044 size = NVRAM_TEST_SIZE;
8045 else if ((magic & 0xff000000) == 0xa5000000) {
8046 if ((magic & 0xe00000) == 0x200000)
8047 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8053 buf = kmalloc(size, GFP_KERNEL);
8058 for (i = 0, j = 0; i < size; i += 4, j++) {
8061 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8063 buf[j] = cpu_to_le32(val);
8068 /* Selfboot format */
8069 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
8070 u8 *buf8 = (u8 *) buf, csum8 = 0;
8072 for (i = 0; i < size; i++)
8084 /* Bootstrap checksum at offset 0x10 */
8085 csum = calc_crc((unsigned char *) buf, 0x10);
8086 if(csum != cpu_to_le32(buf[0x10/4]))
8089 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8090 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8091 if (csum != cpu_to_le32(buf[0xfc/4]))
8101 #define TG3_SERDES_TIMEOUT_SEC 2
8102 #define TG3_COPPER_TIMEOUT_SEC 6
8104 static int tg3_test_link(struct tg3 *tp)
8108 if (!netif_running(tp->dev))
8111 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8112 max = TG3_SERDES_TIMEOUT_SEC;
8114 max = TG3_COPPER_TIMEOUT_SEC;
8116 for (i = 0; i < max; i++) {
8117 if (netif_carrier_ok(tp->dev))
8120 if (msleep_interruptible(1000))
8127 /* Only test the commonly used registers */
8128 static int tg3_test_registers(struct tg3 *tp)
8131 u32 offset, read_mask, write_mask, val, save_val, read_val;
8135 #define TG3_FL_5705 0x1
8136 #define TG3_FL_NOT_5705 0x2
8137 #define TG3_FL_NOT_5788 0x4
8141 /* MAC Control Registers */
8142 { MAC_MODE, TG3_FL_NOT_5705,
8143 0x00000000, 0x00ef6f8c },
8144 { MAC_MODE, TG3_FL_5705,
8145 0x00000000, 0x01ef6b8c },
8146 { MAC_STATUS, TG3_FL_NOT_5705,
8147 0x03800107, 0x00000000 },
8148 { MAC_STATUS, TG3_FL_5705,
8149 0x03800100, 0x00000000 },
8150 { MAC_ADDR_0_HIGH, 0x0000,
8151 0x00000000, 0x0000ffff },
8152 { MAC_ADDR_0_LOW, 0x0000,
8153 0x00000000, 0xffffffff },
8154 { MAC_RX_MTU_SIZE, 0x0000,
8155 0x00000000, 0x0000ffff },
8156 { MAC_TX_MODE, 0x0000,
8157 0x00000000, 0x00000070 },
8158 { MAC_TX_LENGTHS, 0x0000,
8159 0x00000000, 0x00003fff },
8160 { MAC_RX_MODE, TG3_FL_NOT_5705,
8161 0x00000000, 0x000007fc },
8162 { MAC_RX_MODE, TG3_FL_5705,
8163 0x00000000, 0x000007dc },
8164 { MAC_HASH_REG_0, 0x0000,
8165 0x00000000, 0xffffffff },
8166 { MAC_HASH_REG_1, 0x0000,
8167 0x00000000, 0xffffffff },
8168 { MAC_HASH_REG_2, 0x0000,
8169 0x00000000, 0xffffffff },
8170 { MAC_HASH_REG_3, 0x0000,
8171 0x00000000, 0xffffffff },
8173 /* Receive Data and Receive BD Initiator Control Registers. */
8174 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8175 0x00000000, 0xffffffff },
8176 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8177 0x00000000, 0xffffffff },
8178 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8179 0x00000000, 0x00000003 },
8180 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8181 0x00000000, 0xffffffff },
8182 { RCVDBDI_STD_BD+0, 0x0000,
8183 0x00000000, 0xffffffff },
8184 { RCVDBDI_STD_BD+4, 0x0000,
8185 0x00000000, 0xffffffff },
8186 { RCVDBDI_STD_BD+8, 0x0000,
8187 0x00000000, 0xffff0002 },
8188 { RCVDBDI_STD_BD+0xc, 0x0000,
8189 0x00000000, 0xffffffff },
8191 /* Receive BD Initiator Control Registers. */
8192 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8193 0x00000000, 0xffffffff },
8194 { RCVBDI_STD_THRESH, TG3_FL_5705,
8195 0x00000000, 0x000003ff },
8196 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8197 0x00000000, 0xffffffff },
8199 /* Host Coalescing Control Registers. */
8200 { HOSTCC_MODE, TG3_FL_NOT_5705,
8201 0x00000000, 0x00000004 },
8202 { HOSTCC_MODE, TG3_FL_5705,
8203 0x00000000, 0x000000f6 },
8204 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8205 0x00000000, 0xffffffff },
8206 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8207 0x00000000, 0x000003ff },
8208 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8209 0x00000000, 0xffffffff },
8210 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8211 0x00000000, 0x000003ff },
8212 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8213 0x00000000, 0xffffffff },
8214 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8215 0x00000000, 0x000000ff },
8216 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8217 0x00000000, 0xffffffff },
8218 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8219 0x00000000, 0x000000ff },
8220 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8221 0x00000000, 0xffffffff },
8222 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8223 0x00000000, 0xffffffff },
8224 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8225 0x00000000, 0xffffffff },
8226 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8227 0x00000000, 0x000000ff },
8228 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8229 0x00000000, 0xffffffff },
8230 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8231 0x00000000, 0x000000ff },
8232 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8233 0x00000000, 0xffffffff },
8234 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8235 0x00000000, 0xffffffff },
8236 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8237 0x00000000, 0xffffffff },
8238 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8239 0x00000000, 0xffffffff },
8240 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8241 0x00000000, 0xffffffff },
8242 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8243 0xffffffff, 0x00000000 },
8244 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8245 0xffffffff, 0x00000000 },
8247 /* Buffer Manager Control Registers. */
8248 { BUFMGR_MB_POOL_ADDR, 0x0000,
8249 0x00000000, 0x007fff80 },
8250 { BUFMGR_MB_POOL_SIZE, 0x0000,
8251 0x00000000, 0x007fffff },
8252 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8253 0x00000000, 0x0000003f },
8254 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8255 0x00000000, 0x000001ff },
8256 { BUFMGR_MB_HIGH_WATER, 0x0000,
8257 0x00000000, 0x000001ff },
8258 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8259 0xffffffff, 0x00000000 },
8260 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8261 0xffffffff, 0x00000000 },
8263 /* Mailbox Registers */
8264 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8265 0x00000000, 0x000001ff },
8266 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8267 0x00000000, 0x000001ff },
8268 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8269 0x00000000, 0x000007ff },
8270 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8271 0x00000000, 0x000001ff },
8273 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8276 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8281 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8282 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8285 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8288 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8289 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8292 offset = (u32) reg_tbl[i].offset;
8293 read_mask = reg_tbl[i].read_mask;
8294 write_mask = reg_tbl[i].write_mask;
8296 /* Save the original register content */
8297 save_val = tr32(offset);
8299 /* Determine the read-only value. */
8300 read_val = save_val & read_mask;
8302 /* Write zero to the register, then make sure the read-only bits
8303 * are not changed and the read/write bits are all zeros.
8309 /* Test the read-only and read/write bits. */
8310 if (((val & read_mask) != read_val) || (val & write_mask))
8313 /* Write ones to all the bits defined by RdMask and WrMask, then
8314 * make sure the read-only bits are not changed and the
8315 * read/write bits are all ones.
8317 tw32(offset, read_mask | write_mask);
8321 /* Test the read-only bits. */
8322 if ((val & read_mask) != read_val)
8325 /* Test the read/write bits. */
8326 if ((val & write_mask) != write_mask)
8329 tw32(offset, save_val);
8335 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8336 tw32(offset, save_val);
8340 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8342 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8346 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8347 for (j = 0; j < len; j += 4) {
8350 tg3_write_mem(tp, offset + j, test_pattern[i]);
8351 tg3_read_mem(tp, offset + j, &val);
8352 if (val != test_pattern[i])
8359 static int tg3_test_memory(struct tg3 *tp)
8361 static struct mem_entry {
8364 } mem_tbl_570x[] = {
8365 { 0x00000000, 0x00b50},
8366 { 0x00002000, 0x1c000},
8367 { 0xffffffff, 0x00000}
8368 }, mem_tbl_5705[] = {
8369 { 0x00000100, 0x0000c},
8370 { 0x00000200, 0x00008},
8371 { 0x00004000, 0x00800},
8372 { 0x00006000, 0x01000},
8373 { 0x00008000, 0x02000},
8374 { 0x00010000, 0x0e000},
8375 { 0xffffffff, 0x00000}
8376 }, mem_tbl_5755[] = {
8377 { 0x00000200, 0x00008},
8378 { 0x00004000, 0x00800},
8379 { 0x00006000, 0x00800},
8380 { 0x00008000, 0x02000},
8381 { 0x00010000, 0x0c000},
8382 { 0xffffffff, 0x00000}
8384 struct mem_entry *mem_tbl;
8388 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8389 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8390 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8391 mem_tbl = mem_tbl_5755;
8393 mem_tbl = mem_tbl_5705;
8395 mem_tbl = mem_tbl_570x;
8397 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8398 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8399 mem_tbl[i].len)) != 0)
8406 #define TG3_MAC_LOOPBACK 0
8407 #define TG3_PHY_LOOPBACK 1
8409 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8411 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8413 struct sk_buff *skb, *rx_skb;
8416 int num_pkts, tx_len, rx_len, i, err;
8417 struct tg3_rx_buffer_desc *desc;
8419 if (loopback_mode == TG3_MAC_LOOPBACK) {
8420 /* HW errata - mac loopback fails in some cases on 5780.
8421 * Normal traffic and PHY loopback are not affected by
8424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8427 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8428 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8429 MAC_MODE_PORT_MODE_GMII;
8430 tw32(MAC_MODE, mac_mode);
8431 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8432 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8435 /* reset to prevent losing 1st rx packet intermittently */
8436 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8437 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8439 tw32_f(MAC_RX_MODE, tp->rx_mode);
8441 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8442 MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8443 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8444 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8445 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8446 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8448 tw32(MAC_MODE, mac_mode);
8456 skb = dev_alloc_skb(tx_len);
8460 tx_data = skb_put(skb, tx_len);
8461 memcpy(tx_data, tp->dev->dev_addr, 6);
8462 memset(tx_data + 6, 0x0, 8);
8464 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8466 for (i = 14; i < tx_len; i++)
8467 tx_data[i] = (u8) (i & 0xff);
8469 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8471 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8476 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8480 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8485 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8487 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8491 for (i = 0; i < 10; i++) {
8492 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8497 tx_idx = tp->hw_status->idx[0].tx_consumer;
8498 rx_idx = tp->hw_status->idx[0].rx_producer;
8499 if ((tx_idx == tp->tx_prod) &&
8500 (rx_idx == (rx_start_idx + num_pkts)))
8504 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8507 if (tx_idx != tp->tx_prod)
8510 if (rx_idx != rx_start_idx + num_pkts)
8513 desc = &tp->rx_rcb[rx_start_idx];
8514 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8515 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8516 if (opaque_key != RXD_OPAQUE_RING_STD)
8519 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8520 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8523 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8524 if (rx_len != tx_len)
8527 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8529 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8530 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8532 for (i = 14; i < tx_len; i++) {
8533 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8538 /* tg3_free_rings will unmap and free the rx_skb */
8543 #define TG3_MAC_LOOPBACK_FAILED 1
8544 #define TG3_PHY_LOOPBACK_FAILED 2
8545 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8546 TG3_PHY_LOOPBACK_FAILED)
8548 static int tg3_test_loopback(struct tg3 *tp)
8552 if (!netif_running(tp->dev))
8553 return TG3_LOOPBACK_FAILED;
8555 tg3_reset_hw(tp, 1);
8557 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8558 err |= TG3_MAC_LOOPBACK_FAILED;
8559 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8560 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8561 err |= TG3_PHY_LOOPBACK_FAILED;
8567 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8570 struct tg3 *tp = netdev_priv(dev);
8572 if (tp->link_config.phy_is_low_power)
8573 tg3_set_power_state(tp, PCI_D0);
8575 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8577 if (tg3_test_nvram(tp) != 0) {
8578 etest->flags |= ETH_TEST_FL_FAILED;
8581 if (tg3_test_link(tp) != 0) {
8582 etest->flags |= ETH_TEST_FL_FAILED;
8585 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8586 int err, irq_sync = 0;
8588 if (netif_running(dev)) {
8593 tg3_full_lock(tp, irq_sync);
8595 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8596 err = tg3_nvram_lock(tp);
8597 tg3_halt_cpu(tp, RX_CPU_BASE);
8598 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8599 tg3_halt_cpu(tp, TX_CPU_BASE);
8601 tg3_nvram_unlock(tp);
8603 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8606 if (tg3_test_registers(tp) != 0) {
8607 etest->flags |= ETH_TEST_FL_FAILED;
8610 if (tg3_test_memory(tp) != 0) {
8611 etest->flags |= ETH_TEST_FL_FAILED;
8614 if ((data[4] = tg3_test_loopback(tp)) != 0)
8615 etest->flags |= ETH_TEST_FL_FAILED;
8617 tg3_full_unlock(tp);
8619 if (tg3_test_interrupt(tp) != 0) {
8620 etest->flags |= ETH_TEST_FL_FAILED;
8624 tg3_full_lock(tp, 0);
8626 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8627 if (netif_running(dev)) {
8628 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8630 tg3_netif_start(tp);
8633 tg3_full_unlock(tp);
8635 if (tp->link_config.phy_is_low_power)
8636 tg3_set_power_state(tp, PCI_D3hot);
8640 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8642 struct mii_ioctl_data *data = if_mii(ifr);
8643 struct tg3 *tp = netdev_priv(dev);
8648 data->phy_id = PHY_ADDR;
8654 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8655 break; /* We have no PHY */
8657 if (tp->link_config.phy_is_low_power)
8660 spin_lock_bh(&tp->lock);
8661 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8662 spin_unlock_bh(&tp->lock);
8664 data->val_out = mii_regval;
8670 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8671 break; /* We have no PHY */
8673 if (!capable(CAP_NET_ADMIN))
8676 if (tp->link_config.phy_is_low_power)
8679 spin_lock_bh(&tp->lock);
8680 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8681 spin_unlock_bh(&tp->lock);
8692 #if TG3_VLAN_TAG_USED
8693 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8695 struct tg3 *tp = netdev_priv(dev);
8697 tg3_full_lock(tp, 0);
8701 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8702 __tg3_set_rx_mode(dev);
8704 tg3_full_unlock(tp);
8707 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8709 struct tg3 *tp = netdev_priv(dev);
8711 tg3_full_lock(tp, 0);
8713 tp->vlgrp->vlan_devices[vid] = NULL;
8714 tg3_full_unlock(tp);
8718 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8720 struct tg3 *tp = netdev_priv(dev);
8722 memcpy(ec, &tp->coal, sizeof(*ec));
8726 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8728 struct tg3 *tp = netdev_priv(dev);
8729 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8730 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8732 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8733 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8734 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8735 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8736 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8739 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8740 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8741 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8742 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8743 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8744 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8745 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8746 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8747 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8748 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8751 /* No rx interrupts will be generated if both are zero */
8752 if ((ec->rx_coalesce_usecs == 0) &&
8753 (ec->rx_max_coalesced_frames == 0))
8756 /* No tx interrupts will be generated if both are zero */
8757 if ((ec->tx_coalesce_usecs == 0) &&
8758 (ec->tx_max_coalesced_frames == 0))
8761 /* Only copy relevant parameters, ignore all others. */
8762 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8763 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8764 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8765 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8766 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8767 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8768 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8769 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8770 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8772 if (netif_running(dev)) {
8773 tg3_full_lock(tp, 0);
8774 __tg3_set_coalesce(tp, &tp->coal);
8775 tg3_full_unlock(tp);
8780 static struct ethtool_ops tg3_ethtool_ops = {
8781 .get_settings = tg3_get_settings,
8782 .set_settings = tg3_set_settings,
8783 .get_drvinfo = tg3_get_drvinfo,
8784 .get_regs_len = tg3_get_regs_len,
8785 .get_regs = tg3_get_regs,
8786 .get_wol = tg3_get_wol,
8787 .set_wol = tg3_set_wol,
8788 .get_msglevel = tg3_get_msglevel,
8789 .set_msglevel = tg3_set_msglevel,
8790 .nway_reset = tg3_nway_reset,
8791 .get_link = ethtool_op_get_link,
8792 .get_eeprom_len = tg3_get_eeprom_len,
8793 .get_eeprom = tg3_get_eeprom,
8794 .set_eeprom = tg3_set_eeprom,
8795 .get_ringparam = tg3_get_ringparam,
8796 .set_ringparam = tg3_set_ringparam,
8797 .get_pauseparam = tg3_get_pauseparam,
8798 .set_pauseparam = tg3_set_pauseparam,
8799 .get_rx_csum = tg3_get_rx_csum,
8800 .set_rx_csum = tg3_set_rx_csum,
8801 .get_tx_csum = ethtool_op_get_tx_csum,
8802 .set_tx_csum = tg3_set_tx_csum,
8803 .get_sg = ethtool_op_get_sg,
8804 .set_sg = ethtool_op_set_sg,
8805 #if TG3_TSO_SUPPORT != 0
8806 .get_tso = ethtool_op_get_tso,
8807 .set_tso = tg3_set_tso,
8809 .self_test_count = tg3_get_test_count,
8810 .self_test = tg3_self_test,
8811 .get_strings = tg3_get_strings,
8812 .phys_id = tg3_phys_id,
8813 .get_stats_count = tg3_get_stats_count,
8814 .get_ethtool_stats = tg3_get_ethtool_stats,
8815 .get_coalesce = tg3_get_coalesce,
8816 .set_coalesce = tg3_set_coalesce,
8817 .get_perm_addr = ethtool_op_get_perm_addr,
8820 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8822 u32 cursize, val, magic;
8824 tp->nvram_size = EEPROM_CHIP_SIZE;
8826 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8829 if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
8833 * Size the chip by reading offsets at increasing powers of two.
8834 * When we encounter our validation signature, we know the addressing
8835 * has wrapped around, and thus have our chip size.
8839 while (cursize < tp->nvram_size) {
8840 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
8849 tp->nvram_size = cursize;
8852 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8856 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
8859 /* Selfboot format */
8860 if (val != TG3_EEPROM_MAGIC) {
8861 tg3_get_eeprom_size(tp);
8865 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8867 tp->nvram_size = (val >> 16) * 1024;
8871 tp->nvram_size = 0x20000;
8874 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8878 nvcfg1 = tr32(NVRAM_CFG1);
8879 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8880 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8883 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8884 tw32(NVRAM_CFG1, nvcfg1);
8887 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8888 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8889 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8890 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8891 tp->nvram_jedecnum = JEDEC_ATMEL;
8892 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8893 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8895 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8896 tp->nvram_jedecnum = JEDEC_ATMEL;
8897 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8899 case FLASH_VENDOR_ATMEL_EEPROM:
8900 tp->nvram_jedecnum = JEDEC_ATMEL;
8901 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8902 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8904 case FLASH_VENDOR_ST:
8905 tp->nvram_jedecnum = JEDEC_ST;
8906 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8907 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8909 case FLASH_VENDOR_SAIFUN:
8910 tp->nvram_jedecnum = JEDEC_SAIFUN;
8911 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8913 case FLASH_VENDOR_SST_SMALL:
8914 case FLASH_VENDOR_SST_LARGE:
8915 tp->nvram_jedecnum = JEDEC_SST;
8916 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8921 tp->nvram_jedecnum = JEDEC_ATMEL;
8922 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8923 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8927 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8931 nvcfg1 = tr32(NVRAM_CFG1);
8933 /* NVRAM protection for TPM */
8934 if (nvcfg1 & (1 << 27))
8935 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8937 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8938 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8939 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8940 tp->nvram_jedecnum = JEDEC_ATMEL;
8941 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8943 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8944 tp->nvram_jedecnum = JEDEC_ATMEL;
8945 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8946 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8948 case FLASH_5752VENDOR_ST_M45PE10:
8949 case FLASH_5752VENDOR_ST_M45PE20:
8950 case FLASH_5752VENDOR_ST_M45PE40:
8951 tp->nvram_jedecnum = JEDEC_ST;
8952 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8953 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8957 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8958 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8959 case FLASH_5752PAGE_SIZE_256:
8960 tp->nvram_pagesize = 256;
8962 case FLASH_5752PAGE_SIZE_512:
8963 tp->nvram_pagesize = 512;
8965 case FLASH_5752PAGE_SIZE_1K:
8966 tp->nvram_pagesize = 1024;
8968 case FLASH_5752PAGE_SIZE_2K:
8969 tp->nvram_pagesize = 2048;
8971 case FLASH_5752PAGE_SIZE_4K:
8972 tp->nvram_pagesize = 4096;
8974 case FLASH_5752PAGE_SIZE_264:
8975 tp->nvram_pagesize = 264;
8980 /* For eeprom, set pagesize to maximum eeprom size */
8981 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8983 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8984 tw32(NVRAM_CFG1, nvcfg1);
8988 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
8992 nvcfg1 = tr32(NVRAM_CFG1);
8994 /* NVRAM protection for TPM */
8995 if (nvcfg1 & (1 << 27))
8996 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8998 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8999 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9000 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9001 tp->nvram_jedecnum = JEDEC_ATMEL;
9002 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9003 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9005 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9006 tw32(NVRAM_CFG1, nvcfg1);
9008 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9009 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9010 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9011 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9012 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9013 tp->nvram_jedecnum = JEDEC_ATMEL;
9014 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9015 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9016 tp->nvram_pagesize = 264;
9018 case FLASH_5752VENDOR_ST_M45PE10:
9019 case FLASH_5752VENDOR_ST_M45PE20:
9020 case FLASH_5752VENDOR_ST_M45PE40:
9021 tp->nvram_jedecnum = JEDEC_ST;
9022 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9023 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9024 tp->nvram_pagesize = 256;
9029 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9033 nvcfg1 = tr32(NVRAM_CFG1);
9035 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9036 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9037 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9038 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9039 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9040 tp->nvram_jedecnum = JEDEC_ATMEL;
9041 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9042 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9044 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9045 tw32(NVRAM_CFG1, nvcfg1);
9047 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9048 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9049 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9050 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9051 tp->nvram_jedecnum = JEDEC_ATMEL;
9052 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9053 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9054 tp->nvram_pagesize = 264;
9056 case FLASH_5752VENDOR_ST_M45PE10:
9057 case FLASH_5752VENDOR_ST_M45PE20:
9058 case FLASH_5752VENDOR_ST_M45PE40:
9059 tp->nvram_jedecnum = JEDEC_ST;
9060 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9061 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9062 tp->nvram_pagesize = 256;
9067 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9068 static void __devinit tg3_nvram_init(struct tg3 *tp)
9072 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
9075 tw32_f(GRC_EEPROM_ADDR,
9076 (EEPROM_ADDR_FSM_RESET |
9077 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9078 EEPROM_ADDR_CLKPERD_SHIFT)));
9080 /* XXX schedule_timeout() ... */
9081 for (j = 0; j < 100; j++)
9084 /* Enable seeprom accesses. */
9085 tw32_f(GRC_LOCAL_CTRL,
9086 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9089 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9090 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9091 tp->tg3_flags |= TG3_FLAG_NVRAM;
9093 if (tg3_nvram_lock(tp)) {
9094 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9095 "tg3_nvram_init failed.\n", tp->dev->name);
9098 tg3_enable_nvram_access(tp);
9100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9101 tg3_get_5752_nvram_info(tp);
9102 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9103 tg3_get_5755_nvram_info(tp);
9104 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9105 tg3_get_5787_nvram_info(tp);
9107 tg3_get_nvram_info(tp);
9109 tg3_get_nvram_size(tp);
9111 tg3_disable_nvram_access(tp);
9112 tg3_nvram_unlock(tp);
9115 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9117 tg3_get_eeprom_size(tp);
9121 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9122 u32 offset, u32 *val)
9127 if (offset > EEPROM_ADDR_ADDR_MASK ||
9131 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9132 EEPROM_ADDR_DEVID_MASK |
9134 tw32(GRC_EEPROM_ADDR,
9136 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9137 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9138 EEPROM_ADDR_ADDR_MASK) |
9139 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9141 for (i = 0; i < 10000; i++) {
9142 tmp = tr32(GRC_EEPROM_ADDR);
9144 if (tmp & EEPROM_ADDR_COMPLETE)
9148 if (!(tmp & EEPROM_ADDR_COMPLETE))
9151 *val = tr32(GRC_EEPROM_DATA);
9155 #define NVRAM_CMD_TIMEOUT 10000
9157 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9161 tw32(NVRAM_CMD, nvram_cmd);
9162 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9164 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9169 if (i == NVRAM_CMD_TIMEOUT) {
9175 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9177 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9178 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9179 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9180 (tp->nvram_jedecnum == JEDEC_ATMEL))
9182 addr = ((addr / tp->nvram_pagesize) <<
9183 ATMEL_AT45DB0X1B_PAGE_POS) +
9184 (addr % tp->nvram_pagesize);
9189 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9191 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9192 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9193 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9194 (tp->nvram_jedecnum == JEDEC_ATMEL))
9196 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9197 tp->nvram_pagesize) +
9198 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9203 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9207 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9208 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
9212 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9213 return tg3_nvram_read_using_eeprom(tp, offset, val);
9215 offset = tg3_nvram_phys_addr(tp, offset);
9217 if (offset > NVRAM_ADDR_MSK)
9220 ret = tg3_nvram_lock(tp);
9224 tg3_enable_nvram_access(tp);
9226 tw32(NVRAM_ADDR, offset);
9227 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9228 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9231 *val = swab32(tr32(NVRAM_RDDATA));
9233 tg3_disable_nvram_access(tp);
9235 tg3_nvram_unlock(tp);
9240 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9245 err = tg3_nvram_read(tp, offset, &tmp);
9250 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9251 u32 offset, u32 len, u8 *buf)
9256 for (i = 0; i < len; i += 4) {
9261 memcpy(&data, buf + i, 4);
9263 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9265 val = tr32(GRC_EEPROM_ADDR);
9266 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9268 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9270 tw32(GRC_EEPROM_ADDR, val |
9271 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9272 (addr & EEPROM_ADDR_ADDR_MASK) |
9276 for (j = 0; j < 10000; j++) {
9277 val = tr32(GRC_EEPROM_ADDR);
9279 if (val & EEPROM_ADDR_COMPLETE)
9283 if (!(val & EEPROM_ADDR_COMPLETE)) {
9292 /* offset and length are dword aligned */
9293 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9297 u32 pagesize = tp->nvram_pagesize;
9298 u32 pagemask = pagesize - 1;
9302 tmp = kmalloc(pagesize, GFP_KERNEL);
9308 u32 phy_addr, page_off, size;
9310 phy_addr = offset & ~pagemask;
9312 for (j = 0; j < pagesize; j += 4) {
9313 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9314 (u32 *) (tmp + j))))
9320 page_off = offset & pagemask;
9327 memcpy(tmp + page_off, buf, size);
9329 offset = offset + (pagesize - page_off);
9331 tg3_enable_nvram_access(tp);
9334 * Before we can erase the flash page, we need
9335 * to issue a special "write enable" command.
9337 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9339 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9342 /* Erase the target page */
9343 tw32(NVRAM_ADDR, phy_addr);
9345 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9346 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9348 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9351 /* Issue another write enable to start the write. */
9352 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9354 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9357 for (j = 0; j < pagesize; j += 4) {
9360 data = *((u32 *) (tmp + j));
9361 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9363 tw32(NVRAM_ADDR, phy_addr + j);
9365 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9369 nvram_cmd |= NVRAM_CMD_FIRST;
9370 else if (j == (pagesize - 4))
9371 nvram_cmd |= NVRAM_CMD_LAST;
9373 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9380 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9381 tg3_nvram_exec_cmd(tp, nvram_cmd);
9388 /* offset and length are dword aligned */
9389 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9394 for (i = 0; i < len; i += 4, offset += 4) {
9395 u32 data, page_off, phy_addr, nvram_cmd;
9397 memcpy(&data, buf + i, 4);
9398 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9400 page_off = offset % tp->nvram_pagesize;
9402 phy_addr = tg3_nvram_phys_addr(tp, offset);
9404 tw32(NVRAM_ADDR, phy_addr);
9406 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9408 if ((page_off == 0) || (i == 0))
9409 nvram_cmd |= NVRAM_CMD_FIRST;
9410 if (page_off == (tp->nvram_pagesize - 4))
9411 nvram_cmd |= NVRAM_CMD_LAST;
9414 nvram_cmd |= NVRAM_CMD_LAST;
9416 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9417 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9418 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9419 (tp->nvram_jedecnum == JEDEC_ST) &&
9420 (nvram_cmd & NVRAM_CMD_FIRST)) {
9422 if ((ret = tg3_nvram_exec_cmd(tp,
9423 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9428 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9429 /* We always do complete word writes to eeprom. */
9430 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9433 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9439 /* offset and length are dword aligned */
9440 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9444 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9445 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
9449 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9450 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9451 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9455 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9456 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9461 ret = tg3_nvram_lock(tp);
9465 tg3_enable_nvram_access(tp);
9466 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9467 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9468 tw32(NVRAM_WRITE1, 0x406);
9470 grc_mode = tr32(GRC_MODE);
9471 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9473 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9474 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9476 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9480 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9484 grc_mode = tr32(GRC_MODE);
9485 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9487 tg3_disable_nvram_access(tp);
9488 tg3_nvram_unlock(tp);
9491 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9492 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9499 struct subsys_tbl_ent {
9500 u16 subsys_vendor, subsys_devid;
9504 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9505 /* Broadcom boards. */
9506 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9507 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9508 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9509 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9510 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9511 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9512 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9513 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9514 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9515 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9516 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9519 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9520 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9521 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9522 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9523 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9526 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9527 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9528 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9529 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9531 /* Compaq boards. */
9532 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9533 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9534 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9535 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9536 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9539 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9542 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9546 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9547 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9548 tp->pdev->subsystem_vendor) &&
9549 (subsys_id_to_phy_id[i].subsys_devid ==
9550 tp->pdev->subsystem_device))
9551 return &subsys_id_to_phy_id[i];
9556 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9561 /* On some early chips the SRAM cannot be accessed in D3hot state,
9562 * so need make sure we're in D0.
9564 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9565 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9566 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9569 /* Make sure register accesses (indirect or otherwise)
9570 * will function correctly.
9572 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9573 tp->misc_host_ctrl);
9575 tp->phy_id = PHY_ID_INVALID;
9576 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9578 /* Do not even try poking around in here on Sun parts. */
9579 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9580 /* All SUN chips are built-in LOMs. */
9581 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9585 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9586 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9587 u32 nic_cfg, led_cfg;
9588 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9589 int eeprom_phy_serdes = 0;
9591 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9592 tp->nic_sram_data_cfg = nic_cfg;
9594 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9595 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9596 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9597 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9598 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9599 (ver > 0) && (ver < 0x100))
9600 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9602 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9603 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9604 eeprom_phy_serdes = 1;
9606 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9607 if (nic_phy_id != 0) {
9608 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9609 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9611 eeprom_phy_id = (id1 >> 16) << 10;
9612 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9613 eeprom_phy_id |= (id2 & 0x03ff) << 0;
9617 tp->phy_id = eeprom_phy_id;
9618 if (eeprom_phy_serdes) {
9619 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9620 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9622 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9625 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9626 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9627 SHASTA_EXT_LED_MODE_MASK);
9629 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9633 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9634 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9637 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9638 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9641 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9642 tp->led_ctrl = LED_CTRL_MODE_MAC;
9644 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9645 * read on some older 5700/5701 bootcode.
9647 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9649 GET_ASIC_REV(tp->pci_chip_rev_id) ==
9651 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9655 case SHASTA_EXT_LED_SHARED:
9656 tp->led_ctrl = LED_CTRL_MODE_SHARED;
9657 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9658 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9659 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9660 LED_CTRL_MODE_PHY_2);
9663 case SHASTA_EXT_LED_MAC:
9664 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9667 case SHASTA_EXT_LED_COMBO:
9668 tp->led_ctrl = LED_CTRL_MODE_COMBO;
9669 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9670 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9671 LED_CTRL_MODE_PHY_2);
9676 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9677 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9678 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9679 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9681 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9682 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9684 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9685 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9686 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9687 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9689 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9690 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9692 if (cfg2 & (1 << 17))
9693 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9695 /* serdes signal pre-emphasis in register 0x590 set by */
9696 /* bootcode if bit 18 is set */
9697 if (cfg2 & (1 << 18))
9698 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9702 static int __devinit tg3_phy_probe(struct tg3 *tp)
9704 u32 hw_phy_id_1, hw_phy_id_2;
9705 u32 hw_phy_id, hw_phy_id_masked;
9708 /* Reading the PHY ID register can conflict with ASF
9709 * firwmare access to the PHY hardware.
9712 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9713 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9715 /* Now read the physical PHY_ID from the chip and verify
9716 * that it is sane. If it doesn't look good, we fall back
9717 * to either the hard-coded table based PHY_ID and failing
9718 * that the value found in the eeprom area.
9720 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9721 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9723 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9724 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9725 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9727 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9730 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9731 tp->phy_id = hw_phy_id;
9732 if (hw_phy_id_masked == PHY_ID_BCM8002)
9733 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9735 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9737 if (tp->phy_id != PHY_ID_INVALID) {
9738 /* Do nothing, phy ID already set up in
9739 * tg3_get_eeprom_hw_cfg().
9742 struct subsys_tbl_ent *p;
9744 /* No eeprom signature? Try the hardcoded
9745 * subsys device table.
9747 p = lookup_by_subsys(tp);
9751 tp->phy_id = p->phy_id;
9753 tp->phy_id == PHY_ID_BCM8002)
9754 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9758 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9759 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9760 u32 bmsr, adv_reg, tg3_ctrl;
9762 tg3_readphy(tp, MII_BMSR, &bmsr);
9763 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9764 (bmsr & BMSR_LSTATUS))
9765 goto skip_phy_reset;
9767 err = tg3_phy_reset(tp);
9771 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9772 ADVERTISE_100HALF | ADVERTISE_100FULL |
9773 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9775 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9776 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9777 MII_TG3_CTRL_ADV_1000_FULL);
9778 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9779 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9780 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9781 MII_TG3_CTRL_ENABLE_AS_MASTER);
9784 if (!tg3_copper_is_advertising_all(tp)) {
9785 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9787 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9788 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9790 tg3_writephy(tp, MII_BMCR,
9791 BMCR_ANENABLE | BMCR_ANRESTART);
9793 tg3_phy_set_wirespeed(tp);
9795 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9796 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9797 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9801 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9802 err = tg3_init_5401phy_dsp(tp);
9807 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9808 err = tg3_init_5401phy_dsp(tp);
9811 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9812 tp->link_config.advertising =
9813 (ADVERTISED_1000baseT_Half |
9814 ADVERTISED_1000baseT_Full |
9815 ADVERTISED_Autoneg |
9817 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9818 tp->link_config.advertising &=
9819 ~(ADVERTISED_1000baseT_Half |
9820 ADVERTISED_1000baseT_Full);
9825 static void __devinit tg3_read_partno(struct tg3 *tp)
9827 unsigned char vpd_data[256];
9831 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9832 /* Sun decided not to put the necessary bits in the
9833 * NVRAM of their onboard tg3 parts :(
9835 strcpy(tp->board_part_number, "Sun 570X");
9839 if (tg3_nvram_read_swab(tp, 0x0, &magic))
9842 if (magic == TG3_EEPROM_MAGIC) {
9843 for (i = 0; i < 256; i += 4) {
9846 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9849 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9850 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9851 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9852 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9857 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
9858 for (i = 0; i < 256; i += 4) {
9862 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
9865 pci_read_config_word(tp->pdev, vpd_cap +
9866 PCI_VPD_ADDR, &tmp16);
9871 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
9873 tmp = cpu_to_le32(tmp);
9874 memcpy(&vpd_data[i], &tmp, 4);
9878 /* Now parse and find the part number. */
9879 for (i = 0; i < 256; ) {
9880 unsigned char val = vpd_data[i];
9883 if (val == 0x82 || val == 0x91) {
9886 (vpd_data[i + 2] << 8)));
9893 block_end = (i + 3 +
9895 (vpd_data[i + 2] << 8)));
9897 while (i < block_end) {
9898 if (vpd_data[i + 0] == 'P' &&
9899 vpd_data[i + 1] == 'N') {
9900 int partno_len = vpd_data[i + 2];
9902 if (partno_len > 24)
9905 memcpy(tp->board_part_number,
9914 /* Part number not found. */
9919 strcpy(tp->board_part_number, "none");
9922 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
9924 u32 val, offset, start;
9926 if (tg3_nvram_read_swab(tp, 0, &val))
9929 if (val != TG3_EEPROM_MAGIC)
9932 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
9933 tg3_nvram_read_swab(tp, 0x4, &start))
9936 offset = tg3_nvram_logical_addr(tp, offset);
9937 if (tg3_nvram_read_swab(tp, offset, &val))
9940 if ((val & 0xfc000000) == 0x0c000000) {
9941 u32 ver_offset, addr;
9944 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
9945 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
9951 addr = offset + ver_offset - start;
9952 for (i = 0; i < 16; i += 4) {
9953 if (tg3_nvram_read(tp, addr + i, &val))
9956 val = cpu_to_le32(val);
9957 memcpy(tp->fw_ver + i, &val, 4);
9962 #ifdef CONFIG_SPARC64
9963 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9965 struct pci_dev *pdev = tp->pdev;
9966 struct pcidev_cookie *pcp = pdev->sysdata;
9969 int node = pcp->prom_node;
9973 err = prom_getproperty(node, "subsystem-vendor-id",
9974 (char *) &venid, sizeof(venid));
9975 if (err == 0 || err == -1)
9977 if (venid == PCI_VENDOR_ID_SUN)
9980 /* TG3 chips onboard the SunBlade-2500 don't have the
9981 * subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
9982 * are distinguishable from non-Sun variants by being
9983 * named "network" by the firmware. Non-Sun cards will
9984 * show up as being named "ethernet".
9986 if (!strcmp(pcp->prom_name, "network"))
9993 static int __devinit tg3_get_invariants(struct tg3 *tp)
9995 static struct pci_device_id write_reorder_chipsets[] = {
9996 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9997 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9998 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9999 PCI_DEVICE_ID_VIA_8385_0) },
10003 u32 cacheline_sz_reg;
10004 u32 pci_state_reg, grc_misc_cfg;
10009 #ifdef CONFIG_SPARC64
10010 if (tg3_is_sun_570X(tp))
10011 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
10014 /* Force memory write invalidate off. If we leave it on,
10015 * then on 5700_BX chips we have to enable a workaround.
10016 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10017 * to match the cacheline size. The Broadcom driver have this
10018 * workaround but turns MWI off all the times so never uses
10019 * it. This seems to suggest that the workaround is insufficient.
10021 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10022 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10023 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10025 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10026 * has the register indirect write enable bit set before
10027 * we try to access any of the MMIO registers. It is also
10028 * critical that the PCI-X hw workaround situation is decided
10029 * before that as well.
10031 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10034 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10035 MISC_HOST_CTRL_CHIPREV_SHIFT);
10037 /* Wrong chip ID in 5752 A0. This code can be removed later
10038 * as A0 is not in production.
10040 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10041 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10043 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10044 * we need to disable memory and use config. cycles
10045 * only to access all registers. The 5702/03 chips
10046 * can mistakenly decode the special cycles from the
10047 * ICH chipsets as memory write cycles, causing corruption
10048 * of register and memory space. Only certain ICH bridges
10049 * will drive special cycles with non-zero data during the
10050 * address phase which can fall within the 5703's address
10051 * range. This is not an ICH bug as the PCI spec allows
10052 * non-zero address during special cycles. However, only
10053 * these ICH bridges are known to drive non-zero addresses
10054 * during special cycles.
10056 * Since special cycles do not cross PCI bridges, we only
10057 * enable this workaround if the 5703 is on the secondary
10058 * bus of these ICH bridges.
10060 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10061 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10062 static struct tg3_dev_id {
10066 } ich_chipsets[] = {
10067 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10069 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10071 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10073 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10077 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10078 struct pci_dev *bridge = NULL;
10080 while (pci_id->vendor != 0) {
10081 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10087 if (pci_id->rev != PCI_ANY_ID) {
10090 pci_read_config_byte(bridge, PCI_REVISION_ID,
10092 if (rev > pci_id->rev)
10095 if (bridge->subordinate &&
10096 (bridge->subordinate->number ==
10097 tp->pdev->bus->number)) {
10099 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10100 pci_dev_put(bridge);
10106 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10107 * DMA addresses > 40-bit. This bridge may have other additional
10108 * 57xx devices behind it in some 4-port NIC designs for example.
10109 * Any tg3 device found behind the bridge will also need the 40-bit
10112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10113 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10114 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10115 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10116 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10119 struct pci_dev *bridge = NULL;
10122 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10123 PCI_DEVICE_ID_SERVERWORKS_EPB,
10125 if (bridge && bridge->subordinate &&
10126 (bridge->subordinate->number <=
10127 tp->pdev->bus->number) &&
10128 (bridge->subordinate->subordinate >=
10129 tp->pdev->bus->number)) {
10130 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10131 pci_dev_put(bridge);
10137 /* Initialize misc host control in PCI block. */
10138 tp->misc_host_ctrl |= (misc_ctrl_reg &
10139 MISC_HOST_CTRL_CHIPREV);
10140 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10141 tp->misc_host_ctrl);
10143 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10144 &cacheline_sz_reg);
10146 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10147 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10148 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10149 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10155 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10156 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10158 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10159 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10160 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10162 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10164 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10165 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10166 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10168 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1;
10171 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10172 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10173 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10174 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10175 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
10176 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10178 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10179 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10181 /* If we have an AMD 762 or VIA K8T800 chipset, write
10182 * reordering to the mailbox registers done by the host
10183 * controller can cause major troubles. We read back from
10184 * every mailbox register write to force the writes to be
10185 * posted to the chip in order.
10187 if (pci_dev_present(write_reorder_chipsets) &&
10188 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10189 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10192 tp->pci_lat_timer < 64) {
10193 tp->pci_lat_timer = 64;
10195 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10196 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10197 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10198 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10200 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10204 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10207 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10208 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10210 /* If this is a 5700 BX chipset, and we are in PCI-X
10211 * mode, enable register write workaround.
10213 * The workaround is to use indirect register accesses
10214 * for all chip writes not to mailbox registers.
10216 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10220 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10222 /* The chip can have it's power management PCI config
10223 * space registers clobbered due to this bug.
10224 * So explicitly force the chip into D0 here.
10226 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10228 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10229 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10230 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10233 /* Also, force SERR#/PERR# in PCI command. */
10234 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10235 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10236 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10240 /* 5700 BX chips need to have their TX producer index mailboxes
10241 * written twice to workaround a bug.
10243 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10244 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10246 /* Back to back register writes can cause problems on this chip,
10247 * the workaround is to read back all reg writes except those to
10248 * mailbox regs. See tg3_write_indirect_reg32().
10250 * PCI Express 5750_A0 rev chips need this workaround too.
10252 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10253 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10254 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10255 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10257 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10258 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10259 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10260 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10262 /* Chip-specific fixup from Broadcom driver */
10263 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10264 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10265 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10266 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10269 /* Default fast path register access methods */
10270 tp->read32 = tg3_read32;
10271 tp->write32 = tg3_write32;
10272 tp->read32_mbox = tg3_read32;
10273 tp->write32_mbox = tg3_write32;
10274 tp->write32_tx_mbox = tg3_write32;
10275 tp->write32_rx_mbox = tg3_write32;
10277 /* Various workaround register access methods */
10278 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10279 tp->write32 = tg3_write_indirect_reg32;
10280 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10281 tp->write32 = tg3_write_flush_reg32;
10283 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10284 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10285 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10286 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10287 tp->write32_rx_mbox = tg3_write_flush_reg32;
10290 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10291 tp->read32 = tg3_read_indirect_reg32;
10292 tp->write32 = tg3_write_indirect_reg32;
10293 tp->read32_mbox = tg3_read_indirect_mbox;
10294 tp->write32_mbox = tg3_write_indirect_mbox;
10295 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10296 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10301 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10302 pci_cmd &= ~PCI_COMMAND_MEMORY;
10303 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10306 if (tp->write32 == tg3_write_indirect_reg32 ||
10307 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10308 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) ||
10310 (tp->tg3_flags2 & TG3_FLG2_SUN_570X))
10311 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10313 /* Get eeprom hw config before calling tg3_set_power_state().
10314 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10315 * determined before calling tg3_set_power_state() so that
10316 * we know whether or not to switch out of Vaux power.
10317 * When the flag is set, it means that GPIO1 is used for eeprom
10318 * write protect and also implies that it is a LOM where GPIOs
10319 * are not used to switch power.
10321 tg3_get_eeprom_hw_cfg(tp);
10323 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10324 * GPIO1 driven high will bring 5700's external PHY out of reset.
10325 * It is also used as eeprom write protect on LOMs.
10327 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10328 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10329 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10330 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10331 GRC_LCLCTRL_GPIO_OUTPUT1);
10332 /* Unused GPIO3 must be driven as output on 5752 because there
10333 * are no pull-up resistors on unused GPIO pins.
10335 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10336 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10338 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10339 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10341 /* Force the chip into D0. */
10342 err = tg3_set_power_state(tp, PCI_D0);
10344 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10345 pci_name(tp->pdev));
10349 /* 5700 B0 chips do not support checksumming correctly due
10350 * to hardware bugs.
10352 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10353 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10355 /* Derive initial jumbo mode from MTU assigned in
10356 * ether_setup() via the alloc_etherdev() call
10358 if (tp->dev->mtu > ETH_DATA_LEN &&
10359 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10360 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10362 /* Determine WakeOnLan speed to use. */
10363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10364 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10365 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10366 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10367 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10369 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10372 /* A few boards don't want Ethernet@WireSpeed phy feature */
10373 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10374 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10375 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10376 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10377 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10378 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10380 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10381 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10382 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10383 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10384 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10386 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10387 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10388 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10389 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10391 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10394 tp->coalesce_mode = 0;
10395 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10396 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10397 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10399 /* Initialize MAC MI mode, polling disabled. */
10400 tw32_f(MAC_MI_MODE, tp->mi_mode);
10403 /* Initialize data/descriptor byte/word swapping. */
10404 val = tr32(GRC_MODE);
10405 val &= GRC_MODE_HOST_STACKUP;
10406 tw32(GRC_MODE, val | tp->grc_mode);
10408 tg3_switch_clocks(tp);
10410 /* Clear this out for sanity. */
10411 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10413 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10415 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10416 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10417 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10419 if (chiprevid == CHIPREV_ID_5701_A0 ||
10420 chiprevid == CHIPREV_ID_5701_B0 ||
10421 chiprevid == CHIPREV_ID_5701_B2 ||
10422 chiprevid == CHIPREV_ID_5701_B5) {
10423 void __iomem *sram_base;
10425 /* Write some dummy words into the SRAM status block
10426 * area, see if it reads back correctly. If the return
10427 * value is bad, force enable the PCIX workaround.
10429 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10431 writel(0x00000000, sram_base);
10432 writel(0x00000000, sram_base + 4);
10433 writel(0xffffffff, sram_base + 4);
10434 if (readl(sram_base) != 0x00000000)
10435 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10440 tg3_nvram_init(tp);
10442 grc_misc_cfg = tr32(GRC_MISC_CFG);
10443 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10445 /* Broadcom's driver says that CIOBE multisplit has a bug */
10447 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10448 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10449 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10450 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10454 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10455 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10456 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10458 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10459 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10460 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10461 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10462 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10463 HOSTCC_MODE_CLRTICK_TXBD);
10465 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10466 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10467 tp->misc_host_ctrl);
10470 /* these are limited to 10/100 only */
10471 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10472 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10473 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10474 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10475 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10476 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10477 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10478 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10479 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10480 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
10481 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10483 err = tg3_phy_probe(tp);
10485 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10486 pci_name(tp->pdev), err);
10487 /* ... but do not return immediately ... */
10490 tg3_read_partno(tp);
10491 tg3_read_fw_ver(tp);
10493 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10494 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10496 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10497 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10499 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10502 /* 5700 {AX,BX} chips have a broken status block link
10503 * change bit implementation, so we must use the
10504 * status register in those cases.
10506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10507 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10509 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10511 /* The led_ctrl is set during tg3_phy_probe, here we might
10512 * have to force the link status polling mechanism based
10513 * upon subsystem IDs.
10515 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10516 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10517 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10518 TG3_FLAG_USE_LINKCHG_REG);
10521 /* For all SERDES we poll the MAC status register. */
10522 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10523 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10525 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10527 /* All chips before 5787 can get confused if TX buffers
10528 * straddle the 4GB address boundary in some cases.
10530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10532 tp->dev->hard_start_xmit = tg3_start_xmit;
10534 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10538 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10541 /* By default, disable wake-on-lan. User can change this
10542 * using ETHTOOL_SWOL.
10544 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10549 #ifdef CONFIG_SPARC64
10550 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10552 struct net_device *dev = tp->dev;
10553 struct pci_dev *pdev = tp->pdev;
10554 struct pcidev_cookie *pcp = pdev->sysdata;
10557 int node = pcp->prom_node;
10559 if (prom_getproplen(node, "local-mac-address") == 6) {
10560 prom_getproperty(node, "local-mac-address",
10562 memcpy(dev->perm_addr, dev->dev_addr, 6);
10569 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10571 struct net_device *dev = tp->dev;
10573 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10574 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10579 static int __devinit tg3_get_device_address(struct tg3 *tp)
10581 struct net_device *dev = tp->dev;
10582 u32 hi, lo, mac_offset;
10585 #ifdef CONFIG_SPARC64
10586 if (!tg3_get_macaddr_sparc(tp))
10591 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10592 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
10593 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10594 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10596 if (tg3_nvram_lock(tp))
10597 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10599 tg3_nvram_unlock(tp);
10602 /* First try to get it from MAC address mailbox. */
10603 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10604 if ((hi >> 16) == 0x484b) {
10605 dev->dev_addr[0] = (hi >> 8) & 0xff;
10606 dev->dev_addr[1] = (hi >> 0) & 0xff;
10608 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10609 dev->dev_addr[2] = (lo >> 24) & 0xff;
10610 dev->dev_addr[3] = (lo >> 16) & 0xff;
10611 dev->dev_addr[4] = (lo >> 8) & 0xff;
10612 dev->dev_addr[5] = (lo >> 0) & 0xff;
10614 /* Some old bootcode may report a 0 MAC address in SRAM */
10615 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
10618 /* Next, try NVRAM. */
10619 if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
10620 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10621 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10622 dev->dev_addr[0] = ((hi >> 16) & 0xff);
10623 dev->dev_addr[1] = ((hi >> 24) & 0xff);
10624 dev->dev_addr[2] = ((lo >> 0) & 0xff);
10625 dev->dev_addr[3] = ((lo >> 8) & 0xff);
10626 dev->dev_addr[4] = ((lo >> 16) & 0xff);
10627 dev->dev_addr[5] = ((lo >> 24) & 0xff);
10629 /* Finally just fetch it out of the MAC control regs. */
10631 hi = tr32(MAC_ADDR_0_HIGH);
10632 lo = tr32(MAC_ADDR_0_LOW);
10634 dev->dev_addr[5] = lo & 0xff;
10635 dev->dev_addr[4] = (lo >> 8) & 0xff;
10636 dev->dev_addr[3] = (lo >> 16) & 0xff;
10637 dev->dev_addr[2] = (lo >> 24) & 0xff;
10638 dev->dev_addr[1] = hi & 0xff;
10639 dev->dev_addr[0] = (hi >> 8) & 0xff;
10643 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
10644 #ifdef CONFIG_SPARC64
10645 if (!tg3_get_default_macaddr_sparc(tp))
10650 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
10654 #define BOUNDARY_SINGLE_CACHELINE 1
10655 #define BOUNDARY_MULTI_CACHELINE 2
10657 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
10659 int cacheline_size;
10663 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
10665 cacheline_size = 1024;
10667 cacheline_size = (int) byte * 4;
10669 /* On 5703 and later chips, the boundary bits have no
10672 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10673 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
10674 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10677 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
10678 goal = BOUNDARY_MULTI_CACHELINE;
10680 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
10681 goal = BOUNDARY_SINGLE_CACHELINE;
10690 /* PCI controllers on most RISC systems tend to disconnect
10691 * when a device tries to burst across a cache-line boundary.
10692 * Therefore, letting tg3 do so just wastes PCI bandwidth.
10694 * Unfortunately, for PCI-E there are only limited
10695 * write-side controls for this, and thus for reads
10696 * we will still get the disconnects. We'll also waste
10697 * these PCI cycles for both read and write for chips
10698 * other than 5700 and 5701 which do not implement the
10701 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10702 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10703 switch (cacheline_size) {
10708 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10709 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10710 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10712 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10713 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10718 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10719 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10723 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10724 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10727 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10728 switch (cacheline_size) {
10732 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10733 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10734 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10740 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10741 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10745 switch (cacheline_size) {
10747 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10748 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10749 DMA_RWCTRL_WRITE_BNDRY_16);
10754 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10755 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10756 DMA_RWCTRL_WRITE_BNDRY_32);
10761 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10762 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10763 DMA_RWCTRL_WRITE_BNDRY_64);
10768 if (goal == BOUNDARY_SINGLE_CACHELINE) {
10769 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10770 DMA_RWCTRL_WRITE_BNDRY_128);
10775 val |= (DMA_RWCTRL_READ_BNDRY_256 |
10776 DMA_RWCTRL_WRITE_BNDRY_256);
10779 val |= (DMA_RWCTRL_READ_BNDRY_512 |
10780 DMA_RWCTRL_WRITE_BNDRY_512);
10784 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10785 DMA_RWCTRL_WRITE_BNDRY_1024);
10794 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10796 struct tg3_internal_buffer_desc test_desc;
10797 u32 sram_dma_descs;
10800 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10802 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10803 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10804 tw32(RDMAC_STATUS, 0);
10805 tw32(WDMAC_STATUS, 0);
10807 tw32(BUFMGR_MODE, 0);
10808 tw32(FTQ_RESET, 0);
10810 test_desc.addr_hi = ((u64) buf_dma) >> 32;
10811 test_desc.addr_lo = buf_dma & 0xffffffff;
10812 test_desc.nic_mbuf = 0x00002100;
10813 test_desc.len = size;
10816 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10817 * the *second* time the tg3 driver was getting loaded after an
10820 * Broadcom tells me:
10821 * ...the DMA engine is connected to the GRC block and a DMA
10822 * reset may affect the GRC block in some unpredictable way...
10823 * The behavior of resets to individual blocks has not been tested.
10825 * Broadcom noted the GRC reset will also reset all sub-components.
10828 test_desc.cqid_sqid = (13 << 8) | 2;
10830 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10833 test_desc.cqid_sqid = (16 << 8) | 7;
10835 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10838 test_desc.flags = 0x00000005;
10840 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10843 val = *(((u32 *)&test_desc) + i);
10844 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10845 sram_dma_descs + (i * sizeof(u32)));
10846 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10848 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10851 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10853 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10857 for (i = 0; i < 40; i++) {
10861 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10863 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10864 if ((val & 0xffff) == sram_dma_descs) {
10875 #define TEST_BUFFER_SIZE 0x2000
10877 static int __devinit tg3_test_dma(struct tg3 *tp)
10879 dma_addr_t buf_dma;
10880 u32 *buf, saved_dma_rwctrl;
10883 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10889 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10890 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10892 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10894 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10895 /* DMA read watermark not used on PCIE */
10896 tp->dma_rwctrl |= 0x00180000;
10897 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10898 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10900 tp->dma_rwctrl |= 0x003f0000;
10902 tp->dma_rwctrl |= 0x003f000f;
10904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10906 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10908 /* If the 5704 is behind the EPB bridge, we can
10909 * do the less restrictive ONE_DMA workaround for
10910 * better performance.
10912 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
10913 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10914 tp->dma_rwctrl |= 0x8000;
10915 else if (ccval == 0x6 || ccval == 0x7)
10916 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10918 /* Set bit 23 to enable PCIX hw bug fix */
10919 tp->dma_rwctrl |= 0x009f0000;
10920 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10921 /* 5780 always in PCIX mode */
10922 tp->dma_rwctrl |= 0x00144000;
10923 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10924 /* 5714 always in PCIX mode */
10925 tp->dma_rwctrl |= 0x00148000;
10927 tp->dma_rwctrl |= 0x001b000f;
10931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10933 tp->dma_rwctrl &= 0xfffffff0;
10935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10937 /* Remove this if it causes problems for some boards. */
10938 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10940 /* On 5700/5701 chips, we need to set this bit.
10941 * Otherwise the chip will issue cacheline transactions
10942 * to streamable DMA memory with not all the byte
10943 * enables turned on. This is an error on several
10944 * RISC PCI controllers, in particular sparc64.
10946 * On 5703/5704 chips, this bit has been reassigned
10947 * a different meaning. In particular, it is used
10948 * on those chips to enable a PCI-X workaround.
10950 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10953 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10956 /* Unneeded, already done by tg3_get_invariants. */
10957 tg3_switch_clocks(tp);
10961 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10962 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10965 /* It is best to perform DMA test with maximum write burst size
10966 * to expose the 5700/5701 write DMA bug.
10968 saved_dma_rwctrl = tp->dma_rwctrl;
10969 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10970 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10975 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10978 /* Send the buffer to the chip. */
10979 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10981 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10986 /* validate data reached card RAM correctly. */
10987 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10989 tg3_read_mem(tp, 0x2100 + (i*4), &val);
10990 if (le32_to_cpu(val) != p[i]) {
10991 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
10992 /* ret = -ENODEV here? */
10997 /* Now read it back. */
10998 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11000 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11006 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11010 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11011 DMA_RWCTRL_WRITE_BNDRY_16) {
11012 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11013 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11014 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11017 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11023 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11029 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11030 DMA_RWCTRL_WRITE_BNDRY_16) {
11031 static struct pci_device_id dma_wait_state_chipsets[] = {
11032 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11033 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11037 /* DMA test passed without adjusting DMA boundary,
11038 * now look for chipsets that are known to expose the
11039 * DMA bug without failing the test.
11041 if (pci_dev_present(dma_wait_state_chipsets)) {
11042 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11043 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11046 /* Safe to use the calculated DMA boundary. */
11047 tp->dma_rwctrl = saved_dma_rwctrl;
11049 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11053 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11058 static void __devinit tg3_init_link_config(struct tg3 *tp)
11060 tp->link_config.advertising =
11061 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11062 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11063 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11064 ADVERTISED_Autoneg | ADVERTISED_MII);
11065 tp->link_config.speed = SPEED_INVALID;
11066 tp->link_config.duplex = DUPLEX_INVALID;
11067 tp->link_config.autoneg = AUTONEG_ENABLE;
11068 tp->link_config.active_speed = SPEED_INVALID;
11069 tp->link_config.active_duplex = DUPLEX_INVALID;
11070 tp->link_config.phy_is_low_power = 0;
11071 tp->link_config.orig_speed = SPEED_INVALID;
11072 tp->link_config.orig_duplex = DUPLEX_INVALID;
11073 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11076 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11078 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11079 tp->bufmgr_config.mbuf_read_dma_low_water =
11080 DEFAULT_MB_RDMA_LOW_WATER_5705;
11081 tp->bufmgr_config.mbuf_mac_rx_low_water =
11082 DEFAULT_MB_MACRX_LOW_WATER_5705;
11083 tp->bufmgr_config.mbuf_high_water =
11084 DEFAULT_MB_HIGH_WATER_5705;
11086 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11087 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11088 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11089 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11090 tp->bufmgr_config.mbuf_high_water_jumbo =
11091 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11093 tp->bufmgr_config.mbuf_read_dma_low_water =
11094 DEFAULT_MB_RDMA_LOW_WATER;
11095 tp->bufmgr_config.mbuf_mac_rx_low_water =
11096 DEFAULT_MB_MACRX_LOW_WATER;
11097 tp->bufmgr_config.mbuf_high_water =
11098 DEFAULT_MB_HIGH_WATER;
11100 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11101 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11102 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11103 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11104 tp->bufmgr_config.mbuf_high_water_jumbo =
11105 DEFAULT_MB_HIGH_WATER_JUMBO;
11108 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11109 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11112 static char * __devinit tg3_phy_string(struct tg3 *tp)
11114 switch (tp->phy_id & PHY_ID_MASK) {
11115 case PHY_ID_BCM5400: return "5400";
11116 case PHY_ID_BCM5401: return "5401";
11117 case PHY_ID_BCM5411: return "5411";
11118 case PHY_ID_BCM5701: return "5701";
11119 case PHY_ID_BCM5703: return "5703";
11120 case PHY_ID_BCM5704: return "5704";
11121 case PHY_ID_BCM5705: return "5705";
11122 case PHY_ID_BCM5750: return "5750";
11123 case PHY_ID_BCM5752: return "5752";
11124 case PHY_ID_BCM5714: return "5714";
11125 case PHY_ID_BCM5780: return "5780";
11126 case PHY_ID_BCM5755: return "5755";
11127 case PHY_ID_BCM5787: return "5787";
11128 case PHY_ID_BCM8002: return "8002/serdes";
11129 case 0: return "serdes";
11130 default: return "unknown";
11134 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11136 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11137 strcpy(str, "PCI Express");
11139 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11140 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11142 strcpy(str, "PCIX:");
11144 if ((clock_ctrl == 7) ||
11145 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11146 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11147 strcat(str, "133MHz");
11148 else if (clock_ctrl == 0)
11149 strcat(str, "33MHz");
11150 else if (clock_ctrl == 2)
11151 strcat(str, "50MHz");
11152 else if (clock_ctrl == 4)
11153 strcat(str, "66MHz");
11154 else if (clock_ctrl == 6)
11155 strcat(str, "100MHz");
11157 strcpy(str, "PCI:");
11158 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11159 strcat(str, "66MHz");
11161 strcat(str, "33MHz");
11163 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11164 strcat(str, ":32-bit");
11166 strcat(str, ":64-bit");
11170 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11172 struct pci_dev *peer;
11173 unsigned int func, devnr = tp->pdev->devfn & ~7;
11175 for (func = 0; func < 8; func++) {
11176 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11177 if (peer && peer != tp->pdev)
11181 /* 5704 can be configured in single-port mode, set peer to
11182 * tp->pdev in that case.
11190 * We don't need to keep the refcount elevated; there's no way
11191 * to remove one half of this device without removing the other
11198 static void __devinit tg3_init_coal(struct tg3 *tp)
11200 struct ethtool_coalesce *ec = &tp->coal;
11202 memset(ec, 0, sizeof(*ec));
11203 ec->cmd = ETHTOOL_GCOALESCE;
11204 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11205 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11206 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11207 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11208 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11209 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11210 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11211 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11212 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11214 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11215 HOSTCC_MODE_CLRTICK_TXBD)) {
11216 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11217 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11218 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11219 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11222 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11223 ec->rx_coalesce_usecs_irq = 0;
11224 ec->tx_coalesce_usecs_irq = 0;
11225 ec->stats_block_coalesce_usecs = 0;
11229 static int __devinit tg3_init_one(struct pci_dev *pdev,
11230 const struct pci_device_id *ent)
11232 static int tg3_version_printed = 0;
11233 unsigned long tg3reg_base, tg3reg_len;
11234 struct net_device *dev;
11236 int i, err, pm_cap;
11238 u64 dma_mask, persist_dma_mask;
11240 if (tg3_version_printed++ == 0)
11241 printk(KERN_INFO "%s", version);
11243 err = pci_enable_device(pdev);
11245 printk(KERN_ERR PFX "Cannot enable PCI device, "
11250 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11251 printk(KERN_ERR PFX "Cannot find proper PCI device "
11252 "base address, aborting.\n");
11254 goto err_out_disable_pdev;
11257 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11259 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11261 goto err_out_disable_pdev;
11264 pci_set_master(pdev);
11266 /* Find power-management capability. */
11267 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11269 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11272 goto err_out_free_res;
11275 tg3reg_base = pci_resource_start(pdev, 0);
11276 tg3reg_len = pci_resource_len(pdev, 0);
11278 dev = alloc_etherdev(sizeof(*tp));
11280 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11282 goto err_out_free_res;
11285 SET_MODULE_OWNER(dev);
11286 SET_NETDEV_DEV(dev, &pdev->dev);
11288 dev->features |= NETIF_F_LLTX;
11289 #if TG3_VLAN_TAG_USED
11290 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11291 dev->vlan_rx_register = tg3_vlan_rx_register;
11292 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11295 tp = netdev_priv(dev);
11298 tp->pm_cap = pm_cap;
11299 tp->mac_mode = TG3_DEF_MAC_MODE;
11300 tp->rx_mode = TG3_DEF_RX_MODE;
11301 tp->tx_mode = TG3_DEF_TX_MODE;
11302 tp->mi_mode = MAC_MI_MODE_BASE;
11304 tp->msg_enable = tg3_debug;
11306 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11308 /* The word/byte swap controls here control register access byte
11309 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11312 tp->misc_host_ctrl =
11313 MISC_HOST_CTRL_MASK_PCI_INT |
11314 MISC_HOST_CTRL_WORD_SWAP |
11315 MISC_HOST_CTRL_INDIR_ACCESS |
11316 MISC_HOST_CTRL_PCISTATE_RW;
11318 /* The NONFRM (non-frame) byte/word swap controls take effect
11319 * on descriptor entries, anything which isn't packet data.
11321 * The StrongARM chips on the board (one for tx, one for rx)
11322 * are running in big-endian mode.
11324 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11325 GRC_MODE_WSWAP_NONFRM_DATA);
11326 #ifdef __BIG_ENDIAN
11327 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11329 spin_lock_init(&tp->lock);
11330 spin_lock_init(&tp->tx_lock);
11331 spin_lock_init(&tp->indirect_lock);
11332 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11334 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11335 if (tp->regs == 0UL) {
11336 printk(KERN_ERR PFX "Cannot map device registers, "
11339 goto err_out_free_dev;
11342 tg3_init_link_config(tp);
11344 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11345 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11346 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11348 dev->open = tg3_open;
11349 dev->stop = tg3_close;
11350 dev->get_stats = tg3_get_stats;
11351 dev->set_multicast_list = tg3_set_rx_mode;
11352 dev->set_mac_address = tg3_set_mac_addr;
11353 dev->do_ioctl = tg3_ioctl;
11354 dev->tx_timeout = tg3_tx_timeout;
11355 dev->poll = tg3_poll;
11356 dev->ethtool_ops = &tg3_ethtool_ops;
11358 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11359 dev->change_mtu = tg3_change_mtu;
11360 dev->irq = pdev->irq;
11361 #ifdef CONFIG_NET_POLL_CONTROLLER
11362 dev->poll_controller = tg3_poll_controller;
11365 err = tg3_get_invariants(tp);
11367 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11369 goto err_out_iounmap;
11372 /* The EPB bridge inside 5714, 5715, and 5780 and any
11373 * device behind the EPB cannot support DMA addresses > 40-bit.
11374 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11375 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11376 * do DMA address check in tg3_start_xmit().
11378 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11379 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11380 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11381 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11382 #ifdef CONFIG_HIGHMEM
11383 dma_mask = DMA_64BIT_MASK;
11386 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11388 /* Configure DMA attributes. */
11389 if (dma_mask > DMA_32BIT_MASK) {
11390 err = pci_set_dma_mask(pdev, dma_mask);
11392 dev->features |= NETIF_F_HIGHDMA;
11393 err = pci_set_consistent_dma_mask(pdev,
11396 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11397 "DMA for consistent allocations\n");
11398 goto err_out_iounmap;
11402 if (err || dma_mask == DMA_32BIT_MASK) {
11403 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11405 printk(KERN_ERR PFX "No usable DMA configuration, "
11407 goto err_out_iounmap;
11411 tg3_init_bufmgr_config(tp);
11413 #if TG3_TSO_SUPPORT != 0
11414 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11415 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11417 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11418 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11419 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11420 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11421 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11423 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11426 /* TSO is on by default on chips that support hardware TSO.
11427 * Firmware TSO on older chips gives lower performance, so it
11428 * is off by default, but can be enabled using ethtool.
11430 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
11431 dev->features |= NETIF_F_TSO;
11435 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11436 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11437 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11438 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11439 tp->rx_pending = 63;
11442 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11443 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11444 tp->pdev_peer = tg3_find_peer(tp);
11446 err = tg3_get_device_address(tp);
11448 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11450 goto err_out_iounmap;
11454 * Reset chip in case UNDI or EFI driver did not shutdown
11455 * DMA self test will enable WDMAC and we'll see (spurious)
11456 * pending DMA on the PCI bus at that point.
11458 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11459 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11460 pci_save_state(tp->pdev);
11461 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11462 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11465 err = tg3_test_dma(tp);
11467 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11468 goto err_out_iounmap;
11471 /* Tigon3 can do ipv4 only... and some chips have buggy
11474 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11475 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11477 dev->features |= NETIF_F_HW_CSUM;
11479 dev->features |= NETIF_F_IP_CSUM;
11480 dev->features |= NETIF_F_SG;
11481 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11483 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11485 /* flow control autonegotiation is default behavior */
11486 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11490 /* Now that we have fully setup the chip, save away a snapshot
11491 * of the PCI config space. We need to restore this after
11492 * GRC_MISC_CFG core clock resets and some resume events.
11494 pci_save_state(tp->pdev);
11496 err = register_netdev(dev);
11498 printk(KERN_ERR PFX "Cannot register net device, "
11500 goto err_out_iounmap;
11503 pci_set_drvdata(pdev, dev);
11505 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11507 tp->board_part_number,
11508 tp->pci_chip_rev_id,
11509 tg3_phy_string(tp),
11510 tg3_bus_string(tp, str),
11511 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11513 for (i = 0; i < 6; i++)
11514 printk("%2.2x%c", dev->dev_addr[i],
11515 i == 5 ? '\n' : ':');
11517 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11518 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11521 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11522 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11523 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11524 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11525 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11526 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11527 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11528 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11529 dev->name, tp->dma_rwctrl,
11530 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11531 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11533 netif_carrier_off(tp->dev);
11547 pci_release_regions(pdev);
11549 err_out_disable_pdev:
11550 pci_disable_device(pdev);
11551 pci_set_drvdata(pdev, NULL);
11555 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11557 struct net_device *dev = pci_get_drvdata(pdev);
11560 struct tg3 *tp = netdev_priv(dev);
11562 flush_scheduled_work();
11563 unregister_netdev(dev);
11569 pci_release_regions(pdev);
11570 pci_disable_device(pdev);
11571 pci_set_drvdata(pdev, NULL);
11575 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11577 struct net_device *dev = pci_get_drvdata(pdev);
11578 struct tg3 *tp = netdev_priv(dev);
11581 if (!netif_running(dev))
11584 flush_scheduled_work();
11585 tg3_netif_stop(tp);
11587 del_timer_sync(&tp->timer);
11589 tg3_full_lock(tp, 1);
11590 tg3_disable_ints(tp);
11591 tg3_full_unlock(tp);
11593 netif_device_detach(dev);
11595 tg3_full_lock(tp, 0);
11596 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11597 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11598 tg3_full_unlock(tp);
11600 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11602 tg3_full_lock(tp, 0);
11604 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11605 tg3_init_hw(tp, 1);
11607 tp->timer.expires = jiffies + tp->timer_offset;
11608 add_timer(&tp->timer);
11610 netif_device_attach(dev);
11611 tg3_netif_start(tp);
11613 tg3_full_unlock(tp);
11619 static int tg3_resume(struct pci_dev *pdev)
11621 struct net_device *dev = pci_get_drvdata(pdev);
11622 struct tg3 *tp = netdev_priv(dev);
11625 if (!netif_running(dev))
11628 pci_restore_state(tp->pdev);
11630 err = tg3_set_power_state(tp, PCI_D0);
11634 netif_device_attach(dev);
11636 tg3_full_lock(tp, 0);
11638 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11639 tg3_init_hw(tp, 1);
11641 tp->timer.expires = jiffies + tp->timer_offset;
11642 add_timer(&tp->timer);
11644 tg3_netif_start(tp);
11646 tg3_full_unlock(tp);
11651 static struct pci_driver tg3_driver = {
11652 .name = DRV_MODULE_NAME,
11653 .id_table = tg3_pci_tbl,
11654 .probe = tg3_init_one,
11655 .remove = __devexit_p(tg3_remove_one),
11656 .suspend = tg3_suspend,
11657 .resume = tg3_resume
11660 static int __init tg3_init(void)
11662 return pci_module_init(&tg3_driver);
11665 static void __exit tg3_cleanup(void)
11667 pci_unregister_driver(&tg3_driver);
11670 module_init(tg3_init);
11671 module_exit(tg3_cleanup);