2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #define ATHEROS_VENDOR_ID 0x168c
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
30 #define AR5416_AR9100_DEVID 0x000b
32 #define AR_SUBVENDOR_ID_NOG 0x0e11
33 #define AR_SUBVENDOR_ID_NEW_A 0x7065
35 #define ATH9K_TXERR_XRETRY 0x01
36 #define ATH9K_TXERR_FILT 0x02
37 #define ATH9K_TXERR_FIFO 0x04
38 #define ATH9K_TXERR_XTXOP 0x08
39 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
41 #define ATH9K_TX_BA 0x01
42 #define ATH9K_TX_PWRMGMT 0x02
43 #define ATH9K_TX_DESC_CFG_ERR 0x04
44 #define ATH9K_TX_DATA_UNDERRUN 0x08
45 #define ATH9K_TX_DELIM_UNDERRUN 0x10
46 #define ATH9K_TX_SW_ABORTED 0x40
47 #define ATH9K_TX_SW_FILTERED 0x80
51 struct ath_tx_status {
77 struct ath_rx_status {
102 #define ATH9K_RXERR_CRC 0x01
103 #define ATH9K_RXERR_PHY 0x02
104 #define ATH9K_RXERR_FIFO 0x04
105 #define ATH9K_RXERR_DECRYPT 0x08
106 #define ATH9K_RXERR_MIC 0x10
108 #define ATH9K_RX_MORE 0x01
109 #define ATH9K_RX_MORE_AGGR 0x02
110 #define ATH9K_RX_GI 0x04
111 #define ATH9K_RX_2040 0x08
112 #define ATH9K_RX_DELIM_CRC_PRE 0x10
113 #define ATH9K_RX_DELIM_CRC_POST 0x20
114 #define ATH9K_RX_DECRYPT_BUSY 0x40
116 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
117 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
126 struct ath_tx_status tx;
127 struct ath_rx_status rx;
133 #define ds_txstat ds_us.tx
134 #define ds_rxstat ds_us.rx
135 #define ds_stat ds_us.stats
137 #define ATH9K_TXDESC_CLRDMASK 0x0001
138 #define ATH9K_TXDESC_NOACK 0x0002
139 #define ATH9K_TXDESC_RTSENA 0x0004
140 #define ATH9K_TXDESC_CTSENA 0x0008
141 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
142 * the descriptor its marked on. We take a tx interrupt to reap
143 * descriptors when the h/w hits an EOL condition or
144 * when the descriptor is specifically marked to generate
145 * an interrupt with this flag. Descriptors should be
146 * marked periodically to insure timely replenishing of the
147 * supply needed for sending frames. Defering interrupts
148 * reduces system load and potentially allows more concurrent
149 * work to be done but if done to aggressively can cause
150 * senders to backup. When the hardware queue is left too
151 * large rate control information may also be too out of
152 * date. An Alternative for this is TX interrupt mitigation
153 * but this needs more testing. */
154 #define ATH9K_TXDESC_INTREQ 0x0010
155 #define ATH9K_TXDESC_VEOL 0x0020
156 #define ATH9K_TXDESC_EXT_ONLY 0x0040
157 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
158 #define ATH9K_TXDESC_VMF 0x0100
159 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
160 #define ATH9K_TXDESC_CAB 0x0400
162 #define ATH9K_RXDESC_INTREQ 0x0020
168 ATH9K_MODE_11NA_HT20 = 6,
169 ATH9K_MODE_11NG_HT20 = 7,
170 ATH9K_MODE_11NA_HT40PLUS = 8,
171 ATH9K_MODE_11NA_HT40MINUS = 9,
172 ATH9K_MODE_11NG_HT40PLUS = 10,
173 ATH9K_MODE_11NG_HT40MINUS = 11,
178 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
179 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
180 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
181 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
182 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
183 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
184 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
185 ATH9K_HW_CAP_VEOL = BIT(7),
186 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
187 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
188 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
189 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
190 ATH9K_HW_CAP_HT = BIT(12),
191 ATH9K_HW_CAP_GTT = BIT(13),
192 ATH9K_HW_CAP_FASTCC = BIT(14),
193 ATH9K_HW_CAP_RFSILENT = BIT(15),
194 ATH9K_HW_CAP_WOW = BIT(16),
195 ATH9K_HW_CAP_CST = BIT(17),
196 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
197 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
198 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
199 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
202 enum ath9k_capability_type {
203 ATH9K_CAP_CIPHER = 0,
205 ATH9K_CAP_TKIP_SPLIT,
206 ATH9K_CAP_PHYCOUNTERS,
210 ATH9K_CAP_MCAST_KEYSRCH,
211 ATH9K_CAP_TSF_ADJUST,
212 ATH9K_CAP_WME_TKIPMIC,
214 ATH9K_CAP_ANT_CFG_2GHZ,
215 ATH9K_CAP_ANT_CFG_5GHZ
218 struct ath9k_hw_capabilities {
219 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
220 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
223 u16 low_5ghz_chan, high_5ghz_chan;
224 u16 low_2ghz_chan, high_2ghz_chan;
229 u16 tx_triglevel_max;
236 struct ath9k_ops_config {
237 int dma_beacon_response_time;
238 int sw_beacon_response_time;
239 int additional_swba_backoff;
241 int cwm_ignore_extcca;
242 u8 pcie_powersave_enable;
243 u8 pcie_l1skp_enable;
246 int pcie_power_reset;
255 u8 noise_immunity_level;
256 u32 ofdm_weaksignal_det;
257 u32 cck_weaksignal_thr;
258 u8 spur_immunity_level;
260 int8_t rssi_thr_high;
262 u16 diversity_control;
263 u16 antenna_switch_swap;
264 int serialize_regmode;
266 #define SPUR_DISABLE 0
267 #define SPUR_ENABLE_IOCTL 1
268 #define SPUR_ENABLE_EEPROM 2
269 #define AR_EEPROM_MODAL_SPURS 5
270 #define AR_SPUR_5413_1 1640
271 #define AR_SPUR_5413_2 1200
272 #define AR_NO_SPUR 0x8000
273 #define AR_BASE_FREQ_2GHZ 2300
274 #define AR_BASE_FREQ_5GHZ 4900
275 #define AR_SPUR_FEEQ_BOUND_HT40 19
276 #define AR_SPUR_FEEQ_BOUND_HT20 10
278 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
281 enum ath9k_tx_queue {
282 ATH9K_TX_QUEUE_INACTIVE = 0,
284 ATH9K_TX_QUEUE_BEACON,
286 ATH9K_TX_QUEUE_UAPSD,
287 ATH9K_TX_QUEUE_PSPOLL
290 #define ATH9K_NUM_TX_QUEUES 10
292 enum ath9k_tx_queue_subtype {
300 enum ath9k_tx_queue_flags {
301 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
302 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
303 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
304 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
305 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
306 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
307 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
308 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
309 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
312 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
314 #define ATH9K_DECOMP_MASK_SIZE 128
315 #define ATH9K_READY_TIME_LO_BOUND 50
316 #define ATH9K_READY_TIME_HI_BOUND 96
318 enum ath9k_pkt_type {
319 ATH9K_PKT_TYPE_NORMAL = 0,
321 ATH9K_PKT_TYPE_PSPOLL,
322 ATH9K_PKT_TYPE_BEACON,
323 ATH9K_PKT_TYPE_PROBE_RESP,
324 ATH9K_PKT_TYPE_CHIRP,
325 ATH9K_PKT_TYPE_GRP_POLL,
328 struct ath9k_tx_queue_info {
330 enum ath9k_tx_queue tqi_type;
331 enum ath9k_tx_queue_subtype tqi_subtype;
332 enum ath9k_tx_queue_flags tqi_qflags;
340 u32 tqi_cbrOverflowLimit;
347 enum ath9k_rx_filter {
348 ATH9K_RX_FILTER_UCAST = 0x00000001,
349 ATH9K_RX_FILTER_MCAST = 0x00000002,
350 ATH9K_RX_FILTER_BCAST = 0x00000004,
351 ATH9K_RX_FILTER_CONTROL = 0x00000008,
352 ATH9K_RX_FILTER_BEACON = 0x00000010,
353 ATH9K_RX_FILTER_PROM = 0x00000020,
354 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
355 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
356 ATH9K_RX_FILTER_PHYERR = 0x00000100,
357 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
361 ATH9K_INT_RX = 0x00000001,
362 ATH9K_INT_RXDESC = 0x00000002,
363 ATH9K_INT_RXNOFRM = 0x00000008,
364 ATH9K_INT_RXEOL = 0x00000010,
365 ATH9K_INT_RXORN = 0x00000020,
366 ATH9K_INT_TX = 0x00000040,
367 ATH9K_INT_TXDESC = 0x00000080,
368 ATH9K_INT_TIM_TIMER = 0x00000100,
369 ATH9K_INT_TXURN = 0x00000800,
370 ATH9K_INT_MIB = 0x00001000,
371 ATH9K_INT_RXPHY = 0x00004000,
372 ATH9K_INT_RXKCM = 0x00008000,
373 ATH9K_INT_SWBA = 0x00010000,
374 ATH9K_INT_BMISS = 0x00040000,
375 ATH9K_INT_BNR = 0x00100000,
376 ATH9K_INT_TIM = 0x00200000,
377 ATH9K_INT_DTIM = 0x00400000,
378 ATH9K_INT_DTIMSYNC = 0x00800000,
379 ATH9K_INT_GPIO = 0x01000000,
380 ATH9K_INT_CABEND = 0x02000000,
381 ATH9K_INT_CST = 0x10000000,
382 ATH9K_INT_GTT = 0x20000000,
383 ATH9K_INT_FATAL = 0x40000000,
384 ATH9K_INT_GLOBAL = 0x80000000,
385 ATH9K_INT_BMISC = ATH9K_INT_TIM |
389 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
401 ATH9K_INT_NOCARD = 0xffffffff
404 struct ath9k_rate_table {
406 u8 rateCodeToIndex[256];
420 #define ATH9K_RATESERIES_RTS_CTS 0x0001
421 #define ATH9K_RATESERIES_2040 0x0002
422 #define ATH9K_RATESERIES_HALFGI 0x0004
424 struct ath9k_11n_rate_series {
432 #define CHANNEL_CW_INT 0x00002
433 #define CHANNEL_CCK 0x00020
434 #define CHANNEL_OFDM 0x00040
435 #define CHANNEL_2GHZ 0x00080
436 #define CHANNEL_5GHZ 0x00100
437 #define CHANNEL_PASSIVE 0x00200
438 #define CHANNEL_DYN 0x00400
439 #define CHANNEL_HALF 0x04000
440 #define CHANNEL_QUARTER 0x08000
441 #define CHANNEL_HT20 0x10000
442 #define CHANNEL_HT40PLUS 0x20000
443 #define CHANNEL_HT40MINUS 0x40000
445 #define CHANNEL_INTERFERENCE 0x01
446 #define CHANNEL_DFS 0x02
447 #define CHANNEL_4MS_LIMIT 0x04
448 #define CHANNEL_DFS_CLEAR 0x08
449 #define CHANNEL_DISALLOW_ADHOC 0x10
450 #define CHANNEL_PER_11D_ADHOC 0x20
452 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
453 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
454 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
455 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
456 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
457 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
458 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
459 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
460 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
461 #define CHANNEL_ALL \
470 struct ath9k_channel {
474 int8_t maxRegTxPower;
479 bool oneTimeCalsDone;
482 int16_t rawNoiseFloor;
485 u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
486 #ifdef ATH_NF_PER_CHAN
487 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
491 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
492 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
493 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
494 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
495 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
496 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
497 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
498 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
499 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
500 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
501 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
502 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
503 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
504 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
505 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
506 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
508 /* These macros check chanmode and not channelFlags */
509 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
510 ((_c)->chanmode == CHANNEL_G_HT20))
511 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
512 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
513 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
514 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
515 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
517 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
518 #define IS_CHAN_A_5MHZ_SPACED(_c) \
519 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
520 (((_c)->channel % 20) != 0) && \
521 (((_c)->channel % 10) != 0))
523 struct ath9k_keyval {
532 enum ath9k_key_type {
533 ATH9K_KEY_TYPE_CLEAR,
540 ATH9K_CIPHER_WEP = 0,
541 ATH9K_CIPHER_AES_OCB = 1,
542 ATH9K_CIPHER_AES_CCM = 2,
543 ATH9K_CIPHER_CKIP = 3,
544 ATH9K_CIPHER_TKIP = 4,
545 ATH9K_CIPHER_CLR = 5,
546 ATH9K_CIPHER_MIC = 127
549 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
550 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
551 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
552 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
553 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
554 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
555 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
556 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
557 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
559 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
560 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
561 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
562 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
563 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
564 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
566 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
567 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
569 #define SD_NO_CTL 0xE0
580 #define AR_EEPROM_MAC(i) (0x1d+(i))
582 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
583 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
584 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
585 #define AR_EEPROM_RFSILENT_POLARITY_S 1
587 #define CTRY_DEBUG 0x1ff
588 #define CTRY_DEFAULT 0
590 enum reg_ext_bitmap {
591 REG_EXT_JAPAN_MIDBAND = 1,
592 REG_EXT_FCC_DFS_HT40 = 2,
593 REG_EXT_JAPAN_NONDFS_HT40 = 3,
594 REG_EXT_JAPAN_DFS_HT40 = 4
597 struct ath9k_country_entry {
606 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
607 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
609 #define SM(_v, _f) (((_v) << _f##_S) & _f)
610 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
611 #define REG_RMW(_a, _r, _set, _clr) \
612 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
613 #define REG_RMW_FIELD(_a, _r, _f, _v) \
615 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
616 #define REG_SET_BIT(_a, _r, _f) \
617 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
618 #define REG_CLR_BIT(_a, _r, _f) \
619 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
621 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
624 #define INIT_CWMIN 15
625 #define INIT_CWMIN_11B 31
626 #define INIT_CWMAX 1023
627 #define INIT_SH_RETRY 10
628 #define INIT_LG_RETRY 10
629 #define INIT_SSH_RETRY 32
630 #define INIT_SLG_RETRY 32
632 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
634 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
635 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
637 #define IEEE80211_WEP_IVLEN 3
638 #define IEEE80211_WEP_KIDLEN 1
639 #define IEEE80211_WEP_CRCLEN 4
640 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
641 (IEEE80211_WEP_IVLEN + \
642 IEEE80211_WEP_KIDLEN + \
643 IEEE80211_WEP_CRCLEN))
644 #define MAX_RATE_POWER 63
646 enum ath9k_power_mode {
649 ATH9K_PM_NETWORK_SLEEP,
653 struct ath9k_mib_stats {
661 enum ath9k_ant_setting {
662 ATH9K_ANT_VARIABLE = 0,
674 #define ATH9K_SLOT_TIME_6 6
675 #define ATH9K_SLOT_TIME_9 9
676 #define ATH9K_SLOT_TIME_20 20
678 enum ath9k_ht_macmode {
679 ATH9K_HT_MACMODE_20 = 0,
680 ATH9K_HT_MACMODE_2040 = 1,
683 enum ath9k_ht_extprotspacing {
684 ATH9K_HT_EXTPROTSPACING_20 = 0,
685 ATH9K_HT_EXTPROTSPACING_25 = 1,
688 struct ath9k_ht_cwm {
689 enum ath9k_ht_macmode ht_macmode;
690 enum ath9k_ht_extprotspacing ht_extprotspacing;
694 ATH9K_ANI_PRESENT = 0x1,
695 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
696 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
697 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
698 ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
699 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
700 ATH9K_ANI_MODE = 0x40,
701 ATH9K_ANI_PHYERR_RESET = 0x80,
711 #define PHY_CCK PHY_DS
713 enum ath9k_tp_scale {
714 ATH9K_TP_SCALE_MAX = 0,
722 SER_REG_MODE_OFF = 0,
724 SER_REG_MODE_AUTO = 2,
727 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
728 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
729 #define AR_PHY_CCA_MIN_BAD_VALUE -121
730 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
731 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
733 #define ATH9K_NF_CAL_HIST_MAX 5
734 #define NUM_NF_READINGS 6
736 struct ath9k_nfcal_hist {
737 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
743 struct ath9k_beacon_state {
747 #define ATH9K_BEACON_PERIOD 0x0000ffff
748 #define ATH9K_BEACON_ENA 0x00800000
749 #define ATH9K_BEACON_RESET_TSF 0x01000000
752 u16 bs_cfpmaxduration;
755 u16 bs_bmissthreshold;
756 u32 bs_sleepduration;
759 struct ath9k_node_stats {
766 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
768 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
769 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
770 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
771 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
772 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
775 ATH9K_RESET_POWER_ON,
780 #define AH_USE_EEPROM 0x1
789 u16 ah_analog5GhzRev;
790 u16 ah_analog2GhzRev;
793 struct ath_softc *ah_sc;
794 enum ath9k_opmode ah_opmode;
795 struct ath9k_ops_config ah_config;
796 struct ath9k_hw_capabilities ah_caps;
800 int16_t ah_powerLimit;
801 u16 ah_maxPowerLevel;
805 u16 ah_currentRDInUse;
810 struct ath9k_channel ah_channels[150];
811 struct ath9k_channel *ah_curchan;
814 bool ah_isPciExpress;
818 u32 ah_rfkill_polarity;
820 #ifndef ATH_NF_PER_CHAN
821 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
825 struct chan_centers {
831 int ath_hal_getcapability(struct ath_hal *ah,
832 enum ath9k_capability_type type,
835 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
837 void ath9k_hw_detach(struct ath_hal *ah);
838 struct ath_hal *ath9k_hw_attach(u16 devid,
839 struct ath_softc *sc,
842 bool ath9k_regd_init_channels(struct ath_hal *ah,
843 u32 maxchans, u32 *nchans,
845 u32 maxregids, u32 *nregids,
848 bool enableExtendedChannels);
849 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
850 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
851 enum ath9k_int ints);
852 bool ath9k_hw_reset(struct ath_hal *ah,
853 struct ath9k_channel *chan,
854 enum ath9k_ht_macmode macmode,
855 u8 txchainmask, u8 rxchainmask,
856 enum ath9k_ht_extprotspacing extprotspacing,
859 bool ath9k_hw_phy_disable(struct ath_hal *ah);
860 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
862 void ath9k_hw_ani_monitor(struct ath_hal *ah,
863 const struct ath9k_node_stats *stats,
864 struct ath9k_channel *chan);
865 bool ath9k_hw_calibrate(struct ath_hal *ah,
866 struct ath9k_channel *chan,
870 s16 ath9k_hw_getchan_noise(struct ath_hal *ah,
871 struct ath9k_channel *chan);
872 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
874 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
875 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
877 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
878 void ath9k_hw_reset_tsf(struct ath_hal *ah);
879 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
880 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
882 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
884 const struct ath9k_keyval *k,
887 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
889 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
890 bool ath9k_hw_intrpend(struct ath_hal *ah);
891 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
892 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
894 void ath9k_hw_procmibevent(struct ath_hal *ah,
895 const struct ath9k_node_stats *stats);
896 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
897 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
898 bool ath9k_hw_phycounters(struct ath_hal *ah);
899 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
900 bool ath9k_hw_getcapability(struct ath_hal *ah,
901 enum ath9k_capability_type type,
904 bool ath9k_hw_setcapability(struct ath_hal *ah,
905 enum ath9k_capability_type type,
909 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
910 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
911 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
912 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
914 bool ath9k_hw_setpower(struct ath_hal *ah,
915 enum ath9k_power_mode mode);
916 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
917 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
918 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
919 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
920 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
921 enum ath9k_ant_setting settings,
922 struct ath9k_channel *chan,
926 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
927 int ath9k_hw_select_antconfig(struct ath_hal *ah,
929 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
931 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
932 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
933 const struct ath9k_rate_table *rates,
934 u32 frameLen, u16 rateix,
936 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
937 struct ath_desc *lastds,
938 u32 durUpdateEn, u32 rtsctsRate,
940 struct ath9k_11n_rate_series series[],
941 u32 nseries, u32 flags);
942 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
945 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
946 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
947 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
948 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
949 u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
950 struct ath9k_channel *chan);
951 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
952 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
953 struct ath9k_tx_queue_info *qinfo);
954 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
955 const struct ath9k_tx_queue_info *qinfo);
956 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
957 const struct ath9k_channel *c);
958 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
959 u32 pktLen, enum ath9k_pkt_type type,
960 u32 txPower, u32 keyIx,
961 enum ath9k_key_type keyType, u32 flags);
962 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
963 u32 segLen, bool firstSeg,
965 const struct ath_desc *ds0);
966 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
970 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
971 void ath9k_hw_beaconinit(struct ath_hal *ah,
972 u32 next_beacon, u32 beacon_period);
973 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
974 const struct ath9k_beacon_state *bs);
975 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
976 u32 size, u32 flags);
977 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
978 void ath9k_hw_rxena(struct ath_hal *ah);
979 void ath9k_hw_setopmode(struct ath_hal *ah);
980 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
981 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
983 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
984 void ath9k_hw_startpcureceive(struct ath_hal *ah);
985 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
986 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
987 int ath9k_hw_rxprocdesc(struct ath_hal *ah,
988 struct ath_desc *ds, u32 pa,
989 struct ath_desc *nds, u64 tsf);
990 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
991 int ath9k_hw_txprocdesc(struct ath_hal *ah,
992 struct ath_desc *ds);
993 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
995 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
997 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
998 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
999 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1000 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1001 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1002 struct ath_desc *ds, u32 vmf);
1003 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1004 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1005 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1006 const struct ath9k_tx_queue_info *qinfo);
1007 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1008 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1009 bool ath9k_hw_disable(struct ath_hal *ah);
1010 void ath9k_hw_rfdetach(struct ath_hal *ah);
1011 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1012 struct ath9k_channel *chan,
1013 struct chan_centers *centers);
1014 bool ath9k_get_channel_edges(struct ath_hal *ah,
1015 u16 flags, u16 *low,
1017 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
1018 u32 ah_signal_type);
1019 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 value);
1020 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
1021 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);