drivers/net/wireless/b43/dma.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "b43.h"
  31 #include "dma.h"
  32 #include "main.h"
  33 #include "debugfs.h"
  34 #include "xmit.h"
  35
  36 #include <linux/dma-mapping.h>
  37 #include <linux/pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/skbuff.h>
  40
  41 /* 32bit DMA ops. */
  42 static
  43 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
  44                                           int slot,
  45                                           struct b43_dmadesc_meta **meta)
  46 {
  47         struct b43_dmadesc32 *desc;
  48
  49         *meta = &(ring->meta[slot]);
  50         desc = ring->descbase;
  51         desc = &(desc[slot]);
  52
  53         return (struct b43_dmadesc_generic *)desc;
  54 }
  55
  56 static void op32_fill_descriptor(struct b43_dmaring *ring,
  57                                  struct b43_dmadesc_generic *desc,
  58                                  dma_addr_t dmaaddr, u16 bufsize,
  59                                  int start, int end, int irq)
  60 {
  61         struct b43_dmadesc32 *descbase = ring->descbase;
  62         int slot;
  63         u32 ctl;
  64         u32 addr;
  65         u32 addrext;
  66
  67         slot = (int)(&(desc->dma32) - descbase);
  68         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
  69
  70         addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
  71         addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
  72             >> SSB_DMA_TRANSLATION_SHIFT;
  73         addr |= ssb_dma_translation(ring->dev->dev);
  74         ctl = (bufsize - ring->frameoffset)
  75             & B43_DMA32_DCTL_BYTECNT;
  76         if (slot == ring->nr_slots - 1)
  77                 ctl |= B43_DMA32_DCTL_DTABLEEND;
  78         if (start)
  79                 ctl |= B43_DMA32_DCTL_FRAMESTART;
  80         if (end)
  81                 ctl |= B43_DMA32_DCTL_FRAMEEND;
  82         if (irq)
  83                 ctl |= B43_DMA32_DCTL_IRQ;
  84         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
  85             & B43_DMA32_DCTL_ADDREXT_MASK;
  86
  87         desc->dma32.control = cpu_to_le32(ctl);
  88         desc->dma32.address = cpu_to_le32(addr);
  89 }
  90
  91 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
  92 {
  93         b43_dma_write(ring, B43_DMA32_TXINDEX,
  94                       (u32) (slot * sizeof(struct b43_dmadesc32)));
  95 }
  96
  97 static void op32_tx_suspend(struct b43_dmaring *ring)
  98 {
  99         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 100                       | B43_DMA32_TXSUSPEND);
 101 }
 102
 103 static void op32_tx_resume(struct b43_dmaring *ring)
 104 {
 105         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 106                       & ~B43_DMA32_TXSUSPEND);
 107 }
 108
 109 static int op32_get_current_rxslot(struct b43_dmaring *ring)
 110 {
 111         u32 val;
 112
 113         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
 114         val &= B43_DMA32_RXDPTR;
 115
 116         return (val / sizeof(struct b43_dmadesc32));
 117 }
 118
 119 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
 120 {
 121         b43_dma_write(ring, B43_DMA32_RXINDEX,
 122                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 123 }
 124
 125 static const struct b43_dma_ops dma32_ops = {
 126         .idx2desc = op32_idx2desc,
 127         .fill_descriptor = op32_fill_descriptor,
 128         .poke_tx = op32_poke_tx,
 129         .tx_suspend = op32_tx_suspend,
 130         .tx_resume = op32_tx_resume,
 131         .get_current_rxslot = op32_get_current_rxslot,
 132         .set_current_rxslot = op32_set_current_rxslot,
 133 };
 134
 135 /* 64bit DMA ops. */
 136 static
 137 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
 138                                           int slot,
 139                                           struct b43_dmadesc_meta **meta)
 140 {
 141         struct b43_dmadesc64 *desc;
 142
 143         *meta = &(ring->meta[slot]);
 144         desc = ring->descbase;
 145         desc = &(desc[slot]);
 146
 147         return (struct b43_dmadesc_generic *)desc;
 148 }
 149
 150 static void op64_fill_descriptor(struct b43_dmaring *ring,
 151                                  struct b43_dmadesc_generic *desc,
 152                                  dma_addr_t dmaaddr, u16 bufsize,
 153                                  int start, int end, int irq)
 154 {
 155         struct b43_dmadesc64 *descbase = ring->descbase;
 156         int slot;
 157         u32 ctl0 = 0, ctl1 = 0;
 158         u32 addrlo, addrhi;
 159         u32 addrext;
 160
 161         slot = (int)(&(desc->dma64) - descbase);
 162         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 163
 164         addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
 165         addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
 166         addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
 167             >> SSB_DMA_TRANSLATION_SHIFT;
 168         addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
 169         if (slot == ring->nr_slots - 1)
 170                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 171         if (start)
 172                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
 173         if (end)
 174                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
 175         if (irq)
 176                 ctl0 |= B43_DMA64_DCTL0_IRQ;
 177         ctl1 |= (bufsize - ring->frameoffset)
 178             & B43_DMA64_DCTL1_BYTECNT;
 179         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
 180             & B43_DMA64_DCTL1_ADDREXT_MASK;
 181
 182         desc->dma64.control0 = cpu_to_le32(ctl0);
 183         desc->dma64.control1 = cpu_to_le32(ctl1);
 184         desc->dma64.address_low = cpu_to_le32(addrlo);
 185         desc->dma64.address_high = cpu_to_le32(addrhi);
 186 }
 187
 188 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
 189 {
 190         b43_dma_write(ring, B43_DMA64_TXINDEX,
 191                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 192 }
 193
 194 static void op64_tx_suspend(struct b43_dmaring *ring)
 195 {
 196         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 197                       | B43_DMA64_TXSUSPEND);
 198 }
 199
 200 static void op64_tx_resume(struct b43_dmaring *ring)
 201 {
 202         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 203                       & ~B43_DMA64_TXSUSPEND);
 204 }
 205
 206 static int op64_get_current_rxslot(struct b43_dmaring *ring)
 207 {
 208         u32 val;
 209
 210         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
 211         val &= B43_DMA64_RXSTATDPTR;
 212
 213         return (val / sizeof(struct b43_dmadesc64));
 214 }
 215
 216 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
 217 {
 218         b43_dma_write(ring, B43_DMA64_RXINDEX,
 219                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 220 }
 221
 222 static const struct b43_dma_ops dma64_ops = {
 223         .idx2desc = op64_idx2desc,
 224         .fill_descriptor = op64_fill_descriptor,
 225         .poke_tx = op64_poke_tx,
 226         .tx_suspend = op64_tx_suspend,
 227         .tx_resume = op64_tx_resume,
 228         .get_current_rxslot = op64_get_current_rxslot,
 229         .set_current_rxslot = op64_set_current_rxslot,
 230 };
 231
 232 static inline int free_slots(struct b43_dmaring *ring)
 233 {
 234         return (ring->nr_slots - ring->used_slots);
 235 }
 236
 237 static inline int next_slot(struct b43_dmaring *ring, int slot)
 238 {
 239         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
 240         if (slot == ring->nr_slots - 1)
 241                 return 0;
 242         return slot + 1;
 243 }
 244
 245 static inline int prev_slot(struct b43_dmaring *ring, int slot)
 246 {
 247         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
 248         if (slot == 0)
 249                 return ring->nr_slots - 1;
 250         return slot - 1;
 251 }
 252
 253 #ifdef CONFIG_B43_DEBUG
 254 static void update_max_used_slots(struct b43_dmaring *ring,
 255                                   int current_used_slots)
 256 {
 257         if (current_used_slots <= ring->max_used_slots)
 258                 return;
 259         ring->max_used_slots = current_used_slots;
 260         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
 261                 b43dbg(ring->dev->wl,
 262                        "max_used_slots increased to %d on %s ring %d\n",
 263                        ring->max_used_slots,
 264                        ring->tx ? "TX" : "RX", ring->index);
 265         }
 266 }
 267 #else
 268 static inline
 269     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
 270 {
 271 }
 272 #endif /* DEBUG */
 273
 274 /* Request a slot for usage. */
 275 static inline int request_slot(struct b43_dmaring *ring)
 276 {
 277         int slot;
 278
 279         B43_WARN_ON(!ring->tx);
 280         B43_WARN_ON(ring->stopped);
 281         B43_WARN_ON(free_slots(ring) == 0);
 282
 283         slot = next_slot(ring, ring->current_slot);
 284         ring->current_slot = slot;
 285         ring->used_slots++;
 286
 287         update_max_used_slots(ring, ring->used_slots);
 288
 289         return slot;
 290 }
 291
 292 /* Mac80211-queue to b43-ring mapping */
 293 static struct b43_dmaring *priority_to_txring(struct b43_wldev *dev,
 294                                               int queue_priority)
 295 {
 296         struct b43_dmaring *ring;
 297
 298 /*FIXME: For now we always run on TX-ring-1 */
 299         return dev->dma.tx_ring1;
 300
 301         /* 0 = highest priority */
 302         switch (queue_priority) {
 303         default:
 304                 B43_WARN_ON(1);
 305                 /* fallthrough */
 306         case 0:
 307                 ring = dev->dma.tx_ring3;
 308                 break;
 309         case 1:
 310                 ring = dev->dma.tx_ring2;
 311                 break;
 312         case 2:
 313                 ring = dev->dma.tx_ring1;
 314                 break;
 315         case 3:
 316                 ring = dev->dma.tx_ring0;
 317                 break;
 318         case 4:
 319                 ring = dev->dma.tx_ring4;
 320                 break;
 321         case 5:
 322                 ring = dev->dma.tx_ring5;
 323                 break;
 324         }
 325
 326         return ring;
 327 }
 328
 329 /* Bcm43xx-ring to mac80211-queue mapping */
 330 static inline int txring_to_priority(struct b43_dmaring *ring)
 331 {
 332         static const u8 idx_to_prio[] = { 3, 2, 1, 0, 4, 5, };
 333
 334 /*FIXME: have only one queue, for now */
 335         return 0;
 336
 337         return idx_to_prio[ring->index];
 338 }
 339
 340 u16 b43_dmacontroller_base(int dma64bit, int controller_idx)
 341 {
 342         static const u16 map64[] = {
 343                 B43_MMIO_DMA64_BASE0,
 344                 B43_MMIO_DMA64_BASE1,
 345                 B43_MMIO_DMA64_BASE2,
 346                 B43_MMIO_DMA64_BASE3,
 347                 B43_MMIO_DMA64_BASE4,
 348                 B43_MMIO_DMA64_BASE5,
 349         };
 350         static const u16 map32[] = {
 351                 B43_MMIO_DMA32_BASE0,
 352                 B43_MMIO_DMA32_BASE1,
 353                 B43_MMIO_DMA32_BASE2,
 354                 B43_MMIO_DMA32_BASE3,
 355                 B43_MMIO_DMA32_BASE4,
 356                 B43_MMIO_DMA32_BASE5,
 357         };
 358
 359         if (dma64bit) {
 360                 B43_WARN_ON(!(controller_idx >= 0 &&
 361                               controller_idx < ARRAY_SIZE(map64)));
 362                 return map64[controller_idx];
 363         }
 364         B43_WARN_ON(!(controller_idx >= 0 &&
 365                       controller_idx < ARRAY_SIZE(map32)));
 366         return map32[controller_idx];
 367 }
 368
 369 static inline
 370     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
 371                               unsigned char *buf, size_t len, int tx)
 372 {
 373         dma_addr_t dmaaddr;
 374
 375         if (tx) {
 376                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 377                                          buf, len, DMA_TO_DEVICE);
 378         } else {
 379                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 380                                          buf, len, DMA_FROM_DEVICE);
 381         }
 382
 383         return dmaaddr;
 384 }
 385
 386 static inline
 387     void unmap_descbuffer(struct b43_dmaring *ring,
 388                           dma_addr_t addr, size_t len, int tx)
 389 {
 390         if (tx) {
 391                 dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE);
 392         } else {
 393                 dma_unmap_single(ring->dev->dev->dev,
 394                                  addr, len, DMA_FROM_DEVICE);
 395         }
 396 }
 397
 398 static inline
 399     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
 400                                  dma_addr_t addr, size_t len)
 401 {
 402         B43_WARN_ON(ring->tx);
 403         dma_sync_single_for_cpu(ring->dev->dev->dev,
 404                                 addr, len, DMA_FROM_DEVICE);
 405 }
 406
 407 static inline
 408     void sync_descbuffer_for_device(struct b43_dmaring *ring,
 409                                     dma_addr_t addr, size_t len)
 410 {
 411         B43_WARN_ON(ring->tx);
 412         dma_sync_single_for_device(ring->dev->dev->dev,
 413                                    addr, len, DMA_FROM_DEVICE);
 414 }
 415
 416 static inline
 417     void free_descriptor_buffer(struct b43_dmaring *ring,
 418                                 struct b43_dmadesc_meta *meta)
 419 {
 420         if (meta->skb) {
 421                 dev_kfree_skb_any(meta->skb);
 422                 meta->skb = NULL;
 423         }
 424 }
 425
 426 static int alloc_ringmemory(struct b43_dmaring *ring)
 427 {
 428         struct device *dev = ring->dev->dev->dev;
 429         gfp_t flags = GFP_KERNEL;
 430
 431         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
 432          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
 433          * has shown that 4K is sufficient for the latter as long as the buffer
 434          * does not cross an 8K boundary.
 435          *
 436          * For unknown reasons - possibly a hardware error - the BCM4311 rev
 437          * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
 438          * which accounts for the GFP_DMA flag below.
 439          */
 440         if (ring->dma64)
 441                 flags |= GFP_DMA;
 442         ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
 443                                             &(ring->dmabase), flags);
 444         if (!ring->descbase) {
 445                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
 446                 return -ENOMEM;
 447         }
 448         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
 449
 450         return 0;
 451 }
 452
 453 static void free_ringmemory(struct b43_dmaring *ring)
 454 {
 455         struct device *dev = ring->dev->dev->dev;
 456
 457         dma_free_coherent(dev, B43_DMA_RINGMEMSIZE,
 458                           ring->descbase, ring->dmabase);
 459 }
 460
 461 /* Reset the RX DMA channel */
 462 int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
 463 {
 464         int i;
 465         u32 value;
 466         u16 offset;
 467
 468         might_sleep();
 469
 470         offset = dma64 ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
 471         b43_write32(dev, mmio_base + offset, 0);
 472         for (i = 0; i < 10; i++) {
 473                 offset = dma64 ? B43_DMA64_RXSTATUS : B43_DMA32_RXSTATUS;
 474                 value = b43_read32(dev, mmio_base + offset);
 475                 if (dma64) {
 476                         value &= B43_DMA64_RXSTAT;
 477                         if (value == B43_DMA64_RXSTAT_DISABLED) {
 478                                 i = -1;
 479                                 break;
 480                         }
 481                 } else {
 482                         value &= B43_DMA32_RXSTATE;
 483                         if (value == B43_DMA32_RXSTAT_DISABLED) {
 484                                 i = -1;
 485                                 break;
 486                         }
 487                 }
 488                 msleep(1);
 489         }
 490         if (i != -1) {
 491                 b43err(dev->wl, "DMA RX reset timed out\n");
 492                 return -ENODEV;
 493         }
 494
 495         return 0;
 496 }
 497
 498 /* Reset the TX DMA channel */
 499 int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
 500 {
 501         int i;
 502         u32 value;
 503         u16 offset;
 504
 505         might_sleep();
 506
 507         for (i = 0; i < 10; i++) {
 508                 offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
 509                 value = b43_read32(dev, mmio_base + offset);
 510                 if (dma64) {
 511                         value &= B43_DMA64_TXSTAT;
 512                         if (value == B43_DMA64_TXSTAT_DISABLED ||
 513                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
 514                             value == B43_DMA64_TXSTAT_STOPPED)
 515                                 break;
 516                 } else {
 517                         value &= B43_DMA32_TXSTATE;
 518                         if (value == B43_DMA32_TXSTAT_DISABLED ||
 519                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
 520                             value == B43_DMA32_TXSTAT_STOPPED)
 521                                 break;
 522                 }
 523                 msleep(1);
 524         }
 525         offset = dma64 ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
 526         b43_write32(dev, mmio_base + offset, 0);
 527         for (i = 0; i < 10; i++) {
 528                 offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
 529                 value = b43_read32(dev, mmio_base + offset);
 530                 if (dma64) {
 531                         value &= B43_DMA64_TXSTAT;
 532                         if (value == B43_DMA64_TXSTAT_DISABLED) {
 533                                 i = -1;
 534                                 break;
 535                         }
 536                 } else {
 537                         value &= B43_DMA32_TXSTATE;
 538                         if (value == B43_DMA32_TXSTAT_DISABLED) {
 539                                 i = -1;
 540                                 break;
 541                         }
 542                 }
 543                 msleep(1);
 544         }
 545         if (i != -1) {
 546                 b43err(dev->wl, "DMA TX reset timed out\n");
 547                 return -ENODEV;
 548         }
 549         /* ensure the reset is completed. */
 550         msleep(1);
 551
 552         return 0;
 553 }
 554
 555 static int setup_rx_descbuffer(struct b43_dmaring *ring,
 556                                struct b43_dmadesc_generic *desc,
 557                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
 558 {
 559         struct b43_rxhdr_fw4 *rxhdr;
 560         struct b43_hwtxstatus *txstat;
 561         dma_addr_t dmaaddr;
 562         struct sk_buff *skb;
 563
 564         B43_WARN_ON(ring->tx);
 565
 566         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 567         if (unlikely(!skb))
 568                 return -ENOMEM;
 569         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 570         if (dma_mapping_error(dmaaddr)) {
 571                 /* ugh. try to realloc in zone_dma */
 572                 gfp_flags |= GFP_DMA;
 573
 574                 dev_kfree_skb_any(skb);
 575
 576                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 577                 if (unlikely(!skb))
 578                         return -ENOMEM;
 579                 dmaaddr = map_descbuffer(ring, skb->data,
 580                                          ring->rx_buffersize, 0);
 581         }
 582
 583         if (dma_mapping_error(dmaaddr)) {
 584                 dev_kfree_skb_any(skb);
 585                 return -EIO;
 586         }
 587
 588         meta->skb = skb;
 589         meta->dmaaddr = dmaaddr;
 590         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 591                                    ring->rx_buffersize, 0, 0, 0);
 592
 593         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
 594         rxhdr->frame_len = 0;
 595         txstat = (struct b43_hwtxstatus *)(skb->data);
 596         txstat->cookie = 0;
 597
 598         return 0;
 599 }
 600
 601 /* Allocate the initial descbuffers.
 602  * This is used for an RX ring only.
 603  */
 604 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
 605 {
 606         int i, err = -ENOMEM;
 607         struct b43_dmadesc_generic *desc;
 608         struct b43_dmadesc_meta *meta;
 609
 610         for (i = 0; i < ring->nr_slots; i++) {
 611                 desc = ring->ops->idx2desc(ring, i, &meta);
 612
 613                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 614                 if (err) {
 615                         b43err(ring->dev->wl,
 616                                "Failed to allocate initial descbuffers\n");
 617                         goto err_unwind;
 618                 }
 619         }
 620         mb();
 621         ring->used_slots = ring->nr_slots;
 622         err = 0;
 623       out:
 624         return err;
 625
 626       err_unwind:
 627         for (i--; i >= 0; i--) {
 628                 desc = ring->ops->idx2desc(ring, i, &meta);
 629
 630                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 631                 dev_kfree_skb(meta->skb);
 632         }
 633         goto out;
 634 }
 635
 636 /* Do initial setup of the DMA controller.
 637  * Reset the controller, write the ring busaddress
 638  * and switch the "enable" bit on.
 639  */
 640 static int dmacontroller_setup(struct b43_dmaring *ring)
 641 {
 642         int err = 0;
 643         u32 value;
 644         u32 addrext;
 645         u32 trans = ssb_dma_translation(ring->dev->dev);
 646
 647         if (ring->tx) {
 648                 if (ring->dma64) {
 649                         u64 ringbase = (u64) (ring->dmabase);
 650
 651                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 652                             >> SSB_DMA_TRANSLATION_SHIFT;
 653                         value = B43_DMA64_TXENABLE;
 654                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 655                             & B43_DMA64_TXADDREXT_MASK;
 656                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 657                         b43_dma_write(ring, B43_DMA64_TXRINGLO,
 658                                       (ringbase & 0xFFFFFFFF));
 659                         b43_dma_write(ring, B43_DMA64_TXRINGHI,
 660                                       ((ringbase >> 32) &
 661                                        ~SSB_DMA_TRANSLATION_MASK)
 662                                       | (trans << 1));
 663                 } else {
 664                         u32 ringbase = (u32) (ring->dmabase);
 665
 666                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 667                             >> SSB_DMA_TRANSLATION_SHIFT;
 668                         value = B43_DMA32_TXENABLE;
 669                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 670                             & B43_DMA32_TXADDREXT_MASK;
 671                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 672                         b43_dma_write(ring, B43_DMA32_TXRING,
 673                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 674                                       | trans);
 675                 }
 676         } else {
 677                 err = alloc_initial_descbuffers(ring);
 678                 if (err)
 679                         goto out;
 680                 if (ring->dma64) {
 681                         u64 ringbase = (u64) (ring->dmabase);
 682
 683                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 684                             >> SSB_DMA_TRANSLATION_SHIFT;
 685                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
 686                         value |= B43_DMA64_RXENABLE;
 687                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 688                             & B43_DMA64_RXADDREXT_MASK;
 689                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 690                         b43_dma_write(ring, B43_DMA64_RXRINGLO,
 691                                       (ringbase & 0xFFFFFFFF));
 692                         b43_dma_write(ring, B43_DMA64_RXRINGHI,
 693                                       ((ringbase >> 32) &
 694                                        ~SSB_DMA_TRANSLATION_MASK)
 695                                       | (trans << 1));
 696                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 697                                       sizeof(struct b43_dmadesc64));
 698                 } else {
 699                         u32 ringbase = (u32) (ring->dmabase);
 700
 701                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 702                             >> SSB_DMA_TRANSLATION_SHIFT;
 703                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
 704                         value |= B43_DMA32_RXENABLE;
 705                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 706                             & B43_DMA32_RXADDREXT_MASK;
 707                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 708                         b43_dma_write(ring, B43_DMA32_RXRING,
 709                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 710                                       | trans);
 711                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
 712                                       sizeof(struct b43_dmadesc32));
 713                 }
 714         }
 715
 716 out:
 717         return err;
 718 }
 719
 720 /* Shutdown the DMA controller. */
 721 static void dmacontroller_cleanup(struct b43_dmaring *ring)
 722 {
 723         if (ring->tx) {
 724                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
 725                                            ring->dma64);
 726                 if (ring->dma64) {
 727                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
 728                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
 729                 } else
 730                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
 731         } else {
 732                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
 733                                            ring->dma64);
 734                 if (ring->dma64) {
 735                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
 736                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
 737                 } else
 738                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
 739         }
 740 }
 741
 742 static void free_all_descbuffers(struct b43_dmaring *ring)
 743 {
 744         struct b43_dmadesc_generic *desc;
 745         struct b43_dmadesc_meta *meta;
 746         int i;
 747
 748         if (!ring->used_slots)
 749                 return;
 750         for (i = 0; i < ring->nr_slots; i++) {
 751                 desc = ring->ops->idx2desc(ring, i, &meta);
 752
 753                 if (!meta->skb) {
 754                         B43_WARN_ON(!ring->tx);
 755                         continue;
 756                 }
 757                 if (ring->tx) {
 758                         unmap_descbuffer(ring, meta->dmaaddr,
 759                                          meta->skb->len, 1);
 760                 } else {
 761                         unmap_descbuffer(ring, meta->dmaaddr,
 762                                          ring->rx_buffersize, 0);
 763                 }
 764                 free_descriptor_buffer(ring, meta);
 765         }
 766 }
 767
 768 static u64 supported_dma_mask(struct b43_wldev *dev)
 769 {
 770         u32 tmp;
 771         u16 mmio_base;
 772
 773         tmp = b43_read32(dev, SSB_TMSHIGH);
 774         if (tmp & SSB_TMSHIGH_DMA64)
 775                 return DMA_64BIT_MASK;
 776         mmio_base = b43_dmacontroller_base(0, 0);
 777         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
 778         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
 779         if (tmp & B43_DMA32_TXADDREXT_MASK)
 780                 return DMA_32BIT_MASK;
 781
 782         return DMA_30BIT_MASK;
 783 }
 784
 785 /* Main initialization function. */
 786 static
 787 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
 788                                       int controller_index,
 789                                       int for_tx, int dma64)
 790 {
 791         struct b43_dmaring *ring;
 792         int err;
 793         int nr_slots;
 794         dma_addr_t dma_test;
 795
 796         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 797         if (!ring)
 798                 goto out;
 799
 800         nr_slots = B43_RXRING_SLOTS;
 801         if (for_tx)
 802                 nr_slots = B43_TXRING_SLOTS;
 803
 804         ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
 805                              GFP_KERNEL);
 806         if (!ring->meta)
 807                 goto err_kfree_ring;
 808         if (for_tx) {
 809                 ring->txhdr_cache = kcalloc(nr_slots,
 810                                             sizeof(struct b43_txhdr_fw4),
 811                                             GFP_KERNEL);
 812                 if (!ring->txhdr_cache)
 813                         goto err_kfree_meta;
 814
 815                 /* test for ability to dma to txhdr_cache */
 816                 dma_test = dma_map_single(dev->dev->dev,
 817                                           ring->txhdr_cache,
 818                                           sizeof(struct b43_txhdr_fw4),
 819                                           DMA_TO_DEVICE);
 820
 821                 if (dma_mapping_error(dma_test)) {
 822                         /* ugh realloc */
 823                         kfree(ring->txhdr_cache);
 824                         ring->txhdr_cache = kcalloc(nr_slots,
 825                                                     sizeof(struct
 826                                                            b43_txhdr_fw4),
 827                                                     GFP_KERNEL | GFP_DMA);
 828                         if (!ring->txhdr_cache)
 829                                 goto err_kfree_meta;
 830
 831                         dma_test = dma_map_single(dev->dev->dev,
 832                                                   ring->txhdr_cache,
 833                                                   sizeof(struct b43_txhdr_fw4),
 834                                                   DMA_TO_DEVICE);
 835
 836                         if (dma_mapping_error(dma_test))
 837                                 goto err_kfree_txhdr_cache;
 838                 }
 839
 840                 dma_unmap_single(dev->dev->dev,
 841                                  dma_test, sizeof(struct b43_txhdr_fw4),
 842                                  DMA_TO_DEVICE);
 843         }
 844
 845         ring->dev = dev;
 846         ring->nr_slots = nr_slots;
 847         ring->mmio_base = b43_dmacontroller_base(dma64, controller_index);
 848         ring->index = controller_index;
 849         ring->dma64 = !!dma64;
 850         if (dma64)
 851                 ring->ops = &dma64_ops;
 852         else
 853                 ring->ops = &dma32_ops;
 854         if (for_tx) {
 855                 ring->tx = 1;
 856                 ring->current_slot = -1;
 857         } else {
 858                 if (ring->index == 0) {
 859                         ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
 860                         ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
 861                 } else if (ring->index == 3) {
 862                         ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
 863                         ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
 864                 } else
 865                         B43_WARN_ON(1);
 866         }
 867         spin_lock_init(&ring->lock);
 868 #ifdef CONFIG_B43_DEBUG
 869         ring->last_injected_overflow = jiffies;
 870 #endif
 871
 872         err = alloc_ringmemory(ring);
 873         if (err)
 874                 goto err_kfree_txhdr_cache;
 875         err = dmacontroller_setup(ring);
 876         if (err)
 877                 goto err_free_ringmemory;
 878
 879       out:
 880         return ring;
 881
 882       err_free_ringmemory:
 883         free_ringmemory(ring);
 884       err_kfree_txhdr_cache:
 885         kfree(ring->txhdr_cache);
 886       err_kfree_meta:
 887         kfree(ring->meta);
 888       err_kfree_ring:
 889         kfree(ring);
 890         ring = NULL;
 891         goto out;
 892 }
 893
 894 /* Main cleanup function. */
 895 static void b43_destroy_dmaring(struct b43_dmaring *ring)
 896 {
 897         if (!ring)
 898                 return;
 899
 900         b43dbg(ring->dev->wl, "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
 901                (ring->dma64) ? "64" : "32",
 902                ring->mmio_base,
 903                (ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots);
 904         /* Device IRQs are disabled prior entering this function,
 905          * so no need to take care of concurrency with rx handler stuff.
 906          */
 907         dmacontroller_cleanup(ring);
 908         free_all_descbuffers(ring);
 909         free_ringmemory(ring);
 910
 911         kfree(ring->txhdr_cache);
 912         kfree(ring->meta);
 913         kfree(ring);
 914 }
 915
 916 void b43_dma_free(struct b43_wldev *dev)
 917 {
 918         struct b43_dma *dma;
 919
 920         if (b43_using_pio(dev))
 921                 return;
 922         dma = &dev->dma;
 923
 924         b43_destroy_dmaring(dma->rx_ring3);
 925         dma->rx_ring3 = NULL;
 926         b43_destroy_dmaring(dma->rx_ring0);
 927         dma->rx_ring0 = NULL;
 928
 929         b43_destroy_dmaring(dma->tx_ring5);
 930         dma->tx_ring5 = NULL;
 931         b43_destroy_dmaring(dma->tx_ring4);
 932         dma->tx_ring4 = NULL;
 933         b43_destroy_dmaring(dma->tx_ring3);
 934         dma->tx_ring3 = NULL;
 935         b43_destroy_dmaring(dma->tx_ring2);
 936         dma->tx_ring2 = NULL;
 937         b43_destroy_dmaring(dma->tx_ring1);
 938         dma->tx_ring1 = NULL;
 939         b43_destroy_dmaring(dma->tx_ring0);
 940         dma->tx_ring0 = NULL;
 941 }
 942
 943 int b43_dma_init(struct b43_wldev *dev)
 944 {
 945         struct b43_dma *dma = &dev->dma;
 946         struct b43_dmaring *ring;
 947         int err;
 948         u64 dmamask;
 949         int dma64 = 0;
 950
 951         dmamask = supported_dma_mask(dev);
 952         if (dmamask == DMA_64BIT_MASK)
 953                 dma64 = 1;
 954
 955         err = ssb_dma_set_mask(dev->dev, dmamask);
 956         if (err) {
 957 #ifdef B43_PIO
 958                 b43warn(dev->wl, "DMA for this device not supported. "
 959                         "Falling back to PIO\n");
 960                 dev->__using_pio = 1;
 961                 return -EAGAIN;
 962 #else
 963                 b43err(dev->wl, "DMA for this device not supported and "
 964                        "no PIO support compiled in\n");
 965                 return -EOPNOTSUPP;
 966 #endif
 967         }
 968
 969         err = -ENOMEM;
 970         /* setup TX DMA channels. */
 971         ring = b43_setup_dmaring(dev, 0, 1, dma64);
 972         if (!ring)
 973                 goto out;
 974         dma->tx_ring0 = ring;
 975
 976         ring = b43_setup_dmaring(dev, 1, 1, dma64);
 977         if (!ring)
 978                 goto err_destroy_tx0;
 979         dma->tx_ring1 = ring;
 980
 981         ring = b43_setup_dmaring(dev, 2, 1, dma64);
 982         if (!ring)
 983                 goto err_destroy_tx1;
 984         dma->tx_ring2 = ring;
 985
 986         ring = b43_setup_dmaring(dev, 3, 1, dma64);
 987         if (!ring)
 988                 goto err_destroy_tx2;
 989         dma->tx_ring3 = ring;
 990
 991         ring = b43_setup_dmaring(dev, 4, 1, dma64);
 992         if (!ring)
 993                 goto err_destroy_tx3;
 994         dma->tx_ring4 = ring;
 995
 996         ring = b43_setup_dmaring(dev, 5, 1, dma64);
 997         if (!ring)
 998                 goto err_destroy_tx4;
 999         dma->tx_ring5 = ring;
1000
1001         /* setup RX DMA channels. */
1002         ring = b43_setup_dmaring(dev, 0, 0, dma64);
1003         if (!ring)
1004                 goto err_destroy_tx5;
1005         dma->rx_ring0 = ring;
1006
1007         if (dev->dev->id.revision < 5) {
1008                 ring = b43_setup_dmaring(dev, 3, 0, dma64);
1009                 if (!ring)
1010                         goto err_destroy_rx0;
1011                 dma->rx_ring3 = ring;
1012         }
1013
1014         b43dbg(dev->wl, "%d-bit DMA initialized\n",
1015                (dmamask == DMA_64BIT_MASK) ? 64 :
1016                (dmamask == DMA_32BIT_MASK) ? 32 : 30);
1017         err = 0;
1018       out:
1019         return err;
1020
1021       err_destroy_rx0:
1022         b43_destroy_dmaring(dma->rx_ring0);
1023         dma->rx_ring0 = NULL;
1024       err_destroy_tx5:
1025         b43_destroy_dmaring(dma->tx_ring5);
1026         dma->tx_ring5 = NULL;
1027       err_destroy_tx4:
1028         b43_destroy_dmaring(dma->tx_ring4);
1029         dma->tx_ring4 = NULL;
1030       err_destroy_tx3:
1031         b43_destroy_dmaring(dma->tx_ring3);
1032         dma->tx_ring3 = NULL;
1033       err_destroy_tx2:
1034         b43_destroy_dmaring(dma->tx_ring2);
1035         dma->tx_ring2 = NULL;
1036       err_destroy_tx1:
1037         b43_destroy_dmaring(dma->tx_ring1);
1038         dma->tx_ring1 = NULL;
1039       err_destroy_tx0:
1040         b43_destroy_dmaring(dma->tx_ring0);
1041         dma->tx_ring0 = NULL;
1042         goto out;
1043 }
1044
1045 /* Generate a cookie for the TX header. */
1046 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1047 {
1048         u16 cookie = 0x1000;
1049
1050         /* Use the upper 4 bits of the cookie as
1051          * DMA controller ID and store the slot number
1052          * in the lower 12 bits.
1053          * Note that the cookie must never be 0, as this
1054          * is a special value used in RX path.
1055          */
1056         switch (ring->index) {
1057         case 0:
1058                 cookie = 0xA000;
1059                 break;
1060         case 1:
1061                 cookie = 0xB000;
1062                 break;
1063         case 2:
1064                 cookie = 0xC000;
1065                 break;
1066         case 3:
1067                 cookie = 0xD000;
1068                 break;
1069         case 4:
1070                 cookie = 0xE000;
1071                 break;
1072         case 5:
1073                 cookie = 0xF000;
1074                 break;
1075         }
1076         B43_WARN_ON(slot & ~0x0FFF);
1077         cookie |= (u16) slot;
1078
1079         return cookie;
1080 }
1081
1082 /* Inspect a cookie and find out to which controller/slot it belongs. */
1083 static
1084 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1085 {
1086         struct b43_dma *dma = &dev->dma;
1087         struct b43_dmaring *ring = NULL;
1088
1089         switch (cookie & 0xF000) {
1090         case 0xA000:
1091                 ring = dma->tx_ring0;
1092                 break;
1093         case 0xB000:
1094                 ring = dma->tx_ring1;
1095                 break;
1096         case 0xC000:
1097                 ring = dma->tx_ring2;
1098                 break;
1099         case 0xD000:
1100                 ring = dma->tx_ring3;
1101                 break;
1102         case 0xE000:
1103                 ring = dma->tx_ring4;
1104                 break;
1105         case 0xF000:
1106                 ring = dma->tx_ring5;
1107                 break;
1108         default:
1109                 B43_WARN_ON(1);
1110         }
1111         *slot = (cookie & 0x0FFF);
1112         B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1113
1114         return ring;
1115 }
1116
1117 static int dma_tx_fragment(struct b43_dmaring *ring,
1118                            struct sk_buff *skb,
1119                            struct ieee80211_tx_control *ctl)
1120 {
1121         const struct b43_dma_ops *ops = ring->ops;
1122         u8 *header;
1123         int slot;
1124         int err;
1125         struct b43_dmadesc_generic *desc;
1126         struct b43_dmadesc_meta *meta;
1127         struct b43_dmadesc_meta *meta_hdr;
1128         struct sk_buff *bounce_skb;
1129
1130 #define SLOTS_PER_PACKET  2
1131         B43_WARN_ON(skb_shinfo(skb)->nr_frags);
1132
1133         /* Get a slot for the header. */
1134         slot = request_slot(ring);
1135         desc = ops->idx2desc(ring, slot, &meta_hdr);
1136         memset(meta_hdr, 0, sizeof(*meta_hdr));
1137
1138         header = &(ring->txhdr_cache[slot * sizeof(struct b43_txhdr_fw4)]);
1139         b43_generate_txhdr(ring->dev, header,
1140                            skb->data, skb->len, ctl,
1141                            generate_cookie(ring, slot));
1142
1143         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1144                                            sizeof(struct b43_txhdr_fw4), 1);
1145         if (dma_mapping_error(meta_hdr->dmaaddr))
1146                 return -EIO;
1147         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1148                              sizeof(struct b43_txhdr_fw4), 1, 0, 0);
1149
1150         /* Get a slot for the payload. */
1151         slot = request_slot(ring);
1152         desc = ops->idx2desc(ring, slot, &meta);
1153         memset(meta, 0, sizeof(*meta));
1154
1155         memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1156         meta->skb = skb;
1157         meta->is_last_fragment = 1;
1158
1159         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1160         /* create a bounce buffer in zone_dma on mapping failure. */
1161         if (dma_mapping_error(meta->dmaaddr)) {
1162                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1163                 if (!bounce_skb) {
1164                         err = -ENOMEM;
1165                         goto out_unmap_hdr;
1166                 }
1167
1168                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1169                 dev_kfree_skb_any(skb);
1170                 skb = bounce_skb;
1171                 meta->skb = skb;
1172                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1173                 if (dma_mapping_error(meta->dmaaddr)) {
1174                         err = -EIO;
1175                         goto out_free_bounce;
1176                 }
1177         }
1178
1179         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1180
1181         /* Now transfer the whole frame. */
1182         wmb();
1183         ops->poke_tx(ring, next_slot(ring, slot));
1184         return 0;
1185
1186       out_free_bounce:
1187         dev_kfree_skb_any(skb);
1188       out_unmap_hdr:
1189         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1190                          sizeof(struct b43_txhdr_fw4), 1);
1191         return err;
1192 }
1193
1194 static inline int should_inject_overflow(struct b43_dmaring *ring)
1195 {
1196 #ifdef CONFIG_B43_DEBUG
1197         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1198                 /* Check if we should inject another ringbuffer overflow
1199                  * to test handling of this situation in the stack. */
1200                 unsigned long next_overflow;
1201
1202                 next_overflow = ring->last_injected_overflow + HZ;
1203                 if (time_after(jiffies, next_overflow)) {
1204                         ring->last_injected_overflow = jiffies;
1205                         b43dbg(ring->dev->wl,
1206                                "Injecting TX ring overflow on "
1207                                "DMA controller %d\n", ring->index);
1208                         return 1;
1209                 }
1210         }
1211 #endif /* CONFIG_B43_DEBUG */
1212         return 0;
1213 }
1214
1215 int b43_dma_tx(struct b43_wldev *dev,
1216                struct sk_buff *skb, struct ieee80211_tx_control *ctl)
1217 {
1218         struct b43_dmaring *ring;
1219         int err = 0;
1220         unsigned long flags;
1221
1222         ring = priority_to_txring(dev, ctl->queue);
1223         spin_lock_irqsave(&ring->lock, flags);
1224         B43_WARN_ON(!ring->tx);
1225         if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1226                 b43warn(dev->wl, "DMA queue overflow\n");
1227                 err = -ENOSPC;
1228                 goto out_unlock;
1229         }
1230         /* Check if the queue was stopped in mac80211,
1231          * but we got called nevertheless.
1232          * That would be a mac80211 bug. */
1233         B43_WARN_ON(ring->stopped);
1234
1235         err = dma_tx_fragment(ring, skb, ctl);
1236         if (unlikely(err)) {
1237                 b43err(dev->wl, "DMA tx mapping failure\n");
1238                 goto out_unlock;
1239         }
1240         ring->nr_tx_packets++;
1241         if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1242             should_inject_overflow(ring)) {
1243                 /* This TX ring is full. */
1244                 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1245                 ring->stopped = 1;
1246                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1247                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1248                 }
1249         }
1250       out_unlock:
1251         spin_unlock_irqrestore(&ring->lock, flags);
1252
1253         return err;
1254 }
1255
1256 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1257                              const struct b43_txstatus *status)
1258 {
1259         const struct b43_dma_ops *ops;
1260         struct b43_dmaring *ring;
1261         struct b43_dmadesc_generic *desc;
1262         struct b43_dmadesc_meta *meta;
1263         int slot;
1264
1265         ring = parse_cookie(dev, status->cookie, &slot);
1266         if (unlikely(!ring))
1267                 return;
1268         B43_WARN_ON(!irqs_disabled());
1269         spin_lock(&ring->lock);
1270
1271         B43_WARN_ON(!ring->tx);
1272         ops = ring->ops;
1273         while (1) {
1274                 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1275                 desc = ops->idx2desc(ring, slot, &meta);
1276
1277                 if (meta->skb)
1278                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
1279                                          1);
1280                 else
1281                         unmap_descbuffer(ring, meta->dmaaddr,
1282                                          sizeof(struct b43_txhdr_fw4), 1);
1283
1284                 if (meta->is_last_fragment) {
1285                         B43_WARN_ON(!meta->skb);
1286                         /* Call back to inform the ieee80211 subsystem about the
1287                          * status of the transmission.
1288                          * Some fields of txstat are already filled in dma_tx().
1289                          */
1290                         if (status->acked) {
1291                                 meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
1292                         } else {
1293                                 if (!(meta->txstat.control.flags
1294                                       & IEEE80211_TXCTL_NO_ACK))
1295                                         meta->txstat.excessive_retries = 1;
1296                         }
1297                         if (status->frame_count == 0) {
1298                                 /* The frame was not transmitted at all. */
1299                                 meta->txstat.retry_count = 0;
1300                         } else
1301                                 meta->txstat.retry_count = status->frame_count - 1;
1302                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
1303                                                     &(meta->txstat));
1304                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1305                         meta->skb = NULL;
1306                 } else {
1307                         /* No need to call free_descriptor_buffer here, as
1308                          * this is only the txhdr, which is not allocated.
1309                          */
1310                         B43_WARN_ON(meta->skb);
1311                 }
1312
1313                 /* Everything unmapped and free'd. So it's not used anymore. */
1314                 ring->used_slots--;
1315
1316                 if (meta->is_last_fragment)
1317                         break;
1318                 slot = next_slot(ring, slot);
1319         }
1320         dev->stats.last_tx = jiffies;
1321         if (ring->stopped) {
1322                 B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1323                 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1324                 ring->stopped = 0;
1325                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1326                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1327                 }
1328         }
1329
1330         spin_unlock(&ring->lock);
1331 }
1332
1333 void b43_dma_get_tx_stats(struct b43_wldev *dev,
1334                           struct ieee80211_tx_queue_stats *stats)
1335 {
1336         const int nr_queues = dev->wl->hw->queues;
1337         struct b43_dmaring *ring;
1338         struct ieee80211_tx_queue_stats_data *data;
1339         unsigned long flags;
1340         int i;
1341
1342         for (i = 0; i < nr_queues; i++) {
1343                 data = &(stats->data[i]);
1344                 ring = priority_to_txring(dev, i);
1345
1346                 spin_lock_irqsave(&ring->lock, flags);
1347                 data->len = ring->used_slots / SLOTS_PER_PACKET;
1348                 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1349                 data->count = ring->nr_tx_packets;
1350                 spin_unlock_irqrestore(&ring->lock, flags);
1351         }
1352 }
1353
1354 static void dma_rx(struct b43_dmaring *ring, int *slot)
1355 {
1356         const struct b43_dma_ops *ops = ring->ops;
1357         struct b43_dmadesc_generic *desc;
1358         struct b43_dmadesc_meta *meta;
1359         struct b43_rxhdr_fw4 *rxhdr;
1360         struct sk_buff *skb;
1361         u16 len;
1362         int err;
1363         dma_addr_t dmaaddr;
1364
1365         desc = ops->idx2desc(ring, *slot, &meta);
1366
1367         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1368         skb = meta->skb;
1369
1370         if (ring->index == 3) {
1371                 /* We received an xmit status. */
1372                 struct b43_hwtxstatus *hw = (struct b43_hwtxstatus *)skb->data;
1373                 int i = 0;
1374
1375                 while (hw->cookie == 0) {
1376                         if (i > 100)
1377                                 break;
1378                         i++;
1379                         udelay(2);
1380                         barrier();
1381                 }
1382                 b43_handle_hwtxstatus(ring->dev, hw);
1383                 /* recycle the descriptor buffer. */
1384                 sync_descbuffer_for_device(ring, meta->dmaaddr,
1385                                            ring->rx_buffersize);
1386
1387                 return;
1388         }
1389         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1390         len = le16_to_cpu(rxhdr->frame_len);
1391         if (len == 0) {
1392                 int i = 0;
1393
1394                 do {
1395                         udelay(2);
1396                         barrier();
1397                         len = le16_to_cpu(rxhdr->frame_len);
1398                 } while (len == 0 && i++ < 5);
1399                 if (unlikely(len == 0)) {
1400                         /* recycle the descriptor buffer. */
1401                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1402                                                    ring->rx_buffersize);
1403                         goto drop;
1404                 }
1405         }
1406         if (unlikely(len > ring->rx_buffersize)) {
1407                 /* The data did not fit into one descriptor buffer
1408                  * and is split over multiple buffers.
1409                  * This should never happen, as we try to allocate buffers
1410                  * big enough. So simply ignore this packet.
1411                  */
1412                 int cnt = 0;
1413                 s32 tmp = len;
1414
1415                 while (1) {
1416                         desc = ops->idx2desc(ring, *slot, &meta);
1417                         /* recycle the descriptor buffer. */
1418                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1419                                                    ring->rx_buffersize);
1420                         *slot = next_slot(ring, *slot);
1421                         cnt++;
1422                         tmp -= ring->rx_buffersize;
1423                         if (tmp <= 0)
1424                                 break;
1425                 }
1426                 b43err(ring->dev->wl, "DMA RX buffer too small "
1427                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1428                        len, ring->rx_buffersize, cnt);
1429                 goto drop;
1430         }
1431
1432         dmaaddr = meta->dmaaddr;
1433         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1434         if (unlikely(err)) {
1435                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1436                 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1437                 goto drop;
1438         }
1439
1440         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1441         skb_put(skb, len + ring->frameoffset);
1442         skb_pull(skb, ring->frameoffset);
1443
1444         b43_rx(ring->dev, skb, rxhdr);
1445       drop:
1446         return;
1447 }
1448
1449 void b43_dma_rx(struct b43_dmaring *ring)
1450 {
1451         const struct b43_dma_ops *ops = ring->ops;
1452         int slot, current_slot;
1453         int used_slots = 0;
1454
1455         B43_WARN_ON(ring->tx);
1456         current_slot = ops->get_current_rxslot(ring);
1457         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1458
1459         slot = ring->current_slot;
1460         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1461                 dma_rx(ring, &slot);
1462                 update_max_used_slots(ring, ++used_slots);
1463         }
1464         ops->set_current_rxslot(ring, slot);
1465         ring->current_slot = slot;
1466 }
1467
1468 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1469 {
1470         unsigned long flags;
1471
1472         spin_lock_irqsave(&ring->lock, flags);
1473         B43_WARN_ON(!ring->tx);
1474         ring->ops->tx_suspend(ring);
1475         spin_unlock_irqrestore(&ring->lock, flags);
1476 }
1477
1478 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1479 {
1480         unsigned long flags;
1481
1482         spin_lock_irqsave(&ring->lock, flags);
1483         B43_WARN_ON(!ring->tx);
1484         ring->ops->tx_resume(ring);
1485         spin_unlock_irqrestore(&ring->lock, flags);
1486 }
1487
1488 void b43_dma_tx_suspend(struct b43_wldev *dev)
1489 {
1490         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1491         b43_dma_tx_suspend_ring(dev->dma.tx_ring0);
1492         b43_dma_tx_suspend_ring(dev->dma.tx_ring1);
1493         b43_dma_tx_suspend_ring(dev->dma.tx_ring2);
1494         b43_dma_tx_suspend_ring(dev->dma.tx_ring3);
1495         b43_dma_tx_suspend_ring(dev->dma.tx_ring4);
1496         b43_dma_tx_suspend_ring(dev->dma.tx_ring5);
1497 }
1498
1499 void b43_dma_tx_resume(struct b43_wldev *dev)
1500 {
1501         b43_dma_tx_resume_ring(dev->dma.tx_ring5);
1502         b43_dma_tx_resume_ring(dev->dma.tx_ring4);
1503         b43_dma_tx_resume_ring(dev->dma.tx_ring3);
1504         b43_dma_tx_resume_ring(dev->dma.tx_ring2);
1505         b43_dma_tx_resume_ring(dev->dma.tx_ring1);
1506         b43_dma_tx_resume_ring(dev->dma.tx_ring0);
1507         b43_power_saving_ctl_bits(dev, 0);
1508 }