3 Broadcom B43legacy wireless driver
5 DMA ringbuffer and descriptor allocation/management
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
30 #include "b43legacy.h"
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
44 struct b43legacy_dmadesc_generic *op32_idx2desc(
45 struct b43legacy_dmaring *ring,
47 struct b43legacy_dmadesc_meta **meta)
49 struct b43legacy_dmadesc32 *desc;
51 *meta = &(ring->meta[slot]);
52 desc = ring->descbase;
55 return (struct b43legacy_dmadesc_generic *)desc;
58 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
59 struct b43legacy_dmadesc_generic *desc,
60 dma_addr_t dmaaddr, u16 bufsize,
61 int start, int end, int irq)
63 struct b43legacy_dmadesc32 *descbase = ring->descbase;
69 slot = (int)(&(desc->dma32) - descbase);
70 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
72 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
74 >> SSB_DMA_TRANSLATION_SHIFT;
75 addr |= ssb_dma_translation(ring->dev->dev);
76 ctl = (bufsize - ring->frameoffset)
77 & B43legacy_DMA32_DCTL_BYTECNT;
78 if (slot == ring->nr_slots - 1)
79 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
81 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
83 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
85 ctl |= B43legacy_DMA32_DCTL_IRQ;
86 ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
87 & B43legacy_DMA32_DCTL_ADDREXT_MASK;
89 desc->dma32.control = cpu_to_le32(ctl);
90 desc->dma32.address = cpu_to_le32(addr);
93 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
95 b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
96 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
99 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
101 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
102 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
103 | B43legacy_DMA32_TXSUSPEND);
106 static void op32_tx_resume(struct b43legacy_dmaring *ring)
108 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
109 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
110 & ~B43legacy_DMA32_TXSUSPEND);
113 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
117 val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
118 val &= B43legacy_DMA32_RXDPTR;
120 return (val / sizeof(struct b43legacy_dmadesc32));
123 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
126 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
127 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
130 static const struct b43legacy_dma_ops dma32_ops = {
131 .idx2desc = op32_idx2desc,
132 .fill_descriptor = op32_fill_descriptor,
133 .poke_tx = op32_poke_tx,
134 .tx_suspend = op32_tx_suspend,
135 .tx_resume = op32_tx_resume,
136 .get_current_rxslot = op32_get_current_rxslot,
137 .set_current_rxslot = op32_set_current_rxslot,
142 struct b43legacy_dmadesc_generic *op64_idx2desc(
143 struct b43legacy_dmaring *ring,
145 struct b43legacy_dmadesc_meta
148 struct b43legacy_dmadesc64 *desc;
150 *meta = &(ring->meta[slot]);
151 desc = ring->descbase;
152 desc = &(desc[slot]);
154 return (struct b43legacy_dmadesc_generic *)desc;
157 static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
158 struct b43legacy_dmadesc_generic *desc,
159 dma_addr_t dmaaddr, u16 bufsize,
160 int start, int end, int irq)
162 struct b43legacy_dmadesc64 *descbase = ring->descbase;
170 slot = (int)(&(desc->dma64) - descbase);
171 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
173 addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
174 addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT;
177 addrhi |= ssb_dma_translation(ring->dev->dev);
178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
181 ctl0 |= B43legacy_DMA64_DCTL0_FRAMESTART;
183 ctl0 |= B43legacy_DMA64_DCTL0_FRAMEEND;
185 ctl0 |= B43legacy_DMA64_DCTL0_IRQ;
186 ctl1 |= (bufsize - ring->frameoffset)
187 & B43legacy_DMA64_DCTL1_BYTECNT;
188 ctl1 |= (addrext << B43legacy_DMA64_DCTL1_ADDREXT_SHIFT)
189 & B43legacy_DMA64_DCTL1_ADDREXT_MASK;
191 desc->dma64.control0 = cpu_to_le32(ctl0);
192 desc->dma64.control1 = cpu_to_le32(ctl1);
193 desc->dma64.address_low = cpu_to_le32(addrlo);
194 desc->dma64.address_high = cpu_to_le32(addrhi);
197 static void op64_poke_tx(struct b43legacy_dmaring *ring, int slot)
199 b43legacy_dma_write(ring, B43legacy_DMA64_TXINDEX,
200 (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
203 static void op64_tx_suspend(struct b43legacy_dmaring *ring)
205 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
206 b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
207 | B43legacy_DMA64_TXSUSPEND);
210 static void op64_tx_resume(struct b43legacy_dmaring *ring)
212 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
213 b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
214 & ~B43legacy_DMA64_TXSUSPEND);
217 static int op64_get_current_rxslot(struct b43legacy_dmaring *ring)
221 val = b43legacy_dma_read(ring, B43legacy_DMA64_RXSTATUS);
222 val &= B43legacy_DMA64_RXSTATDPTR;
224 return (val / sizeof(struct b43legacy_dmadesc64));
227 static void op64_set_current_rxslot(struct b43legacy_dmaring *ring,
230 b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
231 (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
234 static const struct b43legacy_dma_ops dma64_ops = {
235 .idx2desc = op64_idx2desc,
236 .fill_descriptor = op64_fill_descriptor,
237 .poke_tx = op64_poke_tx,
238 .tx_suspend = op64_tx_suspend,
239 .tx_resume = op64_tx_resume,
240 .get_current_rxslot = op64_get_current_rxslot,
241 .set_current_rxslot = op64_set_current_rxslot,
245 static inline int free_slots(struct b43legacy_dmaring *ring)
247 return (ring->nr_slots - ring->used_slots);
250 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
252 B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
253 if (slot == ring->nr_slots - 1)
258 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
260 B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
262 return ring->nr_slots - 1;
266 #ifdef CONFIG_B43LEGACY_DEBUG
267 static void update_max_used_slots(struct b43legacy_dmaring *ring,
268 int current_used_slots)
270 if (current_used_slots <= ring->max_used_slots)
272 ring->max_used_slots = current_used_slots;
273 if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
274 b43legacydbg(ring->dev->wl,
275 "max_used_slots increased to %d on %s ring %d\n",
276 ring->max_used_slots,
277 ring->tx ? "TX" : "RX",
282 void update_max_used_slots(struct b43legacy_dmaring *ring,
283 int current_used_slots)
287 /* Request a slot for usage. */
289 int request_slot(struct b43legacy_dmaring *ring)
293 B43legacy_WARN_ON(!ring->tx);
294 B43legacy_WARN_ON(ring->stopped);
295 B43legacy_WARN_ON(free_slots(ring) == 0);
297 slot = next_slot(ring, ring->current_slot);
298 ring->current_slot = slot;
301 update_max_used_slots(ring, ring->used_slots);
306 /* Mac80211-queue to b43legacy-ring mapping */
307 static struct b43legacy_dmaring *priority_to_txring(
308 struct b43legacy_wldev *dev,
311 struct b43legacy_dmaring *ring;
313 /*FIXME: For now we always run on TX-ring-1 */
314 return dev->dma.tx_ring1;
316 /* 0 = highest priority */
317 switch (queue_priority) {
319 B43legacy_WARN_ON(1);
322 ring = dev->dma.tx_ring3;
325 ring = dev->dma.tx_ring2;
328 ring = dev->dma.tx_ring1;
331 ring = dev->dma.tx_ring0;
334 ring = dev->dma.tx_ring4;
337 ring = dev->dma.tx_ring5;
344 /* Bcm4301-ring to mac80211-queue mapping */
345 static inline int txring_to_priority(struct b43legacy_dmaring *ring)
347 static const u8 idx_to_prio[] =
348 { 3, 2, 1, 0, 4, 5, };
350 /*FIXME: have only one queue, for now */
353 return idx_to_prio[ring->index];
357 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
360 static const u16 map64[] = {
361 B43legacy_MMIO_DMA64_BASE0,
362 B43legacy_MMIO_DMA64_BASE1,
363 B43legacy_MMIO_DMA64_BASE2,
364 B43legacy_MMIO_DMA64_BASE3,
365 B43legacy_MMIO_DMA64_BASE4,
366 B43legacy_MMIO_DMA64_BASE5,
368 static const u16 map32[] = {
369 B43legacy_MMIO_DMA32_BASE0,
370 B43legacy_MMIO_DMA32_BASE1,
371 B43legacy_MMIO_DMA32_BASE2,
372 B43legacy_MMIO_DMA32_BASE3,
373 B43legacy_MMIO_DMA32_BASE4,
374 B43legacy_MMIO_DMA32_BASE5,
377 if (type == B43legacy_DMA_64BIT) {
378 B43legacy_WARN_ON(!(controller_idx >= 0 &&
379 controller_idx < ARRAY_SIZE(map64)));
380 return map64[controller_idx];
382 B43legacy_WARN_ON(!(controller_idx >= 0 &&
383 controller_idx < ARRAY_SIZE(map32)));
384 return map32[controller_idx];
388 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
396 dmaaddr = ssb_dma_map_single(ring->dev->dev,
400 dmaaddr = ssb_dma_map_single(ring->dev->dev,
408 void unmap_descbuffer(struct b43legacy_dmaring *ring,
414 ssb_dma_unmap_single(ring->dev->dev,
418 ssb_dma_unmap_single(ring->dev->dev,
424 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
428 B43legacy_WARN_ON(ring->tx);
430 ssb_dma_sync_single_for_cpu(ring->dev->dev,
431 addr, len, DMA_FROM_DEVICE);
435 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
439 B43legacy_WARN_ON(ring->tx);
441 ssb_dma_sync_single_for_device(ring->dev->dev,
442 addr, len, DMA_FROM_DEVICE);
446 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
447 struct b43legacy_dmadesc_meta *meta,
452 dev_kfree_skb_irq(meta->skb);
454 dev_kfree_skb(meta->skb);
459 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
461 /* GFP flags must match the flags in free_ringmemory()! */
462 ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
463 B43legacy_DMA_RINGMEMSIZE,
466 if (!ring->descbase) {
467 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
471 memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
476 static void free_ringmemory(struct b43legacy_dmaring *ring)
478 ssb_dma_free_consistent(ring->dev->dev, B43legacy_DMA_RINGMEMSIZE,
479 ring->descbase, ring->dmabase, GFP_KERNEL);
482 /* Reset the RX DMA channel */
483 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
485 enum b43legacy_dmatype type)
493 offset = (type == B43legacy_DMA_64BIT) ?
494 B43legacy_DMA64_RXCTL : B43legacy_DMA32_RXCTL;
495 b43legacy_write32(dev, mmio_base + offset, 0);
496 for (i = 0; i < 10; i++) {
497 offset = (type == B43legacy_DMA_64BIT) ?
498 B43legacy_DMA64_RXSTATUS : B43legacy_DMA32_RXSTATUS;
499 value = b43legacy_read32(dev, mmio_base + offset);
500 if (type == B43legacy_DMA_64BIT) {
501 value &= B43legacy_DMA64_RXSTAT;
502 if (value == B43legacy_DMA64_RXSTAT_DISABLED) {
507 value &= B43legacy_DMA32_RXSTATE;
508 if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
516 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
523 /* Reset the RX DMA channel */
524 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
526 enum b43legacy_dmatype type)
534 for (i = 0; i < 10; i++) {
535 offset = (type == B43legacy_DMA_64BIT) ?
536 B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
537 value = b43legacy_read32(dev, mmio_base + offset);
538 if (type == B43legacy_DMA_64BIT) {
539 value &= B43legacy_DMA64_TXSTAT;
540 if (value == B43legacy_DMA64_TXSTAT_DISABLED ||
541 value == B43legacy_DMA64_TXSTAT_IDLEWAIT ||
542 value == B43legacy_DMA64_TXSTAT_STOPPED)
545 value &= B43legacy_DMA32_TXSTATE;
546 if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
547 value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
548 value == B43legacy_DMA32_TXSTAT_STOPPED)
553 offset = (type == B43legacy_DMA_64BIT) ? B43legacy_DMA64_TXCTL :
554 B43legacy_DMA32_TXCTL;
555 b43legacy_write32(dev, mmio_base + offset, 0);
556 for (i = 0; i < 10; i++) {
557 offset = (type == B43legacy_DMA_64BIT) ?
558 B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
559 value = b43legacy_read32(dev, mmio_base + offset);
560 if (type == B43legacy_DMA_64BIT) {
561 value &= B43legacy_DMA64_TXSTAT;
562 if (value == B43legacy_DMA64_TXSTAT_DISABLED) {
567 value &= B43legacy_DMA32_TXSTATE;
568 if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
576 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
579 /* ensure the reset is completed. */
585 /* Check if a DMA mapping address is invalid. */
586 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
591 if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
594 switch (ring->type) {
595 case B43legacy_DMA_30BIT:
596 if ((u64)addr + buffersize > (1ULL << 30))
599 case B43legacy_DMA_32BIT:
600 if ((u64)addr + buffersize > (1ULL << 32))
603 case B43legacy_DMA_64BIT:
604 /* Currently we can't have addresses beyond 64 bits in the kernel. */
608 /* The address is OK. */
612 /* We can't support this address. Unmap it again. */
613 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
618 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
619 struct b43legacy_dmadesc_generic *desc,
620 struct b43legacy_dmadesc_meta *meta,
623 struct b43legacy_rxhdr_fw3 *rxhdr;
624 struct b43legacy_hwtxstatus *txstat;
628 B43legacy_WARN_ON(ring->tx);
630 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
633 dmaaddr = map_descbuffer(ring, skb->data,
634 ring->rx_buffersize, 0);
635 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
636 /* ugh. try to realloc in zone_dma */
637 gfp_flags |= GFP_DMA;
639 dev_kfree_skb_any(skb);
641 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
644 dmaaddr = map_descbuffer(ring, skb->data,
645 ring->rx_buffersize, 0);
648 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
649 dev_kfree_skb_any(skb);
654 meta->dmaaddr = dmaaddr;
655 ring->ops->fill_descriptor(ring, desc, dmaaddr,
656 ring->rx_buffersize, 0, 0, 0);
658 rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
659 rxhdr->frame_len = 0;
660 txstat = (struct b43legacy_hwtxstatus *)(skb->data);
666 /* Allocate the initial descbuffers.
667 * This is used for an RX ring only.
669 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
673 struct b43legacy_dmadesc_generic *desc;
674 struct b43legacy_dmadesc_meta *meta;
676 for (i = 0; i < ring->nr_slots; i++) {
677 desc = ring->ops->idx2desc(ring, i, &meta);
679 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
681 b43legacyerr(ring->dev->wl,
682 "Failed to allocate initial descbuffers\n");
686 mb(); /* all descbuffer setup before next line */
687 ring->used_slots = ring->nr_slots;
693 for (i--; i >= 0; i--) {
694 desc = ring->ops->idx2desc(ring, i, &meta);
696 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
697 dev_kfree_skb(meta->skb);
702 /* Do initial setup of the DMA controller.
703 * Reset the controller, write the ring busaddress
704 * and switch the "enable" bit on.
706 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
711 u32 trans = ssb_dma_translation(ring->dev->dev);
714 if (ring->type == B43legacy_DMA_64BIT) {
715 u64 ringbase = (u64)(ring->dmabase);
717 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
718 >> SSB_DMA_TRANSLATION_SHIFT;
719 value = B43legacy_DMA64_TXENABLE;
720 value |= (addrext << B43legacy_DMA64_TXADDREXT_SHIFT)
721 & B43legacy_DMA64_TXADDREXT_MASK;
722 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
724 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO,
725 (ringbase & 0xFFFFFFFF));
726 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI,
728 & ~SSB_DMA_TRANSLATION_MASK)
731 u32 ringbase = (u32)(ring->dmabase);
733 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
734 >> SSB_DMA_TRANSLATION_SHIFT;
735 value = B43legacy_DMA32_TXENABLE;
736 value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
737 & B43legacy_DMA32_TXADDREXT_MASK;
738 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
740 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
742 ~SSB_DMA_TRANSLATION_MASK)
746 err = alloc_initial_descbuffers(ring);
749 if (ring->type == B43legacy_DMA_64BIT) {
750 u64 ringbase = (u64)(ring->dmabase);
752 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
753 >> SSB_DMA_TRANSLATION_SHIFT;
754 value = (ring->frameoffset <<
755 B43legacy_DMA64_RXFROFF_SHIFT);
756 value |= B43legacy_DMA64_RXENABLE;
757 value |= (addrext << B43legacy_DMA64_RXADDREXT_SHIFT)
758 & B43legacy_DMA64_RXADDREXT_MASK;
759 b43legacy_dma_write(ring, B43legacy_DMA64_RXCTL,
761 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO,
762 (ringbase & 0xFFFFFFFF));
763 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI,
765 ~SSB_DMA_TRANSLATION_MASK) |
767 b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
770 u32 ringbase = (u32)(ring->dmabase);
772 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
773 >> SSB_DMA_TRANSLATION_SHIFT;
774 value = (ring->frameoffset <<
775 B43legacy_DMA32_RXFROFF_SHIFT);
776 value |= B43legacy_DMA32_RXENABLE;
778 B43legacy_DMA32_RXADDREXT_SHIFT)
779 & B43legacy_DMA32_RXADDREXT_MASK;
780 b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL,
782 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
784 ~SSB_DMA_TRANSLATION_MASK)
786 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
795 /* Shutdown the DMA controller. */
796 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
799 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
801 if (ring->type == B43legacy_DMA_64BIT) {
802 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO, 0);
803 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI, 0);
805 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
807 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
809 if (ring->type == B43legacy_DMA_64BIT) {
810 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO, 0);
811 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI, 0);
813 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
817 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
819 struct b43legacy_dmadesc_generic *desc;
820 struct b43legacy_dmadesc_meta *meta;
823 if (!ring->used_slots)
825 for (i = 0; i < ring->nr_slots; i++) {
826 desc = ring->ops->idx2desc(ring, i, &meta);
829 B43legacy_WARN_ON(!ring->tx);
833 unmap_descbuffer(ring, meta->dmaaddr,
836 unmap_descbuffer(ring, meta->dmaaddr,
837 ring->rx_buffersize, 0);
838 free_descriptor_buffer(ring, meta, 0);
842 static u64 supported_dma_mask(struct b43legacy_wldev *dev)
847 tmp = b43legacy_read32(dev, SSB_TMSHIGH);
848 if (tmp & SSB_TMSHIGH_DMA64)
849 return DMA_64BIT_MASK;
850 mmio_base = b43legacy_dmacontroller_base(0, 0);
851 b43legacy_write32(dev,
852 mmio_base + B43legacy_DMA32_TXCTL,
853 B43legacy_DMA32_TXADDREXT_MASK);
854 tmp = b43legacy_read32(dev, mmio_base +
855 B43legacy_DMA32_TXCTL);
856 if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
857 return DMA_32BIT_MASK;
859 return DMA_30BIT_MASK;
862 /* Main initialization function. */
864 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
865 int controller_index,
867 enum b43legacy_dmatype type)
869 struct b43legacy_dmaring *ring;
874 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
880 nr_slots = B43legacy_RXRING_SLOTS;
882 nr_slots = B43legacy_TXRING_SLOTS;
884 ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
889 ring->txhdr_cache = kcalloc(nr_slots,
890 sizeof(struct b43legacy_txhdr_fw3),
892 if (!ring->txhdr_cache)
895 /* test for ability to dma to txhdr_cache */
896 dma_test = ssb_dma_map_single(dev->dev, ring->txhdr_cache,
897 sizeof(struct b43legacy_txhdr_fw3),
900 if (b43legacy_dma_mapping_error(ring, dma_test,
901 sizeof(struct b43legacy_txhdr_fw3), 1)) {
903 kfree(ring->txhdr_cache);
904 ring->txhdr_cache = kcalloc(nr_slots,
905 sizeof(struct b43legacy_txhdr_fw3),
906 GFP_KERNEL | GFP_DMA);
907 if (!ring->txhdr_cache)
910 dma_test = ssb_dma_map_single(dev->dev,
912 sizeof(struct b43legacy_txhdr_fw3),
915 if (b43legacy_dma_mapping_error(ring, dma_test,
916 sizeof(struct b43legacy_txhdr_fw3), 1))
917 goto err_kfree_txhdr_cache;
920 ssb_dma_unmap_single(dev->dev, dma_test,
921 sizeof(struct b43legacy_txhdr_fw3),
925 ring->nr_slots = nr_slots;
926 ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
927 ring->index = controller_index;
928 if (type == B43legacy_DMA_64BIT)
929 ring->ops = &dma64_ops;
931 ring->ops = &dma32_ops;
934 ring->current_slot = -1;
936 if (ring->index == 0) {
937 ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
938 ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
939 } else if (ring->index == 3) {
940 ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
941 ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
943 B43legacy_WARN_ON(1);
945 spin_lock_init(&ring->lock);
946 #ifdef CONFIG_B43LEGACY_DEBUG
947 ring->last_injected_overflow = jiffies;
950 err = alloc_ringmemory(ring);
952 goto err_kfree_txhdr_cache;
953 err = dmacontroller_setup(ring);
955 goto err_free_ringmemory;
961 free_ringmemory(ring);
962 err_kfree_txhdr_cache:
963 kfree(ring->txhdr_cache);
972 /* Main cleanup function. */
973 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
978 b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
979 " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
980 (ring->tx) ? "TX" : "RX", ring->max_used_slots,
982 /* Device IRQs are disabled prior entering this function,
983 * so no need to take care of concurrency with rx handler stuff.
985 dmacontroller_cleanup(ring);
986 free_all_descbuffers(ring);
987 free_ringmemory(ring);
989 kfree(ring->txhdr_cache);
994 void b43legacy_dma_free(struct b43legacy_wldev *dev)
996 struct b43legacy_dma *dma;
998 if (b43legacy_using_pio(dev))
1002 b43legacy_destroy_dmaring(dma->rx_ring3);
1003 dma->rx_ring3 = NULL;
1004 b43legacy_destroy_dmaring(dma->rx_ring0);
1005 dma->rx_ring0 = NULL;
1007 b43legacy_destroy_dmaring(dma->tx_ring5);
1008 dma->tx_ring5 = NULL;
1009 b43legacy_destroy_dmaring(dma->tx_ring4);
1010 dma->tx_ring4 = NULL;
1011 b43legacy_destroy_dmaring(dma->tx_ring3);
1012 dma->tx_ring3 = NULL;
1013 b43legacy_destroy_dmaring(dma->tx_ring2);
1014 dma->tx_ring2 = NULL;
1015 b43legacy_destroy_dmaring(dma->tx_ring1);
1016 dma->tx_ring1 = NULL;
1017 b43legacy_destroy_dmaring(dma->tx_ring0);
1018 dma->tx_ring0 = NULL;
1021 int b43legacy_dma_init(struct b43legacy_wldev *dev)
1023 struct b43legacy_dma *dma = &dev->dma;
1024 struct b43legacy_dmaring *ring;
1027 enum b43legacy_dmatype type;
1029 dmamask = supported_dma_mask(dev);
1032 B43legacy_WARN_ON(1);
1033 case DMA_30BIT_MASK:
1034 type = B43legacy_DMA_30BIT;
1036 case DMA_32BIT_MASK:
1037 type = B43legacy_DMA_32BIT;
1039 case DMA_64BIT_MASK:
1040 type = B43legacy_DMA_64BIT;
1044 err = ssb_dma_set_mask(dev->dev, dmamask);
1046 #ifdef CONFIG_B43LEGACY_PIO
1047 b43legacywarn(dev->wl, "DMA for this device not supported. "
1048 "Falling back to PIO\n");
1049 dev->__using_pio = 1;
1052 b43legacyerr(dev->wl, "DMA for this device not supported and "
1053 "no PIO support compiled in\n");
1059 /* setup TX DMA channels. */
1060 ring = b43legacy_setup_dmaring(dev, 0, 1, type);
1063 dma->tx_ring0 = ring;
1065 ring = b43legacy_setup_dmaring(dev, 1, 1, type);
1067 goto err_destroy_tx0;
1068 dma->tx_ring1 = ring;
1070 ring = b43legacy_setup_dmaring(dev, 2, 1, type);
1072 goto err_destroy_tx1;
1073 dma->tx_ring2 = ring;
1075 ring = b43legacy_setup_dmaring(dev, 3, 1, type);
1077 goto err_destroy_tx2;
1078 dma->tx_ring3 = ring;
1080 ring = b43legacy_setup_dmaring(dev, 4, 1, type);
1082 goto err_destroy_tx3;
1083 dma->tx_ring4 = ring;
1085 ring = b43legacy_setup_dmaring(dev, 5, 1, type);
1087 goto err_destroy_tx4;
1088 dma->tx_ring5 = ring;
1090 /* setup RX DMA channels. */
1091 ring = b43legacy_setup_dmaring(dev, 0, 0, type);
1093 goto err_destroy_tx5;
1094 dma->rx_ring0 = ring;
1096 if (dev->dev->id.revision < 5) {
1097 ring = b43legacy_setup_dmaring(dev, 3, 0, type);
1099 goto err_destroy_rx0;
1100 dma->rx_ring3 = ring;
1103 b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
1109 b43legacy_destroy_dmaring(dma->rx_ring0);
1110 dma->rx_ring0 = NULL;
1112 b43legacy_destroy_dmaring(dma->tx_ring5);
1113 dma->tx_ring5 = NULL;
1115 b43legacy_destroy_dmaring(dma->tx_ring4);
1116 dma->tx_ring4 = NULL;
1118 b43legacy_destroy_dmaring(dma->tx_ring3);
1119 dma->tx_ring3 = NULL;
1121 b43legacy_destroy_dmaring(dma->tx_ring2);
1122 dma->tx_ring2 = NULL;
1124 b43legacy_destroy_dmaring(dma->tx_ring1);
1125 dma->tx_ring1 = NULL;
1127 b43legacy_destroy_dmaring(dma->tx_ring0);
1128 dma->tx_ring0 = NULL;
1132 /* Generate a cookie for the TX header. */
1133 static u16 generate_cookie(struct b43legacy_dmaring *ring,
1136 u16 cookie = 0x1000;
1138 /* Use the upper 4 bits of the cookie as
1139 * DMA controller ID and store the slot number
1140 * in the lower 12 bits.
1141 * Note that the cookie must never be 0, as this
1142 * is a special value used in RX path.
1144 switch (ring->index) {
1164 B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
1165 cookie |= (u16)slot;
1170 /* Inspect a cookie and find out to which controller/slot it belongs. */
1172 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1173 u16 cookie, int *slot)
1175 struct b43legacy_dma *dma = &dev->dma;
1176 struct b43legacy_dmaring *ring = NULL;
1178 switch (cookie & 0xF000) {
1180 ring = dma->tx_ring0;
1183 ring = dma->tx_ring1;
1186 ring = dma->tx_ring2;
1189 ring = dma->tx_ring3;
1192 ring = dma->tx_ring4;
1195 ring = dma->tx_ring5;
1198 B43legacy_WARN_ON(1);
1200 *slot = (cookie & 0x0FFF);
1201 B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1206 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1207 struct sk_buff *skb)
1209 const struct b43legacy_dma_ops *ops = ring->ops;
1210 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1212 int slot, old_top_slot, old_used_slots;
1214 struct b43legacy_dmadesc_generic *desc;
1215 struct b43legacy_dmadesc_meta *meta;
1216 struct b43legacy_dmadesc_meta *meta_hdr;
1217 struct sk_buff *bounce_skb;
1219 #define SLOTS_PER_PACKET 2
1220 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1222 old_top_slot = ring->current_slot;
1223 old_used_slots = ring->used_slots;
1225 /* Get a slot for the header. */
1226 slot = request_slot(ring);
1227 desc = ops->idx2desc(ring, slot, &meta_hdr);
1228 memset(meta_hdr, 0, sizeof(*meta_hdr));
1230 header = &(ring->txhdr_cache[slot * sizeof(
1231 struct b43legacy_txhdr_fw3)]);
1232 err = b43legacy_generate_txhdr(ring->dev, header,
1233 skb->data, skb->len, info,
1234 generate_cookie(ring, slot));
1235 if (unlikely(err)) {
1236 ring->current_slot = old_top_slot;
1237 ring->used_slots = old_used_slots;
1241 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1242 sizeof(struct b43legacy_txhdr_fw3), 1);
1243 if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
1244 sizeof(struct b43legacy_txhdr_fw3), 1)) {
1245 ring->current_slot = old_top_slot;
1246 ring->used_slots = old_used_slots;
1249 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1250 sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1252 /* Get a slot for the payload. */
1253 slot = request_slot(ring);
1254 desc = ops->idx2desc(ring, slot, &meta);
1255 memset(meta, 0, sizeof(*meta));
1258 meta->is_last_fragment = 1;
1260 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1261 /* create a bounce buffer in zone_dma on mapping failure. */
1262 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1263 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1265 ring->current_slot = old_top_slot;
1266 ring->used_slots = old_used_slots;
1271 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1272 dev_kfree_skb_any(skb);
1275 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1276 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1277 ring->current_slot = old_top_slot;
1278 ring->used_slots = old_used_slots;
1280 goto out_free_bounce;
1284 ops->fill_descriptor(ring, desc, meta->dmaaddr,
1287 wmb(); /* previous stuff MUST be done */
1288 /* Now transfer the whole frame. */
1289 ops->poke_tx(ring, next_slot(ring, slot));
1293 dev_kfree_skb_any(skb);
1295 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1296 sizeof(struct b43legacy_txhdr_fw3), 1);
1301 int should_inject_overflow(struct b43legacy_dmaring *ring)
1303 #ifdef CONFIG_B43LEGACY_DEBUG
1304 if (unlikely(b43legacy_debug(ring->dev,
1305 B43legacy_DBG_DMAOVERFLOW))) {
1306 /* Check if we should inject another ringbuffer overflow
1307 * to test handling of this situation in the stack. */
1308 unsigned long next_overflow;
1310 next_overflow = ring->last_injected_overflow + HZ;
1311 if (time_after(jiffies, next_overflow)) {
1312 ring->last_injected_overflow = jiffies;
1313 b43legacydbg(ring->dev->wl,
1314 "Injecting TX ring overflow on "
1315 "DMA controller %d\n", ring->index);
1319 #endif /* CONFIG_B43LEGACY_DEBUG */
1323 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1324 struct sk_buff *skb)
1326 struct b43legacy_dmaring *ring;
1328 unsigned long flags;
1330 ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1331 spin_lock_irqsave(&ring->lock, flags);
1332 B43legacy_WARN_ON(!ring->tx);
1333 if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1334 b43legacywarn(dev->wl, "DMA queue overflow\n");
1338 /* Check if the queue was stopped in mac80211,
1339 * but we got called nevertheless.
1340 * That would be a mac80211 bug. */
1341 B43legacy_BUG_ON(ring->stopped);
1343 err = dma_tx_fragment(ring, skb);
1344 if (unlikely(err == -ENOKEY)) {
1345 /* Drop this packet, as we don't have the encryption key
1346 * anymore and must not transmit it unencrypted. */
1347 dev_kfree_skb_any(skb);
1351 if (unlikely(err)) {
1352 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1355 ring->nr_tx_packets++;
1356 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1357 should_inject_overflow(ring)) {
1358 /* This TX ring is full. */
1359 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1361 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1362 b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1366 spin_unlock_irqrestore(&ring->lock, flags);
1371 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1372 const struct b43legacy_txstatus *status)
1374 const struct b43legacy_dma_ops *ops;
1375 struct b43legacy_dmaring *ring;
1376 struct b43legacy_dmadesc_generic *desc;
1377 struct b43legacy_dmadesc_meta *meta;
1380 ring = parse_cookie(dev, status->cookie, &slot);
1381 if (unlikely(!ring))
1383 B43legacy_WARN_ON(!irqs_disabled());
1384 spin_lock(&ring->lock);
1386 B43legacy_WARN_ON(!ring->tx);
1389 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1390 desc = ops->idx2desc(ring, slot, &meta);
1393 unmap_descbuffer(ring, meta->dmaaddr,
1396 unmap_descbuffer(ring, meta->dmaaddr,
1397 sizeof(struct b43legacy_txhdr_fw3),
1400 if (meta->is_last_fragment) {
1401 struct ieee80211_tx_info *info;
1403 info = IEEE80211_SKB_CB(meta->skb);
1404 /* Call back to inform the ieee80211 subsystem about the
1405 * status of the transmission.
1406 * Some fields of txstat are already filled in dma_tx().
1409 memset(&info->status, 0, sizeof(info->status));
1411 if (status->acked) {
1412 info->flags |= IEEE80211_TX_STAT_ACK;
1414 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
1415 info->status.excessive_retries = 1;
1417 if (status->frame_count == 0) {
1418 /* The frame was not transmitted at all. */
1419 info->status.retry_count = 0;
1421 info->status.retry_count = status->frame_count
1423 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1424 /* skb is freed by ieee80211_tx_status_irqsafe() */
1427 /* No need to call free_descriptor_buffer here, as
1428 * this is only the txhdr, which is not allocated.
1430 B43legacy_WARN_ON(meta->skb != NULL);
1433 /* Everything unmapped and free'd. So it's not used anymore. */
1436 if (meta->is_last_fragment)
1438 slot = next_slot(ring, slot);
1440 dev->stats.last_tx = jiffies;
1441 if (ring->stopped) {
1442 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1443 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1445 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1446 b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1450 spin_unlock(&ring->lock);
1453 void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
1454 struct ieee80211_tx_queue_stats *stats)
1456 const int nr_queues = dev->wl->hw->queues;
1457 struct b43legacy_dmaring *ring;
1458 unsigned long flags;
1461 for (i = 0; i < nr_queues; i++) {
1462 ring = priority_to_txring(dev, i);
1464 spin_lock_irqsave(&ring->lock, flags);
1465 stats[i].len = ring->used_slots / SLOTS_PER_PACKET;
1466 stats[i].limit = ring->nr_slots / SLOTS_PER_PACKET;
1467 stats[i].count = ring->nr_tx_packets;
1468 spin_unlock_irqrestore(&ring->lock, flags);
1472 static void dma_rx(struct b43legacy_dmaring *ring,
1475 const struct b43legacy_dma_ops *ops = ring->ops;
1476 struct b43legacy_dmadesc_generic *desc;
1477 struct b43legacy_dmadesc_meta *meta;
1478 struct b43legacy_rxhdr_fw3 *rxhdr;
1479 struct sk_buff *skb;
1484 desc = ops->idx2desc(ring, *slot, &meta);
1486 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1489 if (ring->index == 3) {
1490 /* We received an xmit status. */
1491 struct b43legacy_hwtxstatus *hw =
1492 (struct b43legacy_hwtxstatus *)skb->data;
1495 while (hw->cookie == 0) {
1502 b43legacy_handle_hwtxstatus(ring->dev, hw);
1503 /* recycle the descriptor buffer. */
1504 sync_descbuffer_for_device(ring, meta->dmaaddr,
1505 ring->rx_buffersize);
1509 rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1510 len = le16_to_cpu(rxhdr->frame_len);
1517 len = le16_to_cpu(rxhdr->frame_len);
1518 } while (len == 0 && i++ < 5);
1519 if (unlikely(len == 0)) {
1520 /* recycle the descriptor buffer. */
1521 sync_descbuffer_for_device(ring, meta->dmaaddr,
1522 ring->rx_buffersize);
1526 if (unlikely(len > ring->rx_buffersize)) {
1527 /* The data did not fit into one descriptor buffer
1528 * and is split over multiple buffers.
1529 * This should never happen, as we try to allocate buffers
1530 * big enough. So simply ignore this packet.
1536 desc = ops->idx2desc(ring, *slot, &meta);
1537 /* recycle the descriptor buffer. */
1538 sync_descbuffer_for_device(ring, meta->dmaaddr,
1539 ring->rx_buffersize);
1540 *slot = next_slot(ring, *slot);
1542 tmp -= ring->rx_buffersize;
1546 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1547 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1548 len, ring->rx_buffersize, cnt);
1552 dmaaddr = meta->dmaaddr;
1553 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1554 if (unlikely(err)) {
1555 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1557 sync_descbuffer_for_device(ring, dmaaddr,
1558 ring->rx_buffersize);
1562 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1563 skb_put(skb, len + ring->frameoffset);
1564 skb_pull(skb, ring->frameoffset);
1566 b43legacy_rx(ring->dev, skb, rxhdr);
1571 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1573 const struct b43legacy_dma_ops *ops = ring->ops;
1578 B43legacy_WARN_ON(ring->tx);
1579 current_slot = ops->get_current_rxslot(ring);
1580 B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1583 slot = ring->current_slot;
1584 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1585 dma_rx(ring, &slot);
1586 update_max_used_slots(ring, ++used_slots);
1588 ops->set_current_rxslot(ring, slot);
1589 ring->current_slot = slot;
1592 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1594 unsigned long flags;
1596 spin_lock_irqsave(&ring->lock, flags);
1597 B43legacy_WARN_ON(!ring->tx);
1598 ring->ops->tx_suspend(ring);
1599 spin_unlock_irqrestore(&ring->lock, flags);
1602 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1604 unsigned long flags;
1606 spin_lock_irqsave(&ring->lock, flags);
1607 B43legacy_WARN_ON(!ring->tx);
1608 ring->ops->tx_resume(ring);
1609 spin_unlock_irqrestore(&ring->lock, flags);
1612 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1614 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1615 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1616 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1617 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1618 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1619 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1620 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1623 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1625 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1626 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1627 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1628 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1629 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1630 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1631 b43legacy_power_saving_ctl_bits(dev, -1, -1);