1 /******************************************************************************
3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
7 published by the Free Software Foundation.
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc., 59
16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 The full GNU General Public License is included in this distribution in the
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #define WEXT_USECHANNELS 1
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/config.h>
35 #include <linux/init.h>
37 #include <linux/version.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/skbuff.h>
42 #include <linux/etherdevice.h>
43 #include <linux/delay.h>
44 #include <linux/random.h>
45 #include <linux/dma-mapping.h>
47 #include <linux/firmware.h>
48 #include <linux/wireless.h>
49 #include <linux/dma-mapping.h>
52 #include <net/ieee80211.h>
54 #define DRV_NAME "ipw2200"
56 #include <linux/workqueue.h>
58 /* Authentication and Association States */
59 enum connection_manager_assoc_states {
76 #define IPW_WAIT (1<<0)
77 #define IPW_QUIET (1<<1)
78 #define IPW_ROAMING (1<<2)
80 #define IPW_POWER_MODE_CAM 0x00 //(always on)
81 #define IPW_POWER_INDEX_1 0x01
82 #define IPW_POWER_INDEX_2 0x02
83 #define IPW_POWER_INDEX_3 0x03
84 #define IPW_POWER_INDEX_4 0x04
85 #define IPW_POWER_INDEX_5 0x05
86 #define IPW_POWER_AC 0x06
87 #define IPW_POWER_BATTERY 0x07
88 #define IPW_POWER_LIMIT 0x07
89 #define IPW_POWER_MASK 0x0F
90 #define IPW_POWER_ENABLED 0x10
91 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
93 #define IPW_CMD_HOST_COMPLETE 2
94 #define IPW_CMD_POWER_DOWN 4
95 #define IPW_CMD_SYSTEM_CONFIG 6
96 #define IPW_CMD_MULTICAST_ADDRESS 7
97 #define IPW_CMD_SSID 8
98 #define IPW_CMD_ADAPTER_ADDRESS 11
99 #define IPW_CMD_PORT_TYPE 12
100 #define IPW_CMD_RTS_THRESHOLD 15
101 #define IPW_CMD_FRAG_THRESHOLD 16
102 #define IPW_CMD_POWER_MODE 17
103 #define IPW_CMD_WEP_KEY 18
104 #define IPW_CMD_TGI_TX_KEY 19
105 #define IPW_CMD_SCAN_REQUEST 20
106 #define IPW_CMD_ASSOCIATE 21
107 #define IPW_CMD_SUPPORTED_RATES 22
108 #define IPW_CMD_SCAN_ABORT 23
109 #define IPW_CMD_TX_FLUSH 24
110 #define IPW_CMD_QOS_PARAMETERS 25
111 #define IPW_CMD_SCAN_REQUEST_EXT 26
112 #define IPW_CMD_DINO_CONFIG 30
113 #define IPW_CMD_RSN_CAPABILITIES 31
114 #define IPW_CMD_RX_KEY 32
115 #define IPW_CMD_CARD_DISABLE 33
116 #define IPW_CMD_SEED_NUMBER 34
117 #define IPW_CMD_TX_POWER 35
118 #define IPW_CMD_COUNTRY_INFO 36
119 #define IPW_CMD_AIRONET_INFO 37
120 #define IPW_CMD_AP_TX_POWER 38
121 #define IPW_CMD_CCKM_INFO 39
122 #define IPW_CMD_CCX_VER_INFO 40
123 #define IPW_CMD_SET_CALIBRATION 41
124 #define IPW_CMD_SENSITIVITY_CALIB 42
125 #define IPW_CMD_RETRY_LIMIT 51
126 #define IPW_CMD_IPW_PRE_POWER_DOWN 58
127 #define IPW_CMD_VAP_BEACON_TEMPLATE 60
128 #define IPW_CMD_VAP_DTIM_PERIOD 61
129 #define IPW_CMD_EXT_SUPPORTED_RATES 62
130 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
131 #define IPW_CMD_VAP_QUIET_INTERVALS 64
132 #define IPW_CMD_VAP_CHANNEL_SWITCH 65
133 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66
134 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67
135 #define IPW_CMD_VAP_CF_PARAM_SET 68
136 #define IPW_CMD_VAP_SET_BEACONING_STATE 69
137 #define IPW_CMD_MEASUREMENT 80
138 #define IPW_CMD_POWER_CAPABILITY 81
139 #define IPW_CMD_SUPPORTED_CHANNELS 82
140 #define IPW_CMD_TPC_REPORT 83
141 #define IPW_CMD_WME_INFO 84
142 #define IPW_CMD_PRODUCTION_COMMAND 85
143 #define IPW_CMD_LINKSYS_EOU_INFO 90
146 #define NUM_TFD_CHUNKS 6
148 #define TX_QUEUE_SIZE 32
149 #define RX_QUEUE_SIZE 32
151 #define DINO_CMD_WEP_KEY 0x08
152 #define DINO_CMD_TX 0x0B
153 #define DCT_ANTENNA_A 0x01
154 #define DCT_ANTENNA_B 0x02
161 * TX Queue Flag Definitions
164 /* tx wep key definition */
165 #define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
166 #define DCT_WEP_KEY_64Bit 0x40
167 #define DCT_WEP_KEY_128Bit 0x80
168 #define DCT_WEP_KEY_128bitIV 0xC0
169 #define DCT_WEP_KEY_SIZE_MASK 0xC0
171 #define DCT_WEP_KEY_INDEX_MASK 0x0F
172 #define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
174 /* abort attempt if mgmt frame is rx'd */
175 #define DCT_FLAG_ABORT_MGMT 0x01
178 #define DCT_FLAG_CTS_REQUIRED 0x02
180 /* use short preamble */
181 #define DCT_FLAG_LONG_PREAMBLE 0x00
182 #define DCT_FLAG_SHORT_PREAMBLE 0x04
185 #define DCT_FLAG_RTS_REQD 0x08
187 /* dont calculate duration field */
188 #define DCT_FLAG_DUR_SET 0x10
190 /* even if MAC WEP set (allows pre-encrypt) */
191 #define DCT_FLAG_NO_WEP 0x20
193 /* overwrite TSF field */
194 #define DCT_FLAG_TSF_REQD 0x40
196 /* ACK rx is expected to follow */
197 #define DCT_FLAG_ACK_REQD 0x80
199 /* TX flags extension */
200 #define DCT_FLAG_EXT_MODE_CCK 0x01
201 #define DCT_FLAG_EXT_MODE_OFDM 0x00
203 #define DCT_FLAG_EXT_SECURITY_WEP 0x00
204 #define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP
205 #define DCT_FLAG_EXT_SECURITY_CKIP 0x04
206 #define DCT_FLAG_EXT_SECURITY_CCM 0x08
207 #define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
208 #define DCT_FLAG_EXT_SECURITY_MASK 0x0C
210 #define DCT_FLAG_EXT_QOS_ENABLED 0x10
212 #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
213 #define DCT_FLAG_EXT_HC_SIFS 0x20
214 #define DCT_FLAG_EXT_HC_PIFS 0x40
216 #define TX_RX_TYPE_MASK 0xFF
217 #define TX_FRAME_TYPE 0x00
218 #define TX_HOST_COMMAND_TYPE 0x01
219 #define RX_FRAME_TYPE 0x09
220 #define RX_HOST_NOTIFICATION_TYPE 0x03
221 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
222 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
223 #define TFD_NEED_IRQ_MASK 0x04
225 #define HOST_CMD_DINO_CONFIG 30
227 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
228 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
229 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
230 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
231 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
232 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
233 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
234 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
235 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
236 #define HOST_NOTIFICATION_TX_STATUS 19
237 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
238 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
239 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
240 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
241 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
242 #define HOST_NOTIFICATION_NOISE_STATS 25
243 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
244 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
246 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
247 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
248 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
249 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
251 #define MACADRR_BYTE_LEN 6
253 #define DCR_TYPE_AP 0x01
254 #define DCR_TYPE_WLAP 0x02
255 #define DCR_TYPE_MU_ESS 0x03
256 #define DCR_TYPE_MU_IBSS 0x04
257 #define DCR_TYPE_MU_PIBSS 0x05
258 #define DCR_TYPE_SNIFFER 0x06
259 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
261 /* QoS definitions */
263 #define CW_MIN_OFDM 15
264 #define CW_MAX_OFDM 1023
265 #define CW_MIN_CCK 31
266 #define CW_MAX_CCK 1023
268 #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
269 #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
270 #define QOS_TX2_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 )
271 #define QOS_TX3_CW_MIN_OFDM ( (CW_MIN_OFDM + 1) / 4 - 1 )
273 #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
274 #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
275 #define QOS_TX2_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 2 - 1 )
276 #define QOS_TX3_CW_MIN_CCK ( (CW_MIN_CCK + 1) / 4 - 1 )
278 #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
279 #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
280 #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
281 #define QOS_TX3_CW_MAX_OFDM ( (CW_MIN_OFDM + 1) / 2 - 1 )
283 #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
284 #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
285 #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
286 #define QOS_TX3_CW_MAX_CCK ( (CW_MIN_CCK + 1) / 2 - 1 )
288 #define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)
289 #define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)
290 #define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)
291 #define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)
293 #define QOS_TX0_ACM 0
294 #define QOS_TX1_ACM 0
295 #define QOS_TX2_ACM 0
296 #define QOS_TX3_ACM 0
298 #define QOS_TX0_TXOP_LIMIT_CCK 0
299 #define QOS_TX1_TXOP_LIMIT_CCK 0
300 #define QOS_TX2_TXOP_LIMIT_CCK 6016
301 #define QOS_TX3_TXOP_LIMIT_CCK 3264
303 #define QOS_TX0_TXOP_LIMIT_OFDM 0
304 #define QOS_TX1_TXOP_LIMIT_OFDM 0
305 #define QOS_TX2_TXOP_LIMIT_OFDM 3008
306 #define QOS_TX3_TXOP_LIMIT_OFDM 1504
308 #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
309 #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
310 #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
311 #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
313 #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
314 #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
315 #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
316 #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
318 #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
319 #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
320 #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
321 #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
323 #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
324 #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
325 #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
326 #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
328 #define DEF_TX0_AIFS 0
329 #define DEF_TX1_AIFS 0
330 #define DEF_TX2_AIFS 0
331 #define DEF_TX3_AIFS 0
333 #define DEF_TX0_ACM 0
334 #define DEF_TX1_ACM 0
335 #define DEF_TX2_ACM 0
336 #define DEF_TX3_ACM 0
338 #define DEF_TX0_TXOP_LIMIT_CCK 0
339 #define DEF_TX1_TXOP_LIMIT_CCK 0
340 #define DEF_TX2_TXOP_LIMIT_CCK 0
341 #define DEF_TX3_TXOP_LIMIT_CCK 0
343 #define DEF_TX0_TXOP_LIMIT_OFDM 0
344 #define DEF_TX1_TXOP_LIMIT_OFDM 0
345 #define DEF_TX2_TXOP_LIMIT_OFDM 0
346 #define DEF_TX3_TXOP_LIMIT_OFDM 0
348 #define QOS_QOS_SETS 3
349 #define QOS_PARAM_SET_ACTIVE 0
350 #define QOS_PARAM_SET_DEF_CCK 1
351 #define QOS_PARAM_SET_DEF_OFDM 2
353 #define CTRL_QOS_NO_ACK (0x0020)
355 #define IPW_TX_QUEUE_1 1
356 #define IPW_TX_QUEUE_2 2
357 #define IPW_TX_QUEUE_3 3
358 #define IPW_TX_QUEUE_4 4
361 struct ipw_qos_info {
363 struct ieee80211_qos_parameters *def_qos_parm_OFDM;
364 struct ieee80211_qos_parameters *def_qos_parm_CCK;
365 u32 burst_duration_CCK;
366 u32 burst_duration_OFDM;
371 /**************************************************************/
373 * Generic queue structure
375 * Contains common data for Rx and Tx queues
378 int n_bd; /**< number of BDs in this queue */
379 int first_empty; /**< 1-st empty entry (index) */
380 int last_used; /**< last used entry (index) */
381 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
382 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
383 dma_addr_t dma_addr; /**< physical addr for BD's */
384 int low_mark; /**< low watermark, resume queue if free space more than this */
385 int high_mark; /**< high watermark, stop queue if free space less than this */
386 } __attribute__ ((packed));
390 u16 duration; // watch out for endians!
391 u8 addr1[MACADRR_BYTE_LEN];
392 u8 addr2[MACADRR_BYTE_LEN];
393 u8 addr3[MACADRR_BYTE_LEN];
394 u16 seq_ctrl; // more endians!
395 u8 addr4[MACADRR_BYTE_LEN];
397 } __attribute__ ((packed));
401 u16 duration; // watch out for endians!
402 u8 addr1[MACADRR_BYTE_LEN];
403 u8 addr2[MACADRR_BYTE_LEN];
404 u8 addr3[MACADRR_BYTE_LEN];
405 u16 seq_ctrl; // more endians!
406 u8 addr4[MACADRR_BYTE_LEN];
407 } __attribute__ ((packed));
411 u16 duration; // watch out for endians!
412 u8 addr1[MACADRR_BYTE_LEN];
413 u8 addr2[MACADRR_BYTE_LEN];
414 u8 addr3[MACADRR_BYTE_LEN];
415 u16 seq_ctrl; // more endians!
417 } __attribute__ ((packed));
421 u16 duration; // watch out for endians!
422 u8 addr1[MACADRR_BYTE_LEN];
423 u8 addr2[MACADRR_BYTE_LEN];
424 u8 addr3[MACADRR_BYTE_LEN];
425 u16 seq_ctrl; // more endians!
426 } __attribute__ ((packed));
428 // TX TFD with 32 byte MAC Header
430 struct machdr32 mchdr; // 32
431 u32 uivplaceholder[2]; // 8
432 } __attribute__ ((packed));
434 // TX TFD with 30 byte MAC Header
436 struct machdr30 mchdr; // 30
438 u32 uivplaceholder[2]; // 8
439 } __attribute__ ((packed));
441 // tx tfd with 26 byte mac header
443 struct machdr26 mchdr; // 26
444 u8 reserved1[2]; // 2
445 u32 uivplaceholder[2]; // 8
446 u8 reserved2[4]; // 4
447 } __attribute__ ((packed));
449 // tx tfd with 24 byte mac header
451 struct machdr24 mchdr; // 24
452 u32 uivplaceholder[2]; // 8
454 } __attribute__ ((packed));
456 #define DCT_WEP_KEY_FIELD_LENGTH 16
463 } __attribute__ ((packed));
468 u8 station_number; /* 0 for BSS */
480 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
483 u16 next_packet_duration;
485 u16 back_off_counter; //////txop;
490 /* 802.11 MAC Header */
492 struct tx_tfd_24 tfd_24;
493 struct tx_tfd_26 tfd_26;
494 struct tx_tfd_30 tfd_30;
495 struct tx_tfd_32 tfd_32;
498 /* Payload DMA info */
500 u32 chunk_ptr[NUM_TFD_CHUNKS];
501 u16 chunk_len[NUM_TFD_CHUNKS];
502 } __attribute__ ((packed));
504 struct txrx_control_flags {
509 } __attribute__ ((packed));
512 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
515 struct txrx_control_flags control_flags;
517 struct tfd_data data;
518 struct tfd_command cmd;
519 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
521 } __attribute__ ((packed));
523 typedef void destructor_func(const void *);
526 * Tx Queue for DMA. Queue consists of circular buffer of
527 * BD's and required locking structures.
529 struct clx2_tx_queue {
531 struct tfd_frame *bd;
532 struct ieee80211_txb **txb;
536 * RX related structures and functions
538 #define RX_FREE_BUFFERS 32
539 #define RX_LOW_WATERMARK 8
541 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
542 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
543 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
545 // Used for passing to driver number of successes and failures per rate
546 struct rate_histogram {
548 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
549 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
550 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
553 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
554 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
555 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
557 } __attribute__ ((packed));
559 /* statistics command response */
560 struct ipw_cmd_stats {
568 u16 reserved_frame_types;
573 u16 long_distance_ina_fina;
574 u16 dsp_silence_unreachable;
575 u16 accumulated_rssi;
576 u16 rx_ovfl_frame_tossed;
577 u16 rssi_silence_threshold;
578 u16 rx_ovfl_frame_supplied;
579 u16 last_rx_frame_signal;
580 u16 last_rx_frame_noise;
581 u16 rx_autodetec_no_ofdm;
582 u16 rx_autodetec_no_barker;
584 } __attribute__ ((packed));
586 struct notif_channel_result {
588 struct ipw_cmd_stats stats;
590 } __attribute__ ((packed));
592 struct notif_scan_complete {
597 } __attribute__ ((packed));
599 struct notif_frag_length {
602 } __attribute__ ((packed));
604 struct notif_beacon_state {
607 } __attribute__ ((packed));
609 struct notif_tgi_tx_key {
614 } __attribute__ ((packed));
616 struct notif_link_deterioration {
617 struct ipw_cmd_stats stats;
620 struct rate_histogram histogram;
623 } __attribute__ ((packed));
625 struct notif_association {
627 } __attribute__ ((packed));
629 struct notif_authenticate {
631 struct machdr24 addr;
633 } __attribute__ ((packed));
635 struct notif_calibration {
637 } __attribute__ ((packed));
641 } __attribute__ ((packed));
643 struct ipw_rx_notification {
649 struct notif_association assoc;
650 struct notif_authenticate auth;
651 struct notif_channel_result channel_result;
652 struct notif_scan_complete scan_complete;
653 struct notif_frag_length frag_len;
654 struct notif_beacon_state beacon_state;
655 struct notif_tgi_tx_key tgi_tx_key;
656 struct notif_link_deterioration link_deterioration;
657 struct notif_calibration calibration;
658 struct notif_noise noise;
661 } __attribute__ ((packed));
663 struct ipw_rx_frame {
665 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
666 u8 received_channel; // The channel that this frame was received on.
667 // Note that for .11b this does not have to be
668 // the same as the channel that it was sent.
678 u8 control; // control bit should be on in bg
679 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
681 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
684 } __attribute__ ((packed));
686 struct ipw_rx_header {
691 } __attribute__ ((packed));
693 struct ipw_rx_packet {
694 struct ipw_rx_header header;
696 struct ipw_rx_frame frame;
697 struct ipw_rx_notification notification;
699 } __attribute__ ((packed));
701 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
702 #define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \
703 sizeof(struct ipw_rx_frame))
705 struct ipw_rx_mem_buffer {
707 struct ipw_rx_buffer *rxb;
709 struct list_head list;
710 }; /* Not transferred over network, so not __attribute__ ((packed)) */
712 struct ipw_rx_queue {
713 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
714 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
715 u32 processed; /* Internal index to last handled Rx packet */
716 u32 read; /* Shared index to newest available Rx buffer */
717 u32 write; /* Shared index to oldest written Rx packet */
718 u32 free_count; /* Number of pre-allocated buffers in rx_free */
719 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
720 struct list_head rx_free; /* Own an SKBs */
721 struct list_head rx_used; /* No SKB allocated */
723 }; /* Not transferred over network, so not __attribute__ ((packed)) */
725 struct alive_command_responce {
728 u16 software_revision;
729 u8 device_identifier;
733 u16 clock_settle_time;
734 u16 powerup_settle_time;
736 u8 time_stamp[5]; /* month, day, year, hours, minutes */
738 } __attribute__ ((packed));
740 #define IPW_MAX_RATES 12
744 u8 rates[IPW_MAX_RATES];
745 } __attribute__ ((packed));
747 struct command_block {
748 unsigned int control;
752 } __attribute__ ((packed));
754 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
755 struct fw_image_desc {
756 unsigned long last_cb_index;
757 unsigned long current_cb_index;
758 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
760 unsigned long p_addr;
764 struct ipw_sys_config {
767 u8 answer_broadcast_ssid_probe;
768 u8 accept_all_data_frames;
769 u8 accept_non_directed_frames;
770 u8 exclude_unicast_unencrypted;
771 u8 disable_unicast_decryption;
772 u8 exclude_multicast_unencrypted;
773 u8 disable_multicast_decryption;
774 u8 antenna_diversity;
776 u8 dot11g_auto_detection;
777 u8 enable_cts_to_self;
778 u8 enable_multicast_filtering;
779 u8 bt_coexist_collision_thr;
781 u8 accept_all_mgmt_bcpr;
782 u8 accept_all_mgtm_frames;
783 u8 pass_noise_stats_to_host;
785 } __attribute__ ((packed));
787 struct ipw_multicast_addr {
788 u8 num_of_multicast_addresses;
794 } __attribute__ ((packed));
796 #define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
797 #define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
799 #define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
800 #define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
801 #define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
803 #define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
804 #define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
805 #define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
806 #define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
807 //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
815 } __attribute__ ((packed));
817 struct ipw_tgi_tx_key {
824 } __attribute__ ((packed));
826 #define IPW_SCAN_CHANNELS 54
828 struct ipw_scan_request {
831 u8 channels_list[IPW_SCAN_CHANNELS];
832 u8 channels_reserved[3];
833 } __attribute__ ((packed));
836 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
837 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
838 IPW_SCAN_ACTIVE_DIRECT_SCAN,
839 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
840 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
844 struct ipw_scan_request_ext {
846 u8 channels_list[IPW_SCAN_CHANNELS];
847 u8 scan_type[IPW_SCAN_CHANNELS / 2];
849 u16 dwell_time[IPW_SCAN_TYPES];
850 } __attribute__ ((packed));
852 extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
855 return scan->scan_type[index / 2] & 0x0F;
857 return (scan->scan_type[index / 2] & 0xF0) >> 4;
860 extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
861 u8 index, u8 scan_type)
864 scan->scan_type[index / 2] =
865 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
867 scan->scan_type[index / 2] =
868 (scan->scan_type[index / 2] & 0x0F) |
869 ((scan_type & 0x0F) << 4);
872 struct ipw_associate {
874 u8 auth_type:4, auth_key:4;
891 } __attribute__ ((packed));
893 struct ipw_supported_rates {
898 u8 supported_rates[IPW_MAX_RATES];
899 } __attribute__ ((packed));
901 struct ipw_rts_threshold {
904 } __attribute__ ((packed));
906 struct ipw_frag_threshold {
909 } __attribute__ ((packed));
911 struct ipw_retry_limit {
912 u8 short_retry_limit;
915 } __attribute__ ((packed));
917 struct ipw_dino_config {
918 u32 dino_config_addr;
919 u16 dino_config_size;
922 } __attribute__ ((packed));
924 struct ipw_aironet_info {
928 } __attribute__ ((packed));
936 u8 station_address[6];
939 } __attribute__ ((packed));
941 struct ipw_country_channel_info {
945 } __attribute__ ((packed));
947 struct ipw_country_info {
951 struct ipw_country_channel_info groups[7];
952 } __attribute__ ((packed));
954 struct ipw_channel_tx_power {
957 } __attribute__ ((packed));
959 #define SCAN_ASSOCIATED_INTERVAL (HZ)
960 #define SCAN_INTERVAL (HZ / 10)
961 #define MAX_A_CHANNELS 37
962 #define MAX_B_CHANNELS 14
964 struct ipw_tx_power {
967 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
968 } __attribute__ ((packed));
970 struct ipw_rsn_capabilities {
974 } __attribute__ ((packed));
976 struct ipw_sensitivity_calib {
979 } __attribute__ ((packed));
982 * Host command structure.
984 * On input, the following fields should be filled:
988 * - param (if needed)
991 * - \a status contains status;
992 * - \a param filled with status parameters.
995 u32 cmd; /**< Host command */
996 u32 status;/**< Status */
998 /**< How many 32 bit parameters in the status */
999 u32 len; /**< incoming parameters length, bytes */
1001 * command parameters.
1002 * There should be enough space for incoming and
1003 * outcoming parameters.
1004 * Incoming parameters listed 1-st, followed by outcoming params.
1005 * nParams=(len+3)/4+status_len
1008 } __attribute__ ((packed));
1010 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
1012 #define STATUS_INT_ENABLED (1<<1)
1013 #define STATUS_RF_KILL_HW (1<<2)
1014 #define STATUS_RF_KILL_SW (1<<3)
1015 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
1017 #define STATUS_INIT (1<<5)
1018 #define STATUS_AUTH (1<<6)
1019 #define STATUS_ASSOCIATED (1<<7)
1020 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
1022 #define STATUS_ASSOCIATING (1<<8)
1023 #define STATUS_DISASSOCIATING (1<<9)
1024 #define STATUS_ROAMING (1<<10)
1025 #define STATUS_EXIT_PENDING (1<<11)
1026 #define STATUS_DISASSOC_PENDING (1<<12)
1027 #define STATUS_STATE_PENDING (1<<13)
1029 #define STATUS_SCAN_PENDING (1<<20)
1030 #define STATUS_SCANNING (1<<21)
1031 #define STATUS_SCAN_ABORTING (1<<22)
1032 #define STATUS_SCAN_FORCED (1<<23)
1034 #define STATUS_LED_LINK_ON (1<<24)
1035 #define STATUS_LED_ACT_ON (1<<25)
1037 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
1038 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
1039 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
1041 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
1043 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
1044 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
1045 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
1046 #define CFG_CUSTOM_MAC (1<<3)
1047 #define CFG_PREAMBLE_LONG (1<<4)
1048 #define CFG_ADHOC_PERSIST (1<<5)
1049 #define CFG_ASSOCIATE (1<<6)
1050 #define CFG_FIXED_RATE (1<<7)
1051 #define CFG_ADHOC_CREATE (1<<8)
1052 #define CFG_NO_LED (1<<9)
1053 #define CFG_BACKGROUND_SCAN (1<<10)
1054 #define CFG_SPEED_SCAN (1<<11)
1055 #define CFG_NET_STATS (1<<12)
1057 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
1058 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
1060 #define MAX_STATIONS 32
1061 #define IPW_INVALID_STATION (0xff)
1063 struct ipw_station_entry {
1064 u8 mac_addr[ETH_ALEN];
1069 #define AVG_ENTRIES 8
1071 s16 entries[AVG_ENTRIES];
1077 #define MAX_SPEED_SCAN 100
1078 #define IPW_IBSS_MAC_HASH_SIZE 31
1080 struct ipw_ibss_seq {
1084 unsigned long packet_time;
1085 struct list_head list;
1088 struct ipw_error_elem {
1102 } __attribute__ ((packed));
1104 struct ipw_fw_error {
1109 struct ipw_error_elem *elem;
1110 struct ipw_event *log;
1112 } __attribute__ ((packed));
1115 /* ieee device used by generic ieee processing code */
1116 struct ieee80211_device *ieee;
1119 struct semaphore sem;
1121 /* basic pci-network driver stuff */
1122 struct pci_dev *pci_dev;
1123 struct net_device *net_dev;
1125 /* pci hardware address support */
1126 void __iomem *hw_base;
1127 unsigned long hw_len;
1129 struct fw_image_desc sram_desc;
1131 /* result of ucode download */
1132 struct alive_command_responce dino_alive;
1134 wait_queue_head_t wait_command_queue;
1135 wait_queue_head_t wait_state;
1137 /* Rx and Tx DMA processing queues */
1138 struct ipw_rx_queue *rxq;
1139 struct clx2_tx_queue txq_cmd;
1140 struct clx2_tx_queue txq[4];
1147 struct average average_missed_beacons;
1148 struct average average_rssi;
1149 struct average average_noise;
1151 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1152 int rx_pend_max; /**< maximum pending buffers for one IRQ */
1153 u32 hcmd_seq; /**< sequence number for hcmd */
1154 u32 disassociate_threshold;
1155 u32 roaming_threshold;
1157 struct ipw_associate assoc_request;
1158 struct ieee80211_network *assoc_network;
1160 unsigned long ts_scan_abort;
1161 struct ipw_supported_rates rates;
1162 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1163 struct ipw_rates supp; /**< software defined */
1164 struct ipw_rates extended; /**< use for corresp. IE, AP only */
1166 struct notif_link_deterioration last_link_deterioration; /** for statistics */
1167 struct ipw_cmd *hcmd; /**< host command currently executed */
1169 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1170 u32 tsf_bcn[2]; /**< TSF from latest beacon */
1172 struct notif_calibration calib; /**< last calibration */
1174 /* ordinal interface with firmware */
1182 /* context information */
1183 u8 essid[IW_ESSID_MAX_SIZE];
1185 u8 nick[IW_ESSID_MAX_SIZE];
1188 struct ipw_sys_config sys_config;
1192 u8 mac_addr[ETH_ALEN];
1194 u8 stations[MAX_STATIONS][ETH_ALEN];
1195 u8 short_retry_limit;
1196 u8 long_retry_limit;
1198 u32 notif_missed_beacons;
1200 /* Statistics and counters normalized with each association */
1201 u32 last_missed_beacons;
1202 u32 last_tx_packets;
1203 u32 last_rx_packets;
1204 u32 last_tx_failures;
1208 u32 missed_adhoc_beacons;
1214 u8 speed_scan[MAX_SPEED_SCAN];
1219 unsigned long last_packet_time;
1220 struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];
1223 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1227 struct iw_statistics wstats;
1229 struct workqueue_struct *workqueue;
1231 struct work_struct adhoc_check;
1232 struct work_struct associate;
1233 struct work_struct disassociate;
1234 struct work_struct system_config;
1235 struct work_struct rx_replenish;
1236 struct work_struct request_scan;
1237 struct work_struct adapter_restart;
1238 struct work_struct rf_kill;
1239 struct work_struct up;
1240 struct work_struct down;
1241 struct work_struct gather_stats;
1242 struct work_struct abort_scan;
1243 struct work_struct roam;
1244 struct work_struct scan_check;
1245 struct work_struct link_up;
1246 struct work_struct link_down;
1248 struct tasklet_struct irq_tasklet;
1250 /* LED related variables and work_struct */
1252 u32 led_activity_on;
1253 u32 led_activity_off;
1254 u32 led_association_on;
1255 u32 led_association_off;
1259 struct work_struct led_link_on;
1260 struct work_struct led_link_off;
1261 struct work_struct led_act_off;
1262 struct work_struct merge_networks;
1264 #define IPW_2200BG 1
1265 #define IPW_2915ABG 2
1274 struct ipw_fw_error *error;
1278 /* Used to pass the current INTA value from ISR to Tasklet */
1282 struct ipw_qos_info qos_data;
1283 struct work_struct qos_activate;
1284 /*********************************/
1286 /* debugging info */
1294 #ifdef CONFIG_IPW_DEBUG
1295 #define IPW_DEBUG(level, fmt, args...) \
1296 do { if (ipw_debug_level & (level)) \
1297 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1298 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1300 #define IPW_DEBUG(level, fmt, args...) do {} while (0)
1301 #endif /* CONFIG_IPW_DEBUG */
1304 * To use the debug system;
1306 * If you are defining a new debug classification, simply add it to the #define
1307 * list here in the form of:
1309 * #define IPW_DL_xxxx VALUE
1311 * shifting value to the left one bit from the previous entry. xxxx should be
1312 * the name of the classification (for example, WEP)
1314 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1315 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1316 * to send output to that classification.
1318 * To add your debug level to the list of levels seen when you perform
1320 * % cat /proc/net/ipw/debug_level
1322 * you simply need to add your entry to the ipw_debug_levels array.
1324 * If you do not see debug_level in /proc/net/ipw then you do not have
1325 * CONFIG_IPW_DEBUG defined in your kernel configuration
1329 #define IPW_DL_ERROR (1<<0)
1330 #define IPW_DL_WARNING (1<<1)
1331 #define IPW_DL_INFO (1<<2)
1332 #define IPW_DL_WX (1<<3)
1333 #define IPW_DL_HOST_COMMAND (1<<5)
1334 #define IPW_DL_STATE (1<<6)
1336 #define IPW_DL_NOTIF (1<<10)
1337 #define IPW_DL_SCAN (1<<11)
1338 #define IPW_DL_ASSOC (1<<12)
1339 #define IPW_DL_DROP (1<<13)
1340 #define IPW_DL_IOCTL (1<<14)
1342 #define IPW_DL_MANAGE (1<<15)
1343 #define IPW_DL_FW (1<<16)
1344 #define IPW_DL_RF_KILL (1<<17)
1345 #define IPW_DL_FW_ERRORS (1<<18)
1347 #define IPW_DL_LED (1<<19)
1349 #define IPW_DL_ORD (1<<20)
1351 #define IPW_DL_FRAG (1<<21)
1352 #define IPW_DL_WEP (1<<22)
1353 #define IPW_DL_TX (1<<23)
1354 #define IPW_DL_RX (1<<24)
1355 #define IPW_DL_ISR (1<<25)
1356 #define IPW_DL_FW_INFO (1<<26)
1357 #define IPW_DL_IO (1<<27)
1358 #define IPW_DL_TRACE (1<<28)
1360 #define IPW_DL_STATS (1<<29)
1361 #define IPW_DL_MERGE (1<<30)
1362 #define IPW_DL_QOS (1<<31)
1364 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1365 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1366 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1368 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1369 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1370 #define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1371 #define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1372 #define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1373 #define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1374 #define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1375 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1376 #define IPW_DEBUG_LED(f, a...) IPW_DEBUG(IPW_DL_LED, f, ## a)
1377 #define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1378 #define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1379 #define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1380 #define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1381 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1382 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1383 #define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1384 #define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1385 #define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1386 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1387 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1388 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1389 #define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1390 #define IPW_DEBUG_MERGE(f, a...) IPW_DEBUG(IPW_DL_MERGE, f, ## a)
1391 #define IPW_DEBUG_QOS(f, a...) IPW_DEBUG(IPW_DL_QOS, f, ## a)
1393 #include <linux/ctype.h>
1396 * Register bit definitions
1399 /* Dino control registers bits */
1401 #define DINO_ENABLE_SYSTEM 0x80
1402 #define DINO_ENABLE_CS 0x40
1403 #define DINO_RXFIFO_DATA 0x01
1404 #define DINO_CONTROL_REG 0x00200000
1406 #define IPW_INTA_RW 0x00000008
1407 #define IPW_INTA_MASK_R 0x0000000C
1408 #define IPW_INDIRECT_ADDR 0x00000010
1409 #define IPW_INDIRECT_DATA 0x00000014
1410 #define IPW_AUTOINC_ADDR 0x00000018
1411 #define IPW_AUTOINC_DATA 0x0000001C
1412 #define IPW_RESET_REG 0x00000020
1413 #define IPW_GP_CNTRL_RW 0x00000024
1415 #define IPW_READ_INT_REGISTER 0xFF4
1417 #define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
1419 #define IPW_REGISTER_DOMAIN1_END 0x00001000
1420 #define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
1422 #define IPW_SHARED_LOWER_BOUND 0x00000200
1423 #define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1425 #define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
1426 #define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
1428 #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1429 #define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1430 #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1433 * RESET Register Bit Indexes
1435 #define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1436 #define IPW_START_STANDBY (1<<2)
1437 #define IPW_ACTIVITY_LED (1<<4)
1438 #define IPW_ASSOCIATED_LED (1<<5)
1439 #define IPW_OFDM_LED (1<<6)
1440 #define IPW_RESET_REG_SW_RESET (1<<7)
1441 #define IPW_RESET_REG_MASTER_DISABLED (1<<8)
1442 #define IPW_RESET_REG_STOP_MASTER (1<<9)
1443 #define IPW_GATE_ODMA (1<<25)
1444 #define IPW_GATE_IDMA (1<<26)
1445 #define IPW_ARC_KESHET_CONFIG (1<<27)
1446 #define IPW_GATE_ADMA (1<<29)
1448 #define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1449 #define IPW_DOMAIN_0_END 0x1000
1450 #define CLX_MEM_BAR_SIZE 0x1000
1452 #define IPW_BASEBAND_CONTROL_STATUS 0X00200000
1453 #define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
1454 #define IPW_BASEBAND_RX_FIFO_READ 0X00200004
1455 #define IPW_BASEBAND_CONTROL_STORE 0X00200010
1457 #define IPW_INTERNAL_CMD_EVENT 0X00300004
1458 #define IPW_BASEBAND_POWER_DOWN 0x00000001
1460 #define IPW_MEM_HALT_AND_RESET 0x003000e0
1462 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1463 #define IPW_BIT_HALT_RESET_ON 0x80000000
1464 #define IPW_BIT_HALT_RESET_OFF 0x00000000
1466 #define CB_LAST_VALID 0x20000000
1467 #define CB_INT_ENABLED 0x40000000
1468 #define CB_VALID 0x80000000
1469 #define CB_SRC_LE 0x08000000
1470 #define CB_DEST_LE 0x04000000
1471 #define CB_SRC_AUTOINC 0x00800000
1472 #define CB_SRC_IO_GATED 0x00400000
1473 #define CB_DEST_AUTOINC 0x00080000
1474 #define CB_SRC_SIZE_LONG 0x00200000
1475 #define CB_DEST_SIZE_LONG 0x00020000
1479 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1480 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1481 #define DMA_CB_START 0x00000100
1483 #define IPW_SHARED_SRAM_SIZE 0x00030000
1484 #define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
1485 #define CB_MAX_LENGTH 0x1FFF
1487 #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1488 #define IPW_EEPROM_IMAGE_SIZE 0x100
1491 #define IPW_DMA_I_CURRENT_CB 0x003000D0
1492 #define IPW_DMA_O_CURRENT_CB 0x003000D4
1493 #define IPW_DMA_I_DMA_CONTROL 0x003000A4
1494 #define IPW_DMA_I_CB_BASE 0x003000A0
1496 #define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
1497 #define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
1498 #define IPW_TX_QUEUE_0_BD_BASE 0x00000208
1499 #define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
1500 #define IPW_TX_QUEUE_1_BD_BASE 0x00000210
1501 #define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
1502 #define IPW_TX_QUEUE_2_BD_BASE 0x00000218
1503 #define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
1504 #define IPW_TX_QUEUE_3_BD_BASE 0x00000220
1505 #define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
1506 #define IPW_RX_BD_BASE 0x00000240
1507 #define IPW_RX_BD_SIZE 0x00000244
1508 #define IPW_RFDS_TABLE_LOWER 0x00000500
1510 #define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
1511 #define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
1512 #define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
1513 #define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
1514 #define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
1515 #define IPW_RX_READ_INDEX (0x000002A0)
1517 #define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1518 #define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1519 #define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1520 #define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1521 #define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1522 #define IPW_RX_WRITE_INDEX (0x00000FA0)
1525 * EEPROM Related Definitions
1528 #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1529 #define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
1530 #define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
1531 #define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
1532 #define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
1534 #define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
1535 #define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
1536 #define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
1537 #define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
1538 #define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
1539 #define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
1543 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1545 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1546 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1548 /* EEPROM access by BYTE */
1549 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1550 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1551 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1552 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1553 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1554 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1555 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1556 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1557 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1558 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1560 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
1561 #define EEPROM_NIC_TYPE_0 0
1562 #define EEPROM_NIC_TYPE_1 1
1563 #define EEPROM_NIC_TYPE_2 2
1564 #define EEPROM_NIC_TYPE_3 3
1565 #define EEPROM_NIC_TYPE_4 4
1567 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1568 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1569 #define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
1570 #define EEPROM_BIT_SK (1<<0)
1571 #define EEPROM_BIT_CS (1<<1)
1572 #define EEPROM_BIT_DI (1<<2)
1573 #define EEPROM_BIT_DO (1<<4)
1575 #define EEPROM_CMD_READ 0x2
1577 /* Interrupts masks */
1578 #define IPW_INTA_NONE 0x00000000
1580 #define IPW_INTA_BIT_RX_TRANSFER 0x00000002
1581 #define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
1582 #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1585 #define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
1586 #define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
1587 #define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
1588 #define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
1589 #define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
1591 #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1593 #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1594 #define IPW_INTA_BIT_POWER_DOWN 0x00200000
1596 #define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1597 #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1598 #define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
1599 #define IPW_INTA_BIT_FATAL_ERROR 0x40000000
1600 #define IPW_INTA_BIT_PARITY_ERROR 0x80000000
1602 /* Interrupts enabled at init time. */
1603 #define IPW_INTA_MASK_ALL \
1604 (IPW_INTA_BIT_TX_QUEUE_1 | \
1605 IPW_INTA_BIT_TX_QUEUE_2 | \
1606 IPW_INTA_BIT_TX_QUEUE_3 | \
1607 IPW_INTA_BIT_TX_QUEUE_4 | \
1608 IPW_INTA_BIT_TX_CMD_QUEUE | \
1609 IPW_INTA_BIT_RX_TRANSFER | \
1610 IPW_INTA_BIT_FATAL_ERROR | \
1611 IPW_INTA_BIT_PARITY_ERROR | \
1612 IPW_INTA_BIT_STATUS_CHANGE | \
1613 IPW_INTA_BIT_FW_INITIALIZATION_DONE | \
1614 IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1615 IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1616 IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1617 IPW_INTA_BIT_POWER_DOWN | \
1618 IPW_INTA_BIT_RF_KILL_DONE )
1620 /* FW event log definitions */
1621 #define EVENT_ELEM_SIZE (3 * sizeof(u32))
1622 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1624 /* FW error log definitions */
1625 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1626 #define ERROR_START_OFFSET (1 * sizeof(u32))
1628 /* TX power level (dbm) */
1629 #define IPW_TX_POWER_MIN -12
1630 #define IPW_TX_POWER_MAX 20
1631 #define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX
1634 IPW_FW_ERROR_OK = 0,
1636 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1637 IPW_FW_ERROR_MEMORY_OVERFLOW,
1638 IPW_FW_ERROR_BAD_PARAM,
1639 IPW_FW_ERROR_BAD_CHECKSUM,
1640 IPW_FW_ERROR_NMI_INTERRUPT,
1641 IPW_FW_ERROR_BAD_DATABASE,
1642 IPW_FW_ERROR_ALLOC_FAIL,
1643 IPW_FW_ERROR_DMA_UNDERRUN,
1644 IPW_FW_ERROR_DMA_STATUS,
1645 IPW_FW_ERROR_DINO_ERROR,
1646 IPW_FW_ERROR_EEPROM_ERROR,
1647 IPW_FW_ERROR_SYSASSERT,
1648 IPW_FW_ERROR_FATAL_ERROR
1652 #define AUTH_SHARED_KEY 1
1653 #define AUTH_IGNORE 3
1655 #define HC_ASSOCIATE 0
1656 #define HC_REASSOCIATE 1
1657 #define HC_DISASSOCIATE 2
1658 #define HC_IBSS_START 3
1659 #define HC_IBSS_RECONF 4
1660 #define HC_DISASSOC_QUIET 5
1662 #define HC_QOS_SUPPORT_ASSOC 0x01
1664 #define IPW_RATE_CAPABILITIES 1
1665 #define IPW_RATE_CONNECT 0
1668 * Rate values and masks
1670 #define IPW_TX_RATE_1MB 0x0A
1671 #define IPW_TX_RATE_2MB 0x14
1672 #define IPW_TX_RATE_5MB 0x37
1673 #define IPW_TX_RATE_6MB 0x0D
1674 #define IPW_TX_RATE_9MB 0x0F
1675 #define IPW_TX_RATE_11MB 0x6E
1676 #define IPW_TX_RATE_12MB 0x05
1677 #define IPW_TX_RATE_18MB 0x07
1678 #define IPW_TX_RATE_24MB 0x09
1679 #define IPW_TX_RATE_36MB 0x0B
1680 #define IPW_TX_RATE_48MB 0x01
1681 #define IPW_TX_RATE_54MB 0x03
1683 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1684 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1686 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1687 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1688 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1689 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1690 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1691 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1692 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1693 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1696 * Table 0 Entries (all entries are 32 bits)
1699 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1700 IPW_ORD_STAT_FRAG_TRESHOLD,
1701 IPW_ORD_STAT_RTS_THRESHOLD,
1702 IPW_ORD_STAT_TX_HOST_REQUESTS,
1703 IPW_ORD_STAT_TX_HOST_COMPLETE,
1704 IPW_ORD_STAT_TX_DIR_DATA,
1705 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1706 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1707 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1708 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1711 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1712 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1713 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1714 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1715 IPW_ORD_STAT_TX_DIR_DATA_G_9,
1716 IPW_ORD_STAT_TX_DIR_DATA_G_11,
1717 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1718 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1719 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1720 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1721 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1722 IPW_ORD_STAT_TX_DIR_DATA_G_54,
1723 IPW_ORD_STAT_TX_NON_DIR_DATA,
1724 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1725 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1726 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1727 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1730 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1731 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1732 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1733 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1734 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1735 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1736 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1737 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1738 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1739 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1740 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1741 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1742 IPW_ORD_STAT_TX_RETRY,
1743 IPW_ORD_STAT_TX_FAILURE,
1744 IPW_ORD_STAT_RX_ERR_CRC,
1745 IPW_ORD_STAT_RX_ERR_ICV,
1746 IPW_ORD_STAT_RX_NO_BUFFER,
1747 IPW_ORD_STAT_FULL_SCANS,
1748 IPW_ORD_STAT_PARTIAL_SCANS,
1749 IPW_ORD_STAT_TGH_ABORTED_SCANS,
1750 IPW_ORD_STAT_TX_TOTAL_BYTES,
1751 IPW_ORD_STAT_CURR_RSSI_RAW,
1752 IPW_ORD_STAT_RX_BEACON,
1753 IPW_ORD_STAT_MISSED_BEACONS,
1754 IPW_ORD_TABLE_0_LAST
1757 #define IPW_RSSI_TO_DBM 112
1762 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1768 * FW_VERSION: 16 byte string
1769 * FW_DATE: 16 byte string (only 14 bytes used)
1770 * UCODE_VERSION: 4 byte version code
1771 * UCODE_DATE: 5 bytes code code
1772 * ADDAPTER_MAC: 6 byte MAC address
1776 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1777 IPW_ORD_STAT_FW_DATE,
1778 IPW_ORD_STAT_UCODE_VERSION,
1779 IPW_ORD_STAT_UCODE_DATE,
1780 IPW_ORD_STAT_ADAPTER_MAC,
1782 IPW_ORD_TABLE_2_LAST
1787 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1788 IPW_ORD_STAT_TX_PACKET_FAILURE,
1789 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1790 IPW_ORD_STAT_TX_PACKET_ABORTED,
1791 IPW_ORD_TABLE_3_LAST
1796 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1801 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1802 IPW_ORD_STAT_AP_ASSNS,
1804 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1805 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1806 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1807 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1808 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1809 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1810 IPW_ORD_STAT_LINK_UP,
1811 IPW_ORD_STAT_LINK_DOWN,
1812 IPW_ORD_ANTENNA_DIVERSITY,
1814 IPW_ORD_TABLE_5_LAST
1819 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1822 IPW_ORD_TABLE_6_LAST
1827 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1828 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1829 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1830 IPW_ORD_STAT_CURR_RSSI_DBM,
1831 IPW_ORD_TABLE_7_LAST
1834 #define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
1835 #define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
1836 #define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
1837 #define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
1838 #define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
1839 #define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
1840 #define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
1842 struct ipw_fixed_rate {
1845 } __attribute__ ((packed));
1847 #define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1853 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1854 } __attribute__ ((packed));
1856 #define CFG_BT_COEXISTENCE_MIN 0x00
1857 #define CFG_BT_COEXISTENCE_DEFER 0x02
1858 #define CFG_BT_COEXISTENCE_KILL 0x04
1859 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1860 #define CFG_BT_COEXISTENCE_OOB 0x10
1861 #define CFG_BT_COEXISTENCE_MAX 0xFF
1862 #define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM */
1864 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1865 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1866 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1868 #define CFG_SYS_ANTENNA_BOTH 0x000
1869 #define CFG_SYS_ANTENNA_A 0x001
1870 #define CFG_SYS_ANTENNA_B 0x003
1873 * The definitions below were lifted off the ipw2100 driver, which only
1874 * supports 'b' mode, so I'm sure these are not exactly correct.
1876 * Somebody fix these!!
1878 #define REG_MIN_CHANNEL 0
1879 #define REG_MAX_CHANNEL 14
1881 #define REG_CHANNEL_MASK 0x00003FFF
1882 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1884 #define IPW_MAX_CONFIG_RETRIES 10
1886 static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr)
1891 retval = sizeof(struct ieee80211_hdr_3addr);
1892 fc = le16_to_cpu(hdr->frame_ctl);
1895 * Function ToDS FromDS
1901 * Only WDS frames use Address4 among them. --YZ
1903 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1909 #endif /* __ipw2200_h__ */