2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, ®);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
61 udelay(REGISTER_BUSY_DELAY);
67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
73 * Wait until the BBP becomes ready.
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
82 * Write the data into the BBP.
85 rt2x00_set_field32(®, BBPCSR_VALUE, value);
86 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
99 * Wait until the BBP becomes ready.
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
108 * Write the request into the BBP.
111 rt2x00_set_field32(®, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
118 * Wait until the BBP becomes ready.
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, ®);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
143 udelay(REGISTER_BUSY_DELAY);
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
151 rt2x00_set_field32(®, RFCSR_VALUE, value);
152 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(®, RFCSR_BUSY, 1);
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
165 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 static const struct rt2x00debug rt2500pci_rt2x00debug = {
192 .owner = THIS_MODULE,
194 .read = rt2x00pci_register_read,
195 .write = rt2x00pci_register_write,
196 .flags = RT2X00DEBUGFS_OFFSET,
197 .word_base = CSR_REG_BASE,
198 .word_size = sizeof(u32),
199 .word_count = CSR_REG_SIZE / sizeof(u32),
202 .read = rt2x00_eeprom_read,
203 .write = rt2x00_eeprom_write,
204 .word_base = EEPROM_BASE,
205 .word_size = sizeof(u16),
206 .word_count = EEPROM_SIZE / sizeof(u16),
209 .read = rt2500pci_bbp_read,
210 .write = rt2500pci_bbp_write,
211 .word_base = BBP_BASE,
212 .word_size = sizeof(u8),
213 .word_count = BBP_SIZE / sizeof(u8),
216 .read = rt2x00_rf_read,
217 .write = rt2500pci_rf_write,
218 .word_base = RF_BASE,
219 .word_size = sizeof(u32),
220 .word_count = RF_SIZE / sizeof(u32),
223 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
225 #ifdef CONFIG_RT2X00_LIB_RFKILL
226 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
230 rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
231 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
234 #define rt2500pci_rfkill_poll NULL
235 #endif /* CONFIG_RT2X00_LIB_RFKILL */
237 #ifdef CONFIG_RT2X00_LIB_LEDS
238 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
239 enum led_brightness brightness)
241 struct rt2x00_led *led =
242 container_of(led_cdev, struct rt2x00_led, led_dev);
243 unsigned int enabled = brightness != LED_OFF;
246 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
248 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
249 rt2x00_set_field32(®, LEDCSR_LINK, enabled);
250 else if (led->type == LED_TYPE_ACTIVITY)
251 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
253 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
256 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
257 unsigned long *delay_on,
258 unsigned long *delay_off)
260 struct rt2x00_led *led =
261 container_of(led_cdev, struct rt2x00_led, led_dev);
264 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
265 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
266 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
267 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
272 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
273 struct rt2x00_led *led,
276 led->rt2x00dev = rt2x00dev;
278 led->led_dev.brightness_set = rt2500pci_brightness_set;
279 led->led_dev.blink_set = rt2500pci_blink_set;
280 led->flags = LED_INITIALIZED;
282 #endif /* CONFIG_RT2X00_LIB_LEDS */
285 * Configuration handlers.
287 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
288 const unsigned int filter_flags)
293 * Start configuration steps.
294 * Note that the version error will always be dropped
295 * and broadcast frames will always be accepted since
296 * there is no filter for it at this time.
298 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
299 rt2x00_set_field32(®, RXCSR0_DROP_CRC,
300 !(filter_flags & FIF_FCSFAIL));
301 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
302 !(filter_flags & FIF_PLCPFAIL));
303 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
304 !(filter_flags & FIF_CONTROL));
305 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
306 !(filter_flags & FIF_PROMISC_IN_BSS));
307 rt2x00_set_field32(®, RXCSR0_DROP_TODS,
308 !(filter_flags & FIF_PROMISC_IN_BSS) &&
309 !rt2x00dev->intf_ap_count);
310 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
311 rt2x00_set_field32(®, RXCSR0_DROP_MCAST,
312 !(filter_flags & FIF_ALLMULTI));
313 rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0);
314 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
317 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
318 struct rt2x00_intf *intf,
319 struct rt2x00intf_conf *conf,
320 const unsigned int flags)
322 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
323 unsigned int bcn_preload;
326 if (flags & CONFIG_UPDATE_TYPE) {
328 * Enable beacon config
330 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
331 rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
332 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
333 rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min);
334 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
337 * Enable synchronisation.
339 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
340 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
341 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
342 rt2x00_set_field32(®, CSR14_TBCN, 1);
343 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
346 if (flags & CONFIG_UPDATE_MAC)
347 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
348 conf->mac, sizeof(conf->mac));
350 if (flags & CONFIG_UPDATE_BSSID)
351 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
352 conf->bssid, sizeof(conf->bssid));
355 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
356 struct rt2x00lib_erp *erp)
362 * When short preamble is enabled, we should set bit 0x08
364 preamble_mask = erp->short_preamble << 3;
366 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
367 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT,
369 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME,
370 erp->ack_consume_time);
371 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
373 rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
374 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
375 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
376 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
377 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
379 rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
380 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
381 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
382 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
383 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
385 rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
386 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
387 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
388 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
389 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
391 rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
392 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
393 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
394 rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
395 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
397 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
399 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
400 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
401 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
403 rt2x00pci_register_read(rt2x00dev, CSR18, ®);
404 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
405 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
406 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
408 rt2x00pci_register_read(rt2x00dev, CSR19, ®);
409 rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
410 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
411 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
414 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
415 struct antenna_setup *ant)
422 * We should never come here because rt2x00lib is supposed
423 * to catch this and send us the correct antenna explicitely.
425 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
426 ant->tx == ANTENNA_SW_DIVERSITY);
428 rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®);
429 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
430 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
433 * Configure the TX antenna.
437 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
438 rt2x00_set_field32(®, BBPCSR1_CCK, 0);
439 rt2x00_set_field32(®, BBPCSR1_OFDM, 0);
443 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
444 rt2x00_set_field32(®, BBPCSR1_CCK, 2);
445 rt2x00_set_field32(®, BBPCSR1_OFDM, 2);
450 * Configure the RX antenna.
454 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
458 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
463 * RT2525E and RT5222 need to flip TX I/Q
465 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
466 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
467 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
468 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1);
469 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1);
472 * RT2525E does not need RX I/Q Flip.
474 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
475 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
477 rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0);
478 rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0);
481 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
482 rt2500pci_bbp_write(rt2x00dev, 14, r14);
483 rt2500pci_bbp_write(rt2x00dev, 2, r2);
486 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
487 struct rf_channel *rf, const int txpower)
494 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
497 * Switch on tuning bits.
498 * For RT2523 devices we do not need to update the R1 register.
500 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
501 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
502 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
505 * For RT2525 we should first set the channel to half band higher.
507 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
508 static const u32 vals[] = {
509 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
510 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
511 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
512 0x00080d2e, 0x00080d3a
515 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
516 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
517 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
519 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
522 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
523 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
524 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
526 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
529 * Channel 14 requires the Japan filter bit to be set.
532 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
533 rt2500pci_bbp_write(rt2x00dev, 70, r70);
538 * Switch off tuning bits.
539 * For RT2523 devices we do not need to update the R1 register.
541 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
542 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
543 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
546 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
547 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
550 * Clear false CRC during channel switch.
552 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
555 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
560 rt2x00_rf_read(rt2x00dev, 3, &rf3);
561 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
562 rt2500pci_rf_write(rt2x00dev, 3, rf3);
565 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
566 struct rt2x00lib_conf *libconf)
570 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
571 rt2x00_set_field32(®, CSR11_LONG_RETRY,
572 libconf->conf->long_frame_max_tx_count);
573 rt2x00_set_field32(®, CSR11_SHORT_RETRY,
574 libconf->conf->short_frame_max_tx_count);
575 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
578 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
579 struct rt2x00lib_conf *libconf)
583 rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
584 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
585 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
586 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
588 rt2x00pci_register_read(rt2x00dev, CSR12, ®);
589 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
590 libconf->conf->beacon_int * 16);
591 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
592 libconf->conf->beacon_int * 16);
593 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
596 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
597 struct rt2x00lib_conf *libconf,
598 const unsigned int flags)
600 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
601 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
602 libconf->conf->power_level);
603 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
604 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
605 rt2500pci_config_txpower(rt2x00dev,
606 libconf->conf->power_level);
607 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
608 rt2500pci_config_retry_limit(rt2x00dev, libconf);
609 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
610 rt2500pci_config_duration(rt2x00dev, libconf);
616 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
617 struct link_qual *qual)
622 * Update FCS error count from register.
624 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
625 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
628 * Update False CCA count from register.
630 rt2x00pci_register_read(rt2x00dev, CNT3, ®);
631 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
634 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
636 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
637 rt2x00dev->link.vgc_level = 0x48;
640 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
642 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
646 * To prevent collisions with MAC ASIC on chipsets
647 * up to version C the link tuning should halt after 20
648 * seconds while being associated.
650 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
651 rt2x00dev->intf_associated &&
652 rt2x00dev->link.count > 20)
655 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
658 * Chipset versions C and lower should directly continue
659 * to the dynamic CCA tuning. Chipset version D and higher
660 * should go straight to dynamic CCA tuning when they
661 * are not associated.
663 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
664 !rt2x00dev->intf_associated)
665 goto dynamic_cca_tune;
668 * A too low RSSI will cause too much false CCA which will
669 * then corrupt the R17 tuning. To remidy this the tuning should
670 * be stopped (While making sure the R17 value will not exceed limits)
672 if (rssi < -80 && rt2x00dev->link.count > 20) {
674 r17 = rt2x00dev->link.vgc_level;
675 rt2500pci_bbp_write(rt2x00dev, 17, r17);
681 * Special big-R17 for short distance
685 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
690 * Special mid-R17 for middle distance
694 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
699 * Leave short or middle distance condition, restore r17
700 * to the dynamic tuning range.
703 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
710 * R17 is inside the dynamic tuning range,
711 * start tuning the link based on the false cca counter.
713 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
714 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
715 rt2x00dev->link.vgc_level = r17;
716 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
717 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
718 rt2x00dev->link.vgc_level = r17;
723 * Initialization functions.
725 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
727 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
730 if (entry->queue->qid == QID_RX) {
731 rt2x00_desc_read(entry_priv->desc, 0, &word);
733 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
735 rt2x00_desc_read(entry_priv->desc, 0, &word);
737 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
738 rt2x00_get_field32(word, TXD_W0_VALID));
742 static void rt2500pci_clear_entry(struct queue_entry *entry)
744 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
745 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
748 if (entry->queue->qid == QID_RX) {
749 rt2x00_desc_read(entry_priv->desc, 1, &word);
750 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
751 rt2x00_desc_write(entry_priv->desc, 1, word);
753 rt2x00_desc_read(entry_priv->desc, 0, &word);
754 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
755 rt2x00_desc_write(entry_priv->desc, 0, word);
757 rt2x00_desc_read(entry_priv->desc, 0, &word);
758 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
759 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
760 rt2x00_desc_write(entry_priv->desc, 0, word);
764 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
766 struct queue_entry_priv_pci *entry_priv;
770 * Initialize registers.
772 rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
773 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
774 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
775 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
776 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
777 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
779 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
780 rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
781 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
782 entry_priv->desc_dma);
783 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
785 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
786 rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
787 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
788 entry_priv->desc_dma);
789 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
791 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
792 rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
793 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
794 entry_priv->desc_dma);
795 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
797 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
798 rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
799 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
800 entry_priv->desc_dma);
801 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
803 rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
804 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
805 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
806 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
808 entry_priv = rt2x00dev->rx->entries[0].priv_data;
809 rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
810 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
811 entry_priv->desc_dma);
812 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
817 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
821 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
822 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
823 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
824 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
826 rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
827 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
828 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
829 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
830 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
832 rt2x00pci_register_read(rt2x00dev, CSR9, ®);
833 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
834 rt2x00dev->rx->data_size / 128);
835 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
838 * Always use CWmin and CWmax set in descriptor.
840 rt2x00pci_register_read(rt2x00dev, CSR11, ®);
841 rt2x00_set_field32(®, CSR11_CW_SELECT, 0);
842 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
844 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
845 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
846 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
847 rt2x00_set_field32(®, CSR14_TBCN, 0);
848 rt2x00_set_field32(®, CSR14_TCFP, 0);
849 rt2x00_set_field32(®, CSR14_TATIMW, 0);
850 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
851 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
852 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
853 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
855 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
857 rt2x00pci_register_read(rt2x00dev, TXCSR8, ®);
858 rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10);
859 rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1);
860 rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11);
861 rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1);
862 rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13);
863 rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1);
864 rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12);
865 rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1);
866 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
868 rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®);
869 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112);
870 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56);
871 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20);
872 rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10);
873 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
875 rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®);
876 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45);
877 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37);
878 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33);
879 rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29);
880 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
882 rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®);
883 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29);
884 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25);
885 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25);
886 rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25);
887 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
889 rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
890 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */
891 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
892 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */
893 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
894 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
895 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
896 rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */
897 rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1);
898 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
900 rt2x00pci_register_read(rt2x00dev, PCICSR, ®);
901 rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0);
902 rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0);
903 rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3);
904 rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1);
905 rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1);
906 rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1);
907 rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1);
908 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
910 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
912 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
913 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
915 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
918 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
919 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
921 rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
922 rt2x00_set_field32(®, MACCSR2_DELAY, 64);
923 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
925 rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
926 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
927 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26);
928 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1);
929 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
930 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26);
931 rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1);
932 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
934 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
936 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
938 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
939 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
940 rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
941 rt2x00_set_field32(®, CSR1_HOST_READY, 0);
942 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
944 rt2x00pci_register_read(rt2x00dev, CSR1, ®);
945 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
946 rt2x00_set_field32(®, CSR1_HOST_READY, 1);
947 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
950 * We must clear the FCS and FIFO error count.
951 * These registers are cleared on read,
952 * so we may pass a useless variable to store the value.
954 rt2x00pci_register_read(rt2x00dev, CNT0, ®);
955 rt2x00pci_register_read(rt2x00dev, CNT4, ®);
960 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
965 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
966 rt2500pci_bbp_read(rt2x00dev, 0, &value);
967 if ((value != 0xff) && (value != 0x00))
969 udelay(REGISTER_BUSY_DELAY);
972 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
976 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
983 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
986 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
987 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
988 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
989 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
990 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
991 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
992 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
993 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
994 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
995 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
996 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
997 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
998 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
999 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1000 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1001 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1002 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1003 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1004 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1005 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1006 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1007 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1008 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1009 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1010 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1011 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1012 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1013 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1014 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1015 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1017 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1018 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1020 if (eeprom != 0xffff && eeprom != 0x0000) {
1021 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1022 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1023 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1031 * Device state switch handlers.
1033 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1034 enum dev_state state)
1038 rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
1039 rt2x00_set_field32(®, RXCSR0_DISABLE_RX,
1040 (state == STATE_RADIO_RX_OFF) ||
1041 (state == STATE_RADIO_RX_OFF_LINK));
1042 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1045 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1046 enum dev_state state)
1048 int mask = (state == STATE_RADIO_IRQ_OFF);
1052 * When interrupts are being enabled, the interrupt registers
1053 * should clear the register to assure a clean state.
1055 if (state == STATE_RADIO_IRQ_ON) {
1056 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1057 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1061 * Only toggle the interrupts bits we are going to use.
1062 * Non-checked interrupt bits are disabled by default.
1064 rt2x00pci_register_read(rt2x00dev, CSR8, ®);
1065 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
1066 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
1067 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
1068 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
1069 rt2x00_set_field32(®, CSR8_RXDONE, mask);
1070 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1073 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1076 * Initialize all registers.
1078 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1079 rt2500pci_init_registers(rt2x00dev) ||
1080 rt2500pci_init_bbp(rt2x00dev)))
1086 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1090 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1093 * Disable synchronisation.
1095 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1100 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1101 rt2x00_set_field32(®, TXCSR0_ABORT, 1);
1102 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1105 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1106 enum dev_state state)
1114 put_to_sleep = (state != STATE_AWAKE);
1116 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
1117 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
1118 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
1119 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
1120 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1121 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1124 * Device is not guaranteed to be in the requested state yet.
1125 * We must wait until the register indicates that the
1126 * device has entered the correct state.
1128 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1129 rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
1130 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1131 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1132 if (bbp_state == state && rf_state == state)
1140 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1141 enum dev_state state)
1146 case STATE_RADIO_ON:
1147 retval = rt2500pci_enable_radio(rt2x00dev);
1149 case STATE_RADIO_OFF:
1150 rt2500pci_disable_radio(rt2x00dev);
1152 case STATE_RADIO_RX_ON:
1153 case STATE_RADIO_RX_ON_LINK:
1154 case STATE_RADIO_RX_OFF:
1155 case STATE_RADIO_RX_OFF_LINK:
1156 rt2500pci_toggle_rx(rt2x00dev, state);
1158 case STATE_RADIO_IRQ_ON:
1159 case STATE_RADIO_IRQ_OFF:
1160 rt2500pci_toggle_irq(rt2x00dev, state);
1162 case STATE_DEEP_SLEEP:
1166 retval = rt2500pci_set_state(rt2x00dev, state);
1173 if (unlikely(retval))
1174 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1181 * TX descriptor initialization
1183 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1184 struct sk_buff *skb,
1185 struct txentry_desc *txdesc)
1187 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1188 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1189 __le32 *txd = skbdesc->desc;
1193 * Start writing the descriptor words.
1195 rt2x00_desc_read(entry_priv->desc, 1, &word);
1196 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1197 rt2x00_desc_write(entry_priv->desc, 1, word);
1199 rt2x00_desc_read(txd, 2, &word);
1200 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1201 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1202 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1203 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1204 rt2x00_desc_write(txd, 2, word);
1206 rt2x00_desc_read(txd, 3, &word);
1207 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1208 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1209 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1210 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1211 rt2x00_desc_write(txd, 3, word);
1213 rt2x00_desc_read(txd, 10, &word);
1214 rt2x00_set_field32(&word, TXD_W10_RTS,
1215 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1216 rt2x00_desc_write(txd, 10, word);
1218 rt2x00_desc_read(txd, 0, &word);
1219 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1220 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1221 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1222 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1223 rt2x00_set_field32(&word, TXD_W0_ACK,
1224 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1225 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1226 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1227 rt2x00_set_field32(&word, TXD_W0_OFDM,
1228 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1229 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1230 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1231 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1232 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1233 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1234 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1235 rt2x00_desc_write(txd, 0, word);
1239 * TX data initialization
1241 static void rt2500pci_write_beacon(struct queue_entry *entry)
1243 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1244 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1245 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1250 * Disable beaconing while we are reloading the beacon data,
1251 * otherwise we might be sending out invalid data.
1253 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1254 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
1255 rt2x00_set_field32(®, CSR14_TBCN, 0);
1256 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
1257 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1260 * Replace rt2x00lib allocated descriptor with the
1261 * pointer to the _real_ hardware descriptor.
1262 * After that, map the beacon to DMA and update the
1265 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1266 skbdesc->desc = entry_priv->desc;
1268 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1270 rt2x00_desc_read(entry_priv->desc, 1, &word);
1271 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1272 rt2x00_desc_write(entry_priv->desc, 1, word);
1275 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1276 const enum data_queue_qid queue)
1280 if (queue == QID_BEACON) {
1281 rt2x00pci_register_read(rt2x00dev, CSR14, ®);
1282 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1283 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
1284 rt2x00_set_field32(®, CSR14_TBCN, 1);
1285 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
1286 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1291 rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
1292 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1293 rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1294 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1295 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1299 * RX control handlers
1301 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1302 struct rxdone_entry_desc *rxdesc)
1304 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1308 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1309 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1311 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1312 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1313 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1314 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1317 * Obtain the status about this packet.
1318 * When frame was received with an OFDM bitrate,
1319 * the signal is the PLCP value. If it was received with
1320 * a CCK bitrate the signal is the rate in 100kbit/s.
1322 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1323 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1324 entry->queue->rt2x00dev->rssi_offset;
1325 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1327 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1328 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1330 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1331 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1332 rxdesc->dev_flags |= RXDONE_MY_BSS;
1336 * Interrupt functions.
1338 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1339 const enum data_queue_qid queue_idx)
1341 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1342 struct queue_entry_priv_pci *entry_priv;
1343 struct queue_entry *entry;
1344 struct txdone_entry_desc txdesc;
1347 while (!rt2x00queue_empty(queue)) {
1348 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1349 entry_priv = entry->priv_data;
1350 rt2x00_desc_read(entry_priv->desc, 0, &word);
1352 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1353 !rt2x00_get_field32(word, TXD_W0_VALID))
1357 * Obtain the status about this packet.
1360 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1361 case 0: /* Success */
1362 case 1: /* Success with retry */
1363 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1365 case 2: /* Failure, excessive retries */
1366 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1367 /* Don't break, this is a failed frame! */
1368 default: /* Failure */
1369 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1371 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1373 rt2x00lib_txdone(entry, &txdesc);
1377 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1379 struct rt2x00_dev *rt2x00dev = dev_instance;
1383 * Get the interrupt sources & saved to local variable.
1384 * Write register value back to clear pending interrupts.
1386 rt2x00pci_register_read(rt2x00dev, CSR7, ®);
1387 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1392 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1396 * Handle interrupts, walk through all bits
1397 * and run the tasks, the bits are checked in order of
1402 * 1 - Beacon timer expired interrupt.
1404 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1405 rt2x00lib_beacondone(rt2x00dev);
1408 * 2 - Rx ring done interrupt.
1410 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1411 rt2x00pci_rxdone(rt2x00dev);
1414 * 3 - Atim ring transmit done interrupt.
1416 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1417 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1420 * 4 - Priority ring transmit done interrupt.
1422 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1423 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1426 * 5 - Tx ring transmit done interrupt.
1428 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1429 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1435 * Device probe functions.
1437 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1439 struct eeprom_93cx6 eeprom;
1444 rt2x00pci_register_read(rt2x00dev, CSR21, ®);
1446 eeprom.data = rt2x00dev;
1447 eeprom.register_read = rt2500pci_eepromregister_read;
1448 eeprom.register_write = rt2500pci_eepromregister_write;
1449 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1450 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1451 eeprom.reg_data_in = 0;
1452 eeprom.reg_data_out = 0;
1453 eeprom.reg_data_clock = 0;
1454 eeprom.reg_chip_select = 0;
1456 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1457 EEPROM_SIZE / sizeof(u16));
1460 * Start validation of the data that has been read.
1462 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1463 if (!is_valid_ether_addr(mac)) {
1464 random_ether_addr(mac);
1465 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1468 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1469 if (word == 0xffff) {
1470 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1471 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1472 ANTENNA_SW_DIVERSITY);
1473 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1474 ANTENNA_SW_DIVERSITY);
1475 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1477 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1478 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1479 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1480 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1481 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1484 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1485 if (word == 0xffff) {
1486 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1487 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1488 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1489 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1490 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1493 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1494 if (word == 0xffff) {
1495 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1496 DEFAULT_RSSI_OFFSET);
1497 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1498 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1504 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1511 * Read EEPROM word for configuration.
1513 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1516 * Identify RF chipset.
1518 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1519 rt2x00pci_register_read(rt2x00dev, CSR0, ®);
1520 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1522 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1523 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1524 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1525 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1526 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1527 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1528 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1533 * Identify default antenna configuration.
1535 rt2x00dev->default_ant.tx =
1536 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1537 rt2x00dev->default_ant.rx =
1538 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1541 * Store led mode, for correct led behaviour.
1543 #ifdef CONFIG_RT2X00_LIB_LEDS
1544 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1546 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1547 if (value == LED_MODE_TXRX_ACTIVITY)
1548 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1550 #endif /* CONFIG_RT2X00_LIB_LEDS */
1553 * Detect if this device has an hardware controlled radio.
1555 #ifdef CONFIG_RT2X00_LIB_RFKILL
1556 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1557 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1558 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1561 * Check if the BBP tuning should be enabled.
1563 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1565 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1566 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1569 * Read the RSSI <-> dBm offset information.
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1572 rt2x00dev->rssi_offset =
1573 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1579 * RF value list for RF2522
1582 static const struct rf_channel rf_vals_bg_2522[] = {
1583 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1584 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1585 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1586 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1587 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1588 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1589 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1590 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1591 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1592 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1593 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1594 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1595 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1596 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1600 * RF value list for RF2523
1603 static const struct rf_channel rf_vals_bg_2523[] = {
1604 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1605 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1606 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1607 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1608 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1609 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1610 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1611 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1612 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1613 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1614 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1615 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1616 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1617 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1621 * RF value list for RF2524
1624 static const struct rf_channel rf_vals_bg_2524[] = {
1625 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1626 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1627 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1628 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1629 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1630 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1631 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1632 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1633 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1634 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1635 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1636 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1637 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1638 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1642 * RF value list for RF2525
1645 static const struct rf_channel rf_vals_bg_2525[] = {
1646 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1647 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1648 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1649 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1650 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1651 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1652 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1653 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1654 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1655 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1656 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1657 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1658 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1659 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1663 * RF value list for RF2525e
1666 static const struct rf_channel rf_vals_bg_2525e[] = {
1667 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1668 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1669 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1670 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1671 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1672 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1673 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1674 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1675 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1676 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1677 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1678 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1679 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1680 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1684 * RF value list for RF5222
1685 * Supports: 2.4 GHz & 5.2 GHz
1687 static const struct rf_channel rf_vals_5222[] = {
1688 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1689 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1690 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1691 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1692 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1693 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1694 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1695 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1696 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1697 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1698 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1699 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1700 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1701 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1703 /* 802.11 UNI / HyperLan 2 */
1704 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1705 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1706 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1707 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1708 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1709 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1710 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1711 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1713 /* 802.11 HyperLan 2 */
1714 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1715 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1716 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1717 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1718 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1719 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1720 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1721 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1722 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1723 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1726 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1727 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1728 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1729 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1730 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1733 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1735 struct hw_mode_spec *spec = &rt2x00dev->spec;
1736 struct channel_info *info;
1741 * Initialize all hw fields.
1743 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1744 IEEE80211_HW_SIGNAL_DBM;
1746 rt2x00dev->hw->extra_tx_headroom = 0;
1748 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1749 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1750 rt2x00_eeprom_addr(rt2x00dev,
1751 EEPROM_MAC_ADDR_0));
1754 * Initialize hw_mode information.
1756 spec->supported_bands = SUPPORT_BAND_2GHZ;
1757 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1759 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1760 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1761 spec->channels = rf_vals_bg_2522;
1762 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1763 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1764 spec->channels = rf_vals_bg_2523;
1765 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1766 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1767 spec->channels = rf_vals_bg_2524;
1768 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1769 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1770 spec->channels = rf_vals_bg_2525;
1771 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1772 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1773 spec->channels = rf_vals_bg_2525e;
1774 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1775 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1776 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1777 spec->channels = rf_vals_5222;
1781 * Create channel information array
1783 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1787 spec->channels_info = info;
1789 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1790 for (i = 0; i < 14; i++)
1791 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1793 if (spec->num_channels > 14) {
1794 for (i = 14; i < spec->num_channels; i++)
1795 info[i].tx_power1 = DEFAULT_TXPOWER;
1801 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1806 * Allocate eeprom data.
1808 retval = rt2500pci_validate_eeprom(rt2x00dev);
1812 retval = rt2500pci_init_eeprom(rt2x00dev);
1817 * Initialize hw specifications.
1819 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1824 * This device requires the atim queue and DMA-mapped skbs.
1826 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1827 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1830 * Set the rssi offset.
1832 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1838 * IEEE80211 stack callback functions.
1840 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1842 struct rt2x00_dev *rt2x00dev = hw->priv;
1846 rt2x00pci_register_read(rt2x00dev, CSR17, ®);
1847 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1848 rt2x00pci_register_read(rt2x00dev, CSR16, ®);
1849 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1854 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1856 struct rt2x00_dev *rt2x00dev = hw->priv;
1859 rt2x00pci_register_read(rt2x00dev, CSR15, ®);
1860 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1863 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1865 .start = rt2x00mac_start,
1866 .stop = rt2x00mac_stop,
1867 .add_interface = rt2x00mac_add_interface,
1868 .remove_interface = rt2x00mac_remove_interface,
1869 .config = rt2x00mac_config,
1870 .config_interface = rt2x00mac_config_interface,
1871 .configure_filter = rt2x00mac_configure_filter,
1872 .get_stats = rt2x00mac_get_stats,
1873 .bss_info_changed = rt2x00mac_bss_info_changed,
1874 .conf_tx = rt2x00mac_conf_tx,
1875 .get_tx_stats = rt2x00mac_get_tx_stats,
1876 .get_tsf = rt2500pci_get_tsf,
1877 .tx_last_beacon = rt2500pci_tx_last_beacon,
1880 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1881 .irq_handler = rt2500pci_interrupt,
1882 .probe_hw = rt2500pci_probe_hw,
1883 .initialize = rt2x00pci_initialize,
1884 .uninitialize = rt2x00pci_uninitialize,
1885 .get_entry_state = rt2500pci_get_entry_state,
1886 .clear_entry = rt2500pci_clear_entry,
1887 .set_device_state = rt2500pci_set_device_state,
1888 .rfkill_poll = rt2500pci_rfkill_poll,
1889 .link_stats = rt2500pci_link_stats,
1890 .reset_tuner = rt2500pci_reset_tuner,
1891 .link_tuner = rt2500pci_link_tuner,
1892 .write_tx_desc = rt2500pci_write_tx_desc,
1893 .write_tx_data = rt2x00pci_write_tx_data,
1894 .write_beacon = rt2500pci_write_beacon,
1895 .kick_tx_queue = rt2500pci_kick_tx_queue,
1896 .fill_rxdone = rt2500pci_fill_rxdone,
1897 .config_filter = rt2500pci_config_filter,
1898 .config_intf = rt2500pci_config_intf,
1899 .config_erp = rt2500pci_config_erp,
1900 .config_ant = rt2500pci_config_ant,
1901 .config = rt2500pci_config,
1904 static const struct data_queue_desc rt2500pci_queue_rx = {
1905 .entry_num = RX_ENTRIES,
1906 .data_size = DATA_FRAME_SIZE,
1907 .desc_size = RXD_DESC_SIZE,
1908 .priv_size = sizeof(struct queue_entry_priv_pci),
1911 static const struct data_queue_desc rt2500pci_queue_tx = {
1912 .entry_num = TX_ENTRIES,
1913 .data_size = DATA_FRAME_SIZE,
1914 .desc_size = TXD_DESC_SIZE,
1915 .priv_size = sizeof(struct queue_entry_priv_pci),
1918 static const struct data_queue_desc rt2500pci_queue_bcn = {
1919 .entry_num = BEACON_ENTRIES,
1920 .data_size = MGMT_FRAME_SIZE,
1921 .desc_size = TXD_DESC_SIZE,
1922 .priv_size = sizeof(struct queue_entry_priv_pci),
1925 static const struct data_queue_desc rt2500pci_queue_atim = {
1926 .entry_num = ATIM_ENTRIES,
1927 .data_size = DATA_FRAME_SIZE,
1928 .desc_size = TXD_DESC_SIZE,
1929 .priv_size = sizeof(struct queue_entry_priv_pci),
1932 static const struct rt2x00_ops rt2500pci_ops = {
1933 .name = KBUILD_MODNAME,
1936 .eeprom_size = EEPROM_SIZE,
1938 .tx_queues = NUM_TX_QUEUES,
1939 .rx = &rt2500pci_queue_rx,
1940 .tx = &rt2500pci_queue_tx,
1941 .bcn = &rt2500pci_queue_bcn,
1942 .atim = &rt2500pci_queue_atim,
1943 .lib = &rt2500pci_rt2x00_ops,
1944 .hw = &rt2500pci_mac80211_ops,
1945 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1946 .debugfs = &rt2500pci_rt2x00debug,
1947 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1951 * RT2500pci module information.
1953 static struct pci_device_id rt2500pci_device_table[] = {
1954 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1958 MODULE_AUTHOR(DRV_PROJECT);
1959 MODULE_VERSION(DRV_VERSION);
1960 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1961 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1962 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1963 MODULE_LICENSE("GPL");
1965 static struct pci_driver rt2500pci_driver = {
1966 .name = KBUILD_MODNAME,
1967 .id_table = rt2500pci_device_table,
1968 .probe = rt2x00pci_probe,
1969 .remove = __devexit_p(rt2x00pci_remove),
1970 .suspend = rt2x00pci_suspend,
1971 .resume = rt2x00pci_resume,
1974 static int __init rt2500pci_init(void)
1976 return pci_register_driver(&rt2500pci_driver);
1979 static void __exit rt2500pci_exit(void)
1981 pci_unregister_driver(&rt2500pci_driver);
1984 module_init(rt2500pci_init);
1985 module_exit(rt2500pci_exit);