drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static int modparam_nohwcrypt = 0;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * BBP and RF register require indirect register access,
  50  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  51  * These indirect registers work with busy bits,
  52  * and we will try maximal REGISTER_BUSY_COUNT times to access
  53  * the register while taking a REGISTER_BUSY_DELAY us delay
  54  * between each attampt. When the busy bit is still set at that time,
  55  * the access attempt is considered to have failed,
  56  * and we will print an error.
  57  */
  58 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  59 {
  60         u32 reg;
  61         unsigned int i;
  62
  63         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  64                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  65                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  66                         break;
  67                 udelay(REGISTER_BUSY_DELAY);
  68         }
  69
  70         return reg;
  71 }
  72
  73 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  74                               const unsigned int word, const u8 value)
  75 {
  76         u32 reg;
  77
  78         /*
  79          * Wait until the BBP becomes ready.
  80          */
  81         reg = rt61pci_bbp_check(rt2x00dev);
  82         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  83                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  84                 return;
  85         }
  86
  87         /*
  88          * Write the data into the BBP.
  89          */
  90         reg = 0;
  91         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  92         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  93         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  94         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  95
  96         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  97 }
  98
  99 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 100                              const unsigned int word, u8 *value)
 101 {
 102         u32 reg;
 103
 104         /*
 105          * Wait until the BBP becomes ready.
 106          */
 107         reg = rt61pci_bbp_check(rt2x00dev);
 108         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 109                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 110                 return;
 111         }
 112
 113         /*
 114          * Write the request into the BBP.
 115          */
 116         reg = 0;
 117         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 118         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 119         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 120
 121         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 122
 123         /*
 124          * Wait until the BBP becomes ready.
 125          */
 126         reg = rt61pci_bbp_check(rt2x00dev);
 127         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 128                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 129                 *value = 0xff;
 130                 return;
 131         }
 132
 133         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 134 }
 135
 136 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 137                              const unsigned int word, const u32 value)
 138 {
 139         u32 reg;
 140         unsigned int i;
 141
 142         if (!word)
 143                 return;
 144
 145         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 146                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
 147                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 148                         goto rf_write;
 149                 udelay(REGISTER_BUSY_DELAY);
 150         }
 151
 152         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 153         return;
 154
 155 rf_write:
 156         reg = 0;
 157         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 158         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 159         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 160         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 161
 162         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 163         rt2x00_rf_write(rt2x00dev, word, value);
 164 }
 165
 166 #ifdef CONFIG_RT2X00_LIB_LEDS
 167 /*
 168  * This function is only called from rt61pci_led_brightness()
 169  * make gcc happy by placing this function inside the
 170  * same ifdef statement as the caller.
 171  */
 172 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 173                                 const u8 command, const u8 token,
 174                                 const u8 arg0, const u8 arg1)
 175 {
 176         u32 reg;
 177
 178         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 179
 180         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
 181                 ERROR(rt2x00dev, "mcu request error. "
 182                       "Request 0x%02x failed for token 0x%02x.\n",
 183                       command, token);
 184                 return;
 185         }
 186
 187         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 188         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 189         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 190         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 191         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 192
 193         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 194         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 195         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 196         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 197 }
 198 #endif /* CONFIG_RT2X00_LIB_LEDS */
 199
 200 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 201 {
 202         struct rt2x00_dev *rt2x00dev = eeprom->data;
 203         u32 reg;
 204
 205         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 206
 207         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 208         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 209         eeprom->reg_data_clock =
 210             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 211         eeprom->reg_chip_select =
 212             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 213 }
 214
 215 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 216 {
 217         struct rt2x00_dev *rt2x00dev = eeprom->data;
 218         u32 reg = 0;
 219
 220         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 221         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 222         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 223                            !!eeprom->reg_data_clock);
 224         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 225                            !!eeprom->reg_chip_select);
 226
 227         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 228 }
 229
 230 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 231 static const struct rt2x00debug rt61pci_rt2x00debug = {
 232         .owner  = THIS_MODULE,
 233         .csr    = {
 234                 .read           = rt2x00pci_register_read,
 235                 .write          = rt2x00pci_register_write,
 236                 .flags          = RT2X00DEBUGFS_OFFSET,
 237                 .word_base      = CSR_REG_BASE,
 238                 .word_size      = sizeof(u32),
 239                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 240         },
 241         .eeprom = {
 242                 .read           = rt2x00_eeprom_read,
 243                 .write          = rt2x00_eeprom_write,
 244                 .word_base      = EEPROM_BASE,
 245                 .word_size      = sizeof(u16),
 246                 .word_count     = EEPROM_SIZE / sizeof(u16),
 247         },
 248         .bbp    = {
 249                 .read           = rt61pci_bbp_read,
 250                 .write          = rt61pci_bbp_write,
 251                 .word_base      = BBP_BASE,
 252                 .word_size      = sizeof(u8),
 253                 .word_count     = BBP_SIZE / sizeof(u8),
 254         },
 255         .rf     = {
 256                 .read           = rt2x00_rf_read,
 257                 .write          = rt61pci_rf_write,
 258                 .word_base      = RF_BASE,
 259                 .word_size      = sizeof(u32),
 260                 .word_count     = RF_SIZE / sizeof(u32),
 261         },
 262 };
 263 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 264
 265 #ifdef CONFIG_RT2X00_LIB_RFKILL
 266 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 267 {
 268         u32 reg;
 269
 270         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 271         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 272 }
 273 #else
 274 #define rt61pci_rfkill_poll     NULL
 275 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 276
 277 #ifdef CONFIG_RT2X00_LIB_LEDS
 278 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 279                                    enum led_brightness brightness)
 280 {
 281         struct rt2x00_led *led =
 282             container_of(led_cdev, struct rt2x00_led, led_dev);
 283         unsigned int enabled = brightness != LED_OFF;
 284         unsigned int a_mode =
 285             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 286         unsigned int bg_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 288
 289         if (led->type == LED_TYPE_RADIO) {
 290                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 291                                    MCU_LEDCS_RADIO_STATUS, enabled);
 292
 293                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 294                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 295                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 296         } else if (led->type == LED_TYPE_ASSOC) {
 297                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 298                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 301
 302                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 303                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 304                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 305         } else if (led->type == LED_TYPE_QUALITY) {
 306                 /*
 307                  * The brightness is divided into 6 levels (0 - 5),
 308                  * this means we need to convert the brightness
 309                  * argument into the matching level within that range.
 310                  */
 311                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 312                                     brightness / (LED_FULL / 6), 0);
 313         }
 314 }
 315
 316 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 317                              unsigned long *delay_on,
 318                              unsigned long *delay_off)
 319 {
 320         struct rt2x00_led *led =
 321             container_of(led_cdev, struct rt2x00_led, led_dev);
 322         u32 reg;
 323
 324         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 325         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 326         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 327         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 328
 329         return 0;
 330 }
 331
 332 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 333                              struct rt2x00_led *led,
 334                              enum led_type type)
 335 {
 336         led->rt2x00dev = rt2x00dev;
 337         led->type = type;
 338         led->led_dev.brightness_set = rt61pci_brightness_set;
 339         led->led_dev.blink_set = rt61pci_blink_set;
 340         led->flags = LED_INITIALIZED;
 341 }
 342 #endif /* CONFIG_RT2X00_LIB_LEDS */
 343
 344 /*
 345  * Configuration handlers.
 346  */
 347 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 348                                      struct rt2x00lib_crypto *crypto,
 349                                      struct ieee80211_key_conf *key)
 350 {
 351         struct hw_key_entry key_entry;
 352         struct rt2x00_field32 field;
 353         u32 mask;
 354         u32 reg;
 355
 356         if (crypto->cmd == SET_KEY) {
 357                 /*
 358                  * rt2x00lib can't determine the correct free
 359                  * key_idx for shared keys. We have 1 register
 360                  * with key valid bits. The goal is simple, read
 361                  * the register, if that is full we have no slots
 362                  * left.
 363                  * Note that each BSS is allowed to have up to 4
 364                  * shared keys, so put a mask over the allowed
 365                  * entries.
 366                  */
 367                 mask = (0xf << crypto->bssidx);
 368
 369                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 370                 reg &= mask;
 371
 372                 if (reg && reg == mask)
 373                         return -ENOSPC;
 374
 375                 key->hw_key_idx += reg ? ffz(reg) : 0;
 376
 377                 /*
 378                  * Upload key to hardware
 379                  */
 380                 memcpy(key_entry.key, crypto->key,
 381                        sizeof(key_entry.key));
 382                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 383                        sizeof(key_entry.tx_mic));
 384                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 385                        sizeof(key_entry.rx_mic));
 386
 387                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 388                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 389                                               &key_entry, sizeof(key_entry));
 390
 391                 /*
 392                  * The cipher types are stored over 2 registers.
 393                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 394                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 395                  * Using the correct defines correctly will cause overhead,
 396                  * so just calculate the correct offset.
 397                  */
 398                 if (key->hw_key_idx < 8) {
 399                         field.bit_offset = (3 * key->hw_key_idx);
 400                         field.bit_mask = 0x7 << field.bit_offset;
 401
 402                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 403                         rt2x00_set_field32(&reg, field, crypto->cipher);
 404                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 405                 } else {
 406                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 407                         field.bit_mask = 0x7 << field.bit_offset;
 408
 409                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 410                         rt2x00_set_field32(&reg, field, crypto->cipher);
 411                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 412                 }
 413
 414                 /*
 415                  * The driver does not support the IV/EIV generation
 416                  * in hardware. However it doesn't support the IV/EIV
 417                  * inside the ieee80211 frame either, but requires it
 418                  * to be provided seperately for the descriptor.
 419                  * rt2x00lib will cut the IV/EIV data out of all frames
 420                  * given to us by mac80211, but we must tell mac80211
 421                  * to generate the IV/EIV data.
 422                  */
 423                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 424         }
 425
 426         /*
 427          * SEC_CSR0 contains only single-bit fields to indicate
 428          * a particular key is valid. Because using the FIELD32()
 429          * defines directly will cause a lot of overhead we use
 430          * a calculation to determine the correct bit directly.
 431          */
 432         mask = 1 << key->hw_key_idx;
 433
 434         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 435         if (crypto->cmd == SET_KEY)
 436                 reg |= mask;
 437         else if (crypto->cmd == DISABLE_KEY)
 438                 reg &= ~mask;
 439         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 440
 441         return 0;
 442 }
 443
 444 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 445                                        struct rt2x00lib_crypto *crypto,
 446                                        struct ieee80211_key_conf *key)
 447 {
 448         struct hw_pairwise_ta_entry addr_entry;
 449         struct hw_key_entry key_entry;
 450         u32 mask;
 451         u32 reg;
 452
 453         if (crypto->cmd == SET_KEY) {
 454                 /*
 455                  * rt2x00lib can't determine the correct free
 456                  * key_idx for pairwise keys. We have 2 registers
 457                  * with key valid bits. The goal is simple, read
 458                  * the first register, if that is full move to
 459                  * the next register.
 460                  * When both registers are full, we drop the key,
 461                  * otherwise we use the first invalid entry.
 462                  */
 463                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 464                 if (reg && reg == ~0) {
 465                         key->hw_key_idx = 32;
 466                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 467                         if (reg && reg == ~0)
 468                                 return -ENOSPC;
 469                 }
 470
 471                 key->hw_key_idx += reg ? ffz(reg) : 0;
 472
 473                 /*
 474                  * Upload key to hardware
 475                  */
 476                 memcpy(key_entry.key, crypto->key,
 477                        sizeof(key_entry.key));
 478                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 479                        sizeof(key_entry.tx_mic));
 480                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 481                        sizeof(key_entry.rx_mic));
 482
 483                 memset(&addr_entry, 0, sizeof(addr_entry));
 484                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 485                 addr_entry.cipher = crypto->cipher;
 486
 487                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 488                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 489                                               &key_entry, sizeof(key_entry));
 490
 491                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 492                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 493                                               &addr_entry, sizeof(addr_entry));
 494
 495                 /*
 496                  * Enable pairwise lookup table for given BSS idx,
 497                  * without this received frames will not be decrypted
 498                  * by the hardware.
 499                  */
 500                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 501                 reg |= (1 << crypto->bssidx);
 502                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 503
 504                 /*
 505                  * The driver does not support the IV/EIV generation
 506                  * in hardware. However it doesn't support the IV/EIV
 507                  * inside the ieee80211 frame either, but requires it
 508                  * to be provided seperately for the descriptor.
 509                  * rt2x00lib will cut the IV/EIV data out of all frames
 510                  * given to us by mac80211, but we must tell mac80211
 511                  * to generate the IV/EIV data.
 512                  */
 513                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 514         }
 515
 516         /*
 517          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 518          * a particular key is valid. Because using the FIELD32()
 519          * defines directly will cause a lot of overhead we use
 520          * a calculation to determine the correct bit directly.
 521          */
 522         if (key->hw_key_idx < 32) {
 523                 mask = 1 << key->hw_key_idx;
 524
 525                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 526                 if (crypto->cmd == SET_KEY)
 527                         reg |= mask;
 528                 else if (crypto->cmd == DISABLE_KEY)
 529                         reg &= ~mask;
 530                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 531         } else {
 532                 mask = 1 << (key->hw_key_idx - 32);
 533
 534                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 535                 if (crypto->cmd == SET_KEY)
 536                         reg |= mask;
 537                 else if (crypto->cmd == DISABLE_KEY)
 538                         reg &= ~mask;
 539                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 540         }
 541
 542         return 0;
 543 }
 544
 545 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 546                                   const unsigned int filter_flags)
 547 {
 548         u32 reg;
 549
 550         /*
 551          * Start configuration steps.
 552          * Note that the version error will always be dropped
 553          * and broadcast frames will always be accepted since
 554          * there is no filter for it at this time.
 555          */
 556         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 557         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 558                            !(filter_flags & FIF_FCSFAIL));
 559         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 560                            !(filter_flags & FIF_PLCPFAIL));
 561         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 562                            !(filter_flags & FIF_CONTROL));
 563         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 564                            !(filter_flags & FIF_PROMISC_IN_BSS));
 565         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 566                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 567                            !rt2x00dev->intf_ap_count);
 568         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 569         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 570                            !(filter_flags & FIF_ALLMULTI));
 571         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 572         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 573                            !(filter_flags & FIF_CONTROL));
 574         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 575 }
 576
 577 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 578                                 struct rt2x00_intf *intf,
 579                                 struct rt2x00intf_conf *conf,
 580                                 const unsigned int flags)
 581 {
 582         unsigned int beacon_base;
 583         u32 reg;
 584
 585         if (flags & CONFIG_UPDATE_TYPE) {
 586                 /*
 587                  * Clear current synchronisation setup.
 588                  * For the Beacon base registers we only need to clear
 589                  * the first byte since that byte contains the VALID and OWNER
 590                  * bits which (when set to 0) will invalidate the entire beacon.
 591                  */
 592                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 593                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 594
 595                 /*
 596                  * Enable synchronisation.
 597                  */
 598                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 599                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 600                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 601                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 602                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 603         }
 604
 605         if (flags & CONFIG_UPDATE_MAC) {
 606                 reg = le32_to_cpu(conf->mac[1]);
 607                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 608                 conf->mac[1] = cpu_to_le32(reg);
 609
 610                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 611                                               conf->mac, sizeof(conf->mac));
 612         }
 613
 614         if (flags & CONFIG_UPDATE_BSSID) {
 615                 reg = le32_to_cpu(conf->bssid[1]);
 616                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 617                 conf->bssid[1] = cpu_to_le32(reg);
 618
 619                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 620                                               conf->bssid, sizeof(conf->bssid));
 621         }
 622 }
 623
 624 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 625                                struct rt2x00lib_erp *erp)
 626 {
 627         u32 reg;
 628
 629         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 630         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 631         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 632
 633         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 634         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 635                            !!erp->short_preamble);
 636         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 637
 638         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 639
 640         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 641         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 642         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 643
 644         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 645         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 646         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 647         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 648         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 649 }
 650
 651 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 652                                       struct antenna_setup *ant)
 653 {
 654         u8 r3;
 655         u8 r4;
 656         u8 r77;
 657
 658         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 659         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 660         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 661
 662         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 663                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 664
 665         /*
 666          * Configure the RX antenna.
 667          */
 668         switch (ant->rx) {
 669         case ANTENNA_HW_DIVERSITY:
 670                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 671                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 672                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 673                 break;
 674         case ANTENNA_A:
 675                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 676                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 677                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 678                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 679                 else
 680                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 681                 break;
 682         case ANTENNA_B:
 683         default:
 684                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 685                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 686                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 687                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 688                 else
 689                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 690                 break;
 691         }
 692
 693         rt61pci_bbp_write(rt2x00dev, 77, r77);
 694         rt61pci_bbp_write(rt2x00dev, 3, r3);
 695         rt61pci_bbp_write(rt2x00dev, 4, r4);
 696 }
 697
 698 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 699                                       struct antenna_setup *ant)
 700 {
 701         u8 r3;
 702         u8 r4;
 703         u8 r77;
 704
 705         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 706         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 707         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 708
 709         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 710                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 711         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 712                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 713
 714         /*
 715          * Configure the RX antenna.
 716          */
 717         switch (ant->rx) {
 718         case ANTENNA_HW_DIVERSITY:
 719                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 720                 break;
 721         case ANTENNA_A:
 722                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 723                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 724                 break;
 725         case ANTENNA_B:
 726         default:
 727                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 728                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 729                 break;
 730         }
 731
 732         rt61pci_bbp_write(rt2x00dev, 77, r77);
 733         rt61pci_bbp_write(rt2x00dev, 3, r3);
 734         rt61pci_bbp_write(rt2x00dev, 4, r4);
 735 }
 736
 737 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 738                                            const int p1, const int p2)
 739 {
 740         u32 reg;
 741
 742         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 743
 744         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 745         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 746
 747         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 748         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 749
 750         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 751 }
 752
 753 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 754                                         struct antenna_setup *ant)
 755 {
 756         u8 r3;
 757         u8 r4;
 758         u8 r77;
 759
 760         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 761         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 762         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 763
 764         /*
 765          * Configure the RX antenna.
 766          */
 767         switch (ant->rx) {
 768         case ANTENNA_A:
 769                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 770                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 771                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 772                 break;
 773         case ANTENNA_HW_DIVERSITY:
 774                 /*
 775                  * FIXME: Antenna selection for the rf 2529 is very confusing
 776                  * in the legacy driver. Just default to antenna B until the
 777                  * legacy code can be properly translated into rt2x00 code.
 778                  */
 779         case ANTENNA_B:
 780         default:
 781                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 782                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 783                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 784                 break;
 785         }
 786
 787         rt61pci_bbp_write(rt2x00dev, 77, r77);
 788         rt61pci_bbp_write(rt2x00dev, 3, r3);
 789         rt61pci_bbp_write(rt2x00dev, 4, r4);
 790 }
 791
 792 struct antenna_sel {
 793         u8 word;
 794         /*
 795          * value[0] -> non-LNA
 796          * value[1] -> LNA
 797          */
 798         u8 value[2];
 799 };
 800
 801 static const struct antenna_sel antenna_sel_a[] = {
 802         { 96,  { 0x58, 0x78 } },
 803         { 104, { 0x38, 0x48 } },
 804         { 75,  { 0xfe, 0x80 } },
 805         { 86,  { 0xfe, 0x80 } },
 806         { 88,  { 0xfe, 0x80 } },
 807         { 35,  { 0x60, 0x60 } },
 808         { 97,  { 0x58, 0x58 } },
 809         { 98,  { 0x58, 0x58 } },
 810 };
 811
 812 static const struct antenna_sel antenna_sel_bg[] = {
 813         { 96,  { 0x48, 0x68 } },
 814         { 104, { 0x2c, 0x3c } },
 815         { 75,  { 0xfe, 0x80 } },
 816         { 86,  { 0xfe, 0x80 } },
 817         { 88,  { 0xfe, 0x80 } },
 818         { 35,  { 0x50, 0x50 } },
 819         { 97,  { 0x48, 0x48 } },
 820         { 98,  { 0x48, 0x48 } },
 821 };
 822
 823 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 824                                struct antenna_setup *ant)
 825 {
 826         const struct antenna_sel *sel;
 827         unsigned int lna;
 828         unsigned int i;
 829         u32 reg;
 830
 831         /*
 832          * We should never come here because rt2x00lib is supposed
 833          * to catch this and send us the correct antenna explicitely.
 834          */
 835         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 836                ant->tx == ANTENNA_SW_DIVERSITY);
 837
 838         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 839                 sel = antenna_sel_a;
 840                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 841         } else {
 842                 sel = antenna_sel_bg;
 843                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 844         }
 845
 846         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 847                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 848
 849         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 850
 851         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 852                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 853         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 854                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 855
 856         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 857
 858         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 859             rt2x00_rf(&rt2x00dev->chip, RF5325))
 860                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 861         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 862                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 863         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 864                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 865                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 866                 else
 867                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 868         }
 869 }
 870
 871 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 872                                     struct rt2x00lib_conf *libconf)
 873 {
 874         u16 eeprom;
 875         short lna_gain = 0;
 876
 877         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 878                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 879                         lna_gain += 14;
 880
 881                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 882                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 883         } else {
 884                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 885                         lna_gain += 14;
 886
 887                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 888                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 889         }
 890
 891         rt2x00dev->lna_gain = lna_gain;
 892 }
 893
 894 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 895                                    struct rf_channel *rf, const int txpower)
 896 {
 897         u8 r3;
 898         u8 r94;
 899         u8 smart;
 900
 901         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 902         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 903
 904         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 905                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 906
 907         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 908         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 909         rt61pci_bbp_write(rt2x00dev, 3, r3);
 910
 911         r94 = 6;
 912         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 913                 r94 += txpower - MAX_TXPOWER;
 914         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 915                 r94 += txpower;
 916         rt61pci_bbp_write(rt2x00dev, 94, r94);
 917
 918         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 919         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 920         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 921         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 922
 923         udelay(200);
 924
 925         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 926         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 927         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 928         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 929
 930         udelay(200);
 931
 932         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 933         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 934         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 935         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 936
 937         msleep(1);
 938 }
 939
 940 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 941                                    const int txpower)
 942 {
 943         struct rf_channel rf;
 944
 945         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 946         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 947         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 948         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 949
 950         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 951 }
 952
 953 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 954                                     struct rt2x00lib_conf *libconf)
 955 {
 956         u32 reg;
 957
 958         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 959         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 960                            libconf->conf->long_frame_max_tx_count);
 961         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 962                            libconf->conf->short_frame_max_tx_count);
 963         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 964 }
 965
 966 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 967                                     struct rt2x00lib_conf *libconf)
 968 {
 969         u32 reg;
 970
 971         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 972         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 973         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 974
 975         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 976         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 977         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 978
 979         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 980         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 981                            libconf->conf->beacon_int * 16);
 982         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 983 }
 984
 985 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 986                            struct rt2x00lib_conf *libconf,
 987                            const unsigned int flags)
 988 {
 989         /* Always recalculate LNA gain before changing configuration */
 990         rt61pci_config_lna_gain(rt2x00dev, libconf);
 991
 992         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 993                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 994                                        libconf->conf->power_level);
 995         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 996             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 997                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 998         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 999                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1000         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1001                 rt61pci_config_duration(rt2x00dev, libconf);
1002 }
1003
1004 /*
1005  * Link tuning
1006  */
1007 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1008                                struct link_qual *qual)
1009 {
1010         u32 reg;
1011
1012         /*
1013          * Update FCS error count from register.
1014          */
1015         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1016         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1017
1018         /*
1019          * Update False CCA count from register.
1020          */
1021         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1022         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1023 }
1024
1025 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1026 {
1027         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1028         rt2x00dev->link.vgc_level = 0x20;
1029 }
1030
1031 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1032 {
1033         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1034         u8 r17;
1035         u8 up_bound;
1036         u8 low_bound;
1037
1038         rt61pci_bbp_read(rt2x00dev, 17, &r17);
1039
1040         /*
1041          * Determine r17 bounds.
1042          */
1043         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1044                 low_bound = 0x28;
1045                 up_bound = 0x48;
1046                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1047                         low_bound += 0x10;
1048                         up_bound += 0x10;
1049                 }
1050         } else {
1051                 low_bound = 0x20;
1052                 up_bound = 0x40;
1053                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1054                         low_bound += 0x10;
1055                         up_bound += 0x10;
1056                 }
1057         }
1058
1059         /*
1060          * If we are not associated, we should go straight to the
1061          * dynamic CCA tuning.
1062          */
1063         if (!rt2x00dev->intf_associated)
1064                 goto dynamic_cca_tune;
1065
1066         /*
1067          * Special big-R17 for very short distance
1068          */
1069         if (rssi >= -35) {
1070                 if (r17 != 0x60)
1071                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1072                 return;
1073         }
1074
1075         /*
1076          * Special big-R17 for short distance
1077          */
1078         if (rssi >= -58) {
1079                 if (r17 != up_bound)
1080                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1081                 return;
1082         }
1083
1084         /*
1085          * Special big-R17 for middle-short distance
1086          */
1087         if (rssi >= -66) {
1088                 low_bound += 0x10;
1089                 if (r17 != low_bound)
1090                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1091                 return;
1092         }
1093
1094         /*
1095          * Special mid-R17 for middle distance
1096          */
1097         if (rssi >= -74) {
1098                 low_bound += 0x08;
1099                 if (r17 != low_bound)
1100                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1101                 return;
1102         }
1103
1104         /*
1105          * Special case: Change up_bound based on the rssi.
1106          * Lower up_bound when rssi is weaker then -74 dBm.
1107          */
1108         up_bound -= 2 * (-74 - rssi);
1109         if (low_bound > up_bound)
1110                 up_bound = low_bound;
1111
1112         if (r17 > up_bound) {
1113                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1114                 return;
1115         }
1116
1117 dynamic_cca_tune:
1118
1119         /*
1120          * r17 does not yet exceed upper limit, continue and base
1121          * the r17 tuning on the false CCA count.
1122          */
1123         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1124                 if (++r17 > up_bound)
1125                         r17 = up_bound;
1126                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1127         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1128                 if (--r17 < low_bound)
1129                         r17 = low_bound;
1130                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1131         }
1132 }
1133
1134 /*
1135  * Firmware functions
1136  */
1137 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1138 {
1139         char *fw_name;
1140
1141         switch (rt2x00dev->chip.rt) {
1142         case RT2561:
1143                 fw_name = FIRMWARE_RT2561;
1144                 break;
1145         case RT2561s:
1146                 fw_name = FIRMWARE_RT2561s;
1147                 break;
1148         case RT2661:
1149                 fw_name = FIRMWARE_RT2661;
1150                 break;
1151         default:
1152                 fw_name = NULL;
1153                 break;
1154         }
1155
1156         return fw_name;
1157 }
1158
1159 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1160 {
1161         u16 crc;
1162
1163         /*
1164          * Use the crc itu-t algorithm.
1165          * The last 2 bytes in the firmware array are the crc checksum itself,
1166          * this means that we should never pass those 2 bytes to the crc
1167          * algorithm.
1168          */
1169         crc = crc_itu_t(0, data, len - 2);
1170         crc = crc_itu_t_byte(crc, 0);
1171         crc = crc_itu_t_byte(crc, 0);
1172
1173         return crc;
1174 }
1175
1176 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1177                                  const size_t len)
1178 {
1179         int i;
1180         u32 reg;
1181
1182         /*
1183          * Wait for stable hardware.
1184          */
1185         for (i = 0; i < 100; i++) {
1186                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1187                 if (reg)
1188                         break;
1189                 msleep(1);
1190         }
1191
1192         if (!reg) {
1193                 ERROR(rt2x00dev, "Unstable hardware.\n");
1194                 return -EBUSY;
1195         }
1196
1197         /*
1198          * Prepare MCU and mailbox for firmware loading.
1199          */
1200         reg = 0;
1201         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1202         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1203         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1204         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1205         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1206
1207         /*
1208          * Write firmware to device.
1209          */
1210         reg = 0;
1211         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1212         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1213         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1214
1215         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1216                                       data, len);
1217
1218         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1219         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1220
1221         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1222         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1223
1224         for (i = 0; i < 100; i++) {
1225                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1226                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1227                         break;
1228                 msleep(1);
1229         }
1230
1231         if (i == 100) {
1232                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1233                 return -EBUSY;
1234         }
1235
1236         /*
1237          * Hardware needs another millisecond before it is ready.
1238          */
1239         msleep(1);
1240
1241         /*
1242          * Reset MAC and BBP registers.
1243          */
1244         reg = 0;
1245         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1246         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1247         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1248
1249         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1250         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1251         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1252         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1253
1254         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1255         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1256         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1257
1258         return 0;
1259 }
1260
1261 /*
1262  * Initialization functions.
1263  */
1264 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1265 {
1266         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1267         u32 word;
1268
1269         if (entry->queue->qid == QID_RX) {
1270                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1271
1272                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1273         } else {
1274                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1275
1276                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1277                         rt2x00_get_field32(word, TXD_W0_VALID));
1278         }
1279 }
1280
1281 static void rt61pci_clear_entry(struct queue_entry *entry)
1282 {
1283         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1284         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1285         u32 word;
1286
1287         if (entry->queue->qid == QID_RX) {
1288                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1289                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1290                                    skbdesc->skb_dma);
1291                 rt2x00_desc_write(entry_priv->desc, 5, word);
1292
1293                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1294                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1295                 rt2x00_desc_write(entry_priv->desc, 0, word);
1296         } else {
1297                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1298                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1299                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1300                 rt2x00_desc_write(entry_priv->desc, 0, word);
1301         }
1302 }
1303
1304 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1305 {
1306         struct queue_entry_priv_pci *entry_priv;
1307         u32 reg;
1308
1309         /*
1310          * Initialize registers.
1311          */
1312         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1313         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1314                            rt2x00dev->tx[0].limit);
1315         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1316                            rt2x00dev->tx[1].limit);
1317         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1318                            rt2x00dev->tx[2].limit);
1319         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1320                            rt2x00dev->tx[3].limit);
1321         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1322
1323         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1324         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1325                            rt2x00dev->tx[0].desc_size / 4);
1326         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1327
1328         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1329         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1330         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1331                            entry_priv->desc_dma);
1332         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1333
1334         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1335         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1336         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1337                            entry_priv->desc_dma);
1338         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1339
1340         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1341         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1342         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1343                            entry_priv->desc_dma);
1344         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1345
1346         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1347         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1348         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1349                            entry_priv->desc_dma);
1350         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1351
1352         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1353         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1354         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1355                            rt2x00dev->rx->desc_size / 4);
1356         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1357         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1358
1359         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1360         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1361         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1362                            entry_priv->desc_dma);
1363         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1364
1365         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1366         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1367         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1368         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1369         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1370         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1371
1372         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1373         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1374         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1375         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1376         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1377         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1378
1379         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1380         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1381         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1382
1383         return 0;
1384 }
1385
1386 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1387 {
1388         u32 reg;
1389
1390         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1391         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1392         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1393         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1394         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1395
1396         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1397         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1398         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1399         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1400         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1401         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1402         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1403         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1404         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1405         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1406
1407         /*
1408          * CCK TXD BBP registers
1409          */
1410         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1411         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1412         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1413         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1414         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1415         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1416         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1417         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1418         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1419         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1420
1421         /*
1422          * OFDM TXD BBP registers
1423          */
1424         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1425         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1426         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1427         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1428         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1429         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1430         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1431         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1432
1433         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1434         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1435         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1436         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1437         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1438         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1439
1440         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1441         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1442         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1443         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1444         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1445         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1446
1447         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1448         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1449         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1450         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1451         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1452         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1453         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1454         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1455
1456         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1457
1458         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1459
1460         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1461         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1462         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1463
1464         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1465
1466         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1467                 return -EBUSY;
1468
1469         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1470
1471         /*
1472          * Invalidate all Shared Keys (SEC_CSR0),
1473          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1474          */
1475         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1476         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1477         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1478
1479         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1480         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1481         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1482         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1483
1484         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1485
1486         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1487
1488         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1489
1490         /*
1491          * Clear all beacons
1492          * For the Beacon base registers we only need to clear
1493          * the first byte since that byte contains the VALID and OWNER
1494          * bits which (when set to 0) will invalidate the entire beacon.
1495          */
1496         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1497         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1498         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1499         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1500
1501         /*
1502          * We must clear the error counters.
1503          * These registers are cleared on read,
1504          * so we may pass a useless variable to store the value.
1505          */
1506         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1507         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1508         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1509
1510         /*
1511          * Reset MAC and BBP registers.
1512          */
1513         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1514         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1515         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1516         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1517
1518         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1519         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1520         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1521         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1522
1523         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1524         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1525         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1526
1527         return 0;
1528 }
1529
1530 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1531 {
1532         unsigned int i;
1533         u8 value;
1534
1535         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1536                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1537                 if ((value != 0xff) && (value != 0x00))
1538                         return 0;
1539                 udelay(REGISTER_BUSY_DELAY);
1540         }
1541
1542         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1543         return -EACCES;
1544 }
1545
1546 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1547 {
1548         unsigned int i;
1549         u16 eeprom;
1550         u8 reg_id;
1551         u8 value;
1552
1553         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1554                 return -EACCES;
1555
1556         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1557         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1558         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1559         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1560         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1561         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1562         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1563         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1564         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1565         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1566         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1567         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1568         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1569         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1570         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1571         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1572         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1573         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1574         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1575         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1576         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1577         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1578         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1579         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1580
1581         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1582                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1583
1584                 if (eeprom != 0xffff && eeprom != 0x0000) {
1585                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1586                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1587                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1588                 }
1589         }
1590
1591         return 0;
1592 }
1593
1594 /*
1595  * Device state switch handlers.
1596  */
1597 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1598                               enum dev_state state)
1599 {
1600         u32 reg;
1601
1602         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1603         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1604                            (state == STATE_RADIO_RX_OFF) ||
1605                            (state == STATE_RADIO_RX_OFF_LINK));
1606         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1607 }
1608
1609 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1610                                enum dev_state state)
1611 {
1612         int mask = (state == STATE_RADIO_IRQ_OFF);
1613         u32 reg;
1614
1615         /*
1616          * When interrupts are being enabled, the interrupt registers
1617          * should clear the register to assure a clean state.
1618          */
1619         if (state == STATE_RADIO_IRQ_ON) {
1620                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1621                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1622
1623                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1624                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1625         }
1626
1627         /*
1628          * Only toggle the interrupts bits we are going to use.
1629          * Non-checked interrupt bits are disabled by default.
1630          */
1631         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1632         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1633         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1634         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1635         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1636         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1637
1638         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1639         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1640         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1641         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1642         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1643         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1644         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1645         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1646         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1647         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1648 }
1649
1650 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1651 {
1652         u32 reg;
1653
1654         /*
1655          * Initialize all registers.
1656          */
1657         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1658                      rt61pci_init_registers(rt2x00dev) ||
1659                      rt61pci_init_bbp(rt2x00dev)))
1660                 return -EIO;
1661
1662         /*
1663          * Enable RX.
1664          */
1665         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1666         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1667         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1668
1669         return 0;
1670 }
1671
1672 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1673 {
1674         u32 reg;
1675
1676         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1677
1678         /*
1679          * Disable synchronisation.
1680          */
1681         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1682
1683         /*
1684          * Cancel RX and TX.
1685          */
1686         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1687         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1688         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1689         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1690         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1691         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1692 }
1693
1694 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1695 {
1696         u32 reg;
1697         unsigned int i;
1698         char put_to_sleep;
1699
1700         put_to_sleep = (state != STATE_AWAKE);
1701
1702         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1703         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1704         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1705         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1706
1707         /*
1708          * Device is not guaranteed to be in the requested state yet.
1709          * We must wait until the register indicates that the
1710          * device has entered the correct state.
1711          */
1712         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1713                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1714                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1715                 if (state == !put_to_sleep)
1716                         return 0;
1717                 msleep(10);
1718         }
1719
1720         return -EBUSY;
1721 }
1722
1723 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1724                                     enum dev_state state)
1725 {
1726         int retval = 0;
1727
1728         switch (state) {
1729         case STATE_RADIO_ON:
1730                 retval = rt61pci_enable_radio(rt2x00dev);
1731                 break;
1732         case STATE_RADIO_OFF:
1733                 rt61pci_disable_radio(rt2x00dev);
1734                 break;
1735         case STATE_RADIO_RX_ON:
1736         case STATE_RADIO_RX_ON_LINK:
1737         case STATE_RADIO_RX_OFF:
1738         case STATE_RADIO_RX_OFF_LINK:
1739                 rt61pci_toggle_rx(rt2x00dev, state);
1740                 break;
1741         case STATE_RADIO_IRQ_ON:
1742         case STATE_RADIO_IRQ_OFF:
1743                 rt61pci_toggle_irq(rt2x00dev, state);
1744                 break;
1745         case STATE_DEEP_SLEEP:
1746         case STATE_SLEEP:
1747         case STATE_STANDBY:
1748         case STATE_AWAKE:
1749                 retval = rt61pci_set_state(rt2x00dev, state);
1750                 break;
1751         default:
1752                 retval = -ENOTSUPP;
1753                 break;
1754         }
1755
1756         if (unlikely(retval))
1757                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1758                       state, retval);
1759
1760         return retval;
1761 }
1762
1763 /*
1764  * TX descriptor initialization
1765  */
1766 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1767                                   struct sk_buff *skb,
1768                                   struct txentry_desc *txdesc)
1769 {
1770         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1771         __le32 *txd = skbdesc->desc;
1772         u32 word;
1773
1774         /*
1775          * Start writing the descriptor words.
1776          */
1777         rt2x00_desc_read(txd, 1, &word);
1778         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1779         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1780         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1781         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1782         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1783         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1784                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1785         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1786         rt2x00_desc_write(txd, 1, word);
1787
1788         rt2x00_desc_read(txd, 2, &word);
1789         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1790         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1791         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1792         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1793         rt2x00_desc_write(txd, 2, word);
1794
1795         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1796                 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1797                 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1798         }
1799
1800         rt2x00_desc_read(txd, 5, &word);
1801         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1802         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1803                            skbdesc->entry->entry_idx);
1804         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1805                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1806         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1807         rt2x00_desc_write(txd, 5, word);
1808
1809         rt2x00_desc_read(txd, 6, &word);
1810         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1811                            skbdesc->skb_dma);
1812         rt2x00_desc_write(txd, 6, word);
1813
1814         if (skbdesc->desc_len > TXINFO_SIZE) {
1815                 rt2x00_desc_read(txd, 11, &word);
1816                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1817                 rt2x00_desc_write(txd, 11, word);
1818         }
1819
1820         rt2x00_desc_read(txd, 0, &word);
1821         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1822         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1823         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1824                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1825         rt2x00_set_field32(&word, TXD_W0_ACK,
1826                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1827         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1828                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1829         rt2x00_set_field32(&word, TXD_W0_OFDM,
1830                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1831         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1832         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1833                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1834         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1835                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1836         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1837                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1838         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1839         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1840         rt2x00_set_field32(&word, TXD_W0_BURST,
1841                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1842         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1843         rt2x00_desc_write(txd, 0, word);
1844 }
1845
1846 /*
1847  * TX data initialization
1848  */
1849 static void rt61pci_write_beacon(struct queue_entry *entry)
1850 {
1851         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1852         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1853         unsigned int beacon_base;
1854         u32 reg;
1855
1856         /*
1857          * Disable beaconing while we are reloading the beacon data,
1858          * otherwise we might be sending out invalid data.
1859          */
1860         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1861         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1862         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1863         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1864         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1865
1866         /*
1867          * Write entire beacon with descriptor to register.
1868          */
1869         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1870         rt2x00pci_register_multiwrite(rt2x00dev,
1871                                       beacon_base,
1872                                       skbdesc->desc, skbdesc->desc_len);
1873         rt2x00pci_register_multiwrite(rt2x00dev,
1874                                       beacon_base + skbdesc->desc_len,
1875                                       entry->skb->data, entry->skb->len);
1876
1877         /*
1878          * Clean up beacon skb.
1879          */
1880         dev_kfree_skb_any(entry->skb);
1881         entry->skb = NULL;
1882 }
1883
1884 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1885                                   const enum data_queue_qid queue)
1886 {
1887         u32 reg;
1888
1889         if (queue == QID_BEACON) {
1890                 /*
1891                  * For Wi-Fi faily generated beacons between participating
1892                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1893                  */
1894                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1895
1896                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1897                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1898                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1899                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1900                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1901                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1902                 }
1903                 return;
1904         }
1905
1906         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1907         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1908         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1909         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1910         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1911         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1912 }
1913
1914 /*
1915  * RX control handlers
1916  */
1917 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1918 {
1919         u8 offset = rt2x00dev->lna_gain;
1920         u8 lna;
1921
1922         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1923         switch (lna) {
1924         case 3:
1925                 offset += 90;
1926                 break;
1927         case 2:
1928                 offset += 74;
1929                 break;
1930         case 1:
1931                 offset += 64;
1932                 break;
1933         default:
1934                 return 0;
1935         }
1936
1937         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1938                 if (lna == 3 || lna == 2)
1939                         offset += 10;
1940         }
1941
1942         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1943 }
1944
1945 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1946                                 struct rxdone_entry_desc *rxdesc)
1947 {
1948         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1949         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1950         u32 word0;
1951         u32 word1;
1952
1953         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1954         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1955
1956         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1957                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1958
1959         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1960                 rxdesc->cipher =
1961                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1962                 rxdesc->cipher_status =
1963                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1964         }
1965
1966         if (rxdesc->cipher != CIPHER_NONE) {
1967                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
1968                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
1969                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1970
1971                 /*
1972                  * Hardware has stripped IV/EIV data from 802.11 frame during
1973                  * decryption. It has provided the data seperately but rt2x00lib
1974                  * should decide if it should be reinserted.
1975                  */
1976                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1977
1978                 /*
1979                  * FIXME: Legacy driver indicates that the frame does
1980                  * contain the Michael Mic. Unfortunately, in rt2x00
1981                  * the MIC seems to be missing completely...
1982                  */
1983                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1984
1985                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1986                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1987                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1988                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1989         }
1990
1991         /*
1992          * Obtain the status about this packet.
1993          * When frame was received with an OFDM bitrate,
1994          * the signal is the PLCP value. If it was received with
1995          * a CCK bitrate the signal is the rate in 100kbit/s.
1996          */
1997         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1998         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
1999         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2000
2001         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2002                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2003         else
2004                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2005         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2006                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2007 }
2008
2009 /*
2010  * Interrupt functions.
2011  */
2012 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2013 {
2014         struct data_queue *queue;
2015         struct queue_entry *entry;
2016         struct queue_entry *entry_done;
2017         struct queue_entry_priv_pci *entry_priv;
2018         struct txdone_entry_desc txdesc;
2019         u32 word;
2020         u32 reg;
2021         u32 old_reg;
2022         int type;
2023         int index;
2024
2025         /*
2026          * During each loop we will compare the freshly read
2027          * STA_CSR4 register value with the value read from
2028          * the previous loop. If the 2 values are equal then
2029          * we should stop processing because the chance it
2030          * quite big that the device has been unplugged and
2031          * we risk going into an endless loop.
2032          */
2033         old_reg = 0;
2034
2035         while (1) {
2036                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2037                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2038                         break;
2039
2040                 if (old_reg == reg)
2041                         break;
2042                 old_reg = reg;
2043
2044                 /*
2045                  * Skip this entry when it contains an invalid
2046                  * queue identication number.
2047                  */
2048                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2049                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2050                 if (unlikely(!queue))
2051                         continue;
2052
2053                 /*
2054                  * Skip this entry when it contains an invalid
2055                  * index number.
2056                  */
2057                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2058                 if (unlikely(index >= queue->limit))
2059                         continue;
2060
2061                 entry = &queue->entries[index];
2062                 entry_priv = entry->priv_data;
2063                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2064
2065                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2066                     !rt2x00_get_field32(word, TXD_W0_VALID))
2067                         return;
2068
2069                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2070                 while (entry != entry_done) {
2071                         /* Catch up.
2072                          * Just report any entries we missed as failed.
2073                          */
2074                         WARNING(rt2x00dev,
2075                                 "TX status report missed for entry %d\n",
2076                                 entry_done->entry_idx);
2077
2078                         txdesc.flags = 0;
2079                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2080                         txdesc.retry = 0;
2081
2082                         rt2x00lib_txdone(entry_done, &txdesc);
2083                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2084                 }
2085
2086                 /*
2087                  * Obtain the status about this packet.
2088                  */
2089                 txdesc.flags = 0;
2090                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2091                 case 0: /* Success, maybe with retry */
2092                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2093                         break;
2094                 case 6: /* Failure, excessive retries */
2095                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2096                         /* Don't break, this is a failed frame! */
2097                 default: /* Failure */
2098                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2099                 }
2100                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2101
2102                 rt2x00lib_txdone(entry, &txdesc);
2103         }
2104 }
2105
2106 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2107 {
2108         struct rt2x00_dev *rt2x00dev = dev_instance;
2109         u32 reg_mcu;
2110         u32 reg;
2111
2112         /*
2113          * Get the interrupt sources & saved to local variable.
2114          * Write register value back to clear pending interrupts.
2115          */
2116         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2117         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2118
2119         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2120         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2121
2122         if (!reg && !reg_mcu)
2123                 return IRQ_NONE;
2124
2125         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2126                 return IRQ_HANDLED;
2127
2128         /*
2129          * Handle interrupts, walk through all bits
2130          * and run the tasks, the bits are checked in order of
2131          * priority.
2132          */
2133
2134         /*
2135          * 1 - Rx ring done interrupt.
2136          */
2137         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2138                 rt2x00pci_rxdone(rt2x00dev);
2139
2140         /*
2141          * 2 - Tx ring done interrupt.
2142          */
2143         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2144                 rt61pci_txdone(rt2x00dev);
2145
2146         /*
2147          * 3 - Handle MCU command done.
2148          */
2149         if (reg_mcu)
2150                 rt2x00pci_register_write(rt2x00dev,
2151                                          M2H_CMD_DONE_CSR, 0xffffffff);
2152
2153         return IRQ_HANDLED;
2154 }
2155
2156 /*
2157  * Device probe functions.
2158  */
2159 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2160 {
2161         struct eeprom_93cx6 eeprom;
2162         u32 reg;
2163         u16 word;
2164         u8 *mac;
2165         s8 value;
2166
2167         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2168
2169         eeprom.data = rt2x00dev;
2170         eeprom.register_read = rt61pci_eepromregister_read;
2171         eeprom.register_write = rt61pci_eepromregister_write;
2172         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2173             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2174         eeprom.reg_data_in = 0;
2175         eeprom.reg_data_out = 0;
2176         eeprom.reg_data_clock = 0;
2177         eeprom.reg_chip_select = 0;
2178
2179         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2180                                EEPROM_SIZE / sizeof(u16));
2181
2182         /*
2183          * Start validation of the data that has been read.
2184          */
2185         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2186         if (!is_valid_ether_addr(mac)) {
2187                 random_ether_addr(mac);
2188                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2189         }
2190
2191         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2192         if (word == 0xffff) {
2193                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2194                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2195                                    ANTENNA_B);
2196                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2197                                    ANTENNA_B);
2198                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2199                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2200                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2201                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2202                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2203                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2204         }
2205
2206         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2207         if (word == 0xffff) {
2208                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2209                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2210                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2211                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2212                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2213                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2214                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2215                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2216         }
2217
2218         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2219         if (word == 0xffff) {
2220                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2221                                    LED_MODE_DEFAULT);
2222                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2223                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2224         }
2225
2226         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2227         if (word == 0xffff) {
2228                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2229                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2230                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2231                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2232         }
2233
2234         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2235         if (word == 0xffff) {
2236                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2237                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2238                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2239                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2240         } else {
2241                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2242                 if (value < -10 || value > 10)
2243                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2244                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2245                 if (value < -10 || value > 10)
2246                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2247                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2248         }
2249
2250         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2251         if (word == 0xffff) {
2252                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2253                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2254                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2255                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2256         } else {
2257                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2258                 if (value < -10 || value > 10)
2259                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2260                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2261                 if (value < -10 || value > 10)
2262                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2263                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2264         }
2265
2266         return 0;
2267 }
2268
2269 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2270 {
2271         u32 reg;
2272         u16 value;
2273         u16 eeprom;
2274         u16 device;
2275
2276         /*
2277          * Read EEPROM word for configuration.
2278          */
2279         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2280
2281         /*
2282          * Identify RF chipset.
2283          * To determine the RT chip we have to read the
2284          * PCI header of the device.
2285          */
2286         pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2287                              PCI_CONFIG_HEADER_DEVICE, &device);
2288         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2289         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2290         rt2x00_set_chip(rt2x00dev, device, value, reg);
2291
2292         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2293             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2294             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2295             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2296                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2297                 return -ENODEV;
2298         }
2299
2300         /*
2301          * Determine number of antenna's.
2302          */
2303         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2304                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2305
2306         /*
2307          * Identify default antenna configuration.
2308          */
2309         rt2x00dev->default_ant.tx =
2310             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2311         rt2x00dev->default_ant.rx =
2312             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2313
2314         /*
2315          * Read the Frame type.
2316          */
2317         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2318                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2319
2320         /*
2321          * Detect if this device has an hardware controlled radio.
2322          */
2323 #ifdef CONFIG_RT2X00_LIB_RFKILL
2324         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2325                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2326 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2327
2328         /*
2329          * Read frequency offset and RF programming sequence.
2330          */
2331         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2332         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2333                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2334
2335         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2336
2337         /*
2338          * Read external LNA informations.
2339          */
2340         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2341
2342         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2343                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2344         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2345                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2346
2347         /*
2348          * When working with a RF2529 chip without double antenna
2349          * the antenna settings should be gathered from the NIC
2350          * eeprom word.
2351          */
2352         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2353             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2354                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2355                 case 0:
2356                         rt2x00dev->default_ant.tx = ANTENNA_B;
2357                         rt2x00dev->default_ant.rx = ANTENNA_A;
2358                         break;
2359                 case 1:
2360                         rt2x00dev->default_ant.tx = ANTENNA_B;
2361                         rt2x00dev->default_ant.rx = ANTENNA_B;
2362                         break;
2363                 case 2:
2364                         rt2x00dev->default_ant.tx = ANTENNA_A;
2365                         rt2x00dev->default_ant.rx = ANTENNA_A;
2366                         break;
2367                 case 3:
2368                         rt2x00dev->default_ant.tx = ANTENNA_A;
2369                         rt2x00dev->default_ant.rx = ANTENNA_B;
2370                         break;
2371                 }
2372
2373                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2374                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2375                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2376                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2377         }
2378
2379         /*
2380          * Store led settings, for correct led behaviour.
2381          * If the eeprom value is invalid,
2382          * switch to default led mode.
2383          */
2384 #ifdef CONFIG_RT2X00_LIB_LEDS
2385         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2386         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2387
2388         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2389         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2390         if (value == LED_MODE_SIGNAL_STRENGTH)
2391                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2392                                  LED_TYPE_QUALITY);
2393
2394         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2395         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2396                            rt2x00_get_field16(eeprom,
2397                                               EEPROM_LED_POLARITY_GPIO_0));
2398         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2399                            rt2x00_get_field16(eeprom,
2400                                               EEPROM_LED_POLARITY_GPIO_1));
2401         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2402                            rt2x00_get_field16(eeprom,
2403                                               EEPROM_LED_POLARITY_GPIO_2));
2404         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2405                            rt2x00_get_field16(eeprom,
2406                                               EEPROM_LED_POLARITY_GPIO_3));
2407         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2408                            rt2x00_get_field16(eeprom,
2409                                               EEPROM_LED_POLARITY_GPIO_4));
2410         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2411                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2412         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2413                            rt2x00_get_field16(eeprom,
2414                                               EEPROM_LED_POLARITY_RDY_G));
2415         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2416                            rt2x00_get_field16(eeprom,
2417                                               EEPROM_LED_POLARITY_RDY_A));
2418 #endif /* CONFIG_RT2X00_LIB_LEDS */
2419
2420         return 0;
2421 }
2422
2423 /*
2424  * RF value list for RF5225 & RF5325
2425  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2426  */
2427 static const struct rf_channel rf_vals_noseq[] = {
2428         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2429         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2430         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2431         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2432         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2433         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2434         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2435         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2436         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2437         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2438         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2439         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2440         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2441         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2442
2443         /* 802.11 UNI / HyperLan 2 */
2444         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2445         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2446         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2447         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2448         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2449         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2450         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2451         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2452
2453         /* 802.11 HyperLan 2 */
2454         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2455         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2456         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2457         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2458         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2459         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2460         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2461         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2462         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2463         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2464
2465         /* 802.11 UNII */
2466         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2467         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2468         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2469         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2470         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2471         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2472
2473         /* MMAC(Japan)J52 ch 34,38,42,46 */
2474         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2475         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2476         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2477         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2478 };
2479
2480 /*
2481  * RF value list for RF5225 & RF5325
2482  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2483  */
2484 static const struct rf_channel rf_vals_seq[] = {
2485         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2486         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2487         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2488         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2489         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2490         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2491         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2492         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2493         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2494         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2495         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2496         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2497         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2498         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2499
2500         /* 802.11 UNI / HyperLan 2 */
2501         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2502         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2503         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2504         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2505         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2506         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2507         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2508         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2509
2510         /* 802.11 HyperLan 2 */
2511         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2512         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2513         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2514         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2515         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2516         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2517         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2518         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2519         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2520         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2521
2522         /* 802.11 UNII */
2523         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2524         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2525         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2526         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2527         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2528         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2529
2530         /* MMAC(Japan)J52 ch 34,38,42,46 */
2531         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2532         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2533         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2534         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2535 };
2536
2537 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2538 {
2539         struct hw_mode_spec *spec = &rt2x00dev->spec;
2540         struct channel_info *info;
2541         char *tx_power;
2542         unsigned int i;
2543
2544         /*
2545          * Initialize all hw fields.
2546          */
2547         rt2x00dev->hw->flags =
2548             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2549             IEEE80211_HW_SIGNAL_DBM;
2550         rt2x00dev->hw->extra_tx_headroom = 0;
2551
2552         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2553         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2554                                 rt2x00_eeprom_addr(rt2x00dev,
2555                                                    EEPROM_MAC_ADDR_0));
2556
2557         /*
2558          * Initialize hw_mode information.
2559          */
2560         spec->supported_bands = SUPPORT_BAND_2GHZ;
2561         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2562
2563         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2564                 spec->num_channels = 14;
2565                 spec->channels = rf_vals_noseq;
2566         } else {
2567                 spec->num_channels = 14;
2568                 spec->channels = rf_vals_seq;
2569         }
2570
2571         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2572             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2573                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2574                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2575         }
2576
2577         /*
2578          * Create channel information array
2579          */
2580         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2581         if (!info)
2582                 return -ENOMEM;
2583
2584         spec->channels_info = info;
2585
2586         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2587         for (i = 0; i < 14; i++)
2588                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2589
2590         if (spec->num_channels > 14) {
2591                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2592                 for (i = 14; i < spec->num_channels; i++)
2593                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2594         }
2595
2596         return 0;
2597 }
2598
2599 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2600 {
2601         int retval;
2602
2603         /*
2604          * Allocate eeprom data.
2605          */
2606         retval = rt61pci_validate_eeprom(rt2x00dev);
2607         if (retval)
2608                 return retval;
2609
2610         retval = rt61pci_init_eeprom(rt2x00dev);
2611         if (retval)
2612                 return retval;
2613
2614         /*
2615          * Initialize hw specifications.
2616          */
2617         retval = rt61pci_probe_hw_mode(rt2x00dev);
2618         if (retval)
2619                 return retval;
2620
2621         /*
2622          * This device requires firmware and DMA mapped skbs.
2623          */
2624         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2625         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2626         if (!modparam_nohwcrypt)
2627                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2628
2629         /*
2630          * Set the rssi offset.
2631          */
2632         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2633
2634         return 0;
2635 }
2636
2637 /*
2638  * IEEE80211 stack callback functions.
2639  */
2640 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2641                            const struct ieee80211_tx_queue_params *params)
2642 {
2643         struct rt2x00_dev *rt2x00dev = hw->priv;
2644         struct data_queue *queue;
2645         struct rt2x00_field32 field;
2646         int retval;
2647         u32 reg;
2648
2649         /*
2650          * First pass the configuration through rt2x00lib, that will
2651          * update the queue settings and validate the input. After that
2652          * we are free to update the registers based on the value
2653          * in the queue parameter.
2654          */
2655         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2656         if (retval)
2657                 return retval;
2658
2659         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2660
2661         /* Update WMM TXOP register */
2662         if (queue_idx < 2) {
2663                 field.bit_offset = queue_idx * 16;
2664                 field.bit_mask = 0xffff << field.bit_offset;
2665
2666                 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2667                 rt2x00_set_field32(&reg, field, queue->txop);
2668                 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2669         } else if (queue_idx < 4) {
2670                 field.bit_offset = (queue_idx - 2) * 16;
2671                 field.bit_mask = 0xffff << field.bit_offset;
2672
2673                 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2674                 rt2x00_set_field32(&reg, field, queue->txop);
2675                 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2676         }
2677
2678         /* Update WMM registers */
2679         field.bit_offset = queue_idx * 4;
2680         field.bit_mask = 0xf << field.bit_offset;
2681
2682         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2683         rt2x00_set_field32(&reg, field, queue->aifs);
2684         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2685
2686         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2687         rt2x00_set_field32(&reg, field, queue->cw_min);
2688         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2689
2690         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2691         rt2x00_set_field32(&reg, field, queue->cw_max);
2692         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2693
2694         return 0;
2695 }
2696
2697 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2698 {
2699         struct rt2x00_dev *rt2x00dev = hw->priv;
2700         u64 tsf;
2701         u32 reg;
2702
2703         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2704         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2705         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2706         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2707
2708         return tsf;
2709 }
2710
2711 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2712         .tx                     = rt2x00mac_tx,
2713         .start                  = rt2x00mac_start,
2714         .stop                   = rt2x00mac_stop,
2715         .add_interface          = rt2x00mac_add_interface,
2716         .remove_interface       = rt2x00mac_remove_interface,
2717         .config                 = rt2x00mac_config,
2718         .config_interface       = rt2x00mac_config_interface,
2719         .configure_filter       = rt2x00mac_configure_filter,
2720         .set_key                = rt2x00mac_set_key,
2721         .get_stats              = rt2x00mac_get_stats,
2722         .bss_info_changed       = rt2x00mac_bss_info_changed,
2723         .conf_tx                = rt61pci_conf_tx,
2724         .get_tx_stats           = rt2x00mac_get_tx_stats,
2725         .get_tsf                = rt61pci_get_tsf,
2726 };
2727
2728 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2729         .irq_handler            = rt61pci_interrupt,
2730         .probe_hw               = rt61pci_probe_hw,
2731         .get_firmware_name      = rt61pci_get_firmware_name,
2732         .get_firmware_crc       = rt61pci_get_firmware_crc,
2733         .load_firmware          = rt61pci_load_firmware,
2734         .initialize             = rt2x00pci_initialize,
2735         .uninitialize           = rt2x00pci_uninitialize,
2736         .get_entry_state        = rt61pci_get_entry_state,
2737         .clear_entry            = rt61pci_clear_entry,
2738         .set_device_state       = rt61pci_set_device_state,
2739         .rfkill_poll            = rt61pci_rfkill_poll,
2740         .link_stats             = rt61pci_link_stats,
2741         .reset_tuner            = rt61pci_reset_tuner,
2742         .link_tuner             = rt61pci_link_tuner,
2743         .write_tx_desc          = rt61pci_write_tx_desc,
2744         .write_tx_data          = rt2x00pci_write_tx_data,
2745         .write_beacon           = rt61pci_write_beacon,
2746         .kick_tx_queue          = rt61pci_kick_tx_queue,
2747         .fill_rxdone            = rt61pci_fill_rxdone,
2748         .config_shared_key      = rt61pci_config_shared_key,
2749         .config_pairwise_key    = rt61pci_config_pairwise_key,
2750         .config_filter          = rt61pci_config_filter,
2751         .config_intf            = rt61pci_config_intf,
2752         .config_erp             = rt61pci_config_erp,
2753         .config_ant             = rt61pci_config_ant,
2754         .config                 = rt61pci_config,
2755 };
2756
2757 static const struct data_queue_desc rt61pci_queue_rx = {
2758         .entry_num              = RX_ENTRIES,
2759         .data_size              = DATA_FRAME_SIZE,
2760         .desc_size              = RXD_DESC_SIZE,
2761         .priv_size              = sizeof(struct queue_entry_priv_pci),
2762 };
2763
2764 static const struct data_queue_desc rt61pci_queue_tx = {
2765         .entry_num              = TX_ENTRIES,
2766         .data_size              = DATA_FRAME_SIZE,
2767         .desc_size              = TXD_DESC_SIZE,
2768         .priv_size              = sizeof(struct queue_entry_priv_pci),
2769 };
2770
2771 static const struct data_queue_desc rt61pci_queue_bcn = {
2772         .entry_num              = 4 * BEACON_ENTRIES,
2773         .data_size              = 0, /* No DMA required for beacons */
2774         .desc_size              = TXINFO_SIZE,
2775         .priv_size              = sizeof(struct queue_entry_priv_pci),
2776 };
2777
2778 static const struct rt2x00_ops rt61pci_ops = {
2779         .name           = KBUILD_MODNAME,
2780         .max_sta_intf   = 1,
2781         .max_ap_intf    = 4,
2782         .eeprom_size    = EEPROM_SIZE,
2783         .rf_size        = RF_SIZE,
2784         .tx_queues      = NUM_TX_QUEUES,
2785         .rx             = &rt61pci_queue_rx,
2786         .tx             = &rt61pci_queue_tx,
2787         .bcn            = &rt61pci_queue_bcn,
2788         .lib            = &rt61pci_rt2x00_ops,
2789         .hw             = &rt61pci_mac80211_ops,
2790 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2791         .debugfs        = &rt61pci_rt2x00debug,
2792 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2793 };
2794
2795 /*
2796  * RT61pci module information.
2797  */
2798 static struct pci_device_id rt61pci_device_table[] = {
2799         /* RT2561s */
2800         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2801         /* RT2561 v2 */
2802         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2803         /* RT2661 */
2804         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2805         { 0, }
2806 };
2807
2808 MODULE_AUTHOR(DRV_PROJECT);
2809 MODULE_VERSION(DRV_VERSION);
2810 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2811 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2812                         "PCI & PCMCIA chipset based cards");
2813 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2814 MODULE_FIRMWARE(FIRMWARE_RT2561);
2815 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2816 MODULE_FIRMWARE(FIRMWARE_RT2661);
2817 MODULE_LICENSE("GPL");
2818
2819 static struct pci_driver rt61pci_driver = {
2820         .name           = KBUILD_MODNAME,
2821         .id_table       = rt61pci_device_table,
2822         .probe          = rt2x00pci_probe,
2823         .remove         = __devexit_p(rt2x00pci_remove),
2824         .suspend        = rt2x00pci_suspend,
2825         .resume         = rt2x00pci_resume,
2826 };
2827
2828 static int __init rt61pci_init(void)
2829 {
2830         return pci_register_driver(&rt61pci_driver);
2831 }
2832
2833 static void __exit rt61pci_exit(void)
2834 {
2835         pci_unregister_driver(&rt61pci_driver);
2836 }
2837
2838 module_init(rt61pci_init);
2839 module_exit(rt61pci_exit);